Single electron readout circuit and method based on composite dielectric grating photosensitive detector

Abstract

The present invention discloses a single-electron readout circuit and method based on a composite dielectric grating photosensitive detector. The photosensitive detector includes a photosensitive transistor and a reading transistor formed on the same substrate. The two transistors share a composite dielectric gate. The composite dielectric gate includes a bottom dielectric layer, a charge coupling layer, a top dielectric layer and a control gate. The readout circuit includes a correlated double sampling circuit, an amplifier circuit and a quantization circuit. The correlated double sampling circuit is used to sample the drain current of the reading transistor, the amplifier circuit is used to amplify the voltage signal output by the correlated double sampling circuit, and the quantization circuit is used to perform single-bit quantization on the voltage signal output by the amplifier circuit. The present invention provides a low-noise, high-gain, high-frame-rate readout circuit and method based on a composite dielectric grating photosensitive detector, which can achieve single-electron level readout and solve the problem of high-performance imaging of high-resolution low-illuminance scenes.

Description

Technical Field

[0001] The present invention relates to a readout method of a photosensitive detector array, and in particular to a readout circuit and method thereof at a single electron level with low noise, high gain and high frame rate based on a composite dielectric grating photosensitive detector. Background Art

[0002] Photodetectors play an extremely important role in daily life and in the field of national defense and security. Currently, the mainstream photodetectors are divided into two categories: CCD and CMOS-APS. With the development of CMOS technology, CMOS-APS has occupied the vast majority of the market share. However, as the pixel size becomes smaller and smaller, the sensitivity and full well capacity of CMOS-APS are getting lower and lower, resulting in a significant reduction in the signal-to-noise ratio, low dynamic range, and poor imaging quality.

[0003] In order to solve the problem of low signal-to-noise ratio of small pixels, photodetectors based on composite dielectric gratings improve the signal-to-noise ratio by expanding the full-well capacity at small pixel sizes. Since ordinary photodetectors based on composite dielectric gratings do not require high sensitivity in order to detect large full-well signal quantities, photodetection under extremely low illumination requires a long exposure time, which can easily lead to excessive dark current accumulation and drowning of the signal. Summary of the invention

[0004] In view of the fact that existing photosensitive detectors cannot meet the imaging requirements under extremely low illumination, especially in scenarios requiring high resolution, in order to solve the problem of high-performance imaging of high-resolution low-illumination scenes, the present invention provides a low-noise, high-gain, high-frame rate readout circuit and method based on a composite dielectric grating photosensitive detector, which can achieve single-electron level readout.

[0005] The technical solution adopted by the present invention is as follows:

[0006] A single electron readout circuit based on a composite dielectric grating photosensitive detector, wherein the photosensitive detector includes a photosensitive transistor and a reading transistor formed on the same substrate, wherein the two transistors share a composite dielectric grating, wherein the composite dielectric grating includes a bottom dielectric layer, a charge coupling layer, a top dielectric layer and a control gate; the readout circuit includes a correlated double sampling circuit, an amplifying circuit and a quantizing circuit, wherein the correlated double sampling circuit is used to sample the drain current of the reading transistor, the amplifying circuit is used to amplify the voltage signal output by the correlated double sampling circuit, and the quantizing circuit is used to perform single-bit quantization on the voltage signal output by the amplifying circuit.

[0007] Furthermore, the thickness of the top dielectric layer is greater than 10 nm, and the size of the composite dielectric gate is less than 500 nm.

[0008] Furthermore, the amplifier circuit adopts a charge transfer amplifier circuit.

[0009] Furthermore, the quantization circuit adopts a single-bit ADC or a D-latch circuit.

[0010] Furthermore, when the photosensitive detectors are multiple to form an array structure, the array structure is divided into multiple sub-arrays, and each sub-array shares one readout circuit.

[0011] The present invention also provides a readout method of the above-mentioned single electron readout circuit based on the composite dielectric grating photosensitive detector, comprising the following steps:

[0012] (1) Reset: A voltage of -4 V is applied to the control gate and a voltage of -3 V is applied to the substrate to reset the electrons collected by the photosensitive transistor of the photodetector, and the reset signal is read by the correlated double sampling circuit;

[0013] (2) Exposure: A voltage of 0V is applied to the control gate and a voltage of -3V is applied to the substrate. When there is light, when the energy of the photoelectrons is greater than the bandgap width of silicon, an electron-hole pair will be excited. Under the action of the electric field in the depletion region, the photosensitive transistor collects the generated photoelectrons. The potential of the photosensitive transistor will change and couple to the charge coupling layer of the composite dielectric gate to change the potential of the charge coupling layer, thereby changing the threshold voltage of the turn-on reading transistor. The threshold voltage change is U=Q / C, where Q is the charge of the collected photoelectrons and C is the capacitance of the top dielectric layer. The exposure signal is read by the correlated double sampling circuit;

[0014] (3) Reading: During the readout stage, a voltage of 2 to 5 V is applied to the control gate and a voltage of -3 to 0 V is applied to the substrate. These two voltages must satisfy the requirement that the read transistor of the photodetector is in the linear region in both the empty well and the full well. A constant voltage is applied to the drain of the read transistor and a constant voltage of 0 V is applied to the source. The drain current is read out by a correlated double sampling circuit.

[0015] Furthermore, after the photodetector is reset, the correlated double sampling circuit samples the drain current through the reset signal sampling capacitor and outputs a voltage signal VOUTR of the reset signal; after the photodetector is exposed, the correlated double sampling circuit samples the drain current through the exposure signal sampling capacitor and outputs a voltage signal VOUTS of the exposure signal. The difference VOUTS-VOUTR between the two voltage signals is the signal amount corresponding to the photoelectrons collected after exposure.

[0016] The detector of the present invention achieves high gain at the device level, so that the overall signal-to-noise ratio of the signal transmission link is improved, which is conducive to improving the imaging quality. Since the signal collection amount of the photosensitive detector is far lower than the full well capacity in a low-illuminance imaging environment or under extremely high frame rate imaging conditions, the high-gain output of charge to voltage satisfies the dynamic range of the analog circuit, reducing the difficulty of circuit design. In the post-stage circuit, the present invention adopts a correlated double sampling circuit to reduce reset noise, shot noise, etc., further improving the signal-to-noise ratio; the amplifier circuit adopts a charge transfer amplifier circuit, which does not require continuous active input compared to the structure of a traditional operational amplifier, so it has great advantages in power consumption; and in the 1-bit quantization requirement, the requirements for the amplification accuracy of the amplifier circuit in the readout circuit of different arrays are low, so the advantages of the charge transfer amplifier circuit can be fully utilized. In the quantization circuit, only 1-bit quantization is required for low illumination or extremely high frame rate requirements, so a single-bit ADC or D-latch can be used for high frame rate quantization. After this optimization from device to readout circuit, compared with the traditional readout method of ramp voltage scanning device threshold adopted by photosensitive detectors based on composite dielectric gratings, the circuit readout method of the present invention makes the noise lower than 0.2e-, which is only 2% of the traditional solution; the charge-to-voltage conversion gain reaches 1mv / e-, which is 4 times that of the traditional solution; the frame rate can reach 1000fps, while the traditional solution is only 3fps. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of the structure of a composite dielectric grating photosensitive detector according to an embodiment of the present invention;

[0018] Figure 2 A schematic diagram of the structure of a read transistor for a composite dielectric grating photosensitive detector;

[0019] Figure 3 A schematic diagram of a structure in which an m×n pixel subarray shares a readout circuit;

[0020] Figure 4 It is a module schematic diagram of the readout circuit;

[0021] Figure 5 is a structural diagram of a correlated double sampling circuit;

[0022] Figure 6 It is a schematic diagram of the structure of the charge transfer amplifier circuit;

[0023] Figure 7 It is a structural diagram of D-latch;

[0024] Figure 8 A schematic diagram of a module of an m×n photosensor subarray and a readout circuit;

[0025] Fig. 9 Schematic diagram of the structure of an M×N photosensor array integrated with (M / n)×(N / n) readout circuits. DETAILED DESCRIPTION

[0026] This embodiment uses Figure 1 The structure of the photosensitive detector based on the composite dielectric gate shown is as follows: it includes a photosensitive transistor 101 and a read transistor 103 formed on the same P-type semiconductor substrate. The two parts share a composite dielectric gate, wherein the composite dielectric gate includes a bottom dielectric layer 107, a charge coupling layer 106, a top dielectric layer 104 and a control gate 105 from bottom to top. The photosensitive transistor 101 is used to sense light and convert the light signal into an electrical signal, and the read transistor 103 is used to read the electrical signal. The structure of the read transistor 103 is as shown in FIG. Figure 2 As shown, it also includes a drain 201 and a source 202 .

[0027] According to the capacitance formula: C=ε r S / 4πkd, where C is the capacitance, ε r is the dielectric constant, S is the facing area between the two electrode plates, k is the Coulomb constant, and d is the distance between the capacitor plates. If the area of ​​the composite dielectric gate is made smaller and the thickness is made larger, a small composite dielectric gate capacitance can be obtained. According to the formula C=Q / U, where C is capacitance, Q is charge, and U is voltage, a charge can be converted into a larger voltage, thereby improving the sensitivity of the photosensitive detector. Therefore, the capacitance of the composite dielectric gate can be reduced by increasing the thickness of the top dielectric layer 104 and reducing the size of the composite dielectric gate to improve the sensitivity. For example, if the thickness of the top dielectric layer 104 is increased to greater than 10nm and the size of the composite dielectric gate is reduced to less than 500nm, the capacitance of the composite dielectric gate can be made less than 0.15fF. Under this condition, the charge-to-voltage conversion gain, that is, the sensitivity, can be greater than 1mV / e-.

[0028] The photosensitive transistor 101 of the photosensitive detector is used to convert the light signal into photoelectrons. The two are linearly related. The photoelectrons generated by the substrate 102 are coupled to the charge coupling layer 106 and converted into voltage through the capacitor, thereby changing the threshold voltage of the reading transistor 103. When a fixed gate voltage is given, the drain 201 current will vary depending on the threshold voltage. The grayscale value of the photosensitive detector can be calculated by collecting the current signal. For a large array of photosensitive detectors, the large array of photosensitive detectors is divided into multiple sub-arrays, and each sub-array shares a readout circuit (such as Figure 3 As shown in Figure 2), the photosensitive detector array can be read out in parallel to achieve a high frame rate.

[0029] During the exposure process, the photoelectrons collected by the photosensitive transistor 101 are coupled to the charge coupling layer 106 of the composite dielectric gate at the interface between silicon and silicon dioxide, changing the potential of the charge coupling layer 106 of the composite dielectric gate, thereby changing the threshold voltage of the reading transistor 103. During the signal reading process, a positive bias pulse is applied to the control gate 105, and the magnitude of the current in the drain 201 will change with the change of the threshold voltage, thereby determining whether to collect photoelectrons.

[0030] The readout circuit of this embodiment is as follows Figure 4 As shown, it includes a correlated double sampling circuit 401, an amplification circuit 402 and a quantization circuit 403. In the sampling process of the correlated double sampling circuit 401, it is necessary to reset the signal sampling capacitor 501 and the reset signal sampling capacitor 502 first, and read the drain current I of the photosensitive detector after reset. R And the drain current I S , charging the reset signal sampling capacitor 502 and the signal sampling capacitor 501, and the voltage difference between the two is the signal amount generated by the collected photoelectrons. In the amplifier circuit 402, a charge transfer amplifier circuit is used, which has the advantage of low power consumption and can reduce the overall power consumption of a large-scale photosensitive detector array. In the quantization circuit 403, the output signal of the amplifier circuit 402 is single-bit quantized, and a single-bit ADC or D-latch601 can be used to increase the speed and reduce the readout circuit area, which has the advantages of effectively reducing power consumption and high speed, and can meet imaging requirements under low illumination conditions.

[0031] This embodiment provides a single-electron-level low-noise, high-gain, high-frame-rate readout method based on a composite dielectric grating photosensitive detector:

[0032] (1) Reset: A voltage of -4 V is applied to the control gate 105 and a voltage of -3 V is applied to the P-type substrate 102 to reset the electrons collected by the MOS-C photosensitive transistor 101 of the photodetector and switch to the read mode. The reset signal is read by the correlated double sampling circuit;

[0033] (2) Exposure: A voltage of 0V is applied to the control gate 105 and a voltage of -3V is applied to the P-type substrate 102. When there is light, when the energy of the photoelectrons is greater than the bandgap width of silicon, an electron-hole pair will be excited. Under the action of the electric field in the depletion region, the photosensitive transistor 101 will collect the generated photoelectrons. The potential of the photosensitive transistor 101 will change and couple to the charge coupling layer 106 of the composite dielectric gate to change the potential of the charge coupling layer 106, thereby changing the threshold voltage of the turn-on read transistor 103. The threshold voltage change is U=Q / C, where Q is the charge of the collected photoelectrons and C is the capacitance of the top dielectric layer 104. The device is switched to the read mode and the exposure signal is read by the correlated double sampling circuit.

[0034] (3) Reading: In the readout stage, the gate voltage can be 2~5V, such as adding a 3V bias to the control gate 105, and the substrate voltage can be -3~0V, such as adding a -3V bias to the P-type substrate 102. The gate voltage and substrate voltage must satisfy that the read transistor of the photodetector is in the linear region in both the empty well and the full well. The drain of the composite dielectric gate read transistor is given a constant voltage, such as 0.2V, and the source is given a constant voltage of 0V. The drain 201 current is read by the correlated double sampling circuit 401.

[0035] The VIN input terminal of the correlated double sampling circuit is connected to the drain 201 of the composite dielectric gate read transistor 103. After reset, the current of the drain 201 is read. Figure 5 As shown, the reset signal sampling capacitor CR502 of the correlated double sampling circuit samples the drain 201 current and outputs the reset signal voltage signal VOUTR. After exposure, the drain 201 current is read, and the drain 201 current is sampled by the exposure signal sampling capacitor CS501 of the correlated double sampling circuit, and the output signal voltage signal VOUTS. The difference between the two, VOUTS-VOUTR, is the signal amount corresponding to the photoelectrons collected after exposure. The use of the correlated double sampling circuit can effectively reduce reset noise and shot noise.

[0036] The signals VOUTR and VOUTS output by the correlated double sampling circuit are input to Figure 6 The input terminals in1 and in2 of the charge transfer amplifier circuit shown in the figure charge the capacitors C1 and C2 by closing the switch S1, pre-charge the output terminals out1 and out2 by closing the switch S2, and output the voltage signal to out1 and out2 by opening the switch S1. After amplification by the charge transfer amplifier, the gain is C2 / C1. Since the charge transfer amplifier is charged only when the switch is closed, the power consumption can be effectively reduced.

[0037] The quantization circuit can be used as Figure 7 The outputs out1 and out2 of the charge transfer amplifier are used as the input of the D-latch circuit for single-bit quantization. Single-bit quantization can greatly improve the quantization speed, so that the photosensitive detector can have a very short exposure time, meeting the needs of single-photon imaging within the exposure time under low illumination.

[0038] Since the photosensitive detector is very small and the readout circuit is relatively large, in order to save chip area, a plurality of photosensitive detectors can be used to form a sub-array 801 and share a readout circuit 802, such as Figure 8 shown.

[0039] For the photosensitive detector array, in order to achieve high-speed readout, if the photosensitive detector array is composed of M×N photosensitive detectors, each m×n photosensitive detector subarray 901 shares a readout circuit 902, such as Fig. 9 As shown, there are a total of (M / n)×(N / n) photosensitive detector subarrays and readout circuits, and the photosensitive detector subarray 901 corresponds to the readout circuit 902 one by one. Compared with using only one readout circuit, the readout speed is accelerated by (M / n)×(N / n) times, achieving high frame rate fast readout.

Claims

1. A single electron readout circuit based on a composite dielectric grating photosensitive detector, wherein the photosensitive detector comprises a photosensitive transistor and a reading transistor formed on the same substrate, and the two transistors share a composite dielectric grating, wherein the composite dielectric grating comprises a bottom dielectric layer, a charge coupling layer, a top dielectric layer and a control gate; characterized in that: The readout circuit includes a correlated double sampling circuit, an amplification circuit and a quantization circuit, wherein the correlated double sampling circuit is used to sample the drain current of the reading transistor, the amplification circuit is used to amplify the voltage signal output by the correlated double sampling circuit, and the quantization circuit is used to perform single-bit quantization on the voltage signal output by the amplification circuit; the thickness of the top dielectric layer is greater than 10nm, and the size of the composite dielectric gate is less than 500nm.

2. The single electron readout circuit based on the composite dielectric grating photosensitive detector according to claim 1, characterized in that: The amplifier circuit adopts a charge transfer amplifier circuit.

3. The single electron readout circuit based on the composite dielectric grating photosensitive detector according to claim 1, characterized in that: The quantization circuit adopts a single-bit ADC or a D-latch circuit.

4. The single electron readout circuit based on the composite dielectric grating photosensitive detector according to claim 1, characterized in that: When the photosensitive detectors are multiple and form an array structure, the array structure is divided into multiple sub-arrays, and each sub-array shares one readout circuit.

5. The readout method of a single electron readout circuit based on a composite dielectric grating photosensitive detector according to any one of claims 1 to 4, characterized in that: The steps include: (1) Reset: A voltage of -4 V is applied to the control gate and a voltage of -3 V is applied to the substrate to reset the electrons collected by the photosensitive transistor of the photodetector, and the reset signal is read by the correlated double sampling circuit; (2) Exposure: A voltage of 0V is applied to the control gate and a voltage of -3V is applied to the substrate. When there is light, when the energy of the photoelectron is greater than the bandgap width of silicon, an electron-hole pair will be excited. Under the action of the electric field in the depletion region, the photosensitive transistor collects the generated photoelectrons. The potential of the photosensitive transistor will change and couple to the charge coupling layer of the composite dielectric gate to change the potential of the charge coupling layer, thereby changing the threshold voltage of the turn-on reading transistor; the exposure signal is read by the correlated double sampling circuit; (3) Reading: During the readout stage, a voltage of 2 to 5 V is applied to the control gate and a voltage of -3 to 0 V is applied to the substrate. These two voltages must satisfy the requirement that the read transistor of the photodetector is in the linear region in both the empty well and the full well. A constant voltage is applied to the drain of the read transistor and a constant voltage of 0 V is applied to the source. The drain current is read out by a correlated double sampling circuit.

6. The reading method according to claim 5, characterized in that: In step (2), the threshold voltage change of the read transistor is U=Q / C, where Q is the charge of the collected photoelectrons and C is the capacitance of the top dielectric layer.

7. The reading method according to claim 5, characterized in that: After the photodetector is reset, the correlated double sampling circuit samples the drain current through the reset signal sampling capacitor and outputs a voltage signal VOUTR of the reset signal; after the photodetector is exposed, the correlated double sampling circuit samples the drain current through the exposure signal sampling capacitor and outputs a voltage signal VOUTS of the exposure signal. The difference between the two voltage signals VOUTS-VOUTR is the signal amount corresponding to the photoelectrons collected after exposure.

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