Transistor soft breakdown detection methods, devices, media and equipment

Abstract

This disclosure relates to the field of semiconductors and integrated circuits, and discloses a method, apparatus, medium, and device for detecting soft breakdown in transistors. The method includes: continuously applying a gate control signal to the gate oxide layer of the transistor under test (TUT), the gate control signal including a DC signal under test and an AC perturbation signal, the AC perturbation signal having a target frequency and a target amplitude; detecting the leakage current of the gate oxide layer; and detecting whether soft breakdown has occurred in the gate oxide layer of the TUT based on the leakage current. In this method, the superimposed AC perturbation signal does not affect the stress characteristics of the DC signal under test; that is, the detected leakage current characteristics characterize the TDDB characteristics of the DC signal under test for the TUT. Furthermore, by amplifying the equivalent leakage current, it is possible to intuitively determine whether the currently applied DC signal will cause soft breakdown in the transistor. This method also enables in-situ characterization.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors and integrated circuits, and more specifically, to a method, apparatus, medium, and device for detecting soft breakdown of transistors. Background Technology

[0002] TDDB (Time Dependent Dielectric Breakdown) testing generally involves three stages: 1) Defect formation stage: As time increases, the number of charges trapped in the oxide layer increases, causing gate leakage current; 2) Breakdown formation stage: In this stage, the gate leakage current is relatively large, and localized defect clusters are formed inside the gate oxide layer, causing the device to enter a soft breakdown or near-breakdown state; 3) Sudden runaway stage: The gate current of the device suddenly increases. This process is very rapid, and in devices where this phenomenon occurs, the oxide layer has already undergone hard breakdown.

[0003] In related technologies, it is difficult to identify the first two stages of TDDB (soft breakdown stage).

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a method, apparatus, medium and device for detecting transistor soft breakdown.

[0006] According to one aspect of this disclosure, a method for detecting soft breakdown of a transistor is provided, comprising: continuously applying a gate control signal to the gate oxide layer of the transistor under test, the gate control signal including a DC signal under test and an AC disturbance signal, the AC disturbance signal having a target frequency and a target amplitude; detecting the leakage current of the gate oxide layer; and detecting whether soft breakdown has occurred in the gate oxide layer of the transistor under test based on the leakage current.

[0007] In an exemplary embodiment of this disclosure, before continuously applying a gate control signal to the gate oxide layer of the transistor under test, the method further includes: acquiring the AC impedance spectrum of the transistor under test; and determining the characteristic frequency of the gate oxide layer of the transistor under test based on the AC impedance spectrum.

[0008] In an exemplary embodiment of this disclosure, after determining the characteristic frequency of the gate oxide layer of the transistor under test based on the AC impedance spectrum, the method further includes: constructing an equivalent circuit model of the transistor under test, the equivalent circuit model including a first RC parallel circuit, a second RC parallel circuit, and a third RC parallel circuit connected in series, the transistor under test including a substrate, a gate oxide layer, and a gate metal layer stacked in series, the first RC parallel circuit being the equivalent circuit of the interface between the gate oxide layer and the gate metal layer, the second RC parallel circuit being the equivalent circuit of the gate oxide layer, and the third RC parallel circuit being the equivalent circuit of the interface between the gate oxide layer and the substrate; and determining the target frequency of the AC disturbance signal based on the impedance characteristics of the second RC parallel circuit and the characteristic frequency.

[0009] In an exemplary embodiment of this disclosure, determining the target frequency of the AC disturbance signal based on the impedance characteristics of the second RC parallel circuit and the characteristic frequency includes: applying an initial gate control signal to the gate oxide layer of the transistor under test, the initial gate control signal including a DC signal under test and an AC disturbance signal having an initial disturbance frequency; detecting the leakage current of the gate oxide layer corresponding to the initial disturbance frequency; if the leakage current is detected, determining the initial disturbance frequency as the target frequency of the AC disturbance signal; if the leakage current is not detected, increasing the disturbance frequency value based on the initial disturbance frequency, and repeating the steps of applying the initial gate control signal and detecting the leakage current until the leakage current of the gate oxide layer is detected, and determining the current disturbance frequency as the target frequency of the AC disturbance signal.

[0010] In an exemplary embodiment of this disclosure, after determining the target frequency of the AC disturbance signal based on the impedance characteristics of the second RC parallel circuit and the characteristic frequency, the method further includes: determining the target amplitude of the AC disturbance signal based on the target frequency.

[0011] In an exemplary embodiment of this disclosure, determining the target amplitude of the AC disturbance signal based on the target frequency includes: applying an initial gate control signal to the gate oxide layer of the transistor under test, the initial gate control signal including a DC signal under test and an initial AC disturbance signal, the initial AC disturbance signal having an initial amplitude and a target frequency; verifying whether the initial AC disturbance signal is valid based on the response result of the gate oxide layer to the initial gate control signal; if the initial AC disturbance signal is valid, increasing the amplitude of the AC disturbance signal based on the initial amplitude, and repeating the steps of applying the initial gate control signal and verifying whether the initial AC disturbance signal is valid until it is determined that the AC disturbance signal is invalid, and determining the signal amplitude of the previous valid AC disturbance signal before the invalid AC disturbance signal as the target amplitude of the AC disturbance signal.

[0012] In an exemplary embodiment of this disclosure, verifying the validity of the initial AC disturbance signal based on the response of the gate oxide layer to the initial gate control signal includes: detecting the initial leakage current of the gate oxide layer corresponding to the initial gate control signal; determining the initial AC impedance of the gate oxide layer based on the gate control signal and the initial leakage current; and detecting whether the real and imaginary parts of the initial AC impedance conform to the Kramers-Kronig relationship to verify the validity of the initial AC disturbance signal.

[0013] In an exemplary embodiment of this disclosure, the signal amplitude of the DC signal to be tested in the gate control signal is less than the intrinsic breakdown voltage of the transistor to be tested.

[0014] In an exemplary embodiment of this disclosure, the method further includes recording the duration of the applied gate control signal.

[0015] In an exemplary embodiment of this disclosure, after detecting whether the gate oxide layer of the transistor under test has undergone soft breakdown based on the leakage current, the method further includes: if soft breakdown of the gate oxide layer is detected, using the recorded duration as the soft breakdown time of the gate oxide layer; and stopping the application of the gate control signal to the transistor under test.

[0016] In an exemplary embodiment of this disclosure, the step of detecting whether the gate oxide layer of the transistor under test has undergone soft breakdown based on the leakage current includes: detecting the rate of change of the leakage current; if the rate of change is greater than or equal to a preset rate of change threshold, then determining that the gate oxide layer of the transistor under test has undergone soft breakdown.

[0017] In an exemplary embodiment of this disclosure, the AC disturbance signal is a periodic clock signal or a periodic sine wave signal.

[0018] According to a second aspect of this disclosure, a transistor soft breakdown detection device is also provided, comprising: a signal application module for continuously applying a gate control signal to the gate oxide layer of the transistor under test, the gate control signal including a DC signal under test and an AC disturbance signal, the AC disturbance signal having a target frequency and a target amplitude; a current detection module for detecting leakage current of the gate oxide layer; and a detection module for detecting whether soft breakdown has occurred in the gate oxide layer of the transistor under test based on the leakage current.

[0019] According to a third aspect of this disclosure, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the transistor soft breakdown detection method described in any embodiment of this disclosure.

[0020] According to a fourth aspect of this disclosure, a detection device is also provided, comprising: one or more processors; and a storage device for storing one or more programs, which, when executed by the one or more processors, cause the one or more processors to implement the transistor soft breakdown detection method according to any embodiment of this disclosure.

[0021] This disclosed detection method superimposes an AC disturbance signal onto the DC signal under test. The AC disturbance signal has a target frequency and can significantly reduce the equivalent impedance of the gate oxide layer of the transistor under test (TUT), thereby amplifying the equivalent leakage current of the TUT's gate oxide layer. This allows the gate current to be monitored, enabling timely detection of whether the TUT has experienced soft breakdown. Furthermore, the superimposed AC disturbance signal does not affect the stress characteristics of the DC signal under test; the detected leakage current characteristics characterize the TDDB (Total Variable Current Scale) of the DC signal on the TUT. By amplifying the equivalent leakage current, it is possible to directly determine whether the applied DC signal will cause soft breakdown in the transistor.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0024] Figure 1 This is a flowchart of a transistor soft breakdown detection method according to one embodiment of the present disclosure;

[0025] Figure 2A Bode diagram of a transistor according to one embodiment of the present disclosure;

[0026] Figure 3 This is a schematic diagram of the structure of a transistor according to one embodiment of the present disclosure;

[0027] Figure 4 for Figure 3 The equivalent circuit diagram;

[0028] Figure 5 A graph showing the change of TDDB test current over time for a transistor according to one embodiment of the present disclosure;

[0029] Figure 6 This is a structural block diagram of a transistor soft breakdown detection device according to one embodiment of the present disclosure;

[0030] Figure 7 This is a schematic diagram of the structure of a testing device according to one embodiment of the present disclosure. Detailed Implementation

[0031] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0032] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0033] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0034] Figure 1Here is a flowchart of a transistor soft breakdown detection method according to one embodiment of this disclosure, as follows: Figure 1 As shown, this detection method can be used to identify the early stages of TDDB (Soft Breakdown) during transistor TDDB testing, promptly detecting whether the transistor under test has experienced soft breakdown, thus helping to prevent hard breakdown. This method can be executed by a testing device, such as a computer running specific software. Figure 1 As shown, the method may include the following steps:

[0035] S110. A gate control signal is continuously applied to the gate oxide layer of the transistor under test. The gate control signal includes a DC signal under test and an AC disturbance signal. The AC disturbance signal has a target frequency and a target amplitude.

[0036] S120, Detect the leakage current of the gate oxide layer;

[0037] S130. Detect whether the gate oxide layer of the transistor under test has undergone soft breakdown based on leakage current.

[0038] This disclosed detection method superimposes an AC perturbation signal onto the DC signal under test. The AC perturbation signal has a target frequency, which significantly reduces the equivalent impedance of the gate oxide layer of the transistor under test (TUT), thereby amplifying the equivalent leakage current of the gate oxide layer and enabling monitoring of the gate current. This allows for timely detection of whether the TUT has experienced soft breakdown. In this method, the superimposed AC perturbation signal does not affect the stress characteristics of the DC signal under test; that is, the detected leakage current characteristics characterize the TDDB characteristics of the DC signal under test on the TUT. Furthermore, by amplifying the equivalent leakage current, it is possible to directly determine whether the applied DC signal will cause soft breakdown in the transistor. Moreover, this method enables in-situ characterization, meaning that the early stages of the TDDB effect of the transistor are characterized in-situ by detecting the leakage current of the gate oxide layer to the AC perturbation signal during the TDDB test.

[0039] The steps described above in this example implementation will now be explained in more detail.

[0040] In step S110, a gate control signal is continuously applied to the gate oxide layer of the transistor under test. The gate control signal includes a DC signal under test and an AC disturbance signal. The AC disturbance signal has a target frequency and a target amplitude.

[0041] In this disclosure, the transistor under test (DUT) can be, for example, a MOSFET. The gate control signal includes a DC signal under test and an AC perturbation signal. This can be understood as superimposing the AC perturbation signal onto the DC signal applied to the DUT, thereby reducing the equivalent impedance of the gate oxide layer and amplifying the leakage current of the gate oxide layer. The superimposed AC perturbation signal has a target frequency and therefore does not affect the stress characteristics of the DC signal under test on the gate oxide layer, but only amplifies the leakage current of the gate oxide layer. It is understood that after applying the gate control signal, the duration of the applied gate control signal can be recorded, thereby allowing for the classification and statistical analysis of the soft breakdown time of the DUT.

[0042] It is understood that the amplitude of the DC signal applied in this disclosure is less than the intrinsic breakdown voltage of the transistor under test, so as to avoid hard breakdown of the transistor under test.

[0043] The AC disturbance signal has a target frequency and a target amplitude, indicating that the AC disturbance signal in this disclosure is a periodic signal with a fixed frequency and the amplitude of the periodic signal is the target amplitude. The target frequency is high frequency, that is, the AC disturbance signal is a high frequency signal. This disclosure can amplify the equivalent leakage current of the gate oxide layer by superimposing the high-frequency AC disturbance signal, and the high-frequency AC disturbance signal has a target amplitude. Therefore, the high-frequency AC disturbance signal should not change the stress characteristics of the DC signal under test and can improve the signal-to-noise ratio of the gate oxide leakage current. The method for determining the target frequency and target amplitude can be found in the description of the following embodiments, and will not be detailed here.

[0044] It should be understood that both the DC signal and the AC disturbance signal under test are voltage signals. In an exemplary embodiment, the AC disturbance signal may be, for example, a sinusoidal signal with a fixed frequency or a clock signal with a fixed frequency. For example, a clock signal can be used as the AC disturbance signal, as long as the amplitude of the clock signal is adjusted to the target amplitude and the frequency is adjusted to the target frequency.

[0045] Understandably, before step S110, it is necessary to determine the target frequency and target amplitude of the AC disturbance signal in advance.

[0046] In an exemplary embodiment, prior to step S110, the method may further include the following steps:

[0047] S111. Obtain the AC impedance spectrum of the transistor under test;

[0048] S112. Determine the characteristic frequency of the gate oxide layer of the transistor under test based on the AC impedance spectrum.

[0049] The AC impedance spectrum is used to determine the characteristic frequencies of the AC disturbance signal to be superimposed in subsequent steps. The AC impedance spectrum can be determined, for example, by using the Bode plot or Nyquist plot of the transistor under test.

[0050] For example, Figure 2 This is a Bode plot of a transistor according to one embodiment of the present disclosure, where f1 is the characteristic frequency. As can be seen from the Bode plot, the higher the frequency of the AC signal disturbance, the smaller the equivalent impedance of the gate oxide layer. The present disclosure obtains the characteristic frequency of the gate oxide layer through the AC impedance spectrum of the gate oxide layer, thereby determining the target frequency based on this characteristic frequency. The equivalent leakage current of the gate oxide layer is amplified using the AC disturbance signal at the target frequency to monitor the leakage current.

[0051] In an exemplary embodiment, determining the target frequency of the AC disturbance signal using the characteristic frequency obtained in step S112 may specifically include the following steps:

[0052] S113. Construct an equivalent circuit model of the transistor under test. The equivalent circuit model includes a first RC parallel circuit, a second RC parallel circuit, and a third RC parallel circuit connected in series. The transistor under test includes a substrate, a gate oxide layer, and a gate metal layer stacked in series. The first RC parallel circuit is the equivalent circuit of the interface between the gate oxide layer and the gate metal layer. The second RC parallel circuit is the equivalent circuit of the gate oxide layer. The third RC parallel circuit is the equivalent circuit of the interface between the gate oxide layer and the substrate.

[0053] S114. Determine the target frequency of the AC disturbance signal based on the impedance characteristics and characteristic frequency of the second RC parallel circuit.

[0054] For example, Figure 3 This is a schematic diagram of the structure of a transistor according to one embodiment of the present disclosure, as shown below. Figure 3 As shown, the transistor includes a substrate 210, a gate oxide layer 220 and a gate metal layer 230 stacked together. The gate metal layer 230 is used to apply a gate control signal, and the substrate 210 is grounded. Figure 4 for Figure 3 The equivalent circuit diagram, from Figure 4 It can be seen that the transistor can be equivalently represented by three parallel branches connected in series. Specifically, the equivalent circuit includes a first RC parallel circuit, a second RC parallel circuit, and a third RC parallel circuit connected in series. The first RC parallel circuit is the equivalent circuit of the interface between the gate oxide layer 220 and the gate metal layer 230, which includes a first equivalent resistor R connected in parallel. OB and the first equivalent capacitance C OBThe second RC parallel circuit is the equivalent circuit of the gate oxide layer 220, which includes the second equivalent resistor Roxide and the second equivalent capacitor Coxide connected in parallel. The third RC parallel circuit is the equivalent circuit of the interface between the gate oxide layer 220 and the substrate 210, which includes the third equivalent resistor Rmo and the third equivalent capacitor Cmo connected in parallel.

[0055] As is known, during soft breakdown of a transistor, defects continuously form and accumulate within the gate oxide layer 220, affecting its impedance and consequently its leakage current. In other words, the leakage current of the gate oxide layer 220 can be used to determine whether soft breakdown has occurred. Before hard breakdown, the high impedance of the gate oxide layer 220 prevents the applied DC signal from generating a detectable current in the gate oxide layer 220, thus making leakage current undetectable. This disclosure addresses this by superimposing a high-frequency AC disturbance signal with a target frequency onto the DC signal under test. This high-frequency disturbance signal reduces the equivalent impedance of the gate oxide layer 220, amplifying its leakage current. The change in leakage current then allows for the determination of whether soft breakdown has occurred in the gate oxide layer 220.

[0056] In an exemplary embodiment, step S114 may specifically include the following steps:

[0057] S1141. Apply an initial gate control signal to the gate oxide layer of the transistor under test. The initial gate control signal includes the DC signal under test and an AC disturbance signal with an initial disturbance frequency.

[0058] S1142. Detect the leakage current of the gate oxide layer corresponding to the initial perturbation frequency;

[0059] S1143. If leakage current is detected, the initial disturbance frequency is determined as the target frequency of the AC disturbance signal.

[0060] S1144. If no leakage current is detected, increase the perturbation frequency value based on the initial perturbation frequency, and repeat the steps of applying the initial gate control signal and detecting leakage current until leakage current of the gate oxide layer is detected, and determine the current perturbation frequency as the target frequency of the AC perturbation signal.

[0061] For example, because the gate oxide layer has a relatively high impedance, an initial perturbation frequency can be determined first based on the characteristic frequency determined in the aforementioned steps. Then, an AC perturbation signal containing the initial perturbation frequency is superimposed onto the applied DC signal to be measured to detect whether the leakage current of the gate oxide layer can be detected. If the leakage current can be detected, it indicates that the initial AC perturbation signal with the initial perturbation frequency can amplify the equivalent leakage current of the gate oxide layer to a level that can be monitored. That is, the current initial perturbation frequency can be used as the target frequency of the AC perturbation signal. Conversely, if the gate oxide layer leakage current cannot be detected, it indicates that the initial AC perturbation signal with the initial perturbation frequency does not have sufficient amplification capability for the equivalent leakage current of the gate oxide layer. Since the equivalent impedance of the gate oxide layer decreases as the frequency of the AC perturbation signal increases, the perturbation frequency value can be further increased, and it can be detected whether a monitorable leakage current of the gate oxide layer can be obtained. This continues until the gate oxide layer leakage current can be monitored after superimposing the AC perturbation signal, indicating that the current AC perturbation signal has sufficient amplification capability for the equivalent leakage current of the gate oxide layer. In this case, the current perturbation frequency can be determined as the target frequency of the AC perturbation signal. As can be seen, this disclosure can determine the target frequency of the AC perturbation signal by continuously trying based on the characteristic frequency of the obtained gate oxide layer. For example, in an exemplary embodiment, it can be 10 5 *f1 is the target frequency of the AC disturbance signal, where f1 is the characteristic frequency of the gate oxide layer.

[0062] It should be understood that the superimposed AC disturbance signal in this disclosure cannot change the stress characteristics of the DC signal under test for the gate oxide layer. In an exemplary embodiment, after determining the target frequency of the AC disturbance signal, it is necessary to further verify the effectiveness of the AC disturbance signal to determine the target amplitude of the AC disturbance signal. The AC disturbance signal with the target amplitude does not change the stress characteristics of the DC signal under test, and can also improve the signal-to-noise ratio of the leakage current, thereby reducing noise interference.

[0063] In an exemplary embodiment, the effectiveness of the superimposed AC disturbance signal is verified, specifically, whether the AC disturbance signal satisfies the causality, stability, and linearity conditions. When the AC disturbance signal satisfies the causality, stability, and linearity conditions, it indicates that the superimposed AC disturbance signal is an effective signal and does not affect the stress characteristics of the DC signal under test.

[0064] Stability, in this context, refers to the ability of a system to return to its initial state after a certain period of time following the removal of an AC disturbance signal. Generally, the higher the impedance of a system, the better its stability. The gate oxide material of the transistor under test is typically SiO2. SiO2 gate oxide has very good stability, and correspondingly, the amplitude of the superimposed AC disturbance signal can be relatively large.

[0065] The so-called linear condition means that the response signal (the amplified equivalent leakage current) and the AC disturbance signal have the same angular frequency.

[0066] The following section further explains the process of validating the AC disturbance signal to determine the target amplitude of the AC disturbance signal.

[0067] In an exemplary embodiment, an initial AC disturbance signal can be determined first. The amplitude of the AC disturbance signal is gradually increased through multiple trials until the AC disturbance signal with the largest amplitude that meets the validity requirements is found. This is the target amplitude of the AC disturbance signal superimposed during the final TDDB test. The process of determining the target amplitude of the AC disturbance signal may include the following steps:

[0068] S115. Apply an initial gate control signal to the gate oxide layer of the transistor under test. The initial gate control signal includes the DC signal under test and an initial AC disturbance signal. The initial AC disturbance signal has an initial amplitude and a target frequency.

[0069] S116. Verify the effectiveness of the initial AC disturbance signal based on the response of the gate oxide layer to the initial gate control signal;

[0070] S117. If the initial AC disturbance signal is valid, the amplitude of the AC disturbance signal is increased based on the initial amplitude, and the steps of applying the initial gate control signal and verifying whether the initial AC disturbance signal is valid are repeated until it is determined that the AC disturbance signal is invalid. Then, the signal amplitude of the previous valid AC disturbance signal is determined as the target amplitude of the AC disturbance signal.

[0071] Because the SiO2 gate oxide layer has a high impedance and good stability, the initial amplitude of the initial AC perturbation signal can be set relatively large. For example, a nanoscale thin film Cr2O3 can be used as a reference, where the initial AC perturbation signal amplitude can be 50mV. Then, the effectiveness of the initial AC perturbation signal is determined by detecting the response of the gate oxide layer to the initial AC perturbation signal, that is, whether the initial AC perturbation signal satisfies the causality, stability, and linearity conditions.

[0072] If the initial AC disturbance signal is determined to be valid, its initial amplitude can be used as the target amplitude of the AC disturbance signal superimposed during the final TDDB test. Otherwise, if the initial AC disturbance signal is determined to be invalid, the amplitude of the AC disturbance signal can be increased based on the initial amplitude. This increased amplitude AC disturbance signal is then superimposed on the DC signal under test and applied to the gate oxide layer. The validity of the increased amplitude AC disturbance signal is verified by analyzing the response of the gate oxide layer to it. Through multiple attempts, the valid AC disturbance signal with the maximum signal amplitude can be determined, and this maximum amplitude can be used as the target amplitude of the AC disturbance signal superimposed during the TDDB test. It should be understood that validity verification is required after each adjustment of the AC disturbance signal amplitude until a valid maximum amplitude is found. This disclosure determines the maximum amplitude of the AC disturbance signal that can be applied through validity verification. By superimposing the AC disturbance signal with the maximum amplitude for TDDB testing, the signal-to-noise ratio of the gate oxide leakage current can be significantly improved, that is, the noise signal interference can be significantly reduced, which helps to distinguish the effective leakage current. Then, based on the change of leakage current, it can be determined whether the transistor under test has experienced soft breakdown, thereby improving the accuracy of the detection results.

[0073] In an exemplary embodiment, the effectiveness of detecting AC disturbance signals can be specifically achieved through the following methods:

[0074] Detect the leakage current of the gate oxide layer corresponding to the current AC disturbance signal;

[0075] The AC impedance of the gate oxide layer is determined based on the current AC perturbation signal and leakage current.

[0076] The real and imaginary parts of the AC impedance of the gate oxide layer are tested to see if they conform to the Kramers-Kronig relationship, in order to verify whether the current AC disturbance signal is valid.

[0077] For example, when verifying the validity of the initial AC disturbance signal, the leakage current of the gate oxide layer under the initial AC disturbance signal is first obtained. Then, the corresponding AC impedance of the gate oxide layer is calculated using the initial AC disturbance signal and the corresponding leakage current. Next, it is checked whether the real and imaginary parts of the obtained AC impedance conform to the Kramers-Kronig relationship. If they conform, the initial AC disturbance signal is valid; otherwise, if the real and imaginary parts of the AC impedance do not conform to the Kramers-Kronig relationship, the initial AC disturbance signal is invalid. The specific calculation method for the Kramers-Kronig relationship will not be detailed here.

[0078] In summary, in steps S111 to S117, the target frequency and target amplitude of the AC disturbance signal to be superimposed during TDDB testing can be determined. This allows the superimposed AC disturbance signal to be used to fully amplify the gate oxide current in subsequent steps, improve the signal-to-noise ratio of the gate oxide leakage current, reduce the interference of noise signals, and facilitate timely detection of the leakage current change characteristics of the gate oxide in the early stages of TDDB.

[0079] In step S120, the leakage current of the gate oxide layer is detected.

[0080] As mentioned above, by superimposing an AC disturbance signal with a target frequency, the equivalent leakage current of the gate oxide layer is sufficiently amplified, thereby enabling the detection of the gate oxide layer leakage current. Furthermore, because the AC disturbance signal has a target amplitude, it can reduce the interference of noise signals without affecting the stress characteristics of the DC signal under test. Therefore, this step can monitor the leakage current of the gate oxide layer.

[0081] In step S130, the gate oxide layer of the transistor under test is detected to determine whether soft breakdown has occurred based on the leakage current.

[0082] This disclosure, by sufficiently amplifying the equivalent leakage current of the gate oxide layer, allows for the detection of whether the transistor under test has experienced soft breakdown in the early stages of TDDB testing based on the characteristics of the leakage current change before the gate oxide layer is hard-broken.

[0083] For example, in devices where this phenomenon occurs, the gate oxide layer has been broken down, resulting in irreversible damage. This could be, for instance, based on... Figure 5 The leakage current variation characteristics shown are used to determine whether the transistor under test has experienced soft breakdown.

[0084] In an exemplary embodiment, whether the transistor under test has experienced soft breakdown can be determined based on the rate of change of the detected equivalent leakage current of the gate oxide layer. For example, Figure 5 The graph shows the TDDB test current of a transistor according to one embodiment of this disclosure over time. Figure 5 As shown, TDDB generally goes through three stages: 1) Defect formation stage. Over time, the number of charges trapped in the oxide layer increases, causing gate leakage current; 2) Breakdown formation stage. In this stage, the gate leakage current is relatively large, and localized defect clusters are formed inside the gate oxide layer, causing the device to enter a soft breakdown or quasi-breakdown state; 3) Sudden runaway stage, where the gate current of the device suddenly increases, and this process is very rapid. This can be determined based on... Figure 5The leakage current change curve shown determines the leakage current change rate threshold. When the detected leakage current change rate is greater than or equal to the predetermined leakage current change rate threshold, it can be determined that the transistor under test has experienced soft breakdown. In other embodiments, for example, the magnitude of the leakage current can also be used to determine whether the transistor under test has experienced soft breakdown.

[0085] In an exemplary embodiment, when it is determined that the transistor under test has experienced soft breakdown, the recorded duration is taken as the soft breakdown time of the gate oxide layer. It is also understood that when soft breakdown of the transistor under test is detected, the application of the gate control signal to the transistor under test should be stopped, i.e., power should be turned off, to prevent hard breakdown of the transistor under test.

[0086] This disclosed method, by superimposing an AC disturbance signal onto the DC signal under test and adjusting the frequency of the AC disturbance signal to a target frequency, can reduce the equivalent impedance of the gate oxide layer in the transistor under test, thereby amplifying the leakage current of the gate oxide layer. This allows for direct monitoring of the gate oxide layer leakage current value. Furthermore, the superimposed AC disturbance signal has a target amplitude, which, on the one hand, does not affect the stress characteristics of the DC signal under test on the transistor under test, i.e., it can characterize the early stage of the TDDB of the DC signal under test in situ; on the other hand, it can improve the signal-to-noise ratio of the leakage current and reduce noise interference. Therefore, based on the monitored changes in leakage current, it is possible to determine whether the applied DC signal under test has experienced soft breakdown, which helps to detect the risk of hard breakdown of the transistor in advance.

[0087] This disclosure also provides a transistor soft breakdown detection device. Figure 6 This is a structural block diagram of a transistor soft breakdown detection device according to one embodiment of the present disclosure, such as... Figure 6 As shown, the detection device 600 may include: a signal application module 610, a current detection module 620, and a detection module 630, wherein:

[0088] The signal application module 610 is used to continuously apply a gate control signal to the gate oxide layer of the transistor under test. The gate control signal includes a DC signal under test and an AC disturbance signal. The AC disturbance signal has a target frequency and a target amplitude.

[0089] Current detection module 620 is used to detect the leakage current of the gate oxide layer;

[0090] The detection module 630 is used to detect whether the gate oxide layer of the transistor under test has undergone soft breakdown based on the leakage current.

[0091] In an exemplary embodiment of this disclosure, the detection device 600 may further include:

[0092] An AC impedance spectroscopy acquisition module is used to acquire the AC impedance spectrum of the transistor under test.

[0093] The characteristic frequency determination module is used to determine the characteristic frequency of the gate oxide layer of the transistor under test based on the AC impedance spectrum.

[0094] In an exemplary embodiment of this disclosure, the detection device 600 may further include:

[0095] An equivalent circuit component module is used to construct an equivalent circuit model of the transistor under test. The equivalent circuit model includes a first RC parallel circuit, a second RC parallel circuit, and a third RC parallel circuit connected in series. The transistor under test includes a substrate, a gate oxide layer, and a gate metal layer stacked in series. The first RC parallel circuit is the equivalent circuit of the interface between the gate oxide layer and the gate metal layer. The second RC parallel circuit is the equivalent circuit of the gate oxide layer. The third RC parallel circuit is the equivalent circuit of the interface between the gate oxide layer and the substrate.

[0096] The target frequency determination module is used to determine the target frequency of the AC disturbance signal based on the impedance characteristics of the second RC parallel circuit and the characteristic frequency.

[0097] In an exemplary embodiment of this disclosure, the target frequency determination module may also be used to:

[0098] An initial gate control signal is applied to the gate oxide layer of the transistor under test. The initial gate control signal includes the DC signal under test and an AC disturbance signal with an initial disturbance frequency.

[0099] Detect the leakage current of the gate oxide layer corresponding to the initial perturbation frequency;

[0100] If the leakage current is detected, the initial disturbance frequency is determined as the target frequency of the AC disturbance signal;

[0101] If the leakage current is not detected, the perturbation frequency value is increased based on the initial perturbation frequency, and the steps of applying the initial gate control signal and detecting the leakage current are repeated until the leakage current of the gate oxide layer is detected, and the current perturbation frequency is determined as the target frequency of the AC perturbation signal.

[0102] In an exemplary embodiment of this disclosure, the detection device 600 may further include:

[0103] The target amplitude determination module is used to determine the target amplitude of the AC disturbance signal based on the target frequency.

[0104] In an exemplary embodiment of this disclosure, the target amplitude determination module may include:

[0105] An initial signal application unit is used to apply an initial gate control signal to the gate oxide layer of the transistor under test. The initial gate control signal includes a DC signal under test and an initial AC disturbance signal. The initial AC disturbance signal has an initial amplitude and a target frequency.

[0106] The verification unit is used to verify whether the initial AC disturbance signal is valid based on the response result of the gate oxide layer to the initial gate control signal;

[0107] The repeating unit is used to, if the initial AC disturbance signal is valid, increase the amplitude of the AC disturbance signal based on the initial amplitude, and repeat the steps of applying the initial gate control signal and verifying whether the initial AC disturbance signal is valid, until it is determined that the AC disturbance signal is invalid, and then determine the signal amplitude of the previous valid AC disturbance signal before the invalid AC disturbance signal as the target amplitude of the AC disturbance signal.

[0108] In exemplary embodiments of this disclosure, the verification unit may also be used for:

[0109] Detect the initial leakage current of the gate oxide layer corresponding to the initial gate control signal;

[0110] The initial AC impedance of the gate oxide layer is determined based on the gate control signal and the initial leakage current.

[0111] The validity of the initial AC disturbance signal is verified by detecting whether the real and imaginary parts of the initial AC impedance conform to the Kramers-Kronig relationship.

[0112] In an exemplary embodiment of this disclosure, the signal amplitude of the DC signal to be tested in the gate control signal is less than the intrinsic breakdown voltage of the transistor to be tested.

[0113] In an exemplary embodiment of this disclosure, the detection device 600 may further include:

[0114] The time recording module is used to record the duration of the applied gate control signal.

[0115] In an exemplary embodiment of this disclosure, the detection device 600 may further include:

[0116] A soft breakdown time determination module is used to determine the soft breakdown time of the gate oxide layer if soft breakdown is detected.

[0117] A shutdown module is used to stop applying the gate control signal to the transistor under test.

[0118] In an exemplary embodiment of this disclosure, the detection module 630 may also be used for:

[0119] Detect the rate of change of leakage current;

[0120] If the rate of change is greater than or equal to a preset rate of change threshold, then it is determined that the gate oxide layer of the transistor under test has undergone soft breakdown.

[0121] Figure 7 This is a schematic diagram of the structure of a detection device according to one embodiment of the present disclosure. It should be noted that... Figure 7 The detection device 700 shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein. Figure 7 As shown, the testing device 700 may include, but is not limited to, a PC or server running preset software.

[0122] like Figure 7 As shown, the detection device 700 includes a central processing unit (CPU) 701, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a storage section 708 into a random access memory (RAM) 703. The RAM 703 also stores various programs and data required for system operation. The CPU 701, ROM 702, and RAM 703 are interconnected via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0123] The following components are connected to the (I / O) interface 705: an input section 706 including a keyboard, mouse, etc.; an output section 707 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 708 including a hard disk, etc.; and a communication section 709 including a network interface card such as a LAN card, modem, etc. The communication section 709 performs communication processing via a network such as the Internet. A drive 710 is also connected to the (I / O) interface 705 as needed. A removable medium 711, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 710 as needed so that computer programs read from it can be installed into the storage section 708 as needed.

[0124] Specifically, according to embodiments of this disclosure, the above reference flow Figure 3The described process can be implemented as a computer software program. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable storage medium, the computer program containing program code for performing the methods shown in the flowchart. In such embodiments, the computer program can be downloaded and installed from a network via communication section 709, and / or installed from removable medium 711. When the computer program is executed by central processing unit (CPU) 701, it performs the various functions defined in the methods and apparatus of this disclosure.

[0125] It should be noted that the computer-readable storage medium disclosed herein may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable storage medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable storage medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, etc., or any suitable combination thereof.

[0126] In another aspect, this disclosure also provides a computer-readable storage medium, which may be included in the detection device 700 described in the above embodiments; or it may exist independently and not assembled into the detection device 700. The computer-readable storage medium carries one or more programs that, when executed by the detection device 700, cause the detection device 700 to implement the methods in the above embodiments. For example, the detection device 700 may implement... Figure 1The various steps shown are as follows.

[0127] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the generality of this disclosure and include, but are not disclosed herein, common knowledge or customary techniques in the art. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

Claims

1. A method for detecting soft breakdown of a transistor, characterized in that, include: A gate control signal is continuously applied to the gate oxide layer of the transistor under test. The gate control signal includes a DC signal under test and an AC disturbance signal. The AC disturbance signal has a target frequency and a target amplitude. Detect the leakage current of the gate oxide layer; The leakage current is used to detect whether the gate oxide layer of the transistor under test has undergone soft breakdown.

2. The method according to claim 1, characterized in that, Before continuously applying a gate control signal to the gate oxide layer of the transistor under test, the method further includes: Obtain the AC impedance spectrum of the transistor under test; The characteristic frequency of the gate oxide layer of the transistor under test is determined based on the AC impedance spectrum.

3. The method according to claim 2, characterized in that, After determining the characteristic frequency of the gate oxide layer of the transistor under test based on the AC impedance spectrum, the method further includes: An equivalent circuit model of the transistor under test is constructed. The equivalent circuit model includes a first RC parallel circuit, a second RC parallel circuit, and a third RC parallel circuit connected in series. The transistor under test includes a substrate, a gate oxide layer, and a gate metal layer stacked in series. The first RC parallel circuit is the equivalent circuit of the interface between the gate oxide layer and the gate metal layer. The second RC parallel circuit is the equivalent circuit of the gate oxide layer. The third RC parallel circuit is the equivalent circuit of the interface between the gate oxide layer and the substrate. The target frequency of the AC disturbance signal is determined based on the impedance characteristics of the second RC parallel circuit and the characteristic frequency.

4. The method according to claim 3, characterized in that, Determining the target frequency of the AC disturbance signal based on the impedance characteristics of the second RC parallel circuit and the characteristic frequency includes: An initial gate control signal is applied to the gate oxide layer of the transistor under test. The initial gate control signal includes the DC signal under test and an AC disturbance signal with an initial disturbance frequency. Detect the leakage current of the gate oxide layer corresponding to the initial perturbation frequency; If the leakage current is detected, the initial disturbance frequency is determined as the target frequency of the AC disturbance signal; If the leakage current is not detected, the perturbation frequency value is increased based on the initial perturbation frequency, and the steps of applying the initial gate control signal and detecting the leakage current are repeated until the leakage current of the gate oxide layer is detected, and the current perturbation frequency is determined as the target frequency of the AC perturbation signal.

5. The method according to claim 3, characterized in that, After determining the target frequency of the AC disturbance signal based on the impedance characteristics of the second RC parallel circuit and the characteristic frequency, the method further includes: The target amplitude of the AC disturbance signal is determined based on the target frequency.

6. The method according to claim 5, characterized in that, Determining the target amplitude of the AC disturbance signal based on the target frequency includes: An initial gate control signal is applied to the gate oxide layer of the transistor under test. The initial gate control signal includes a DC signal under test and an initial AC disturbance signal. The initial AC disturbance signal has an initial amplitude and a target frequency. The effectiveness of the initial AC disturbance signal is verified based on the response of the gate oxide layer to the initial gate control signal. If the initial AC disturbance signal is valid, the amplitude of the AC disturbance signal is increased based on the initial amplitude, and the steps of applying the initial gate control signal and verifying whether the initial AC disturbance signal is valid are repeated until it is determined that the AC disturbance signal is invalid. Then, the signal amplitude of the previous valid AC disturbance signal is determined as the target amplitude of the AC disturbance signal.

7. The method according to claim 6, characterized in that, The verification of the validity of the initial AC disturbance signal based on the response of the gate oxide layer to the initial gate control signal includes: Detect the initial leakage current of the gate oxide layer corresponding to the initial gate control signal; The initial AC impedance of the gate oxide layer is determined based on the gate control signal and the initial leakage current. The validity of the initial AC disturbance signal is verified by detecting whether the real and imaginary parts of the initial AC impedance conform to the Kramers-Kronig relationship.

8. The method according to claim 1, characterized in that, The amplitude of the DC signal to be tested in the gate control signal is less than the intrinsic breakdown voltage of the transistor to be tested.

9. The method according to claim 1, characterized in that, The method further includes: Record the duration of the applied gate control signal.

10. The method according to claim 9, characterized in that, After detecting whether the gate oxide layer of the transistor under test has undergone soft breakdown based on the leakage current, the method further includes: If soft breakdown of the gate oxide layer is detected, the recorded duration is taken as the soft breakdown time of the gate oxide layer. Stop applying the gate control signal to the transistor under test.

11. The method according to claim 1, characterized in that, The step of detecting whether the gate oxide layer of the transistor under test has undergone soft breakdown based on the leakage current includes: Detect the rate of change of leakage current; If the rate of change is greater than or equal to a preset rate of change threshold, then it is determined that the gate oxide layer of the transistor under test has undergone soft breakdown.

12. The method according to claim 1, characterized in that, The AC disturbance signal is a periodic clock signal or a periodic sine wave signal.

13. A transistor soft breakdown detection device, characterized in that, include: A signal application module is used to continuously apply a gate control signal to the gate oxide layer of the transistor under test. The gate control signal includes a DC signal under test and an AC disturbance signal. The AC disturbance signal has a target frequency and a target amplitude. A current detection module is used to detect the leakage current of the gate oxide layer; The detection module is used to detect whether the gate oxide layer of the transistor under test has undergone soft breakdown based on the leakage current.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the transistor soft breakdown detection method as described in any one of claims 1 to 12.

15. A testing device, characterized in that, include: One or more processors; A storage device for storing one or more programs, which, when executed by one or more processors, cause the one or more processors to implement the transistor soft breakdown detection method as described in any one of claims 1 to 12.

Images