Modeling Method, Device, Computer Equipment and Storage Medium

Abstract

The present invention relates to a modeling method, apparatus, computer device, and storage medium. The method includes: obtaining the electrical parameters of each sub-structure in a through-silicon via structure; obtaining an electrical topology network model according to the connection relationship of each of the through-silicon via structures between two dies; and obtaining a simulation model according to the electrical topology network model and the electrical parameters for simulation. The above-mentioned modeling method, apparatus, computer device, and storage medium can simulate a three-dimensional integrated circuit including a through-silicon via structure, so as to know the influence of the through-silicon via structure on the entire three-dimensional integrated circuit.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technologies, and in particular, to a modeling method, apparatus, computer device, and storage medium. Background Art

[0002] Currently, the through-silicon via (TSV) technology is a new technical solution for interconnecting stacked chips in three-dimensional integrated circuits. The TSV technology forms a through-silicon via structure between two adjacent semiconductor chips (also known as dies) to achieve electrical connection between the two adjacent dies.

[0003] For example, double data rate (DDR) products of dynamic random access memory (DRAM) use the through-silicon via (TSV) technology to stack two or more DDR chips. The through-silicon via structure formed between two adjacent DDR chips enables electrical connection between the adjacent DDR chips, forming a 3D stacked structure, thereby reducing the additional loss caused by packaging.

[0004] However, traditional technologies cannot simulate three-dimensional integrated circuits containing through-silicon via structures, and thus it is impossible to know the impact of through-silicon via structures on three-dimensional integrated circuits. Summary of the Invention

[0005] Based on this, it is necessary to provide a modeling method, apparatus, computer device, and storage medium for the problem that existing technologies cannot simulate three-dimensional integrated circuits containing through-silicon via structures, and thus it is impossible to know the impact of through-silicon via structures on three-dimensional integrated circuits.

[0006] To achieve the above object, on the one hand, the present invention provides a modeling method, including:

[0007] Obtaining the electrical parameters of each sub-structure in the through-silicon via structure;

[0008] Obtaining an electrical topology network model according to the connection relationship of each of the through-silicon via structures between two dies;

[0009] Obtaining a simulation model according to the electrical topology network model and the electrical parameters for simulation.

[0010] In one embodiment, the two dies are a first die and a second die respectively, and each of the sub-structures includes a bump pad sub-structure and a through-silicon via sub-structure. One end of the bump pad sub-structure is electrically connected to the second die, and the other end of the bump pad sub-structure is electrically connected to one end of the through-silicon via sub-structure. A through hole is formed on the first die for the through-silicon via sub-structure to pass through so as to electrically connect the other end of the through-silicon via sub-structure to the first die. The electrical parameters include the electrical parameters of the bump pad sub-structure and the electrical parameters of the through-silicon via sub-structure.

[0011] In one embodiment, obtaining the electrical parameters of each sub-structure in the through-silicon via structure includes:

[0012] Obtaining a schematic diagram of the structure of the through-silicon via structure;

[0013] Obtaining a material composition cross-sectional view of each sub-structure in the through-silicon via structure according to the schematic diagram of the structure of the through-silicon via structure; the material composition cross-sectional view of the sub-structure includes the material information and size information of the sub-structure;

[0014] Obtaining the electrical parameters according to the material information and size information of each sub-structure.

[0015] In one embodiment, the electrical parameters include resistance parameters, capacitance parameters and inductance parameters.

[0016] In one embodiment, when the number of through-silicon via structures between the two dies is multiple, each of the through-silicon via structures is the same, and the electrical topology network model includes multiple sub-network models, and the number of sub-network models is equal to the number of through-silicon via structures;

[0017] Each sub-network model includes a bump pad resistance, a through-silicon via resistance, a bump pad capacitance, a through-silicon via capacitance, a bump pad inductance and a through-silicon via inductance. The bump pad resistance, the bump pad inductance, the through-silicon via inductance and the through-silicon via resistance are connected in series between the second die and the first die in sequence. One end of the bump pad capacitance is connected between the second die and the bump pad resistance, and the other end of the bump pad capacitance is connected to a preset remote end. One end of the through-silicon via capacitance is connected between the bump pad inductance and the through-silicon via inductance, and the other end of the through-silicon via capacitance is connected to the through-silicon via capacitance in another sub-network model.

[0018] In one embodiment, obtaining a simulation model according to the electrical topology network model and the electrical parameters for simulation includes:

[0019] Obtaining a simulation model file according to the sub-network model and the electrical parameters;

[0020] Configure the through - silicon via structure symbols between the circuit model of the first die and the circuit model of the second die according to the number of the through - silicon via structures between the two dies, so as to obtain a first circuit model;

[0021] Obtain the simulation model according to the first circuit model and the simulation model file for simulation.

[0022] In one embodiment, when the number of the dies is greater than two, the step of obtaining the simulation model according to the electrical topology network model and the electrical parameters for simulation includes:

[0023] Obtain a simulation model file according to the sub - network model and the electrical parameters;

[0024] Configure the through - silicon via structure symbols between all adjacent two dies respectively according to the number of the through - silicon via structures between adjacent two dies, so as to obtain a second circuit model; and

[0025] Obtain the simulation model according to the second circuit model and the simulation model file for simulation.

[0026] In one embodiment, the bump sub - structure includes a first copper layer, a second copper layer, a first nickel layer, a tin - silver alloy layer and a second nickel layer stacked in sequence; the through - silicon via sub - structure includes a third copper layer;

[0027] In the step of obtaining the electrical parameters according to the material information and the size information of each sub - structure, obtain the electrical parameters of the bump sub - structure according to the material information and the size information of the first copper layer, the second copper layer, the first nickel layer, the tin - silver alloy layer and the second nickel layer, and obtain the electrical parameters of the through - silicon via sub - structure according to the material information and the size information of the third copper layer.

[0028] In one embodiment, it further includes:

[0029] Obtain the optimized structure of the through - silicon via structure according to the simulation result.

[0030] In one embodiment, the step of obtaining the optimized structure of the through - silicon via structure according to the simulation result includes at least one of optimizing the height and / or width of the bump sub - structure, optimizing the width and / or height of the through - silicon via sub - structure, optimizing the material composition and ratio in the bump sub - structure, and optimizing the spacing between each of the through - silicon via structures between the two dies.

[0031] In one embodiment, the first die includes a substrate layer and a plurality of metal layers, the plurality of metal layers are sequentially stacked under the substrate layer, through holes are formed in the substrate layer for the silicon via sub-structure to pass through, and the silicon via sub-structure is electrically connected to one of the metal layers; the optimized structure of the silicon via structure obtained according to the simulation results includes: re-determining the metal layer electrically connected to the silicon via sub-structure.

[0032] A modeling device includes:

[0033] An acquisition module for acquiring the electrical parameters of each sub-structure in the silicon via structure;

[0034] An electrical topology network model processing module for obtaining an electrical topology network model according to the connection relationship of each silicon via structure between two dies;

[0035] A simulation model processing module for obtaining a simulation model according to the electrical topology network model and the electrical parameters for simulation.

[0036] In one embodiment, the two dies are a first die and a second die respectively, each sub-structure includes a bump pad sub-structure and a silicon via sub-structure, one end of the bump pad sub-structure is electrically connected to the second die, the other end of the bump pad sub-structure is electrically connected to one end of the silicon via sub-structure, through holes are formed in the first die for the silicon via sub-structure to pass through to electrically connect the other end of the silicon via sub-structure to the first die, and the electrical parameters include the electrical parameters of the bump pad sub-structure and the electrical parameters of the silicon via sub-structure.

[0037] A computer device includes a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, the steps of the method described in any one of the above are implemented.

[0038] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method described in any one of the above are implemented.

[0039] The above modeling method, device, computer device and storage medium obtain the electrical parameters of each sub-structure in the silicon via structure and the total electrical topology network model of each silicon via structure between two dies, and obtain a simulation model of a three-dimensional integrated circuit according to the electrical topology network model and the electrical parameters, so that it is possible to simulate a three-dimensional integrated circuit including a silicon via structure, thereby knowing the influence of the silicon via structure on the entire three-dimensional integrated circuit. Description of the Drawings

[0040] To more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0041] Figure 1 Flowchart of the modeling method provided in an embodiment of the present application;

[0042] Figure 2 Schematic diagram of the internal structure of a three-dimensional integrated circuit provided in an embodiment of the present application;

[0043] Figure 3 Flowchart of the modeling method provided in a specific embodiment of the present application;

[0044] Figure 4 Cross-sectional view of the bump pad sub-structure provided in an embodiment of the present application;

[0045] Figure 5 Cross-sectional view of the through-silicon via sub-structure provided in an embodiment of the present application;

[0046] Figure 6 Schematic diagram of the electrical topology network model provided in an embodiment of the present application;

[0047] Figure 7 Schematic diagram of the first circuit model provided in an embodiment of the present application;

[0048] Figure 8 Specific step flowchart of step S130 provided in another embodiment of the present application;

[0049] Figure 9 Schematic diagram of the second circuit model provided in an embodiment of the present application;

[0050] Figure 10 Block diagram of the modeling apparatus provided in an embodiment of the present application.

[0051] Explanation of reference numerals:

[0052] 10. Through-Silicon Via (TSV) structure; 11. Bump pad sub-structure; 111. First metal layer; 1111. First copper layer; 1112. Second copper layer; 112. Second metal layer; 113. Solder ball; 114. Third metal layer; 12. TSV sub-structure; 121. Fourth metal layer; 13. TSV structure symbol; 20. Second die; 21. Second substrate layer; 22. Fifth metal layer; 23. Sixth metal layer; 24. Seventh metal layer; 25. Eighth metal layer; 26. Circuit model of the second die; 30. First die; 31. Substrate layer; 32. Ninth metal layer; 33. Tenth metal layer; 34. Eleventh metal layer; 35. Twelfth metal layer; 36. Circuit model of the first die; 40. Bottom bump pad structure; 41. Thirteenth metal layer; 42. Fourteenth metal layer; 50. Circuit model of the Xth die; 27. First insulating layer; 28. First silicon oxide substrate; 37. Second silicon oxide substrate; 38. Second insulating layer. Detailed implementation manners

[0053] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0055] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be referred to as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0056] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.

[0057] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprises" and / or "comprising" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be determined, but one or more other features, integers, steps, operations, elements, components and / or groups are not excluded from the presence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0058] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention, such that variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the invention should not be limited to the specific shapes of regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between that buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0059] Please refer to Figure 1 , the present invention provides a modeling method, comprising the following steps:

[0060] Step S110, obtaining the electrical parameters of each sub-structure in the through-silicon via structure.

[0061] Step S120, obtaining an electrical topology network model according to the connection relationship of each through-silicon via structure between two dies.

[0062] Step S130, obtaining a simulation model according to the electrical topology network model and the electrical parameters for simulation.

[0063] In the modeling method in the above embodiment, by obtaining the electrical parameters of each sub-structure in the through-silicon via structure and the overall electrical topology network model of each through-silicon via structure between two dies, and obtaining a simulation model of the three-dimensional integrated circuit according to the electrical topology network model and the electrical parameters, it is possible to simulate the three-dimensional integrated circuit including the through-silicon via structure, so as to know the influence of the through-silicon via structure on the entire three-dimensional integrated circuit.

[0064] In step S110, please refer to Figure 1 step S110 in

[0065] In some examples, please refer to Figure 2 , the three-dimensional integrated circuit may include two or more than two dies. Each die may be the same type of chip or different types of chips. For example, the die may be a DRAM chip, and further, it may be a DDR chip. Among them, the two dies are respectively referred to as the first die 30 and the second die 20.

[0066] Each sub-structure may include a bump pad sub-structure 11 and a silicon via sub-structure 12. One end of the bump pad sub-structure 11 is electrically connected to the second die 20. The other end of the bump pad sub-structure 11 is electrically connected to one end of the silicon via sub-structure 12. A through hole is formed in the first die 30 for the silicon via sub-structure 12 to pass through so as to electrically connect the other end of the silicon via sub-structure 12 to the first die 30. The electrical parameters include the electrical parameters of the bump pad sub-structure 11 and the electrical parameters of the silicon via sub-structure 12.

[0067] In some examples, referring to Figure 2 , the silicon via structure 10 may include a first metal layer 111, a second metal layer 112, a solder ball 113, a third metal layer 114, and a fourth metal layer 121 stacked in sequence. The bump pad sub-structure 11 may be configured to include the first metal layer 111 to the third metal layer 114, and the silicon via sub-structure 12 may include the fourth metal layer 121.

[0068] In other examples, each layer in the silicon via structure 10 may also be divided into other sub-structures different from the bump pad sub-structure 11 and the silicon via sub-structure 12 according to actual requirements.

[0069] In some examples, referring to Figure 2 , the second die 20 may include a second substrate layer 21 and a plurality of metal layers stacked in sequence. The first metal layer 111 of the silicon via structure 10 may be electrically connected to any one of the metal layers in the second die 20. For example, the second die 20 may include a fifth metal layer 22, a sixth metal layer 23, a seventh metal layer 24, and an eighth metal layer 25 stacked below the second substrate layer 21 in sequence. The first metal layer 111 may be in electrical contact with the eighth metal layer 25, such that one end of the bump pad sub-structure 11 is in electrical contact with the second die 20. Since the third metal layer 114 is in contact with the fourth metal layer 121, the other end of the bump pad sub-structure 11 is in electrical contact with one end of the silicon via sub-structure 12.

[0070] In some examples, referring to Figure 2 , the first die 30 may include a substrate layer 31 and a plurality of metal layers, and the plurality of metal layers are stacked below the substrate layer 31 in sequence. A through hole is formed in the substrate layer 31 for the silicon via sub-structure 12 to pass through, and the fourth metal layer 121 of the silicon via structure 10 may be electrically connected to any one of the metal layers in the first die 30. For example, the first die 30 may include a ninth metal layer 32, a tenth metal layer 33, an eleventh metal layer 34, and a twelfth metal layer 35 stacked below the substrate layer 31 in sequence. The fourth metal layer 121 may be in electrical contact with the tenth metal layer 33, such that the other end of the silicon via sub-structure 12 is in electrical contact with the first die 30.

[0071] In some examples, referring to Figure 3, step S110 specifically includes steps S111 to S113.

[0072] Step S111, obtain a structural schematic diagram of the through-silicon via structure.

[0073] Specifically, an operator can use input devices such as a mouse, keyboard, and touch screen to construct a structural schematic diagram of the through-silicon via structure 10 between die-to-die, so as to obtain the structural schematic diagram of the through-silicon via structure 10. This structural schematic diagram can be a three-dimensional schematic diagram or a planar schematic diagram. The number of through-silicon via structures 10 between die-to-die can be one or multiple. When the number of through-silicon via structures 10 between die-to-die is multiple, each through-silicon via structure 10 can be the same or different. Hereinafter, the case where each through-silicon via structure 10 is the same will be taken as an example for description.

[0074] Step S112, obtain a material composition cross-section diagram of each sub-structure in the through-silicon via structure according to the structural schematic diagram of the through-silicon via structure; the material composition cross-section diagram of the sub-structure includes the material information and size information of the sub-structure.

[0075] Specifically, a material composition cross-section diagram of each sub-structure in the through-silicon via structure 10 can be constructed according to the structural schematic diagram of the through-silicon via structure 10. In this embodiment, the through-silicon via structure 10 may include a bump pad sub-structure 11 and a through-silicon via sub-structure 12. Please refer to Figure 4 and Figure 5 , and respectively obtain a material composition cross-section diagram of the bump pad sub-structure 11 and a material composition cross-section diagram of the through-silicon via sub-structure 12 according to the structural schematic diagram of the through-silicon via structure 10. The material composition cross-section diagram of the bump pad sub-structure 11 includes the material information and size information of the bump pad sub-structure 11, and the material composition cross-section diagram of the through-silicon via sub-structure 12 includes the material information and size information of the through-silicon via sub-structure 12.

[0076] In some examples, please refer to Figure 2 and Figure 4 , in the material composition cross-section diagram of the bump pad sub-structure 11, the bump pad sub-structure 11 includes a first metal layer 111, a second metal layer 112, a solder ball 113, and a third metal layer 114 stacked in sequence ( Figure 4(not shown). The first metal layer 111 may include a first copper layer 1111 and a second copper layer 1112. In a three-dimensional integrated circuit, a first insulating layer 27 may also be provided at the bottom periphery of the first copper layer 1111. The first insulating layer 27 may include a first silicon nitride layer, which functions as an isolation insulator. The second die 20 may also include a first silicon oxide substrate 28, and the first silicon oxide substrate 28 may be located above the first insulating layer 27 and cover the eighth metal layer 25. The second metal layer 112 may include a first nickel layer. The solder ball 113 may include a tin-silver alloy layer. The third metal layer 114 may include a second nickel layer. That is, the bump pad sub-structure 11 may include a first copper layer 1111, a second copper layer 1112, a first nickel layer, a tin-silver alloy layer, and a second nickel layer stacked in sequence. The material composition cross-section of the bump pad sub-structure 11 also includes the dimensional information of each layer, Figure 4 The dimensional information is not shown in the figure.

[0077] Please refer to Figure 2 and 5 , in the material composition cross-section of the silicon through-hole sub-structure 12, the silicon through-hole sub-structure 12 includes a fourth metal layer 121, and the fourth metal layer 121 may include a third copper layer. In a three-dimensional integrated circuit, a second insulating layer 38 may also be provided at the bottom periphery of the fourth metal layer 121. The second insulating layer 38 includes a second silicon nitride layer, which functions as an isolation insulator. The first die 30 may also include a second silicon oxide substrate 37, and the second silicon oxide substrate 37 may be located above the second insulating layer 38 and cover a part of the side surface of the fourth metal layer 121. The material composition cross-section of the silicon through-hole sub-structure 12 also includes the dimensional information of each layer, Figure 5 The dimensional information is not shown in the figure.

[0078] Step S113: Obtain electrical parameters according to the material information and dimensional information of each sub-structure.

[0079] Specifically, the electrical parameters of each layer may be obtained first according to the material information and dimensional information of each layer of each sub-structure in the silicon through-hole structure 10, and then the electrical parameters of the sub-structure may be calculated according to the electrical parameters of each layer in the sub-structure. In this embodiment, the electrical parameters of the bump pad sub-structure 11 are obtained according to the material information and dimensional information of the first copper layer 1111, the second copper layer 1112, the first nickel layer, the tin-silver alloy layer, and the second nickel layer. In this embodiment, the electrical parameters of the third copper layer, that is, the electrical parameters of the silicon through-hole sub-structure 12, may also be obtained according to the material information and dimensional information of the third copper layer.

[0080] In some examples, the electrical parameters include resistance parameters, capacitance parameters, and inductance parameters. For example, the resistance parameters and capacitance parameters of the bump pad sub-structure 11 can be obtained based on the material information and layer size information of the first copper layer 1111, the second copper layer 1112, the first nickel layer, the tin-silver alloy layer, and the second nickel layer. The resistance parameters and capacitance parameters of the silicon via sub-structure 12 can be obtained based on the material information and size information of the third copper layer. Specifically, the width of the first copper layer 1111 is 8 - 12 μm, and the height is 2 - 6 μm. The width of the second copper layer 1112 is 20 - 40 μm, and the height is 2 - 6 μm. The width of the first nickel layer is 20 - 40 μm, and the height is 1 - 4 μm. The width of the tin-silver alloy layer is 20 - 40 μm, and the height is 4 - 9 μm. The width of the second nickel layer is 20 - 40 μm, and the height is 3 - 8 μm. The width of the third copper layer is 4 - 8 μm, and the height is 40 - 70 μm.

[0081] In some examples, when calculating the electrical parameters of the bump pad sub-structure 11 and the silicon via sub-structure 12, the following formulas can be used for calculation. Among them, Equation (1) is the formula for calculating the resistance parameter, Equation (2) is the formula for calculating the inductance parameter, and Equation (3) is the formula for calculating the capacitance parameter. The parameters in Equations (1) to (3) can all be calculated based on the material information and layer size information of each layer in the bump pad sub-structure 11 and the silicon via sub-structure 12. The resistance parameters, inductance parameters, and capacitance parameters of each layer in each sub-structure can be calculated separately using Equations (1) to (3), and then the resistance parameters, inductance parameters, and capacitance parameters of each sub-structure can be calculated based on the electrical parameters of each layer in the sub-structure.

[0082] R = ρL / S (1)

[0083] Where ρ is the resistivity of the resistance, L represents the length of the resistance, and S represents the cross-sectional area of the resistance.

[0084] L = μ0N 2 S / L (2)

[0085] Where μ0 is the magnetic permeability of the solenoid, N is the total number of turns of the solenoid, S is the cross-sectional area of the solenoid, and L is the length of the solenoid.

[0086] C = εA / d (3)

[0087] Where ε is the dielectric constant of the capacitor, A is the area facing each other between the two plates of the capacitor, and d is the distance between the two plates of the capacitor.

[0088] In step S120, please refer to Figure 1 step S120 in, and obtain the electrical topology network model according to the connection relationship of each silicon via structure between the two dies.

[0089] Specifically, the number of the through-silicon via structures 10 between two dies can be one or multiple. When the number of the through-silicon via structures 10 between two dies is multiple, the through-silicon via structures 10 can be the same or different, and the connection manners of the same through-silicon via structures 10 with the two dies can also be the same. For example, the number of the through-silicon via structures 10 between two dies is 2, and both of the two through-silicon via structures 10 include a bump pad sub-structure 11 and a through-silicon via sub-structure 12, and it is the bump pad sub-structure 11 that is in electrical contact connection with the second die 20 and the through-silicon via sub-structure 12 that is in electrical contact connection with the first die 30. The electrical topology network model is the total equivalent circuit model of the through-silicon via structures 10 between two dies.

[0090] In some examples, please refer to Figure 6 , when the number of the through-silicon via structures 10 between two dies is multiple, the through-silicon via structures 10 are the same. The electrical topology network model includes multiple sub-network models, and the number of the sub-network models is equal to the number of the through-silicon via structures 10. Each sub-network model includes a bump pad resistance R_bp, a through-silicon via resistance R_tsv, a bump pad capacitance C_bp, a through-silicon via capacitance C_tsv, a bump pad inductance L_bp, and a through-silicon via inductance L_tsv. The bump pad resistance R_bp, the bump pad inductance L_bp, the through-silicon via inductance L_tsv, and the through-silicon via resistance R_tsv are connected in series between the second die 20 and the first die 30 in sequence. One end of the bump pad capacitance C_bp is connected between the second die 20 and the bump pad resistance R_bp, and the other end of the bump pad capacitance C_bp is connected to a preset far end. The preset far end can be at infinity. One end of the through-silicon via capacitance C_tsv is connected between the bump pad inductance L_bp and the through-silicon via inductance L_tsv, and the other end of the through-silicon via capacitance C_tsv is connected to the through-silicon via capacitance C_tsv in another sub-network model.

[0091] In this embodiment, by setting the equivalent electrical components of each sub-structure, accurate simulation results can be obtained without laying out the layout.

[0092] In some examples, the through-silicon via capacitors C_tsv of two through-silicon via structures 10 are connected through a substrate resistance Rsub and a substrate capacitance Csub. The substrate resistance Rsub can be the equivalent resistance of the substrate layer 31, and the substrate capacitance Csub can be the equivalent capacitance of the substrate layer 31. The two ends after the parallel connection of the substrate resistance Rsub and the substrate capacitance Csub are respectively connected to the through-silicon via capacitors C_tsv of the two through-silicon via structures 10. The inventors creatively found that the substrate resistance Rsub is approximately infinite compared with the bump pad resistance R_bp and the through-silicon via resistance R_tsv, and the substrate capacitance Csub is approximately infinite compared with the bump pad capacitance C_bp and the through-silicon via capacitance C_tsv. Therefore, the substrate resistance Rsub and the substrate capacitance Csub are ignored in the electrical topology network model, thereby simplifying the electrical topology network model.

[0093] In step S130, refer to Figure 1 step S130 in, and obtain a simulation model according to the electrical topology network model and electrical parameters for simulation.

[0094] Specifically, the electrical parameters include the parameter values of each equivalent electronic component in the electrical topology network model. The electrical topology network model is the total equivalent circuit model of each through-silicon via structure 10 between two dies. The simulation model is the simulation model of the three-dimensional integrated circuit. According to the electrical topology network model and the electrical parameters, the simulation model of the three-dimensional integrated circuit can be obtained for simulation, so that the influence of the through-silicon via structure on the three-dimensional integrated circuit can be obtained.

[0095] In some examples, refer to Figure 3 , step S130 specifically includes steps S131 to S133.

[0096] Step S131, obtain a simulation model file according to the sub-network model and electrical parameters.

[0097] Specifically, in this embodiment, it is described by taking the case where each through - silicon via structure 10 is the same, that is, each sub - network model in the electrical topology network model is the same. In other examples, if the sub - network models are different, the corresponding simulation model file can be obtained according to the sub - network model and the corresponding electrical parameters. The simulation model file can define the parameter identifiers and parameter values of each equivalent electronic component between the connection points (i.e., the top) of the electrical network topology model and the second die 20 and the connection points (i.e., the bottom) of the electrical network topology model and the first die 30 according to a predefined format. For example, the simulation model file can include the parameter identifier C_bp of the bump pad capacitor and its parameter value a, the parameter identifier R_bp of the bump pad resistor and its parameter value b, the parameter identifier L_bp of the bump pad inductor and its parameter value c, the parameter identifier C_tsv of the through - silicon via capacitor and its parameter value d, the parameter identifier L_tsv of the through - silicon via inductor and its parameter value e, and the parameter identifier R_tsv of the through - silicon via resistor and its parameter value f. The simulation model file can also calculate the resistance value tsv_r, inductance value tsv_l, capacitance value tsv_c, etc. of the through - silicon via structure according to these parameter identifiers and parameter values.

[0098] Step S132: Configure the through - silicon via structure symbols between the circuit model of the first die and the circuit model of the second die according to the number of through - silicon via structures between the two dies, so as to obtain the first circuit model.

[0099] Specifically, please refer to Figure 7 , the first circuit model is the equivalent circuit model of the three - dimensional integrated circuit. Configure the through - silicon via structure symbols 13 between the circuit model 36 of the first die 30 and the circuit model 26 of the second die 20 according to the number of through - silicon via structures 10 between the first die 30 and the second die 20, so as to obtain the first circuit model. Figure 7 In the embodiment, the number of through - silicon via structures 10 between the first die 30 and the second die 20 is 6. In this embodiment, the first die 30 can also be called the master die, and the second die 20 can also be called the slave die.

[0100] Step S133: Obtain a simulation model according to the first circuit model and the simulation model file for simulation.

[0101] Specifically, the through - silicon via structure 10 symbols in the first circuit model can be associated with the simulation model file, so that the first circuit model after the association operation is used for simulation, and thus the influence of the through - silicon via structure 10 on the three - dimensional integrated circuit can be obtained.

[0102] In this embodiment, the first circuit model includes the circuit model 36 of the first die, the circuit model 26 of the second die, and the through-silicon via structure symbol 13 configured between these two circuit models. Using the first circuit model and the simulation model file to obtain a simulation model for simulation is a simulation of the entire three-dimensional integrated circuit, which can better reflect the impact of the through-silicon via structure 10 on the entire three-dimensional integrated circuit compared to the simulation only for the first die 30 or the second die 20.

[0103] In some other examples, please refer to Figure 8 , step S130 specifically includes steps S134 to S136.

[0104] Step S134, obtaining a simulation model file according to the sub-network model and electrical parameters.

[0105] Specifically, the specific execution process of step S134 can be the same as that of step S131.

[0106] Step S135, respectively configuring through-silicon via structure symbols between all adjacent dies according to the number of through-silicon via structures 10 between adjacent dies to obtain a second circuit model.

[0107] In this embodiment, the number of dies is greater than two. The three-dimensional integrated circuit may include a first die 30, a second die 20... an Xth die, where X is an integer greater than 2. In this embodiment, the first die 30 may also be called the main die, and the second die 20 to the Xth die may all be called slave dies. The number of through-silicon vias between adjacent dies may be the same or different. Please refer to Figure 9 , the circuit model 36 of the first die to the circuit model 50 of the Xth die can be constructed, and through-silicon via structure symbols 13 are set between the circuit models of all adjacent dies according to the number of through-silicon via structures 10, so as to obtain a second circuit model. The second circuit model is an equivalent circuit model of the three-dimensional integrated circuit. Figure 9 In the embodiment, the number of through-silicon via structures 10 between all adjacent dies is 6.

[0108] In some examples, in the first circuit model and the second circuit model, the circuit model 36 of the first die to the circuit model 50 of the Xth die can be respectively replaced by corresponding symbols, and each symbol is associated with the information of the corresponding die.

[0109] Step S136, obtaining a simulation model according to the second circuit model and the simulation model file for simulation.

[0110] Specifically, each through-silicon via structure symbol 13 in the second circuit model can be associated with the simulation model file, so that simulation is performed using the second circuit model after the association operation, and thus the impact of the through-silicon via structure 10 on the three-dimensional integrated circuit can be obtained.

[0111] In some examples, refer to Figure 3 , the modeling method further includes step S140.

[0112] Step S140: Obtain an optimized structure of the through-silicon via structure according to the simulation result.

[0113] Specifically, the simulation result may include current parameters, voltage parameters, etc. of each die in the three-dimensional integrated circuit. For example, when the voltage value of the die is small, it can be understood that the resistance value of the through-silicon via structure 10 is large, and thus the factors affecting the resistance parameters of the through-silicon via structure 10 can be adjusted. In this way, the through-silicon via structure 10 can be optimized according to the simulation result to avoid negative impacts of the through-silicon via structure 10 on the functions of the three-dimensional integrated circuit.

[0114] In some examples, step S140 includes at least one of optimizing the height and / or width of the bump pad sub-structure 11, optimizing the width and / or height of the through-silicon via sub-structure 12, optimizing the material composition and ratio in the bump pad sub-structure 11, and optimizing the spacing between the through-silicon via structures 10 between two dies.

[0115] In some examples, refer to Figure 2 , when optimizing the height of the bump pad sub-structure 11, specifically, the height of any one or more of the first metal layer 111, the second metal layer 112, the solder ball 113, and the third metal layer 114 in the bump pad sub-structure 11 can be changed. When optimizing the width of the bump pad sub-structure 11, specifically, the width of any one or more of the first metal layer 111, the second metal layer 112, the solder ball 113, and the third metal layer 114 in the bump pad sub-structure 11 can be changed. When optimizing the width of the through-silicon via sub-structure 12, the width of the fourth metal layer 121 can be changed. When optimizing the height of the through-silicon via sub-structure 12, the height of the fourth metal layer 121 can be changed. When optimizing the material composition and ratio in the bump pad sub-structure 11, the material and ratio of any one or more of the first metal layer 111, the second metal layer 112, the solder ball 113, and the third metal layer 114 can be changed. When optimizing the spacing between the through-silicon via structures 10 between two dies, only the spacing between some of the through-silicon via structures 10 can be changed; or the spacing between all the through-silicon via structures 10 can be changed simultaneously so that the spacing between the through-silicon via structures 10 is equal, thus facilitating the simplification of the manufacturing process of the through-silicon via structure 10.

[0116] In some other examples, step S140 may include re-determining the metal layer electrically connected to the through-silicon via sub-structure 12.

[0117] Specifically, refer to Figure 2, the first die 30 includes a substrate layer 31 and a plurality of metal layers, the plurality of metal layers are sequentially stacked below the substrate layer 31, a through hole is formed in the substrate layer 31 for the silicon through hole sub-structure 12 to pass through, and the silicon through hole sub-structure 12 is electrically connected to one of the metal layers. Figure 2 In the example, the silicon through hole sub-structure 12 is in contact electrical connection with the tenth metal layer 33. In other examples, according to the simulation structure, the metal layer in contact electrical connection with the silicon through hole sub-structure 12 can be the ninth metal layer 32, the eleventh metal layer 34 or the twelfth metal layer 35. In this embodiment, re-determining the metal layer in contact connection with the silicon through hole sub-structure 12 according to the simulation result is beneficial to minimizing the parasitic effect and is most beneficial to the layout of the three-dimensional integrated circuit, and changing the metal layer in contact connection with the silicon through hole sub-structure 12 can also change the layout of the metal layer.

[0118] In some examples, please refer to Figure 2 , the three-dimensional integrated circuit can also be provided with a bottom bump pad structure 40 at the bottom of the first die 30. The bottom bump pad structure 40 can include a thirteenth metal layer 41 and a fourteenth metal layer 42. When establishing the simulation model in the above embodiment, the model of the bottom bump pad structure 40 can also be considered, so as to obtain the influence of the bump pad structure 40 on the three-dimensional integrated circuit. The specific method of establishing the model of the bump pad structure 40 can be similar to the modeling method of the silicon through hole structure 40, which will not be elaborated here.

[0119] It should be understood that although Figure 1 , 3 and the steps in the flowcharts of 8 are sequentially shown according to the indication of the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, Figure 1 , 3 and at least a part of the steps in 8 can include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of the steps or stages in other steps or other steps.

[0120] Please refer to Figure 10, this application also provides a modeling device 60. The modeling device 60 includes: an acquisition module 61, an electrical topology network model processing module 62, and a simulation model processing module 63. The acquisition module 61 is used to acquire the electrical parameters of each sub-structure in the through-silicon via structure; the electrical topology network model processing module 62 is used to obtain an electrical topology network model according to the connection relationship of each through-silicon via structure between two bare dies; the simulation model processing module 63 is used to obtain a simulation model according to the electrical topology network model and the electrical parameters for simulation.

[0121] In some examples, the two bare dies are a first bare die and a second bare die respectively. Each sub-structure includes a bump pad sub-structure and a through-silicon via sub-structure. One end of the bump pad sub-structure is electrically connected to the second bare die, and the other end of the bump pad sub-structure is electrically connected to one end of the through-silicon via sub-structure. A through hole is formed on the first bare die for the through-silicon via sub-structure to pass through to electrically connect the other end of the through-silicon via sub-structure to the first bare die. The electrical parameters include the electrical parameters of the bump pad sub-structure and the electrical parameters of the through-silicon via sub-structure.

[0122] In some examples, the acquisition module 61 includes: a structure schematic diagram acquisition unit, a cross-sectional view acquisition unit, and an electrical parameter acquisition unit. The structure schematic diagram acquisition unit is used to acquire the structure schematic diagram of the through-silicon via structure; the cross-sectional view acquisition unit is used to obtain the material composition cross-sectional view of each sub-structure in the through-silicon via structure according to the structure schematic diagram of the through-silicon via structure; the material composition cross-sectional view of the sub-structure includes the material information and size information of the sub-structure; the electrical parameter acquisition unit is used to obtain the electrical parameters according to the material information and size information of each sub-structure.

[0123] In some examples, the electrical parameters include resistance parameters, capacitance parameters, and inductance parameters.

[0124] In some examples, when the number of through-silicon via structures between two bare dies is multiple, each through-silicon via structure is the same. The electrical topology network model includes multiple sub-network models, and the number of sub-network models is equal to the number of through-silicon via structures; each of the sub-network models includes a bump pad resistor, a through-silicon via resistor, a bump pad capacitor, a through-silicon via capacitor, a bump pad inductor, and a through-silicon via inductor. The bump pad resistor, the bump pad inductor, the through-silicon via inductor, and the through-silicon via resistor are connected in series between the second bare die and the first bare die in sequence. One end of the bump pad capacitor is connected between the second bare die and the bump pad resistor, and the other end of the bump pad capacitor is connected to a preset far end. One end of the through-silicon via capacitor is connected between the bump pad inductor and the through-silicon via inductor, and the other end of the through-silicon via capacitor is connected to the through-silicon via capacitor in another sub-network model.

[0125] In some examples, the simulation model processing module 63 includes: a simulation model file processing unit, a through-silicon via symbol processing unit, and a simulation model processing unit. The simulation model file processing unit obtains a simulation model file according to the sub-network model and electrical parameters; the through-silicon via symbol processing unit configures through-silicon via structure symbols between the circuit model of the first die and the circuit model of the second die according to the number of through-silicon via structures between the two dies, so as to obtain a first circuit model; the simulation model processing unit obtains a simulation model according to the first circuit model and the simulation model file for simulation.

[0126] In some examples, when the number of dies is greater than two, the simulation model processing module 63 includes: a simulation model file processing unit, a through-silicon via symbol processing unit, and a simulation model processing unit. The simulation model file processing unit is used to obtain a simulation model file according to the sub-network model and electrical parameters; the through-silicon via symbol processing unit is used to configure through-silicon via structure symbols between all adjacent two dies respectively according to the number of through-silicon via structures between adjacent two dies, so as to obtain a second circuit model; the simulation model processing unit is used to obtain the simulation model according to the second circuit model and the simulation model file for simulation.

[0127] In some examples, the bump sub-structure includes a first copper layer, a second copper layer, a first nickel layer, a tin-silver alloy layer, and a second nickel layer stacked in sequence; the through-silicon via sub-structure includes a third copper layer; the electrical parameter acquisition unit obtains the electrical parameters of the bump sub-structure according to the material information and size information of the first copper layer, the second copper layer, the first nickel layer, the tin-silver alloy layer, and the second nickel layer, and obtains the electrical parameters of the through-silicon via sub-structure according to the material information and size information of the third copper layer.

[0128] In some examples, an optimization module is further included, which is used to obtain an optimized structure of the through-silicon via structure according to the simulation result.

[0129] In some examples, the optimization module is used to optimize at least one of the height and / or width of the bump sub-structure, the width and / or height of the through-silicon via sub-structure, the material composition and ratio in the bump sub-structure, and the pitch between each through-silicon via structure between two dies.

[0130] In other examples, the first die includes a substrate layer and a plurality of metal layers, the plurality of metal layers are sequentially stacked below the substrate layer, through holes are formed in the substrate layer for the through-silicon via sub-structure to pass through, and the through-silicon via sub-structure is electrically connected to one of the metal layers; the optimization module is used to re-determine the metal layer electrically connected to the through-silicon via sub-structure.

[0131] The present application also provides a computer device, including a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, the steps of the method described in any one of the above embodiments are implemented.

[0132] The present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method described in any one of the above embodiments are implemented.

[0133] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the various embodiments provided by the present application can include at least one of non-volatile and volatile memories. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0134] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0135] The above embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A modeling method, characterized in that: It includes: Obtaining the electrical parameters of each sub-structure in the through-silicon via structure; Obtaining an electrical topology network model according to the connection relationship of each of the through-silicon via structures between two bare chips; Obtaining a simulation model according to the electrical topology network model and the electrical parameters for simulation; The two bare chips are respectively a first bare chip and a second bare chip. Each sub-structure includes a bump pad sub-structure and a through-silicon via sub-structure. One end of the bump pad sub-structure is electrically connected to the second bare chip, and the other end of the bump pad sub-structure is electrically connected to one end of the through-silicon via sub-structure. A through hole is provided on the first bare chip for the through-silicon via sub-structure to pass through to electrically connect the other end of the through-silicon via sub-structure to the first bare chip. The electrical parameters include the electrical parameters of the bump pad sub-structure and the electrical parameters of the through-silicon via sub-structure; The obtaining of the electrical parameters of each sub-structure in the through-silicon via structure includes: Obtaining a structural schematic diagram of the through-silicon via structure; Obtaining a material composition cross-sectional view of each sub-structure in the through-silicon via structure according to the structural schematic diagram of the through-silicon via structure; the material composition cross-sectional view of the sub-structure includes the material information and size information of the sub-structure; Obtaining the electrical parameters according to the material information and size information of each sub-structure.

2. The modeling method according to claim 1, characterized in that: The electrical parameters include resistance parameters, capacitance parameters and inductance parameters.

3. The modeling method according to claim 2, characterized in that: When the number of through-silicon via structures between the two bare chips is multiple, each of the through-silicon via structures is the same. The electrical topology network model includes multiple sub-network models, and the number of sub-network models is equal to the number of through-silicon via structures; Each sub-network model includes a bump pad resistance, a through-silicon via resistance, a bump pad capacitance, a through-silicon via capacitance, a bump pad inductance and a through-silicon via inductance. The bump pad resistance, the bump pad inductance, the through-silicon via inductance and the through-silicon via resistance are sequentially connected in series between the second bare chip and the first bare chip. One end of the bump pad capacitance is connected between the second bare chip and the bump pad resistance, and the other end of the bump pad capacitance is connected to a preset far end. One end of the through-silicon via capacitance is connected between the bump pad inductance and the through-silicon via inductance, and the other end of the through-silicon via capacitance is connected to the through-silicon via capacitance in another sub-network model.

4. The modeling method according to claim 3, characterized in that: The obtaining of the simulation model according to the electrical topology network model and the electrical parameters for simulation includes: Obtaining a simulation model file according to the sub-network model and the electrical parameters; Configuring through-silicon via structure symbols between the circuit model of the first bare chip and the circuit model of the second bare chip according to the number of through-silicon via structures between the two bare chips to obtain a first circuit model; Obtaining the simulation model according to the first circuit model and the simulation model file for simulation.

5. The modeling method according to claim 3, characterized in that: When the number of the dies is greater than two, obtaining a simulation model according to the electrical topology network model and the electrical parameters for simulation includes: Obtaining a simulation model file according to the sub-network model and the electrical parameters; Configuring via - silicon - through structure symbols respectively between all adjacent two dies according to the number of the via - silicon - through structures between adjacent two dies to obtain a second circuit model; and Obtaining the simulation model according to the second circuit model and the simulation model file for simulation.

6. The modeling method according to claim 1, wherein The bump pad sub - structure includes a first copper layer, a second copper layer, a first nickel layer, a tin - silver alloy layer, and a second nickel layer stacked in sequence; the via - silicon - through sub - structure includes a third copper layer; In the step of obtaining the electrical parameters according to the material information and size information of each sub - structure, the electrical parameters of the bump pad sub - structure are obtained according to the material information and size information of the first copper layer, the second copper layer, the first nickel layer, the tin - silver alloy layer, and the second nickel layer, and the electrical parameters of the via - silicon - through sub - structure are obtained according to the material information and size information of the third copper layer.

7. The modeling method according to claim 6, wherein It further includes: Obtaining an optimized structure of the via - silicon - through structure according to the simulation result.

8. The modeling method according to claim 7, wherein Obtaining the optimized structure of the via - silicon - through structure according to the simulation result includes at least one of optimizing the height and / or width of the bump pad sub - structure, optimizing the width and / or height of the via - silicon - through sub - structure, optimizing the material composition and ratio in the bump pad sub - structure, and optimizing the pitch between each of the via - silicon - through structures between two dies.

9. The modeling method according to claim 7, wherein The first die includes a substrate layer and a plurality of metal layers, the plurality of metal layers are sequentially stacked below the substrate layer, through - holes are formed in the substrate layer for the via - silicon - through sub - structure to pass through, and the via - silicon - through sub - structure is electrically connected to one of the metal layers; Obtaining the optimized structure of the via - silicon - through structure according to the simulation result includes: re - determining the metal layer electrically connected to the via - silicon - through sub - structure.

10. A modeling device, wherein It includes: An acquisition module, configured to acquire the electrical parameters of each sub - structure in the via - silicon - through structure; An electrical topology network model processing module, configured to obtain an electrical topology network model according to the connection relationship of each of the via - silicon - through structures between two dies; A simulation model processing module, configured to obtain a simulation model according to the electrical topology network model and the electrical parameters for simulation; The two dies are a first die and a second die respectively. Each of the sub-structures includes a bump pad sub-structure and a through-silicon via sub-structure. One end of the bump pad sub-structure is electrically connected to the second die, and the other end of the bump pad sub-structure is electrically connected to one end of the through-silicon via sub-structure. A through hole is formed in the first die for the through-silicon via sub-structure to pass through so as to electrically connect the other end of the through-silicon via sub-structure to the first die. The electrical parameters include the electrical parameters of the bump pad sub-structure and the electrical parameters of the through-silicon via sub-structure; The obtaining of the electrical parameters of each sub-structure in the through-silicon via structure includes: Obtaining a schematic diagram of the structure of the through-silicon via structure; Obtaining a material composition cross-sectional view of each sub-structure in the through-silicon via structure according to the schematic diagram of the structure of the through-silicon via structure; the material composition cross-sectional view of the sub-structure includes the material information and size information of the sub-structure; Obtaining the electrical parameters according to the material information and size information of each sub-structure.

11. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, the steps of the method according to any one of claims 1 to 9 are implemented.

12. A computer-readable storage medium, having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

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