Thin film transistor and electronic device

Abstract

A thin film transistor and an electronic device are provided. The thin film transistor includes a crystalline active pattern including a channel, two contact portions connected to opposite sides of the channel in a direction intersecting a thickness direction of the crystalline active pattern, and a recess extending in the thickness direction of the crystalline active pattern on at least one of the two contact portions, a source electrode and a drain electrode connected to the two contact portions, respectively, and a heat retaining layer in contact with the channel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a thin-film transistor and electronic device. Background Technology

[0002] Integrating integrated circuits onto a glass substrate (System on Glass, SOG) can significantly improve the integration level of display panels and reduce their manufacturing costs. However, achieving this integration requires improving the mobility of thin-film transistors.

[0003] Therefore, improving the mobility of thin-film transistors is a technical problem that needs to be solved. Summary of the Invention

[0004] The purpose of this application is to provide a thin-film transistor and electronic device that is beneficial to improving the mobility of the thin-film transistor.

[0005] To achieve the above objectives, the technical solution is as follows:

[0006] A thin-film transistor, the thin-film transistor comprising:

[0007] Active crystallization pattern, wherein the active crystallization pattern includes:

[0008] Ditch;

[0009] Two contact portions are connected on opposite sides of the channel in a direction intersecting the thickness direction of the crystalline active pattern; and

[0010] A groove is located on at least one of the two contact portions and extends in the thickness direction of the crystalline active pattern;

[0011] The source and drain are respectively connected to the two contact portions; and

[0012] An insulation layer that is in contact with the channel.

[0013] In some embodiments of the thin-film transistor, the crystalline active pattern further includes two transition portions, one of which is connected between one of the contact portions and the channel, and the insulation layer is also in contact with both of the transition portions.

[0014] In some embodiments of the thin-film transistor, the crystalline active pattern includes grains with a size greater than or equal to 300 nanometers.

[0015] In some embodiments of the thin-film transistor, the refractive index of the insulation layer is n, the thickness of the insulation layer is d, and n, d, and the wavelength λ of the laser satisfy the following formula:

[0016] 2d×n=k×λ, where k is an integer greater than or equal to 1, and the wavelength λ of the laser is greater than or equal to 180 nanometers and less than or equal to 420 nanometers.

[0017] In some embodiments of the thin-film transistor, the thickness of the insulation layer is greater than or equal to 100 angstroms and less than or equal to 1000 angstroms.

[0018] In some embodiments of the thin-film transistor, the depth of the groove is less than or equal to the thickness of the crystalline active pattern, and the groove is located at at least one of the contacts near the channel.

[0019] In some embodiments of the thin-film transistor, the depth of the groove is less than the thickness of the crystalline active pattern, and the groove on one of the contacts completely overlaps with the contact.

[0020] In some embodiments, the thin-film transistor further includes:

[0021] A gate is disposed corresponding to the channel;

[0022] A gate insulating layer is located between the gate and the crystalline active pattern;

[0023] An interlayer insulating layer is located between the crystalline active pattern and the source and drain electrodes;

[0024] Two contact holes, penetrating at least the interlayer insulation layer, are provided, and the source and drain are respectively connected to the two contact portions through the two contact holes.

[0025] In some embodiments of the thin-film transistor, the gate is located between the crystalline active pattern and the source and drain, and the interlayer insulating layer is located between the gate and the source and drain;

[0026] The two contact holes also penetrate the gate insulating layer, and at least one of the two contact holes overlaps with the groove, the diameter of the contact hole being larger than the opening size of the groove.

[0027] An electronic device comprising the aforementioned thin-film transistor.

[0028] Beneficial effects: This application provides a thin film transistor and electronic device. By providing a groove on at least one of the two contact portions of the crystallized active pattern, it is beneficial to form a seed crystal at the groove during the crystallization process to form the crystallized active pattern. The seed crystal grows towards the channel before crystallization. With the help of the heat insulation layer, the heat dissipation of the channel before crystallization is slower, so that large-sized grains are formed in the channel, reducing the grain boundaries in the channel of the crystallized active pattern, thereby improving the mobility of the thin film transistor. Attached Figure Description

[0029] Figure 1 This is a planar schematic diagram of an array substrate according to an embodiment of this application;

[0030] Figure 2 For along Figure 1 A schematic diagram of the cross-section of the array substrate AA shown.

[0031] Figure 3 For along Figure 1 A schematic diagram of the cross-section of the array substrate BB tangent shown;

[0032] Figure 4 This is a cross-sectional schematic diagram of an array substrate according to another embodiment of this application;

[0033] Figure 5 for Figure 4 A planar schematic diagram of an active crystallization pattern;

[0034] Figure 6 This is a cross-sectional schematic diagram of an array substrate according to another embodiment of this application;

[0035] Figures 7A-7J A schematic diagram illustrating the process of manufacturing an array substrate according to an embodiment of this application;

[0036] Figure 8 This is a cross-sectional schematic diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0038] Please see Figure 1 , Figure 2 as well as Figure 3 , Figure 1 This is a planar schematic diagram of an array substrate according to an embodiment of this application. Figure 2 For along Figure 1 A schematic diagram of the cross-section of the array substrate AA shown. Figure 3 For along Figure 1 A schematic diagram of the cross-section of the BB tangent on the array substrate shown.

[0039] In this embodiment, the array substrate 100 includes a substrate 10 and a plurality of thin-film transistors 11 arranged in an array on the substrate 10. The substrate 10 is an insulating substrate, such as a glass substrate, but is not limited thereto; the substrate 10 may also be a flexible substrate. The thin-film transistors 11 are low-temperature polycrystalline silicon thin-film transistors, but are not limited thereto; the thin-film transistors 11 may also be crystalline metal oxide thin-film transistors.

[0040] In this embodiment, the array substrate 100 further includes a light-shielding pattern 12 and a buffer layer 13. The light-shielding pattern 12 is located between the thin-film transistor 11 and the substrate 10, and the buffer layer 13 is located between the light-shielding pattern 12 and the thin-film transistor 11.

[0041] In this embodiment, the light-shielding pattern 12 is disposed on the substrate 10 in a flat state. The material used to prepare the light-shielding pattern 12 includes at least one of metal or black organic material.

[0042] In this embodiment, the buffer layer 13 covers the light-shielding pattern 12 and the substrate 10. The material used to fabricate the buffer layer 13 includes at least one of silicon nitride or silicon oxide. The thickness of the buffer layer 13 is greater than or equal to 2500 angstroms and less than or equal to 3500 angstroms, for example, 2500 angstroms, 2800 angstroms, 3000 angstroms or 3500 angstroms.

[0043] In this embodiment, the thin-film transistor 11 includes a crystalline active pattern 111, a gate 112, a source 1161, a drain 1162, a gate insulating layer 113, an interlayer insulating layer 114, and a heat insulation layer 115.

[0044] In this embodiment, the crystalline active pattern 111 is a low-temperature polycrystalline silicon active pattern, but it is not limited to this; the crystalline active pattern 111 can also be a crystalline metal oxide active pattern. The thickness of the crystalline active pattern 111 is greater than or equal to 300 angstroms and less than or equal to 600 angstroms, for example, 350 angstroms, 380 angstroms, 400 angstroms, 420 angstroms, 450 angstroms, 480 angstroms, 500 angstroms, or 600 angstroms.

[0045] In this embodiment, a crystallized active pattern 111 is disposed on a buffer layer 13. The crystallized active pattern 111 includes a channel 1111, two contact portions 1112, and two transition portions 1113. In a direction intersecting the thickness direction of the crystallized active pattern 111, the two contact portions 1112 are connected to opposite sides of the channel 1111, and a transition portion 1113 is connected between a contact portion 1112 and the channel 1111.

[0046] Specifically, in a direction perpendicular to the thickness of the crystalline active pattern 111, two contact portions 1112 are respectively connected to opposite sides of the channel 1111, and a transition portion 1113 is connected between one contact portion 1112 and the channel 1111. The channel 1111 and the two transition portions 1113 overlap with the light-shielding pattern 12, so that the light-shielding pattern 12 can block light incident on the channel 1111 and the two transition portions 1113.

[0047] It should be noted that the channel 1111 is not doped with ions, while the two contact portions 1112 and the two transition portions 1113 are doped with ions. The ion doping concentration of the two transition portions 1113 is lower than that of the two contact portions 1112.

[0048] In this embodiment, the active crystal pattern 111 further includes a groove 111a, which is located on at least one of the two contact portions 1112. The groove 111a is located on the side of the contact portion 1112 away from the substrate 10. The groove 111a extends in the thickness direction of the active crystal pattern 111, and the depth of the groove 111a is less than or equal to the thickness of the active crystal pattern 111.

[0049] It is understood that the groove 111a can be provided on one contact portion 1112 or on two contact portions 1112. Each contact portion 1112 can have one, two or more grooves 111a. The depth of the groove 111a can be equal to the thickness of the crystalline active pattern 111, or the depth of the groove 111a can be less than the thickness of the crystalline active pattern 111.

[0050] In this embodiment, the groove 111a is located at at least one contact portion 1112 near the channel 1111. In other words, the groove 111a is located at a portion of the contact portion 1112, and the groove 111a is disposed near the transition portion 1113.

[0051] The design of the groove in the active crystallization pattern of this application embodiment makes the active crystallization pattern before crystallization have abrupt change points. These abrupt change points are more likely to generate seed crystals, thereby enabling the groove to play a role in grain positioning during the crystallization process to form the active crystallization pattern. The groove is set close to the transition part, which is conducive to the lateral growth of seed crystals towards the transition part and the channel before crystallization.

[0052] Specifically, such as Figure 1 and Figure 2As shown, a groove 111a is located near a channel 1111 of a contact portion 1112. The depth of the groove 111a is equal to the thickness of the crystalline active pattern 111, meaning the groove 111a is a through-hole located near the channel 1111. Furthermore, the orthographic projection of the groove 111a on the substrate 10 lies within the orthographic projection of the contact portion 1112 on the substrate 10. The area of ​​the orthographic projection of the groove 111a on the substrate 10 is smaller than the area of ​​the orthographic projection of the contact portion 1112 on the substrate 10. The groove 111a does not divide the contact portion 1112 into two separate parts.

[0053] In another embodiment of this application, such as Figure 4 and Figure 5 As shown, Figure 4 This is a cross-sectional schematic diagram of an array substrate according to another embodiment of this application. Figure 5 for Figure 4 A planar schematic diagram of the active crystal pattern. Two grooves 111a are located at the positions of the two contact portions 1112 near the channel 1111, respectively. The two grooves 111a are symmetrically arranged on opposite sides of the channel 1111, and the depth of the two grooves 111a is less than the thickness of the active crystal pattern 111.

[0054] In this embodiment, the shape of the cross-section of the groove 111a along the thickness direction of the crystalline active pattern 111 can be rectangular, trapezoidal, or other shapes. The shape of the cross-section of the groove 111a along the direction perpendicular to the thickness of the crystalline active pattern 111 can be rectangular, circular, or other shapes.

[0055] In this embodiment, the insulation layer 115 serves to insulate the heat and reduce the heat dissipation rate. The insulation layer 115 is in contact with the channel 1111. The insulation layer 115 is located on the surface of the crystalline active pattern 111 away from the substrate 10, but it is not limited thereto. The insulation layer 115 may also be located between the crystalline active pattern 111 and the buffer layer 13 and in contact with the surface of the crystalline active pattern 111 near the substrate 10.

[0056] The thickness of the insulation layer 115 is greater than or equal to 100 angstroms and less than or equal to 1000 angstroms, for example, 200 angstroms, 300 angstroms, 400 angstroms, 600 angstroms, 800 angstroms or 1000 angstroms. The materials used to prepare the insulation layer 115 include, but are not limited to, silicon oxide.

[0057] The insulation layer 115 contacts the channel 1111 and the two transition portions 1113, while the insulation layer 115 does not contact the two contact portions 1112, so as to reduce the heat dissipation rate of the channel 1111 and the two transition portions 1113 before crystallization after laser annealing, which is beneficial to the formation of large-sized grains in the channel 1111 and the two transition portions 1113.

[0058] During the formation of crystalline active patterns, after the amorphous active patterns are annealed and crystallized using lasers, the insulation layer keeps the channels and two transition sections before crystallization warm. The heat dissipation of the sections of the amorphous active patterns to be formed, including the channels and two transition sections, slows down. The seed crystals generated at the grooves grow laterally along the sections of the amorphous active patterns to be formed, including the channels and two transition sections, thereby forming large-sized grains in the channels and two transition sections.

[0059] In this embodiment, the refractive index of the insulation layer 115 is n, the thickness of the insulation layer 115 is d, and the wavelength of the laser is λ. n, d, and λ satisfy the following formula: 2d×n=k×λ, where k is an integer greater than or equal to 1, and the wavelength of the laser λ is greater than or equal to 180 nanometers and less than or equal to 420 nanometers.

[0060] The wavelength λ of the laser can be from 305 nm to 310 nm, for example, a laser with a wavelength λ of 308 nm emitted by an XeCl excimer laser. It can also be understood that the wavelength λ can be from 185 nm to 200 nm, for example, a laser with a wavelength of 193 nm emitted by an ArF excimer laser; or the wavelength λ can be from 230 nm to 250 nm, for example, a laser with a wavelength of 248 nm emitted by a KrF excimer laser.

[0061] When the insulation layer 115 is made of silicon oxide, its refractive index is 1.6. The value of k can be 2, 3, 4, 5, or 6.

[0062] In this embodiment, the thickness of the insulation layer is d = kλ / (2n), which enables the insulation layer to resist laser reflection during the annealing and crystallization process of the amorphous active pattern with a wavelength of λ. More laser light passes through the insulation layer, and the amorphous active pattern below the insulation layer receives more laser energy. Larger-sized grains tend to form in the amorphous active pattern below the insulation layer. Correspondingly, larger-sized grains are formed in the channel and the two transition parts, which is beneficial to improving the mobility of thin-film transistors and thus facilitates the integration of integrated chips on the insulating substrate.

[0063] In this embodiment, due to the interaction between the heat insulation layer and the groove, the crystalline active pattern 111 includes grains with a size greater than or equal to 300 nanometers, such as grains with a size of 320 nanometers, 330 nanometers, 345 nanometers, 350 nanometers, 360 nanometers, 370 nanometers, 380 nanometers, 390 nanometers, or 400 nanometers.

[0064] In this embodiment, the gate 112 is located on the side of the insulation layer 115 away from the substrate 10; in other words, the thin-film transistor 11 is a top-gate thin-film transistor. It is understood that the gate 112 may also be located between the crystalline active pattern 111 and the buffer layer 13; in other words, the thin-film transistor 11 is a bottom-gate thin-film transistor. The gate 112 is disposed corresponding to the channel 1111. The material used to fabricate the gate 112 includes, but is not limited to, at least one of molybdenum, aluminum, titanium, copper, and silver.

[0065] In this embodiment, a gate insulating layer 113 is disposed between the gate 112 and the insulation layer 115. The material used to fabricate the gate insulating layer 113 includes, but is not limited to, at least one of silicon nitride or silicon oxide. The thickness of the gate insulating layer 113 is greater than or equal to 500 angstroms and less than or equal to 1500 angstroms, for example, 800 angstroms, 1000 angstroms, 1200 angstroms, 1300 angstroms, or 1500 angstroms.

[0066] In this embodiment, the gate 112 is located between the crystalline active pattern 111 and the source 1161 and drain 1162. The source 1161 and drain 1162 are disposed in the same layer, and the source 1161 and drain 1162 are respectively connected to two contact portions 1112. The materials used to fabricate the source 1161 and drain 1162 include, but are not limited to, at least one of molybdenum, aluminum, titanium, copper, and silver.

[0067] In this embodiment, the interlayer insulating layer 114 is located between the crystalline active pattern 111 and the source 1161 and drain 1162, and the interlayer insulating layer 114 is located between the gate 112 and the source 1161 and drain 1162. The material used to fabricate the interlayer insulating layer 114 includes, but is not limited to, silicon nitride or silicon oxide. The thickness of the interlayer insulating layer 114 is greater than or equal to 5000 angstroms and less than or equal to 6500 angstroms, for example, 5200 angstroms, 5400 angstroms, 5500 angstroms, 5600 angstroms, or 5800 angstroms.

[0068] In this embodiment, the array substrate 100 further includes two contact holes 100a, which are respectively disposed corresponding to two contact portions 1112. The two contact holes 100a penetrate the interlayer insulating layer 114 and the gate insulating layer 113. The source 1161 contacts one contact portion 1112 through one contact hole 100a, and the drain 1162 contacts another contact portion 1112 through the other contact hole 100a.

[0069] It is understandable that when the thin-film transistor 11 is a bottom-gate thin-film transistor, the two contact holes 100a only need to penetrate the interlayer insulating layer 114.

[0070] At least one of the two contact holes 100a overlaps with the groove 111a. Specifically, when a groove 111a is provided on a contact portion 1112, one contact hole 100a overlaps with one groove 111a, and one of the source electrode 1161 and the drain electrode 1162 contacts a contact portion 1112 through a contact hole 100a and a groove 111a, so that one of the source electrode 1161 and the drain electrode 1162 forms a ring contact with the contact portion 1112; the other of the source electrode 1161 and the drain electrode 1162 contacts the surface of another contact portion 1112 away from the substrate 10 through another contact hole 100a.

[0071] It is understandable that when a groove 111a is provided on each of the two contact portions 1112, the two contact holes 100a and the two grooves 111a can also overlap one-to-one. The source electrode 1161 forms a ring contact with one contact portion 1112 through one contact hole 100a and one groove 111a, and the drain electrode 1162 forms a ring contact with another contact portion 1112 through another contact hole 100a and another groove 111a.

[0072] When the groove 111a is located at a portion of the contact portion 1112, the aperture R of the contact hole 100a is larger than the opening size L of the groove 111a, so that the gate insulating layer located in the groove 111a can be etched away during the formation of the contact hole 100a, thereby realizing the connection between the contact hole 100a and the groove 111a, and thus realizing the connection between one of the source 1161 and the drain 1162 and a contact portion 1112.

[0073] It is understandable that the two contact holes 100a may not overlap with the groove 111a. The groove 111a is located at a part of the contact portion 1112. The source electrode 1161 and the drain electrode 1162 contact the part of the contact portion 1112 other than the groove 111a through the two contact holes 100a.

[0074] Please see Figure 6 This is a cross-sectional schematic diagram of an array substrate according to another embodiment of this application. The array substrate of this embodiment is... Figure 4 The array substrates shown are basically similar, and the similarities will not be repeated. The differences include that the depth of the groove 111a is less than the thickness of the crystalline active pattern 111, and the groove 111a on a contact portion 1112 completely overlaps with the contact portion 1112. Correspondingly, at least one contact portion 1112 and the transition portion 1113 form a step.

[0075] In this embodiment, the orthographic projection of a groove 111a on the substrate 10 completely coincides with the orthographic projection of a contact portion 1112 on the substrate 10. Correspondingly, the area of ​​the orthographic projection of a groove 111a on the substrate 10 is equal to the area of ​​the orthographic projection of a contact portion 1112 on the substrate 10. Therefore, the groove 111a is formed by thinning the contact portion 1112 in the thickness direction of the crystalline active pattern 111.

[0076] In addition, this application also provides a method for manufacturing an array substrate, the method comprising the following steps:

[0077] like Figure 7A As shown, the light-shielding metal layer is patterned using the first patterning process to obtain the light-shielding pattern 12 on the substrate 10, forming a buffer layer 13 covering the light-shielding pattern 12 and the substrate 10.

[0078] like Figure 7B , Figure 7C as well as Figure 7D As shown, a full-surface amorphous silicon semiconductor layer 14 and a full-surface heat-insulating film 115a are formed on the buffer layer 13. A second patterning process is used to pattern the heat-insulating film 115a to obtain the heat-insulating layer 115. A third patterning process is then used to pattern the amorphous silicon semiconductor layer 14 to obtain an amorphous silicon semiconductor pattern 141. The amorphous silicon semiconductor pattern 141 has a channel region 141a, two contact regions 141b, and two transition regions 141c. The two contact regions 141b are located in the channel region 141a in a direction perpendicular to the thickness of the amorphous silicon semiconductor pattern 141. On opposite sides, a transition region 141c connects the channel region 141a and a contact region 141b. The heat insulation layer 115 overlaps with the two transition regions 141c and the channel region 141a of the amorphous silicon semiconductor pattern 141. The light-shielding pattern 12 overlaps with the two transition regions 141c and the channel region 141a of the amorphous silicon semiconductor pattern 141. The amorphous silicon semiconductor pattern 141 includes a groove 111a, which is located at a portion of the contact region 141b and close to the transition region 141c. The depth of the groove 111a is equal to the thickness of the amorphous silicon semiconductor pattern 141.

[0079] like Figure 7E and Figure 7FAs shown, an amorphous silicon semiconductor pattern 141 is annealed using a XeCl excimer laser with a wavelength λ of 308 nm to obtain a polycrystalline silicon semiconductor pattern 142. During laser annealing, seed crystals 1411 are easily formed at the groove 111a. The amorphous silicon semiconductor pattern 141, located in the two transition regions 141c and the channel region 141a, dissipates heat slowly under the influence of the insulation layer 115. The seed crystals 1411 grow laterally into the transition regions 141c and the channel region 141a, making it easier for large-sized grains to form in the transition regions 141c and the channel region 141a.

[0080] In addition, when the refractive index n of the insulation layer 115, the thickness d of the insulation layer 115, and the wavelength λ of the laser satisfy the formula 2d×n=k×λ, k is an integer greater than or equal to 1, the insulation layer 115 plays an anti-reflection role for the laser during the annealing and crystallization process of the amorphous silicon semiconductor pattern 141. More laser light passes through the insulation layer 115, and the amorphous silicon semiconductor pattern 141 below the insulation layer 115 obtains more laser energy. Larger grains tend to form in the amorphous silicon semiconductor pattern 141 below the insulation layer 115. Correspondingly, larger grains are further formed in the transition region 141c and the channel region 141a.

[0081] like Figure 7G As shown, the two contact regions 141b of the polycrystalline silicon semiconductor pattern 142 are processed by heavy ion doping to obtain a heavily doped polycrystalline silicon semiconductor pattern 143. The heavily doped polycrystalline silicon semiconductor pattern 143 includes contact portions 1112 located in the two contact regions 141b.

[0082] like Figure 7H As shown, a gate insulating layer 113 is formed covering a heavily doped polysilicon semiconductor pattern 143 and a buffer layer 13. The gate metal layer is patterned on the gate insulating layer 113 through a fourth patterning process to obtain a gate 112. The gate 112 is disposed corresponding to the channel region 141a. Using the gate 112 as a mask, two transition regions 141c are processed by a light ion doping process to obtain an active pattern 111. The crystallized active pattern 111 includes a channel 1111 located in the channel region 141a and a transition portion 1113 located in the two transition regions 141c. A transition portion 1113 is connected between a contact portion 1112 and the channel 1111.

[0083] like Figure 7I As shown, an interlayer insulating layer 114 is formed to cover the gate 112 and the gate insulating layer 113. The interlayer insulating layer 114 and the gate insulating layer 113 are patterned using a fifth patterning process to obtain two contact holes 100a. The two contact holes 100a are each provided with two contact portions 1112, and one of the two contact holes 100a is connected to the groove 111a.

[0084] like Figure 7J As shown, source and drain electrode metal layers are formed on the surface of the interlayer insulating layer 114 away from the gate insulating layer 113, in the two contact holes 100a and the groove 111a. The source and drain electrode metal layers are patterned using a sixth patterning process to obtain source 1161 and drain 1162. Source 1161 forms an annular contact with a contact portion 1112 through a contact hole 100a and the groove 111a. Drain 1162 contacts another contact portion 1112 through another contact hole 100a.

[0085] The method for manufacturing an array substrate according to the embodiments of this application involves setting a groove in at least one of the two contact areas of an amorphous silicon semiconductor pattern. This facilitates the formation of a seed crystal at the groove during the crystallization of the amorphous silicon semiconductor pattern to form a crystalline active pattern. The seed crystal grows into the transition region and the channel region. Combined with a heat insulation layer, the amorphous silicon semiconductor pattern in the transition region and the channel region dissipates heat more slowly, thereby forming large-sized grains in the transition region and the channel region, reducing grain boundaries in the channel of the crystalline active pattern, and thus improving the mobility of the thin-film transistor.

[0086] This application also provides an electronic device 200, which is a display panel. The electronic device 200 can be at least one of liquid crystal display panel, organic light-emitting diode display panel, quantum dot light-emitting diode display panel, sub-millimeter light-emitting diode display panel, and micron light-emitting diode display panel.

[0087] Specifically, such as Figure 8 The diagram shown is a cross-sectional schematic of an electronic device according to an embodiment of this application. The electronic device 200 includes an array substrate 100, a color filter substrate 300, and a liquid crystal layer (not shown) located between the array substrate 100 and the color filter substrate 300. The array substrate 100 and the aforementioned… Figure 1 and Figure 2 The array substrate 100 shown is basically similar, and the similarities will not be repeated. The differences include that the array substrate 100 also includes a planarization layer 15, a common electrode 16, a passivation layer 17, and a pixel electrode 18.

[0088] In this structure, planarization layer 15 covers interlayer insulating layer 114, source electrode 1161 and drain electrode 1162, common electrode 16 is disposed on planarization layer 15, passivation layer 17 covers common electrode 16 and planarization layer 15, pixel electrode 18 is disposed on passivation layer 17, and pixel electrode 18 is connected to drain electrode 1162 through vias penetrating passivation layer 17 and planarization layer 15.

[0089] In this embodiment of the electronic device, a groove is provided on at least one of the two contact portions of the crystalline active pattern. This facilitates the formation of seed crystals at the grooves during the crystallization process to form the crystalline active pattern. The seed crystals grow towards the channel before crystallization. Combined with the heat insulation layer, the heat dissipation of the channel before crystallization is slowed down, so that large-sized grains are formed in the channel, reducing the grain boundaries in the channel of the crystalline active pattern, thereby improving the mobility of thin-film transistors. This is beneficial for integrating integrated chips on the insulating substrate of the electronic device and reducing the cost of the electronic device.

[0090] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A thin-film transistor, characterized in that, The thin-film transistor includes: Active crystallization pattern, wherein the active crystallization pattern includes: Ditch; Two contact portions are connected on opposite sides of the channel in a direction intersecting the thickness direction of the crystalline active pattern; and A groove is located on at least one of the two contact portions and extends in the thickness direction of the crystalline active pattern; The source and drain are respectively connected to the two contact portions; and An insulation layer that contacts the channel but not the contact portion.

2. The thin-film transistor according to claim 1, characterized in that, The crystalline active pattern also includes two transition portions, one of which is connected between one of the contact portions and the channel, and the insulation layer is in contact with both of the transition portions.

3. The thin-film transistor according to claim 1 or 2, characterized in that, The crystalline active pattern includes grains with a size greater than or equal to 300 nanometers.

4. The thin-film transistor according to claim 1, characterized in that, The refractive index of the insulation layer is n, and the thickness of the insulation layer is d. The refractive index of n, the thickness of d, and the wavelength λ of the laser satisfy the following formula: 2d×n=k×λ, where k is an integer greater than or equal to 1, and the wavelength λ of the laser is greater than or equal to 180 nanometers and less than or equal to 420 nanometers.

5. The thin-film transistor according to claim 1 or 4, characterized in that, The thickness of the insulation layer is greater than or equal to 100 angstroms and less than or equal to 1000 angstroms.

6. The thin-film transistor according to claim 1, characterized in that, The depth of the groove is less than or equal to the thickness of the crystalline active pattern, and the groove is located at at least one of the contact portions near the channel.

7. The thin-film transistor according to claim 1, characterized in that, The depth of the groove is less than the thickness of the crystalline active pattern, and the groove on one of the contact portions completely overlaps with the contact portion.

8. The thin-film transistor according to claim 1, characterized in that, The thin-film transistor further includes: A gate is disposed corresponding to the channel; A gate insulating layer is located between the gate and the crystalline active pattern; An interlayer insulating layer is located between the crystalline active pattern and the source and drain electrodes; Two contact holes, penetrating at least the interlayer insulation layer, are provided, and the source and drain are respectively connected to the two contact portions through the two contact holes.

9. The thin-film transistor according to claim 8, characterized in that, The gate is located between the crystal active pattern and the source and drain, and the interlayer insulating layer is located between the gate and the source and drain; The two contact holes also penetrate the gate insulating layer, and at least one of the two contact holes overlaps with the groove, the diameter of the contact hole being larger than the opening size of the groove.

10. An electronic device, characterized in that, The electronic device includes a thin-film transistor as described in any one of claims 1-9.

Images