Magnetoresistive random access memory

Abstract

This invention discloses a magnetoresistive random access memory, which mainly includes a first array region and a second array region disposed on a substrate, a first magnetic tunneling junction (MTJ) disposed in the first array region, a first upper electrode disposed on the first MTJ, a second MTJ disposed in the second array region, and a second upper electrode disposed on the second MTJ, wherein the first upper electrode and the second upper electrode contain different nitrogen-to-titanium ratios.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a magnetoresistive random access memory (MRAM) device. Background Technology

[0002] Magnetoresistance (MR) is the effect of a material's resistance changing with the application of a magnetic field. Its physical quantity is defined as the rate of change of resistance, calculated by dividing the resistance difference (with and without a magnetic field) by the original resistance. Currently, the magnetoresistance effect has been successfully applied in hard disk manufacturing, demonstrating significant commercial value. Furthermore, by utilizing the characteristic that giant magnetoresistance materials have different resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can be fabricated, offering the advantage of retaining stored data even without power.

[0003] The aforementioned magnetoresistive effect is also applied in the field of magnetic field sensing, such as in the electronic compass components of mobile phones that integrate with the Global Positioning System (GPS) to provide users with information such as their location. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistive (AMR) sensing elements, giant magnetoresistive (GMR) sensing elements, and magnetic tunneling junction (MTJ) sensing elements. However, these existing technologies typically have drawbacks, including larger chip area, higher manufacturing costs, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, necessitating further improvements. Summary of the Invention

[0004] This invention discloses a magnetoresistive random access memory, which mainly includes a first array region and a second array region disposed on a substrate, a first magnetic tunneling junction (MTJ) disposed in the first array region, a first upper electrode disposed on the first MTJ, a second MTJ disposed in the second array region, and a second upper electrode disposed on the second MTJ, wherein the first upper electrode and the second upper electrode contain different nitrogen-to-titanium ratios.

[0005] Another embodiment of the present invention discloses a magnetoresistive random access memory, which mainly includes a first array region and a second array region disposed on a substrate, a first magnetic tunneling junction (MTJ) disposed in the first array region, a first gap wall disposed next to the first MTJ, a second MTJ disposed in the second array region, and a second gap wall disposed next to the second MTJ, wherein the first gap wall and the second gap wall have different thicknesses. Attached Figure Description

[0006] Figures 1 to 5 This is a schematic diagram of a method for fabricating an MRAM cell according to an embodiment of the present invention;

[0007] Figure 6 This is a schematic diagram of the structure of a semiconductor element according to an embodiment of the present invention;

[0008] Figure 7 This is a schematic diagram of the structure of a semiconductor element according to an embodiment of the present invention.

[0009] Explanation of main component symbols

[0010] 12: Base

[0011] 14: MRAM region

[0012] 16: Logical Area

[0013] 18: Interlayer dielectric layer

[0014] 20: Metal interconnect structure

[0015] 22: Metal interconnect structure

[0016] 24: Intermetallic dielectric layer

[0017] 26: Metal interconnects

[0018] 28: Stop Layer

[0019] 30: Intermetallic dielectric layer

[0020] 32: Metal interconnects

[0021] 34: Barrier Layer

[0022] 36: Metal layer

[0023] 38: MTJ stacked structure

[0024] 42: Lower electrode

[0025] 44: Fixed layer

[0026] 46: Barrier Layer

[0027] 48: Free Layer

[0028] 50: Upper electrode

[0029] 52:MTJ

[0030] 56: Covering layer

[0031] 58: Interstitial wall

[0032] 60: Interstitial wall

[0033] 62: Intermetallic dielectric layer

[0034] 70: Metal interconnects

[0035] 72: Stop Layer

[0036] 74: Intermetallic Dielectric Layer

[0037] 76: Metal interconnects

[0038] 78: Stop Layer

[0039] 102: Array area

[0040] 104: Array area Detailed Implementation

[0041] Please refer to Figures 1 to 5 , Figures 1 to 5 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material may be selected from the group consisting of silicon, germanium, silicon-germanium composites, silicon carbide, gallium arsenide, etc. A MRAM region 14 and a logic region 16 are preferably defined on the substrate 12, wherein the MRAM region 14 further comprises multiple array regions, such as array region 102 and array region 104.

[0042] The substrate 12 may contain active (active) devices such as metal-oxide-semiconductor (MOS) transistors, passive (passive) devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 16 covering it. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor devices, wherein the MOS transistors may include gate structures (such as metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 18 may be disposed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric layer 18 may have multiple contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistors. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here.

[0043] Then, metal interconnect structures 20 and 22 are sequentially formed on the interlayer dielectric layer 18 to electrically connect the aforementioned contact plug. The metal interconnect structure 20 includes an intermetal dielectric layer 24 and a metal interconnect 26 embedded in the intermetal dielectric layer 24. The metal interconnect structure 22 includes a stop layer 28, an intermetal dielectric layer 30 and a metal interconnect 32 embedded in the stop layer 28 and the intermetal dielectric layer 30.

[0044] In this embodiment, each metal interconnect 26 in the metal interconnect structure 20 preferably includes a trench conductor, and the metal interconnect 32 in the MRAM region 14 of the metal interconnect structure 22 includes a via conductor. Furthermore, each metal interconnect 26 and 32 in the metal interconnect structures 20 and 22 can be embedded in the inter-metal dielectric layers 24 and 30 and / or the stop layer 28 and electrically connected to each other using a single damascene fabrication process or a double damascene fabrication process. For example, each metal interconnect 26 and 32 may further include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. Furthermore, in this example, the metal layer 36 in the metal interconnect 26 preferably contains copper, the metal layer 36 in the metal interconnect 32 preferably contains tungsten, the intermetallic dielectric layers 24 and 30 preferably contain silicon oxide such as tetraethyl orthosilicate (TEOS), and the stop layer 28 contains a nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.

[0045] Next, a lower electrode 42, an MTJ stack structure 38, an upper electrode 50, and a patterned mask (not shown) are formed on the metal interconnect structure 22. The MTJ stack structure 38 can be formed by first sequentially forming a pinned layer 44, a barrier layer 46, and a free layer 48 on the lower electrode 42. In this embodiment, the lower electrode 42 and the upper electrode 50 preferably contain conductive materials, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer 44 may contain ferromagnetic materials, such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), and cobalt (Co). Furthermore, the fixing layer 44 can also be made of an antiferromagnetic (AFM) material, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers. The barrier layer 46 can be made of an insulating material containing oxides, such as aluminum oxide (AlO). x The free layer 48 can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer 48 can be "freely" changed by an external magnetic field.

[0046] Subsequently, as Figure 2 As shown, a patterned mask is used as the mask to perform one or more etching processes to remove a portion of the upper electrode 50, a portion of the MTJ stack structure 38, a portion of the lower electrode 42, and a portion of the intermetallic dielectric layer 30 to form multiple MTJs 52 in each array region 102 and array region 104. It is worth noting that the etching process performed on the patterned upper electrode 50, MTJ stack structure 38, lower electrode 42, and intermetallic dielectric layer 30 in this embodiment may include reactive ion etching (RIE) and / or ion beam etching (IBE). Due to the characteristics of the ion beam etching process, the remaining upper surface of the intermetallic dielectric layer 30 is preferably slightly lower than the upper surface of the metal interconnect 32, and the upper surface of the intermetallic dielectric layer 30 preferably presents an arc or curved surface. In addition, when removing part of the intermetallic dielectric layer 30 using the ion beam etching process in this embodiment, it is preferable to remove part of the metal interconnects 32 at the same time, so that the metal interconnects 32 form an inclined sidewall near the junction of MTJ 52.

[0047] It should also be noted that, in this embodiment, the upper electrode 50 disposed in each array region 102, 104 is preferably made of titanium nitride, and the present invention preferably adjusts the nitrogen-to-titanium ratio in the upper electrode 50 before or after the aforementioned patterning fabrication process so that the upper electrode 50 in array region 102 and the upper electrode 50 in array region 104 have different nitrogen-to-titanium ratios. For example, the present invention can first form a patterned mask (not shown) to cover array region 104 before or after the aforementioned patterned MTJ stack structure 38 forms MTJ 52, and then use an ion implantation process to implant nitrogen ions into array region 102 or introduce nitrogen-containing gas into array region 102 in a plasma manner, and then remove the patterned mask on array region 104. In this way, the nitrogen-to-titanium ratio of the upper electrode 50 in array region 102 can be higher than that of the upper electrode 50 in array region 104. In this embodiment, the nitrogen-to-titanium ratio of the upper electrode 50 in array region 102 is between 0.3 and 1.5, with an optimal ratio of about 1.09, while the nitrogen-to-titanium ratio of the upper electrode 50 in array region 104 is between 0.3 and 1.5, with an optimal ratio of about 0.99.

[0048] According to a preferred embodiment of the present invention, the upper electrode 50 in array region 102 with a higher nitrogen-to-titanium ratio can generate a lower tunnel magnetoresistance (TMR), which is suitable for memory blocks in MRAM cells that require high speed. On the other hand, the upper electrode 50 in array region 104 with a lower nitrogen-to-titanium ratio can generate a higher tunnel magnetoresistance (TMR), which is suitable for memory blocks in MRAM cells that require high retention.

[0049] A masking layer 56 is then formed on the MTJ 52 and covers the surface of the inter-metal dielectric layer 30 of the MRAM region 14 and the logic region 16. In this embodiment, the masking layer 56 preferably comprises silicon nitride, but other dielectric materials such as, but not limited to, silicon oxide, silicon oxynitride, or silicon carbide may be selected according to the fabrication process requirements.

[0050] Then as Figure 3As shown, firstly, a portion of the masking layer 56 is removed using etch-back to form spacer walls 58 and 60 on the sidewalls of each MTJ 52. Then, an intermetallic dielectric layer 62 is formed to cover each MTJ 52 and the intermetallic dielectric layer 30 of the logic region 16. In this embodiment, the intermetallic dielectric layer 62 preferably comprises an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, such as, but not limited to, silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH). Since the top of the intermetallic dielectric layer 62 in the MRAM region 14 may be slightly higher than the top of the intermetallic dielectric layer 62 in the logic region 16 at this stage, a planarization process can be selectively performed subsequently, such as using a chemical mechanical polishing (CMP) process to remove a portion of the intermetallic dielectric layer 62 in the MRAM region 14 and the logic region 16, so that the tops of the intermetallic dielectric layer 62 in the MRAM region 14 and the logic region 16 are approximately flush.

[0051] Then as Figure 4 As shown, a pattern transfer fabrication process is performed, for example, by using a patterned mask (not shown) to remove part of the intermetallic dielectric layer 62, part of the intermetallic dielectric layer 30, and part of the stop layer 28 of the logic region 16 to form contact holes (not shown) and expose the underlying metal interconnects 26. Then, the contact holes are filled with the desired metal material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization fabrication process is performed, for example, by chemical mechanical polishing to remove part of the metal material to form contact plugs or metal interconnects 70 that electrically connect the metal interconnects 26 within the contact holes.

[0052] Subsequently, as Figure 5As shown, a stop layer 72 is first formed in the MRAM region 14 and the logic region 16, covering the intermetallic dielectric layer 62 and the metal interconnects 70. An intermetallic dielectric layer 74 is then formed on the stop layer 72. One or more photolithography and etching processes are performed to remove portions of the intermetallic dielectric layer 74, the stop layer 72, and the intermetallic dielectric layer 62 in the MRAM region 14 and the logic region 16, forming contact holes (not shown). Next, conductive material is filled into each contact hole, and a planarization process such as CMP is used to form metal interconnects 76 in the array regions 102 and 104 and the logic region 16, respectively, connecting the underlying MTJ 52 and the metal interconnects 70. Preferably, the metal interconnects 76 in the array regions 102 and 104 directly contact the underlying upper electrode 50, while the metal interconnects 76 in the logic region 16 contact the underlying metal interconnects 70. Next, another stop layer 78 is formed on the intermetal dielectric layer 70 and covers the metal interconnects 76.

[0053] In this embodiment, stop layer 72 and stop layer 78 may contain the same or different materials, both of which can be selected from the group consisting of nitrogen-doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN). As with the aforementioned metal interconnects, the metal interconnects 76 disposed within the intermetallic dielectric layer 74 can be embedded within the intermetallic dielectric layer 74 using a single damascene fabrication process or a double damascene fabrication process. For example, the metal interconnects 76 may further include a barrier layer and a metal layer, wherein the barrier layer can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. This completes the fabrication of a semiconductor element according to an embodiment of the present invention.

[0054] Please refer to again Figure 6 , Figure 6 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. Figure 6 As shown, compared to the previous embodiment where the gap walls 58 and 60 of array region 102 and array region 104 have the same thickness, the present invention can also be selected to... Figure 3When forming the spacer walls 58 and 60, the thickness of the spacer walls 58 and 60 in each array region 102 and 104 is adjusted so that the spacer walls 58 and 60 in array region 102 have different thicknesses than those in array region 104. For example, it can be selected that... Figure 3 After forming the spacer walls 58 and 60, a patterned mask (not shown) is first formed to cover the array region 102. Then, etching is used to remove part of the spacer walls 58 and 60 in the array region 104 so that their thickness is slightly lower than the thickness of each spacer wall 58 and 60 in the array region 102. After that, the patterned mask is removed, an intermetallic dielectric layer 62 is formed on the spacer walls 58 and 60, and subsequent metal interconnect fabrication processes are performed.

[0055] It should be noted that the thickness of the so-called spacer walls 58 and 60 in the two array regions 102 and 104 preferably refers to the width of the spacer walls 58 and 60 extending along the direction of the top surface of the substrate 12 or the top surface of the upper electrode 50. The thickness of each spacer wall 58 and 60 in array region 104 is preferably less than the thickness of each spacer wall 58 and 60 in array region 102, or preferably about two or three times the thickness of each spacer wall 58 and 60 in array region 104. More specifically, the thickness of each spacer wall 58 and 60 in array regions 102 and 104 is preferably between 50 angstroms and 400 angstroms, with the thickness or width of each spacer wall 58 and 60 in array region 102 preferably between 330 angstroms and 400 angstroms, or preferably about 365 angstroms, while the thickness or width of each spacer wall 58 and 60 in array region 104 is preferably between 60 angstroms and 120 angstroms, or preferably about 90 angstroms.

[0056] According to a preferred embodiment of the present invention, the upper electrode 50 in array region 102 with thicker spacer walls 58, 60 can generate lower tunnel magnetoresistance (TMR), which is suitable for memory blocks in MRAM cells that require high speed. On the other hand, the upper electrode 50 in array region 104 with thinner spacer walls 58, 60 can generate higher tunnel magnetoresistance (TMR), which is suitable for memory blocks in MRAM cells that require high retention.

[0057] Please refer to again Figure 7 , Figure 7 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. Figure 7 As shown, compared to Figure 5 The upper electrode 50 in the middle array region 102 has a different nitrogen-to-titanium ratio than the upper electrode 50 in the array region 104. Figure 6The gap walls 58 and 60 of the middle array region 102 and the gap walls 58 and 60 of the array region 104 have different thicknesses, and the present invention can optionally combine them. Figure 5 and Figure 6 The embodiments in which the upper electrodes 50 in the array regions 102 and 104 have different nitrogen-to-titanium ratios, and the gap walls 58 and 60 of the outer array regions 102 and 104 have different thicknesses, are also within the scope of this invention.

[0058] Generally, in existing magnetoresistive random access memory (MRAM), the coercivity of the free layer can be modulated by changing the critical dimension (CD) or perpendicular magnetic anisotropy (PMA) of the MTJ in different array regions. This allows different array regions or memory blocks to meet applications requiring higher speed or higher retention, thereby achieving a fusion chip with hybrid memory functionality. According to the foregoing embodiments, the present invention can adjust the nitrogen-to-titanium ratio of the upper electrode in different array regions, as in the first embodiment. This allows the upper electrode with a higher nitrogen-to-titanium ratio in the array region to generate a lower tunneling magnetoresistance (TMR) suitable for memory blocks in MRAM cells requiring higher speed, or vice versa.

[0059] Furthermore, according to the second embodiment, the present invention can select and adjust the thickness or width of the gap wall in different array regions, so that the upper electrode with a thicker gap wall in the array region generates a lower tunnel magnetoresistance (TMR) and is suitable for memory blocks in MRAM cells that require high speed, or so that the upper electrode with a thinner gap wall in the array region generates a higher tunnel magnetoresistance (TMR) and is suitable for memory blocks in MRAM cells that require high retention.

[0060] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A magnetoresistive random access memory, characterized in that, Include: The first array region and the second array region are located on the substrate; A first magnetic tunnel junction is disposed in the first array region; The first upper electrode is disposed on the first magnetic tunnel junction; A second magnetic tunnel junction is disposed in the second array region; as well as The second upper electrode is disposed on the second magnetic tunnel junction, wherein the first upper electrode and the second upper electrode contain different nitrogen-to-titanium ratios.

2. The magnetoresistive random access memory of claim 1, wherein the first upper electrode and the second upper electrode comprise titanium nitride.

3. The magnetoresistive random access memory as claimed in claim 1, wherein the nitrogen-to-titanium ratio of the first upper electrode is between 0.3 and 1.

5.

4. The magnetoresistive random access memory as claimed in claim 1, wherein the nitrogen-to-titanium ratio of the second upper electrode is between 0.3 and 1.5.

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