Multi-power-domain electrostatic discharge protection circuit

Abstract

The present invention discloses a multi-power-domain electrostatic discharge protection circuit, which is formed by connecting a clamping circuit two, a buffer two, a clamping circuit four, and a buffer four. In the buffer four, an inverter is jointly composed of an NMOS transistor Mn24 and a PMOS transistor Mp23. The source of the NMOS transistor Mn24 is connected to VSS2, the gate is connected to node 24, and the drain is connected to the drain of the PMOS transistor Mp23; the source of the PMOS transistor Mp23 is connected to VDD2, the gate is connected to node 24, and the drain is connected to the drain of the NMOS transistor Mn24 and the connection point is denoted as node 25; additionally, a first-stage inverter in the buffer four is composed of an NMOS transistor Mn21 and a PMOS transistor Mp21. The structure of the present invention reduces the risk of gate-source breakdown of the transistor and enhances the ESD protection effect.

Description

Technical Field

[0001] The present invention belongs to the technical field of electrostatic discharge (ESD) protection for integrated circuits, and relates to a multi-power-domain electrostatic discharge protection circuit. Background Art

[0002] In existing integrated circuits with multiple power domains, each power domain contains internal circuits, input or output buffers, and clamping circuits for ESD protection. The ground wires of different power domains need to be isolated by diodes connected in reverse parallel. The buffer is generally composed of several cascaded inverters. The clamping circuit is usually an RC clamping circuit, which is the most basic and common ESD protection structure between the power supply and the ground wire. Suppose power domain one generates an output signal and transmits it to power domain two. When an ESD discharge occurs from the power supply line VDD1 of power domain one to the ground wire VSS2 of power domain two, the ESD current flows from VDD1 through the clamping circuit in power domain one, reaches the ground wire VSS1 of power domain one, then flows through the isolation diode, reaches the ground wire VSS2 of power domain two, and finally flows into the external ground. During this process, since the internal circuits and buffers are in an indeterminate state, it may cause the input buffer of power domain two to receive a high voltage, that is, the gate voltage of the NMOS transistor in this input buffer is approximately equal to the voltage of VDD1, which is the highest voltage in the entire circuit at this time; and because the source voltage of this NMOS transistor is VSS2, that is, connected to the external ground, then the voltage drop between the gate and source of this NMOS transistor is the largest voltage drop in the entire circuit, making this NMOS transistor the most easily failed device [1]. At the same time, when a discharge event occurs from the power supply line VDD2 of power domain two to VSS1, the PMOS transistor in the input buffer of power domain two becomes the most easily failed device. This kind of ESD event where the power supply line of one power domain discharges to the ground wire of another power domain is one of the most threatening situations in the multi-power-domain ESD category, and such problems need to be solved urgently.

[0003] To improve the ability of multi-power-domain ESD protection, there are various methods available. One of them is to improve the design of the buffers for inputs or outputs. The literature [1] (i.e., Cheng-Yun Hsueh, Ming-Dou Ker. Stacking-MOS Protection Design for Interface Circuits Against Cross-Domain CDM ESD Stresses. IEEE Transactions on Electron Devices, 2021) proposed a method of device stacking on the first inverter at the interface. This method utilizes device stacking. During an ESD event, the gate oxide capacitances and drain / substrate reverse-biased pn junctions of different devices are stacked, thereby reducing the voltage division on the gate oxide and further reducing the risk of breakdown. However, the effect of reducing the voltage stress on the device by series-parasitic capacitance voltage division is "slight" (see the original text on page 5 of [1]: "Note that, compared with the reference design, the proposed Type-A, Type-B, and Type-C designs have a slight voltage-divided effect"). Therefore, there is an urgent need to develop a new type of multi-power-domain ESD protection circuit to significantly reduce the voltage stress on the device during the above-mentioned cross-power-domain ESD event, thereby improving the ESD protection level. Summary of the Invention

[0004] The object of the present invention is to provide a multi-power-domain electrostatic discharge protection circuit, which solves the problem that the electrostatic discharge protection circuit of the prior art has poor ESD protection effect due to unreasonable design.

[0005] The technical solution adopted by the present invention is a multi-power-domain electrostatic discharge protection circuit, which is formed by connecting a clamping circuit two, a buffer two, a clamping circuit four, and a buffer four. The specific connection method is as follows:

[0006] Buffer four includes several inverters. Among them, an NMOS transistor Mn24 and a PMOS transistor Mp23 together form an inverter. The source of the NMOS transistor Mn24 is connected to VSS2, the gate is connected to node 24, and the drain is connected to the drain of the PMOS transistor Mp23. The source of the PMOS transistor Mp23 is connected to VDD2, the gate is connected to node 24, and the drain is connected to the drain of the NMOS transistor Mn24, and the connection point is denoted as node 25. Additionally, an NMOS transistor Mn21 and a PMOS transistor Mp21 form the first-stage inverter in buffer four. The source of the NMOS transistor Mn21 is connected to VSS2, the gate is connected to node 21 output from power domain one, and the drain is connected to the drain of the PMOS transistor Mp21. The source of the PMOS transistor Mp21 is connected to node 25, the gate is connected to node 21, and the drain is connected to the drain of the NMOS transistor Mn21.

[0007] The beneficial effect of the present invention is that when an ESD event occurs where discharge occurs from the power supply line VDD1 of power domain one to the ground line VSS2 of power domain two, the voltage difference between node 21 and VSS2 (i.e., the gate-source voltage of the NMOS transistor Mn21) decreases. When an ESD event occurs where discharge occurs from the power supply line VDD2 of power domain two to the ground line VSS1 of power domain one, the voltage difference between node 25 and node 21 (i.e., the gate-source voltage of the PMOS transistor Mp21) decreases. The above results mean that the risk of gate-source breakdown of the NMOS transistor Mn21 and the PMOS transistor Mp21 decreases, and the ESD protection effect is enhanced. Description of the Drawings

[0008] Figure 1 is a multi-power-domain ESD protection circuit diagram of the prior art;

[0009] Figure 2 is a schematic diagram of discharge from the power supply line (VDD1) of the power domain of the output signal to the ground line (VSS2) of the power domain receiving the signal in the multi-power-domain ESD protection circuit of the prior art;

[0010] Figure 3 is a schematic diagram of discharge from the power supply line (VDD2) of the power domain receiving the signal to the ground line (VSS1) of the power domain of the output signal in the multi-power-domain ESD protection circuit of the prior art;

[0011] Figure 4 is the circuit diagram of the multi-power-domain ESD protection circuit in Document [1];

[0012] Figure 5 is the circuit diagram of the multi-power-domain ESD protection circuit of the present invention;

[0013] Figure 6 It is the simulation voltage waveform diagram of the protection circuit of the present invention for discharging between VDD1 and VSS2 under ESD events;

[0014] Figure 7 It is the simulation voltage waveform diagram of the protection circuit of the present invention for discharging between VDD2 and VSS1 under ESD events. Specific Embodiments

[0015] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0016] Referring to Figure 1 , it is the structure of a multi - power - domain ESD protection circuit in the prior art. In power domain one, a clamping circuit one, an internal circuit one, and a buffer one are connected between VDD1 and VSS1, and the output node is node 21; meanwhile, in power domain two, a clamping circuit two, an internal circuit two, and a buffer two are connected between VDD2 and VSS2, and the input node is node 21; in addition, a branch of diodes D1 and D2 in reverse parallel is provided between VSS1 and VSS2.

[0017] Referring to Figure 2 , it is the process of discharging from the power supply line (VDD1) of the output signal power domain to the ground wire (VSS2) of the receiving signal power domain in the multi - power - domain ESD protection circuit of the prior art, and its deficiencies can be referred to the relevant descriptions in the background art.

[0018] Referring to Figure 3 , it is the process of discharging from the power supply line (VDD2) of the receiving signal power domain to the ground wire (VSS1) of the receiving output power domain in the multi - power - domain ESD protection circuit of the prior art, and its deficiencies can be referred to the relevant descriptions in the background art.

[0019] Referring to Figure 4 , it is the circuit diagram of the multi - power - domain ESD protection circuit disclosed in Document [1]. Compared with the traditional structure shown in Figure 1 , the setting of PMOS transistor Mp31 and NMOS transistor Mn31 is added in power domain two. For details, see Figure Five in the original text of Document [1].

[0020] Referring to Figure 5 , the structure of the multi - power - domain ESD protection circuit of the present invention is formed by connecting a clamping circuit two, a buffer two, a clamping circuit four, and a buffer four. The specific connection method is

[0021] The clamping circuit two includes a first RC network (resistor-capacitor network), a first inverter, and a first discharge tube. Among them, the first RC network is formed by connecting capacitor C1 and resistor R1 in series. One end of capacitor C1 is connected to VSS1, the other end of capacitor C1 is connected to resistor R1, the other end of resistor R1 is connected to VDD1, and the common connection point of capacitor C1 and resistor R1 is denoted as node 13; the first inverter is composed of NMOS transistor Mn13 and PMOS transistor Mp13. The source of NMOS transistor Mn13 is connected to VSS1, the gate is connected to node 13, and the drain is connected to the drain of PMOS transistor Mp13 and denoted as node 14; the source of PMOS transistor Mp13 is connected to VDD1, the gate is connected to node 13, and the drain is connected to the drain of NMOS transistor Mn13; the first discharge tube uses NMOS transistor Mn14. The source of NMOS transistor Mn14 is connected to VSS1, the drain is connected to VDD1, and the gate is connected to node 14;

[0022] The buffer two includes several inverters. Figure 4 In the embodiment, two-stage inverters are provided. That is, NMOS transistor Mn12 and PMOS transistor Mp12 form the penultimate-stage inverter in buffer two. The source of NMOS transistor Mn12 is connected to node 14, the gate is connected to the output signal of internal circuit one and denoted as node 11, and the drain is connected to the drain of PMOS transistor Mp12 and denoted as node 12; the source of PMOS transistor Mp12 is connected to VDD1, the gate is connected to the gate of NMOS transistor Mn12, and the drain is connected to node 12; at the same time, NMOS transistor Mn11 and PMOS transistor Mp11 form the last-stage inverter in buffer two. The source of NMOS transistor Mn11 is connected to VSS1, the gate is connected to node 12, and the drain is connected to the drain of PMOS transistor Mp11 and denoted as node 21, which is used as the output signal of power supply domain one and output to buffer four of power supply domain two; the source of PMOS transistor Mp11 is connected to VDD1, the gate is connected to node 12, and the drain is connected to node 21; the source of PMOS transistor Mp14 is connected to VDD1, the gate is connected to node 13, and the drain is connected to node 12;

[0023] The clamping circuit four includes a second RC network, a second inverter, and a second discharge transistor. Among them, the second RC network is formed by connecting capacitor C2 and resistor R2 in series. One end of capacitor C2 is connected to VSS2, the other end of capacitor C2 is connected to resistor R2, the other end of resistor R2 is connected to VDD2, and the common connection point of capacitor C2 and resistor R2 is denoted as node 23. The second inverter is composed of NMOS transistor Mn22 and PMOS transistor Mp22. The source of NMOS transistor Mn22 is connected to VSS2, the gate is connected to node 23, and the drain is connected to the drain of PMOS transistor Mp22 and denoted as node 24. The source of PMOS transistor Mp22 is connected to VDD2, the gate is connected to node 23, and the drain is connected to the drain of NMOS transistor Mn22. The second discharge transistor uses NMOS transistor Mn23. The source of NMOS transistor Mn23 is connected to VSS2, the drain is connected to VDD2, and the gate is connected to node 24.

[0024] The buffer four also includes several inverters. Among them, the inverter composed of NMOS transistor Mn24 and PMOS transistor Mp23 is a newly added structure of the present invention. The source of NMOS transistor Mn24 is connected to VSS2, the gate is connected to node 24, and the drain is connected to the drain of PMOS transistor Mp23. The source of PMOS transistor Mp23 is connected to VDD2, the gate is connected to node 24, and the drain is connected to the drain of NMOS transistor Mn24 and the connection point is denoted as node 25. The first-stage inverter in buffer four is composed of NMOS transistor Mn21 and PMOS transistor Mp21. The source of NMOS transistor Mn21 is connected to VSS2, the gate is connected to node 21 output from power domain one, and the drain is connected to the drain of PMOS transistor Mp21. The source of PMOS transistor Mp21 is connected to node 25, the gate is connected to node 21, and the drain is connected to the drain of NMOS transistor Mn21.

[0025] The structure of the present invention is improved on the basis of the traditional ESD protection architecture. The traditional ESD protection architecture mainly refers to a clamping circuit containing a resistor-capacitor network (i.e., RC network), an inverter, and a large NMOS transistor in each power domain, and isolation diodes (D1 / D2) are set between the ground wires of different power domains. The power domain one of the present invention contains clamping circuit two, and the power domain two contains clamping circuit four.

[0026] Compared with the prior art, the innovation points of the present invention are as follows: First, to cope with the ESD event from VDD1 to VSS2, a PMOS transistor Mp14 is inserted between the last two inverters of buffer two, and the source connection relationship of the NMOS transistor Mn12 is changed. That is, the source of the PMOS transistor Mp14 is connected to VDD1, the drain is connected to node 12 in the buffer, and the gate is connected to node 13 in clamp circuit two; the source of the NMOS transistor Mn12 is connected to node 14 in clamp circuit two. Second, to cope with the ESD event from VDD2 to VSS1, an inverter composed of an NMOS transistor Mn24 and a PMOS transistor Mp23 is added, and the source of the PMOS transistor Mp21 in buffer four is no longer connected to VDD2. That is, the source of the NMOS transistor Mn24 is connected to VSS2, the gate is connected to node 24 in clamp circuit four, the drain is connected to the drain of the PMOS transistor Mp23, and the connection point is node 25; the source of the PMOS transistor Mp23 is connected to VDD2, the gate is connected to node 24, and the drain is connected to node 25; the source of the PMOS transistor Mp21 is connected to node 25.

[0027] It should be emphasized that the body potential of the PMOS transistor Mp21 in the present invention is not connected to the power supply (VDD1 or VDD2), but is connected to its own source and then to a non-power supply node, that is, the PMOS transistor Mp21 needs to be self-isolated; for the other NMOS transistors involved in the present invention, their body potentials are all grounded (VSS1 or VSS2), and for the other PMOS transistors involved, their body potentials are all connected to the power supply line (VDD1 or VDD2).

[0028] The working principle of the circuit protected by the present invention is as follows:

[0029] First, when an ESD event from VDD1 to VSS2 occurs (VDD1 is at a high level and VSS2 is grounded), the voltage of VDD1 rises rapidly, the first RC network in clamp circuit two generates a response, node 13 is at a low level, node 14 is at a high level, and the NMOS transistor Mn14 in the first discharge tube conducts. Therefore, the ESD current flows from VDD1 through the NMOS transistor Mn14 into VSS1, and then through the diode D1 into VSS2. Since node 13 and node 14 are at a low level and a high level respectively, the pull-down path of node 12 is turned off by the NMOS transistor Mn13, and the PMOS transistor Mp14 plays a pull-up role and pulls node 12 up to a high level. Therefore, node 21 is at a low level, that is, the same potential as VSS1. At this time, the gate-source voltage of the NMOS transistor Mn21 is the voltage drop across the diode D1, and this voltage drop is significantly lower than the voltage drop from VDD1 to VSS2, indicating that the circuit of the present invention can effectively protect the NMOS transistor Mn21 from being broken down.

[0030] The above effects can be further illustrated by the following simulations. Through the characteristic simulation verification of the traditional structure circuit, the circuit in Document [1], and the circuit of the present invention under the same 0.18-μm process, except for the devices added due to their respective special designs, the parameters of other devices in the three circuits are the same. The applied conditions are that the VDD1 voltage rises from 0 to 10 V in 0.2 ns and then remains, while VSS2 is grounded. The simulation results are the node voltages, as Figure 6 shown. The node 21 of the traditional structure circuit remains at 10 V, that is, the gate-source voltage of the NMOS transistor Mn21 is 10 V; the node 21 in the circuit of the present invention remains at 3.8 V, that is, the gate-source voltage of the NMOS transistor Mn21 is 3.8 V; in the circuit of Document [1], the node 21 is 10 V, and the node Vn is about 0.7 V, that is, the gate-source voltage of the NMOS transistor Mn21 is about 9.3 V. Therefore, the NMOS transistor Mn21 in the circuit of the present invention is subjected to the minimum voltage stress, indicating that it can better reduce the risk of ESD damage and provide the ESD protection level.

[0031] Second, when an ESD event from VDD2 to VSS1 occurs (VDD2 is at a high level and VSS1 is grounded), the VDD2 voltage rises rapidly, the second RC network in the clamping circuit four generates a response, the node 23 is at a low level, the node 24 level is high, and the discharge tube NMOS transistor Mn23 is turned on. Therefore, the ESD current flows from VDD1 through the NMOS transistor Mn23 into VSS2, and then through the diode D2 into VSS1. Since the node 24 is at a high level, then the node 25 is at a low level, that is, the source voltage of the PMOS transistor Mp21 is the voltage of VSS2. Therefore, the source-gate voltage of the PMOS transistor Mp21 is the voltage drop across the diode D2, and this voltage is significantly less than the voltage drop from VDD2 to VSS1, indicating that the circuit of the present invention can effectively protect the PMOS transistor Mp21 from being broken down.

[0032] The above effects can be further illustrated by the following simulations. Through the characteristic simulation verification of the traditional structure circuit, the circuit in Document [1], and the circuit of the present invention under the same 0.18-μm process, except for the devices added due to their respective special designs, the parameters of other devices in the three circuits are the same. The applied conditions are that the VDD2 voltage rises from 0 to 10 V in 0.2 ns and then remains, while VSS1 is grounded. The simulation results are the node voltages, as Figure 7As shown. In the circuit of Document [1], since the gate voltage of PMOS transistor Mp31 is low, PMOS transistor Mp31 is turned on, pulling up the source voltage (node Vp) of PMOS transistor Mp21 to VDD2 (10V); in the circuit of the present invention, the source voltage (node 25) of PMOS transistor Mp21 is maintained at 3.8V. The source voltage of PMOS transistor Mp21 in the traditional structure circuit is obviously VDD2 (10V). Also, the voltage of node 21 is mainly determined by the state of power supply domain 1. Since the state of power supply domain 1 in the three circuits is the same at this time, the voltages of node 21 (i.e., the gate of PMOS transistor Mp21) in the three circuits are also basically the same. It can be seen that the source-gate voltage of PMOS transistor Mp21 in the circuit of the present invention is the smallest, indicating that it can better reduce the risk of ESD damage and provide the ESD protection level.

[0033] In summary, the multi-power-supply-domain ESD protection circuit of the present invention can better reduce the voltage stress on the device under ESD events, thereby improving the ESD protection level.

Claims

1. A multi-power-domain electrostatic discharge protection circuit, characterized in that: It is formed by connecting a clamping circuit II, a buffer II, a clamping circuit IV, and a buffer IV. The specific connection method is as follows: The clamping circuit II includes a first RC network, a first inverter, and a first discharge transistor. Among them, the first RC network is formed by connecting a capacitor C1 and a resistor R1 in series. One end of the capacitor C1 is connected to VSS1, the other end of the capacitor C1 is connected to the resistor R1, the other end of the resistor R1 is connected to VDD1, and the common connection point of the capacitor C1 and the resistor R1 is denoted as node 13; the first inverter is composed of an NMOS transistor Mn13 and a PMOS transistor Mp13. The source of the NMOS transistor Mn13 is connected to VSS1, the gate is connected to node 13, and the drain is connected to the drain of the PMOS transistor Mp13 and denoted as node 14; the source of the PMOS transistor Mp13 is connected to VDD1, the gate is connected to node 13, and the drain is connected to the drain of the NMOS transistor Mn13; the first discharge transistor uses an NMOS transistor Mn14. The source of the NMOS transistor Mn14 is connected to VSS1, the drain is connected to VDD1, and the gate is connected to node 14; The buffer II includes several inverters. When set to two-stage inverters, that is, the NMOS transistor Mn12 and the PMOS transistor Mp12 form the penultimate-stage inverter in the buffer II. The source of the NMOS transistor Mn12 is connected to node 14, the gate is connected to the output signal of the internal circuit I and denoted as node 11, and the drain is connected to the drain of the PMOS transistor Mp12 and denoted as node 12; the source of the PMOS transistor Mp12 is connected to VDD1, the gate is connected to the gate of the NMOS transistor Mn12, and the drain is connected to node 12; at the same time, the NMOS transistor Mn11 and the PMOS transistor Mp11 form the last-stage inverter in the buffer II. The source of the NMOS transistor Mn11 is connected to VSS1, the gate is connected to node 12, and the drain is connected to the drain of the PMOS transistor Mp11 and denoted as node 21, which is used as the output signal of power supply domain I and output to the buffer IV of power supply domain II; the source of the PMOS transistor Mp11 is connected to VDD1, the gate is connected to node 12, and the drain is connected to node 21; the source of the PMOS transistor Mp14 is connected to VDD1, the gate is connected to node 13, and the drain is connected to node 12; The described clamping circuit four includes a second RC network, a second inverter, and a second discharge transistor. Among them, the second RC network is formed by connecting capacitor C2 and resistor R2 in series. One end of capacitor C2 is connected to VSS2, the other end of capacitor C2 is connected to resistor R2, the other end of resistor R2 is connected to VDD2, and the common connection point of capacitor C2 and resistor R2 is denoted as node 23; the second inverter is composed of NMOS transistor Mn22 and PMOS transistor Mp22. The source of NMOS transistor Mn22 is connected to VSS2, the gate is connected to node 23, and the drain is connected to the drain of PMOS transistor Mp22 and denoted as node 24; the source of PMOS transistor Mp22 is connected to VDD2, the gate is connected to node 23, and the drain is connected to the drain of NMOS transistor Mn22; the second discharge transistor uses NMOS transistor Mn23. The source of NMOS transistor Mn23 is connected to VSS2, the drain is connected to VDD2, and the gate is connected to node 24; Buffer four includes several inverters. Among them, an inverter is jointly composed of NMOS transistor Mn24 and PMOS transistor Mp23. The source of NMOS transistor Mn24 is connected to VSS2, the gate is connected to node 24, and the drain is connected to the drain of PMOS transistor Mp23; the source of PMOS transistor Mp23 is connected to VDD2, the gate is connected to node 24, and the drain is connected to the drain of NMOS transistor Mn24 and the connection point is denoted as node 25; additionally, the first-stage inverter in buffer four is composed of NMOS transistor Mn21 and PMOS transistor Mp21. The source of NMOS transistor Mn21 is connected to VSS2, the gate is connected to node 21 output from power domain one, and the drain is connected to the drain of PMOS transistor Mp21; the source of PMOS transistor Mp21 is connected to node 25, the gate is connected to node 21, and the drain is connected to the drain of NMOS transistor Mn21.

2. The multi-power-domain electrostatic discharge protection circuit according to claim 1, wherein: The body potential of the described PMOS transistor Mp21 is not connected to power supply VDD1 or VDD2, but is connected to its own source and then connected to a non-power supply node.

3. The multi-power-domain electrostatic discharge protection circuit according to any one of claims 1-2, characterized in that: The body potential of each NMOS transistor is grounded to VSS1 or VSS2, and for each PMOS transistor other than PMOS transistor Mp21, its body potential is connected to power supply line VDD1 or VDD2.

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