Counting device

Abstract

This invention provides a counting device that can improve operating speed. The counting device includes multiple counting circuit stages and a first logic operation circuit. The counting circuit stages are connected in series sequentially. The first counting circuit stage performs a counting operation according to a first clock signal and generates a first-level counting result. The second to Nth counting circuit stages perform counting operations according to a second clock signal, where N is a positive integer greater than 2. The first logic operation circuit provides the first-level counting result as the second clock signal according to an indication signal.

Description

Technical Field

[0001] This invention relates to a counting device, and more particularly to a counting device that can increase working speed. Background Technology

[0002] In the application of counting devices, an initial value can be set for the counting device. Then, during the counting operation, the counting device can operate according to the clock signal and output the counting result of multiple bits.

[0003] In common knowledge, a counting device can be programmed with a target value as the counting endpoint. The logic circuitry within the device is activated; as the clock signal oscillates, the circuitry performs calculations on the decreasing count, and outputs a counting termination signal when the target value is reached. In such applications, if the clock signal frequency is too high (period too short), and the logic circuitry's calculation speed cannot keep up with generating the counting termination signal, the counting device will malfunction. Summary of the Invention

[0004] This invention relates to a counting device that can effectively increase the operating frequency.

[0005] According to an embodiment of the present invention, the counting device includes a plurality of counting circuit stages and a first logic operation circuit. The counting circuit stages are sequentially connected in series, wherein the first counting circuit stage performs a counting operation according to a first clock signal and generates a first-level counting result. The second to Nth counting circuit stages perform counting operations according to a second clock signal, where N is a positive integer greater than 2. The first logic operation circuit is coupled to the plurality of counting circuit stages and provides the first-level counting result as the second clock signal according to an indication signal.

[0006] Based on the above, the present invention operates the first-stage counting circuit according to a relatively high-frequency first clock signal, and then downclocks the first clock signal to generate a second clock signal. The subsequent second-stage to Nth-stage counting circuits then operate according to a lower-frequency second clock signal. In this way, the counting device of the present invention can generate the counting result based on the first clock signal without errors due to the computational circuit not being able to operate in time, effectively improving the speed of the counting device. Attached Figure Description

[0007] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0008] Figure 1This is a schematic diagram of a counting device according to an embodiment of the present invention;

[0009] Figure 2 This is a circuit diagram of multiple counting circuit stages of the counting device according to an embodiment of the present invention;

[0010] Figure 3 This is a component symbol diagram of the flip-flop in the counting circuit stage of an embodiment of the present invention;

[0011] Figure 4 This is a schematic diagram of the logic operation circuit of the counting device according to an embodiment of the present invention;

[0012] Figure 5 This is a circuit diagram of the logic operation circuit used to generate a counting termination signal in the counting device in an embodiment of the present invention;

[0013] Figure 6A as well as Figure 6B The following are waveform diagrams of the counting actions performed by the counting device according to different initial values ​​in the embodiments of the present invention.

[0014] Explanation of icon numbers

[0015] 100: Counting device;

[0016] 111~11N, 211~217: Counting circuit stage;

[0017] 120, 400, 500: Logic operation circuits;

[0018] CK: Clock input;

[0019] CK1: First clock signal;

[0020] CK2: Second clock signal;

[0021] CNT <0> ~CNT <n-1>: Counting results;

[0022] CNTB <1> ~CNTB <6> : Reverse counting result;

[0023] D: Data terminal;

[0024] DEL: Delay unit;

[0025] FF1~FF7, FFx, DFF1, DFF51, DFF52: flip-flops;

[0026] i0~i6: Initial values;

[0027] Ini: Initial end;

[0028] IV1~IV9, IV41~IV45, IV51: Inverters;

[0029] ND1~ND4, ND41, ND42, ND51, ND52: NAND gates;

[0030] NO1, NO2, NO3, NO51: NOR gate;

[0031] OR1, OR41: OR gates;

[0032] Q: Output terminal;

[0033] R: Reset terminal;

[0034] RST: Reset signal;

[0035] RUN: Indicator signal;

[0036] RUNX: Indicator signal receiver;

[0037] SRUN: Synchronization indicator signal;

[0038] STP: Counting stop signal;

[0039] T1~T4: Time points;

[0040] X1~X6: Anti-mutually exclusive OR gates. Detailed Implementation

[0041] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0042] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a counting device according to an embodiment of the present invention. The counting device 100 includes multiple counting circuit stages 111-11N and a logic operation circuit 120. The counting circuit stages 111-11N are connected in series and coupled in sequence. The first stage counting circuit stage 111 receives a first clock signal CK1 and performs a counting operation according to the first clock signal CK1 to generate a first stage counting result CNT. <0> The logic operation circuit 120 is coupled to the counting circuit stages 111~11N. The first-stage counting circuit stage 111 transmits the first-stage counting result CNT. <0> To the logic operation circuit 120. The logic operation circuit 120 and the first-stage counting result CNT <0> And the indicator signal RUN to provide the first-stage counting result CNT <0> This generates the second clock signal CK2.

[0043] In counting circuit stages 111 to 11N, the second-stage counting circuit stage 112 to the Nth-stage counting circuit stage 11N all receive the second clock signal CK2. The second-stage counting circuit stage 112 to the Nth-stage counting circuit stage 11N performs counting operations according to the second clock signal CK2, and generates the second counting result to the Nth counting result CNT respectively. <1> ~CNT <n-1>The frequency of the second clock signal CK2 is lower than the frequency of the first clock signal CK1.

[0044] In this embodiment, the logic operation circuit 120 can determine the first-level counting result CNT based on the indication signal RUN. <0> To determine whether the second clock signal CK2 is equal to the first-stage counting result CNT <0> Or the first clock signal CK1. Wherein, when the indicator signal RUN is at the first logic level, the logic operation circuit 120 can provide the first-level counting result CNT. <0> The second clock signal CK2 is used as the second clock signal. Conversely, when the indicator signal RUN is at the second logic level, the logic operation circuit 120 can provide the first clock signal CK1 as the second clock signal CK2. Additionally, the counting circuit stages 111~11N receive the indicator signal RUN and are activated to perform accelerated counting operations when the indicator signal RUN is at the first logic level. In this embodiment, the first logic level can be logic 1 or logic 0, and the second logic level can be logic 0 or logic 1.

[0045] In this embodiment, the counting circuit stages 111-11N can be configured as synchronous counters. The counting circuit stages 111-11N can each receive multiple initial values ​​at an initial time point. These initial values ​​are used to set the counting start point of the counting device 100. The counting circuit stages 111-11N then perform a decrementing counting operation from this counting start point during the counting process. The counting operation of the counting circuit stages 111-11N can be performed from the first level counting result to the Nth level counting result CNT. <0> ~CNT <n-1>The process ends when the value equals a default value.

[0046] It is noteworthy that in this embodiment, only the first-stage counting circuit 111, corresponding to the least significant bit, performs counting based on a first clock signal CK1 with a relatively high frequency, while the counting operations of the remaining second-stage counting circuit 112 to the Nth-stage counting circuit 11N are all based on a first clock signal CK2 with a relatively low frequency. Therefore, errors caused by the peripheral arithmetic circuits being unable to process the count due to an excessively high frequency clock signal can be effectively avoided. Consequently, the counting device 100 can produce a correct counting result CNT. <0> ~CNT <n-1>Under the premise of this, the speed of counting can be effectively improved.

[0047] Please refer to Figure 2 as well as Figure 3 ,in Figure 2 This is a circuit diagram of multiple counting circuit stages of the counting device according to an embodiment of the present invention. Figure 3 This is a component symbol diagram of the flip-flop in the counting circuit stage of an embodiment of the present invention. Figure 2 In the counting device 200, there are counting circuit stages 211-217. The first-stage counting circuit stage 211 receives a first clock signal CK1 and performs counting operations according to the first clock signal CK1. In this embodiment, the first-stage counting circuit stage 211 includes a flip-flop FF1 and an inverter IV1. Please refer to [reference needed]. Figure 3 , Figure 2 The circuit symbols for the flip-flops FF1~FF7 in the embodiment can be as follows: Figure 3 The flip-flop FFx is shown. FFx has a clock input CK, a reset input R, an initial input ini, an indicator signal receiver RUNX, a data input D, and an output Q. FFx can receive the operating frequency via the clock input CK; receive the initial value for initialization via the initial input ini; receive the indicator signal RUN via the indicator signal receiver RUNX; receive the reset signal via the reset input R; and generate the counting result via the output Q.

[0048] Please refer to the above again. Figure 2 In the first-stage counting circuit stage 211, the initial terminal of the flip-flop FF1 receives the initial value i0; the clock terminal of the flip-flop FF1 receives the first clock signal CK1; the indicator signal receiving terminal of the flip-flop FF1 receives the indicator signal RUN; the data terminal of the flip-flop FF1 is coupled to the output terminal of the inverter IV1; and the output terminal of the flip-flop FF1 generates the first-stage counting result CNT. <0> In this embodiment, the flip-flop FF1 can be configured as a frequency divider and used to divide the frequency of the first clock signal CK1 by 2 to produce the first-stage counting result CNT. <0> .

[0049] Furthermore, the second-stage counting circuit 212 includes a flip-flop FF2, an inverse OR gate X1, and inverters IV2 and IV3. The inverse OR gate X1 has a first input terminal to receive the second-stage counting result CNT. <1> It also has a second input terminal to receive the logic operation result generated based on the counting result of the previous stage. Specifically, in the second-stage counting circuit 212, the second input terminal of the anti-mutex OR gate X1 receives the first-stage counting result CNT generated by the inverter IV2. <0> The inverse signal. The output of the anti-mutex OR gate X1 is then coupled to the data terminal of the flip-flop FF2.

[0050] Furthermore, the initial terminal of the flip-flop FF2 receives the initial value i1; the clock terminal of the flip-flop FF2 receives the second clock signal CK2; the indicator signal receiving terminal of the flip-flop FF2 receives the indicator signal RUN; and the output terminal of the flip-flop FF2 generates the second-stage counting result CNT. <1> Furthermore, inverter IV3 is coupled to the output of inverter FF2 to generate the second-stage inverse counting result CNTB. <1> .

[0051] In this embodiment, the third-stage counting circuit 213 includes a flip-flop FF3, an inverse OR gate X2, and inverters IV4 and IV5. The inverse OR gate X2 has a first input terminal to receive the third-stage counting result CNT. <2> It also has a second input terminal to receive the logic operation result generated based on the counting result of the previous stage. Specifically, in the third-stage counting circuit stage 213, the second input terminal of the anti-mutex OR gate X2 receives the first-stage counting result CNT generated by the inverter IV4 and the NOR gate NO1. <0> And the second-level counting result CNT <1> The result of the OR operation. The output of the anti-mutex OR gate X2 is then coupled to the data terminal of the flip-flop FF3.

[0052] In addition, the initial terminal of the flip-flop FF3 receives the initial value i2; the clock terminal of the flip-flop FF3 receives the second clock signal CK2; the indicator signal receiving terminal of the flip-flop FF3 receives the indicator signal RUN; and the output terminal of the flip-flop FF3 generates the third-stage counting result CNT. <2> Inverter IV5 is coupled to the output of flip-flop FF3 to generate the second-stage inverted counting result CNTB. <2> .

[0053] The circuit architecture of the fourth-stage counting circuit 214 to the seventh-stage counting circuit 217 is similar to that of the fourth-stage counting circuit 213, and related details will not be elaborated further. The fourth-stage counting circuit 214 to the seventh-stage counting circuit 217 respectively include flip-flops FF4~FF7, inverse OR gates X3~X6, and inverters IV6~IV9. Furthermore, the inverse OR gate X3 receives multiple counting results from the previous stage (the first-stage counting result CNT) through NAND gate ND1 and NOR gate NO1. <0> The third-level count result CNT <2> The logical operation result of ); the anti-mutex OR gate X4 receives multiple previous stage count results (first stage count result CNT) through NAND gate ND2, NOR gate NO2 and NOR gate NO1. <0> The fourth-level count result CNT <3> The logical operation result of ); the anti-mutex OR gate X5 receives multiple previous stage count results (first stage count result CNT) through NAND gate ND3, NOR gate NO1 and NOR gate NO2. <0> The fifth level of counting results CNT <4> The logical operation result of ); the anti-mutex OR gate X6 receives multiple previous stage count results (first stage count result CNT) through NAND gate ND4, NOR gates NO1, NO2 and NO3. <0> The sixth level of counting results CNT <5> The result of logical operations.

[0054] Incidentally, inverters IV6 to IV9 respectively generate the fourth-stage reverse counting result CNTB. <3> CNTB up to the seventh level reverse counting result <6> The flip-flops FF4~FF7 perform initialization actions according to their initial values ​​i3~i6 respectively.

[0055] In this embodiment, the flip-flops FF1 to FF7 can be JK type flip-flops.

[0056] The counting circuit stages 211~217 can perform synchronous counting operations and obtain the counting start point according to the initial values ​​i0~i6 at the initial time point. The flip-flop FF1 performs a decrementing counting operation according to the first clock signal CK1, while the flip-flops FF2~FF7 perform a decrementing counting operation according to the second clock signal CK2, starting from the counting start point.

[0057] Please refer to the following: Figure 4 , Figure 4 This is a schematic diagram of the logic operation circuit of the counting device according to an embodiment of the present invention. The logic operation circuit 400 is used to provide a second clock signal CK2 according to the indication signal RUN. The logic operation circuit 400 includes a flip-flop DFF1, inverters IV41~IV45, NAND gates ND41 and ND42, an OR gate OR41, and a delay circuit DEL. The flip-flop DFF1 is a D-type flip-flop that receives the indication signal RUN and synchronizes it with the indication signal RUN according to the first clock signal CK1, generating a synchronization indication signal SRUN. Additionally, the flip-flop DFF1 can perform a reset operation according to the reset signal RST. Inverters IV41 and IV42 are connected in series between the output of the flip-flop DFF1 and one input of the NAND gate ND41. The other input of the NAND gate ND41 receives the first-stage counting result CNT. <0> The NAND gate ND41 is used for the synchronization indicator signal SRUN and the first-stage counting result CNT. <0> A NAND operation is performed, and the result is transmitted to the NAND gate ND42 via the series-connected inverters IV43 and IV44 and the delay unit DEL. Specifically, when the synchronization indicator signal SRUN is at logic level 1, the first-stage counting result CNT... <0> After being delayed, the signal can be transmitted to one input of the NAND gate ND42. Conversely, when the synchronization indicator signal SRUN is at logic level 0, the delay unit DEL transmits logic level 1 to the NAND gate ND42.

[0058] On the other hand, OR gate OR41 receives the first clock signal CK1 and the synchronization indicator signal SRUN. When the synchronization indicator signal SRUN is at logic level 1, the first clock signal CK1 can be shielded and not transmitted to NAND gate ND42. Conversely, if the synchronization indicator signal SRUN is at logic level 0, the first clock signal CK1 can be transmitted to NAND gate ND42.

[0059] Continuing from the above explanation, when the synchronization indicator signal SRUN is at logic level 1, the NAND gate ND42 can output the first-stage counting result CNT. <0> The inverted signal, through inverter IV45, makes the second clock signal CK2 substantially synchronized with the first-stage counting result CNT. <0> The same. Conversely, when the synchronization indicator signal SRUN is at logic level 0, the NAND gate ND42 outputs the inverted signal of the first clock signal CK1, and through the inverter IV45, the second clock signal CK2 can be made substantially the same as the first clock signal.

[0060] Please refer to the following: Figure 5 , Figure 5 This is a circuit diagram of a logic operation circuit in a counting device used to generate a counting stop signal in an embodiment of the present invention. In this embodiment, the counting device may also be equipped with a logic operation circuit 500 to generate a counting stop signal STP. The counting stop signal STP is used to indicate that the counting operation of the counting device has been completed. The application circuits downstream of the counting device can perform various required operations based on the counting stop signal.

[0061] correspond Figure 2 In this embodiment, the counting device 200 has its counting termination point set, for example, at the second-level counting result CNT. <1> The CNT count result up to the seventh level <6> These represent logic levels 1, 0, 0, 0, 0, and 0, respectively. The logic operation circuit 500 includes an inverter IV51, NAND gates ND51 and ND52, a NOR gate NO51, and flip-flops DFF51 and DFF52. The inverter IV51, NAND gate ND51 and ND52, and NOR gate NO51 are used to calculate the second-stage inverse counting result CNTB. <1> CNTB up to the seventh level reverse counting result <6> Perform logical operations, and when the second-level counting result is CNT <1> The CNT count result up to the seventh level <6> When the logic levels are 1, 0, 0, 0, 0, and 0 respectively, the NOR gate NO51 generates an output signal of logic level 1. This output signal of logic level 1 can be synchronized with flip-flops DFF51 and DFF52 according to the first clock signal CK1 to generate a counting stop signal STP. In addition, flip-flops DFF51 and DFF52 can perform a reset operation according to the reset signal RST.

[0062] It is worth mentioning that in this embodiment, the designer can set the required counting termination point and change the inverter IV51, NAND gates ND51 and ND52, and NOR gate NO51 in the logic expression required for the set counting termination point. The relevant logic expressions and the corresponding logic gate settings are well known to those skilled in the art and will not be described in detail here.

[0063] Please refer to Figure 6A as well as Figure 6B , Figure 6A as well as Figure 6B The following are waveform diagrams showing the counting actions performed by the counting device according to different initial values ​​in embodiments of the present invention. Figure 6A In the middle, corresponding Figure 2 The counting device 200 of the embodiment receives an initial value i6-i0 with a hexadecimal value of 38 as the starting point for counting, and initiates the counting operation at time point T1. At time point T1, the seventh-level counting result CNT... <6> The second-level counting result CNT <1> The hexadecimal value is 1c, and the reverse count result of the seventh level is CNTB. <6> CNTB, the reverse counting result to the second level <1> The hexadecimal value is 23, and the first-level count result is CNT. <0> It is logic level 0.

[0064] After time point T1, the first-level count result CNT <0> Based on the state transition of the first clock signal CK1, the second-level counting result CNT <1> The CNT count result up to the seventh level <6> Then, based on the first-level counting result CNT <0> Transition. First-level counting result CNT <0> The CNT count result up to the seventh level <6> The digital value can be decreased sequentially with the first clock signal CK1. At time T2, the first-stage count result CNT <0> The CNT count result up to the seventh level <6> The count termination signal STP is equal to the set termination time point, therefore, the count termination signal STP is pulled up to logic level 1, and the counting operation of the counting device 200 can be stopped.

[0065] exist Figure 6B In the middle, the corresponding Figure 2 The counting device 200 of the embodiment receives an initial value i6-i0 with a hexadecimal value of 39 as the starting point for counting, and initiates the counting operation at time point T3. At time point T3, the seventh-level counting result CNT is... <6> The second-level counting result CNT <1> The hexadecimal value is 1c, and the reverse count result of the seventh level is CNTB. <6> CNTB, the reverse counting result to the second level <1> The hexadecimal value is 23, and the first-level count result is CNT. <0> It represents logic level 1.

[0066] After time point T3, the first-level count result CNT <0> Based on the state transition of the first clock signal CK1, the second-level counting result CNT <1> The CNT count result up to the seventh level <6> Then, based on the first-level counting result CNT <0> Transition. First-level counting result CNT <0> The CNT count result up to the seventh level <6> The digital value can be decreased sequentially with the first clock signal CK1. At time T4, the first-stage count result CNT <0> The CNT count result up to the seventh level <6> The count termination signal STP is equal to the set termination time point, therefore, the count termination signal STP is pulled up to logic level 1, and the counting operation of the counting device 200 can be stopped.

[0067] Depend on Figure 6A as well as Figure 6B As can be seen from the waveform, the counting device of this embodiment can complete the counting action under the relatively high-speed first clock signal CK1, and will not cause errors due to the logic operation circuit not having enough time to perform the calculation.

[0068] It is worth mentioning that, Figure 6A as well as Figure 6B In the waveforms, the counting device always performs a decrementing counting action. However, within the scope of this invention, the counting device is not limited to performing a decrementing counting action. Based on the various embodiments and descriptions of the present invention, those skilled in the art will readily develop a counting device that performs an incrementing counting action according to the same concept.

[0069] Based on the above, the present invention operates the first-stage counting circuit according to a relatively high-frequency first clock signal, thus maintaining the normal counting behavior of the counting device. The present invention also downclocks the first clock signal to generate a second clock signal, and then operates the subsequent second-stage counting circuits up to the Nth stage according to a lower-frequency second clock signal. In this way, the counting device of the present invention does not produce errors due to the arithmetic circuit not being able to operate in time, effectively improving the speed of the counting device.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A counting device, comprising: Multiple counting circuit stages are connected sequentially. The first stage of the counting circuit stage performs a counting operation according to a first clock signal and generates a first-level counting result. The second to Nth stages of the counting circuit stage perform a counting operation according to a second clock signal, where N is a positive integer greater than 2. The multiple counting circuit stages jointly receive an indication signal, and the second to Nth stages of the counting circuit stage jointly receive the second clock signal. as well as A first logic operation circuit, coupled to the plurality of counting circuit stages, provides the counting result of the first stage as the second clock signal based on the indication signal. The first logic operation circuit is characterized in that, when the indication signal is at a first logic level, it makes the first-level counting result the second clock signal, and when the indication signal is at a second logic level, it makes the first clock signal the second clock signal.

2. The counting device according to claim 1, characterized in that, The frequency of the second clock signal is lower than the frequency of the first clock signal.

3. The counting device according to claim 1, characterized in that, The multiple counting circuit stages form a synchronous counter.

4. The counting device according to claim 1, characterized in that, The multiple counting circuit stages receive multiple initial values ​​at the initial time point, and set the counting start point of the counting device according to the multiple initial values.

5. The counting device according to claim 1, characterized in that, Also includes: The second logic operation circuit receives the first-level counting result and the second-level counting results to the Nth-level counting results generated by the counting circuit stages of the second level to the Nth level respectively. The second logic operation circuit performs logic operations based on the first-level counting results to the Nth-level counting results to generate a counting termination signal.

6. The counting device according to claim 1, characterized in that, The first logic operation circuit includes: A flip-flop receives the indication signal and generates a synchronization indication signal based on the first clock signal to synchronize the indication signal. The first NAND gate performs a NAND operation on the synchronization indication signal and the first-level counting result to generate a first signal; Delay unit, which delays the first signal to generate the second signal; An OR gate is used to perform an OR operation on the synchronization indication signal and the first clock signal to generate a third signal; and The second NAND gate performs a NAND operation on the second signal and the third signal to generate the second clock signal.

7. The counting device according to claim 1, characterized in that, The first stage of the counting circuit includes: Inverter; and A flip-flop has a data terminal coupled to the output terminal of the flip-flop, the output terminal of the flip-flop generates the first-stage counting result and is coupled to the input terminal of the flip-flop, the clock terminal of the flip-flop receives the first clock signal, the flip-flop is activated according to the indication signal to perform a counting operation, and the initial signal terminal of the flip-flop receives an initial value.

8. The counting device according to claim 1, characterized in that, Each of the second-level counting circuit stage to the Nth-level counting circuit stage includes: An anti-mutex OR gate has one input to receive the current stage count result and another input to receive the logical operation result generated based on multiple previous stage count results; and A flip-flop has a data terminal coupled to the output of the inverse OR gate, the output of the flip-flop generates the current-level count result and is coupled to the input of the inverse OR gate, the clock terminal of the flip-flop receives a second clock signal, the flip-flop is activated according to the indication signal to perform a counting operation, and the initial signal terminal of the flip-flop receives an initial value; and An inverter, coupled to the output of the flip-flop, generates an inverse current count result based on the current count result.

9. The counting device according to claim 1, characterized in that, The plurality of counting circuit stages perform a decrementing counting action according to the indication signal.

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