Instruction execution method, execution engine, processor, chip and electronic device

Abstract

The embodiment of the present application provides an instruction execution method, an execution engine, a processor, a chip and an electronic device, wherein the method comprises the following steps: inputting data of a plurality of instructions into the execution engine through a plurality of pipelines, one pipeline inputting data of one instruction; logical operation units in the execution engine are divided into a plurality of logical operation groups, and one logical operation group is configured for one pipeline to be used alone; data input by each pipeline is selected to the logical operation group configured for each pipeline, so that each logical operation group performs logical operation on the data input by each pipeline; and logical operation results of each logical operation group are output. The embodiment of the present application can reduce the degree of waste of data bit width resources of the logical operation unit, and improve the resource utilization rate of the logical operation unit.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of processor, in particular to an instruction execution method, an execution engine, a processor, a chip and an electronic device. BACKGROUND

[0002] To improve the performance of the processor, the processor can use superscalar architectures to improve the instruction set parallelism of the processor. Superscalar architectures can be considered as a kind of processor design, and the processor using superscalar architectures (referred to as superscalar processor) can execute multiple instructions in one clock cycle.

[0003] When the execution engine of the superscalar processor executes instructions, the logical operation unit in the execution engine can perform logical operations on the data of the instructions (referred to as the data of the instructions) to start the operation. At this time, how to improve the resource utilization of the logical operation unit has become a technical problem that needs to be solved by those skilled in the art. SUMMARY

[0004] Therefore, embodiments of the present application provide an instruction execution method, an execution engine, a processor, a chip and an electronic device to improve the resource utilization of the logical operation unit.

[0005] To achieve the above object, embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present application provides an instruction execution method, comprising:

[0007] The data of multiple instructions input by multiple pipelines is selected and given to the logical operation groups configured for the pipelines, so that each logical operation group performs logical operations on the data input by each pipeline;

[0008] The data input by each pipeline is selected and given to the logical operation groups configured for the pipelines, so that each logical operation group performs logical operations on the data input by each pipeline;

[0009] The logical operation results of each logical operation group are output.

[0010] In a second aspect, an embodiment of the present application provides an execution engine, comprising: a data selector and a logical operation unit; the logical operation unit is divided into multiple logical operation groups, and one logical operation group is configured for a pipeline to be used alone;

[0011] The execution engine acquires the data of multiple instructions input by multiple pipelines in an instruction emission stage, and one pipeline inputs the data of one instruction;

[0012] The data selector is configured to select the data input by each pipeline to the logic operation group configured for the corresponding pipeline.

[0013] The logic operation group is configured to perform logic operation on the data input by the corresponding pipeline and output the logic operation result.

[0014] In a third aspect, an embodiment of the present application provides a processor, including the execution engine as described above.

[0015] In a fourth aspect, an embodiment of the present application provides a chip, including the processor as described above.

[0016] In a fifth aspect, an embodiment of the present application provides an electronic device, including the chip as described above.

[0017] The instruction execution method provided by the embodiment of the present application can divide the logic operation unit in the execution engine into multiple logic operation groups, and one logic operation group is configured for one pipeline to use individually; on this basis, the data of multiple instructions can be input into the execution engine through multiple pipelines, and one pipeline inputs the data of one instruction; based on the configuration relationship between the pipeline and the logic operation group, the data input by each pipeline can be selected to the logic operation group configured for the pipeline, so that each logic operation group performs logic operation on the data input by each pipeline; and then the embodiment of the present application can output the logic operation result of each logic operation group to complete instruction execution.

[0018] It can be seen that in the case of dividing the logic operation unit into multiple logic operation groups, each pipeline supporting logic operation in the processor can use one logic operation group individually to perform logic operation on data; therefore, after the data input by each pipeline is selected to the logic operation group configured correspondingly, multiple logic operation groups can process the data input by multiple pipelines in parallel; and different logic operation groups correspond to different data bit width ranges in the logic operation unit, so that the data bit width resources in different ranges in the logic operation unit can be processed in parallel to process the data input by multiple pipelines, so that the data bit width resources in the logic operation unit are fully utilized, and the degree of idle and waste of the data bit width resources in the logic operation unit is reduced, and the resource utilization rate of the logic operation unit is improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only only the embodiments of the present application, and for those skilled in the art, other drawings can be obtained on the premise of not paying creative labor according to the provided drawings.

[0020] Figure 1 An example diagram for two pipelines to occupy logical operation units respectively.

[0021] Figure 2 Another example diagram for two pipelines to occupy logical operation units respectively.

[0022] Figure 3A An example diagram for resource grouping of logical operation units.

[0023] Figure 3B An example diagram for a unit execution unit of a logical operation unit.

[0024] Figure 3C A method flow diagram for dividing a logical operation unit into a logical operation group.

[0025] Figure 3D An example diagram for a logical operation group of a logical operation unit.

[0026] Figure 4 A flow diagram of an instruction execution method.

[0027] Figure 5A A system architecture diagram for implementing instruction execution.

[0028] Figure 5B Another system architecture diagram for implementing instruction execution.

[0029] Figure 5C Still another system architecture diagram for implementing instruction execution.

[0030] Figure 6 An example diagram for implementing an instruction execution method.

[0031] Figure 7 Another flow diagram of an instruction execution method.

[0032] Figure 8 Another example diagram for implementing an instruction execution method. DETAILED DESCRIPTION

[0033] With reference to the drawings and embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0034] After instruction decoding, the superscalar processor can transmit the decoded instructions (also referred to as microinstructions) to the execution engine for execution in a multi-issue manner. That is, in the same instruction transmission period, multiple pipelines can input data of multiple instructions to the execution engine. The instructions referred to herein can be SIMD (Single Instruction Multiple Data) instructions. The SIMD is a technology for improving data-level parallelism, that is, a single instruction can be used to perform the same operation on multiple data. That is, the superscalar processor using the SIMD technology can use a single instruction to start the same operation on multiple data, thereby improving the instruction execution efficiency of the processor and reducing the energy consumption of the processor.

[0035] During instruction execution, the logic operation unit in the execution engine can perform logic operation on the data input by the pipeline. In order to save the area of the superscalar processor, a complete set of functional logic operation units is not configured for each pipeline, but a logic operation unit with only part of the function is configured for each pipeline, or multiple pipelines compete for the hardware resources of the same logic operation unit, so as to process the data input by multiple pipelines. For example, the logic operation unit is allocated a clock period for exclusive use by the pipeline, so that multiple pipelines respectively occupy the logic operation unit for data processing in the respective clock periods. The embodiments of the present application mainly optimize the case where multiple pipelines compete for the hardware resources of the same logic operation unit.

[0036] For ease of understanding, two pipelines are taken as an example, Figure 1 An example diagram in which two pipelines respectively occupy the logic operation unit is shown. As Figure 1 shown, data 101 and data 102 are data for instruction start operation, for example, two data for the same operation operation started by the SIMD instruction, and data 101 is input to the execution engine through the pipeline 111, and data 102 is input to the execution engine through the pipeline 112.

[0037] In the execution engine, the logic operation unit 113 is occupied by the pipeline 111 and the pipeline 112 respectively, so the input data of the pipeline 111 and the pipeline 112 need to be controlled by the pipeline selection signal, and after data selection by the data selector 114, the input data is input into the logic operation unit 113; that is, the data 101 input by the pipeline 111 and the data 102 input by the pipeline 112 need to be selected by the data selector 114 and then input into the logic operation unit 113;

[0038] When multiple pipelines occupy the logic operation unit, the logic operation unit can be used as a whole and allocated to a pipeline for exclusive use in one clock cycle; that is, the data selector selects the data input by a pipeline in one clock cycle and sends the data into the logic operation unit for processing; therefore, the data selector 114 can select the data 101 input by the pipeline 111 or the data 102 input by the pipeline 112 to the logic operation unit 113 based on the pipeline to which the logic operation unit 113 is allocated for exclusive use in the current clock cycle; for example, the logic operation unit 113 is allocated to the pipeline 111 for exclusive use in the current clock cycle, so the data selector 114 can select the data 101 to the logic operation unit 113 for logic operation; after the logic operation unit 113 completes the logic operation of the data 101, the data selector 114 can select the data 102 to the logic operation unit 113 for logic operation. That is, in the case where the logic operation unit cannot be pipelined, the delay of the logic operation unit in processing the data input by the next pipeline is determined by the time for the logic operation unit to complete the logic operation; for example, assuming that the logic operation unit is a divider for performing division operation and the divider cannot be pipelined, the time for the divider to complete the division operation is 11 clock cycles, so the delay of the divider in processing the data input by the next pipeline is 11 cycles; it should be noted that the specific delay value here is only an example.

[0039] It can be understood that when multiple pipelines occupy the logic operation unit, if the logic operation unit is used by a pipeline for exclusive use in one clock cycle, when the data bit width of the data input by the pipeline is lower than the data bit width of the logic operation unit (for example, the data input by the pipeline is lower than the maximum data bit width supported by the logic operation unit), the calculation resources of the high-bit data bit width in the logic operation unit will be wasted, resulting in a problem of low resource utilization of the logic operation unit.

[0040] It should be noted that instructions (such as SIMD instructions) may require operations on data with different data bit widths. Therefore, the arithmetic logic unit (ALU) needs to support logical operations on data with different bit widths. For example, if the width of a single-precision floating-point number is 32 bits (one bit is considered one byte) and the width of a floating-point register is 256 bits, then the ALU may need to process instructions with a 32-bit data width (one single-precision floating-point bit width), instructions with a 64-bit data width (two single-precision floating-point bits), instructions with a 128-bit data width (four single-precision floating-point bits), and instructions with a 256-bit data width (eight single-precision floating-point bits). Accordingly, the ALU needs to support logical operations on floating-point data with 32-bit, 64-bit, 128-bit, and 256-bit data widths. Based on this, if the logic unit processes only one pipeline input data in one clock cycle, and the data bit width of the pipeline input data is lower than the data bit width of the logic unit, the high-bit data bit width resources of the logic unit will be idle, resulting in low resource utilization of the logic unit.

[0041] In one example, Figure 1 Based on this, taking a logic operation unit that supports 256-bit data width logic operations and two pipelines that each input two 128-bit data as an example, Figure 2 Another example diagram is shown, illustrating two pipelines each occupying a logic unit, in conjunction with... Figure 1 and Figure 2 As shown, the data width of the logic operation unit 113 is 256 bits. The data 101 input to pipeline 111 is 128 bits, and the data 102 input to pipeline 112 is 128 bits. When data 101 and data 102 are input to the data selector 114, if the logic operation unit 113 is allocated to pipeline 111 for single use in the current clock cycle, the data selector 114 selects data 101 for the logic operation unit 113 to perform logical operations. At this time, the logic operation unit 113 uses the lower 128 bits of data width resources to perform logical operations on data 101, while the higher 128 bits of data width resources in the logic operation unit 113 will be idle.

[0042] After the logic operation unit 113 completes the logical operation on data 101, the data selector 114 can select data 102 for the logic operation unit 113 to perform logical operations. Thus, the logic operation unit 113 uses the lower 128 bits of its data width resource to perform logical operations on data 102, while the higher 128 bits of its data width resource remain idle. In other words, the logic operation unit 113 uses the lower 128 bits of its data width resource to process data 101 and data 102 respectively, while the higher 128 bits of its data width resource are wasted.

[0043] As can be seen from the foregoing description, in the case that multiple pipelines compete for the hardware resources of the same logical operation unit, if the logical operation unit as a whole can only be used by one pipeline at a time (such as one clock cycle), when the data bit width of the pipeline input data is lower than the data bit width of the logical operation unit, the data bit width resources of the logical operation unit will be left unused, resulting in a problem of low resource utilization of the logical operation unit.

[0044] Based on this, the embodiments of the present application provide an improved instruction execution scheme, by grouping the resources of the logical operation unit, so as to divide the logical operation unit into multiple logical operation groups, and one logical operation group is configured for one pipeline to use alone; so that the multiple pipelines configured with logical operation groups can simultaneously use the respective configured logical operation groups (i.e. multiple pipelines can simultaneously reuse the logical operation unit, rather than using the logical operation unit alone in different clock cycles), thereby ensuring that the data bit width resources of the logical operation unit can be fully utilized, achieving the effect of improving the resource utilization of the logical operation unit.

[0045] Based on the above idea, the embodiments of the present application can divide the logical operation unit into multiple logical operation groups, and one logical operation group is configured for one pipeline to use alone, wherein the number of logical operation groups can be less than or equal to the number of pipelines in the processor; for example, in the case that one logical operation group is configured for one pipeline to use alone, the number of multiple logical operation groups divided from the logical operation unit can be less than or equal to the number of pipelines in the superscalar processor. In one example, taking the number of pipelines in the superscalar processor as 4 as an example, the logical operation unit can be divided into 4 logical operation groups, and one logical operation group is configured for one pipeline to use alone, so that the 4 pipelines are all configured with logical operation groups; in another example, the logical operation unit can also be divided into 2 logical operation groups, the 2 logical operation groups can be configured for two of the 4 pipelines, and one logical operation group is configured for one pipeline to use alone, while the other two of the 4 pipelines can not be configured with logical operation groups. As an optional implementation, the embodiments of the present application can set the number of logical operation groups, and set the number of logical operation groups to be equal to or less than the number of pipelines, and then the embodiments of the present application can divide the logical operation unit into multiple logical operation groups according to the set number of logical operation groups.

[0046] As an optional implementation, Figure 3A An example diagram showing the grouping of resources of the logical operation unit is shown as follows: Figure 3AAs shown, the logic operation unit 113 can be divided into n logic operation groups 311 to 31n, and one logic operation group is configured for one pipeline to use individually, and each logic operation group can perform logic operation on data through the divided data bit width resource, and the divided n logic operation groups can be equal to or less than the number of pipelines in the superscalar processor.

[0047] In one example, if the number of the divided logic operation groups of the logic operation unit corresponds to the number of pipelines in the processor, the embodiment of the present application can divide the data bit width resource of the logic operation unit 113 into multiple groups according to the number of pipelines in the processor, so as to obtain multiple logic operation groups corresponding to the number of pipelines. In the embodiment of the present application, one logic operation group can be configured for one pipeline to use individually, so that the data input of each pipeline configured with the logic operation group can be logically operated through the individually used logic operation group.

[0048] In some embodiments, in the optional implementation of dividing the logic operation unit into multiple logic operation groups, the embodiment of the present application can obtain the multiple logic operation groups of the divided logic operation unit by combining the unit execution units of the logic operation unit. It should be noted that the logic operation unit can be formed by multiple unit execution units which are independent and repeated, and the unit execution unit can be considered as a unit bit width logic operation circuit forming the logic operation unit, and multiple repeated unit bit width logic operation circuits can form the logic operation unit. That is, the logic operation unit as a circuit for performing logic operation can be formed by multiple independent and repeated unit circuits, and the unit circuit here can be understood as the unit execution unit described above.

[0049] It should be noted that the unit bit width of the unit execution unit can be considered as the minimum bit width of the logic operation unit which can independently complete data operation; for example, a unit bit width logic operation circuit can be the minimum bit width logic operation circuit for the logic operation unit to perform data operation, and each unit bit width logic operation circuit can independently complete the logic operation of a single data.

[0050] In one example, Figure 3B An example of the unit execution unit of the logic operation unit is shown as follows, Figure 3B As shown, taking the data bit width of the logic operation unit as 256 bits and the data bit width of the unit execution unit as 32 bits as an example (that is, one 32-bit data bit width unit execution unit can independently complete the logic operation of one 32-bit data), the logic operation unit can be formed by 8 32-bit unit execution units; for example, the data bit width of the unit execution unit performing division operation in the single precision floating point divider is 32 bits, and the 256-bit single precision floating point divider can be formed by 8 32-bit unit execution units.

[0051] It should be noted that the 32-bit data width per unit of execution is merely an example. The specific value of the data width per unit of execution can be determined according to the actual situation. For example, for 32-bit single-precision instructions (such as SIMD instructions), the data width (i.e., unit width) of the unit of execution in the arithmetic logic unit (ALU) can be no less than 32 bits; while for double-precision 64-bit instructions (such as SIMD instructions), the data width per unit of execution in the ALU can be no less than 64 bits. It should be further noted that the ALU can support the processing of various floating-point data formats, such as single-precision floating-point data (32 bits per data point) and double-precision floating-point data (64 bits per data point). This means that for a 256-bit instruction (such as a SIMD instruction), if processing single-precision floating-point data, it contains 8 data points; if processing double-precision floating-point data, it contains 4 data points.

[0052] As an optional implementation, based on multiple execution units forming a logic operation unit, embodiments of this application can combine the execution units to obtain multiple logic operation groups with a number equal to or less than the number of pipelines of the processor. For example, when the number of multiple logic operation groups is equal to the number of pipelines of the processor, embodiments of this application can combine the execution units according to the multiple execution units of the logic operation unit and the number of pipelines of the processor to obtain multiple logic operation groups with a number corresponding to the number of pipelines of the processor. In embodiments of this application, a logic operation group can be regarded as a combination of several execution units, and correspondingly, the data width of a logic operation group can be the sum of the data widths of the combined execution units.

[0053] As an optional implementation Figure 3C An exemplary flowchart of an optional method for dividing a logic operation unit into logic operation groups, provided in an embodiment of this application, is illustrated. Optionally, this method can be implemented during the processor design phase (e.g., the superscalar processing design phase); in other possible implementations, the method can be implemented during processor operation, for example, the processor can dynamically adjust the connections and links between hardware circuits to divide the logic operation unit into multiple logic operation groups.

[0054] Reference Figure 3C The method process may include the following steps.

[0055] In step S31, multiple unit execution units of the logic operation unit are determined. Each unit execution unit supports logical operations on data with a unit bit width, where the unit bit width is the data bit width of the unit execution unit.

[0056] A logic operation unit can be formed by multiple execution units. The data bit width of one execution unit can be called the unit bit width of the logic operation unit, and one execution unit can support logical operations on data of unit bit width. For example, a single-precision floating-point divider can be formed by multiple execution units that perform division operations, and one execution unit supports division operations on 32-bit data. In the embodiments of this application, multiple execution units forming a logic operation unit can be determined. For example, a 256-bit divider is formed by eight 32-bit execution units that perform division operations.

[0057] In step S32, the unit execution units are combined according to the number of logical operation groups to obtain multiple logical operation groups with a number equal to or less than the number of pipeline lines; wherein, the data bit width of a logical operation group is the sum of the data bit widths of the combined unit execution units.

[0058] After determining multiple execution units of the logic operation unit, based on the set number of logic operation groups (equal to or less than the number of pipelines), this embodiment can combine the execution units to obtain multiple logic operation groups with a number equal to or less than the number of pipelines of the processor. Then, one logic operation group can be configured for use by a single pipeline supporting the logic operation. For example, this embodiment can set the number of logic operation groups, and set the number of logic operation groups to be equal to or less than the number of pipelines. Therefore, this embodiment can combine the execution units of the logic operation unit according to the number of logic operation groups to obtain multiple logic operation groups.

[0059] Optionally, when the number of logical operation groups is set to be equal to the number of pipelines of the processor, the embodiments of this application can combine the unit execution units based on the number of pipelines of the processor, thereby obtaining a number of logical operation groups corresponding to the number of pipelines of the processor.

[0060] A logical operation group in this application embodiment can be obtained by combining several unit execution units. By combining unit execution units, multiple logical operation groups with a number equal to or less than the number of pipelines of the processor can be obtained.

[0061] In some embodiments, the number of execution units in each logical operation group may be the same (corresponding to the same number of data bits in each logical operation group), or different (corresponding to different numbers of data bits in each logical operation group), or the number of execution units in some logical operation groups may be the same, and the number of execution units in some logical operation groups may be different.

[0062] Optionally, in the optional implementation of combining unit execution units to obtain multiple logical operation groups, the embodiments of this application can determine the number of unit execution units corresponding to a logical operation group (i.e., the number of unit execution units required to combine to obtain a logical operation group) based on the number of logical operation groups and the number of multiple unit execution units, thereby combining the unit execution units of the combined number into a logical operation group, so as to obtain multiple logical operation groups with a number equal to or less than the number of pipelines by combining multiple unit execution units in the logical operation unit.

[0063] In one implementation example, the present application embodiment can divide the number of unit execution units by the number of logical operation groups (the number of logical operation groups can correspond to the number of pipelines supporting the logical operations of the logical operation groups, which can be less than or equal to the number of pipelines in the processor) to obtain the number of combinations of unit execution units corresponding to a logical operation group; thereby combining the combined number of unit execution units into a logical operation group to obtain multiple logical operation groups.

[0064] For ease of understanding, in Figure 3B Based on the example, let's take two pipelines input data as an example. Figure 3D An example diagram illustrating the logical operation grouping of the logical operation unit is shown, such as... Figure 3D As shown, a 256-bit logic unit can be formed by eight 32-bit unit execution units, based on two pipeline lines. This example can be configured with two logic operation groups; thus, the number of unit execution units corresponding to one logic operation group is four. That is, in this example, four unit execution units are combined to obtain a 128-bit logic operation group; furthermore, this example can combine the first four unit execution units into one logic operation group and the last four unit execution units into another logic operation group.

[0065] As an optional implementation, when combining a number of unit execution units into a logical operation group, the embodiments of this application may sequentially combine the number of unit execution units into a logical operation group in the logical operation unit (e.g., according to the bit width order of the unit execution units in the logical operation unit), so that multiple logical operation groups are obtained through multiple unit execution units in the logical operation unit. Therefore, the data bit widths of the multiple logical operation groups can be arranged sequentially (e.g., sequentially increasing or decreasing); furthermore, the data bit width ranges of the multiple logical operation groups are different, for example, there are logical operation groups with low-bit data widths and logical operation groups with high-bit data widths among the multiple logical operation groups. In one example, combined with... Figure 3DAs shown, when the execution units are combined sequentially according to the data bit width, the logical operation group obtained by combining the first 4 execution units can be a logical operation group with a low data bit width (e.g., a logical operation group with a low 128 bits), while the logical operation group obtained by combining the last 4 execution units can be a logical operation group with a high data bit width (e.g., a logical operation group with a high 128 bits).

[0066] Furthermore, after dividing the logic operation group into multiple logic operation groups, the embodiments of this application can configure one logic operation group for use by a pipeline alone, so that multiple pipelines configured with logic operation groups in the superscalar processor each have their own logic operation groups for independent use, providing a basis for multiple pipelines to reuse logic operation units at the same time and use their respective logic operation groups.

[0067] In some embodiments, the present application embodiments can configure a logical operation group to be used alone by a pipeline in the same order, according to the pipeline order and the logical operation group order; of course, the present application embodiments can also support configuring logical operation groups and pipelines out of order, as long as it is ensured that a logical operation group is configured to be used by a pipeline.

[0068] By dividing the logic operation unit into multiple logic operation groups and configuring separate logic operation groups for each pipeline that supports logic operations, the embodiments of this application can process the data input by the corresponding pipeline by each logic operation group during the instruction execution stage, thereby improving the resource utilization of the logic operation unit when multiple logic operation groups in the logic operation unit are fully used by multiple pipelines.

[0069] As an optional implementation Figure 4 An exemplary flowchart of an optional instruction execution method provided in an embodiment of this application is shown. (Refer to...) Figure 4 The method process may include the following steps.

[0070] In step S41, multiple instruction data are input into the execution engine through multiple pipelines, with one instruction data input into each pipeline; the logic operation unit in the execution engine is divided into multiple logic operation groups, and one logic operation group is configured for use by one pipeline alone.

[0071] In this embodiment, multiple pipelines can input data for multiple instructions into the execution engine, while one pipeline inputs data for one instruction. The data can be used to initiate computation by the instruction. In one example, the instruction that initiates data computation can be a SIMD instruction. A SIMD instruction can initiate the same computational operation on multiple data items with a single instruction. For example, multiple SIMD instructions can be issued simultaneously, so data from different SIMD instructions can be input into the execution engine through different pipelines. Thus, multiple pipelines can input instructions for multiple SIMD instructions into the execution engine, while one pipeline inputs data for one SIMD instruction. Multiple data items that are computed by a single SIMD instruction can be input into the execution engine through one pipeline. Alternatively, during the instruction issuance stage, based on a multi-issue method, multiple pipelines can input data for multiple instructions into the execution engine, and one pipeline can input data for one instruction.

[0072] Based on the preceding description, the execution engine includes logic operation units (LOUs) for performing logical operations. These LEUs are divided into multiple logical operation groups (the number of these groups can be less than or equal to the number of pipelines in the processor), and each logical operation group is assigned to a single pipeline for exclusive use. The method for dividing the LEU into multiple logical operation groups can be found in the relevant sections above and will not be repeated here.

[0073] In step S42, the data input to each pipeline is selected and assigned to the logic operation group configured for each pipeline, so that each logic operation group can perform logic operations on the data input to each pipeline.

[0074] A pipeline uses configured logical operation groups to perform logical operations on data. For data input from multiple pipelines, the execution engine can select input data for each logical operation group based on the configuration relationship between the pipeline and the logical operation group (i.e., a pipeline has a configured, separately used logical operation group). Thus, the execution engine can select the logical operation group configured for each pipeline based on the data input from each pipeline, and then each logical operation group can perform logical operations on the data input from the corresponding configured pipeline.

[0075] In some embodiments, the data selector in the execution engine can perform the above-described operation of selecting the logical operation group configured for each pipeline from the data input to each pipeline. Alternatively, data from multiple pipeline inputs can be passed to the data selector, so that the data selector can select the logical operation group configured for each pipeline from the data input to each pipeline based on the configuration relationship between the pipelines and the logical operation groups.

[0076] For ease of understanding, Figure 5AAn exemplary diagram illustrates an optional system architecture for implementing instruction execution according to an embodiment of this application, such as... Figure 5A As shown, multiple pipelines 111 to 11n input data. During the instruction issue phase, data 101 to 10n can be input into the execution engine through multiple pipelines 111 to 11n; wherein, pipeline 111 inputs data 101, pipeline 112 inputs data 102, and so on, pipeline 11n inputs data 10n; the data 101 to 10n input from multiple pipelines 111 to 11n can be passed to the data selector 114 of the execution engine;

[0077] When the logic operation unit 113 of the execution engine is divided into multiple logic operation groups 311 to 31n, one logic operation group can be configured for use by a single pipeline. For example, logic operation group 311 is configured for use by pipeline 111, logic operation group 312 is configured for use by pipeline 112, and so on, with logic operation group 31n configured for use by pipeline 11n. Thus, after the data selector 114 obtains the data 101 to 10n input from multiple pipelines 111 to 11n, the data selector 114 can, based on the configuration relationship between the pipeline and the logic operation group, select the data 101 input from pipeline 111 to logic operation group 311 for logical operation, select the data 102 input from pipeline 112 to logic operation group 312 for logical operation, and so on, select the data 10n input from pipeline 11n to logic operation group 31n for logical operation.

[0078] In a further implementation example, the execution engine can configure multiple data selectors, with the number of data selectors corresponding to the number of logical operation groups. Each logical operation group is configured with one data selector for data selection; thus, a data selector can pass the data input to the pipeline to the corresponding logical operation group. Optionally, Figure 5B An exemplary diagram illustrates another optional system architecture for implementing instruction execution according to an embodiment of this application, in conjunction with... Figure 5A and Figure 5B As shown, in Figure 5B In the system architecture shown, Figure 5A The data selector shown includes multiple data selectors 511 to 51n, and one data selector is configured for each logic operation group; for example, pipeline 111 and logic operation group 311 are configured with data selector 511, pipeline 112 and logic operation group 312 are configured with data selector 512, and so on, pipeline 11n and logic operation group 31n are configured with data selector 51n;

[0079] Based on this, when data from multiple instructions is input into the execution engine through multiple pipelines, one pipeline can input data to the data selector corresponding to the configured logical operation group. That is, in this embodiment, data from each pipeline can be input to the data selector corresponding to the configured logical operation group of each pipeline. For example, data 101 is input to the data selector 511 corresponding to pipeline 111 through pipeline 111, data 102 is input to the data selector 512 corresponding to pipeline 112 through pipeline 112, and so on, data 10n is input to the data selector 51n corresponding to pipeline 11n through pipeline 11n.

[0080] Furthermore, each data selector can pass the input data to the corresponding configured logic operation group, so that the logic operation group can obtain the data input by the corresponding configured pipeline and perform logic operation processing; for example, data selector 511 can pass the input data 101 to the corresponding configured logic operation group 311, data selector 512 can pass the input data 102 to the corresponding configured logic operation group 312, and so on, data selector 51n can pass the input data 10n to the corresponding configured logic operation group 31n.

[0081] It should be noted that setting multiple data selectors in this application embodiment is only one optional implementation. When configuring the pipeline and logic operation grouping relationships, this application embodiment can also use a single data selector to transmit data input from multiple pipelines to the corresponding configured logic operation group for each pipeline. For example, when setting pipeline identifiers (e.g., pipeline numbers) for pipelines and group identifiers (e.g., group numbers) for logic operation groups, the data selector can determine the pipeline identifier corresponding to the input data, and then select the data to the logic operation group corresponding to the group identifier based on the configuration relationship between the pipeline and logic operation grouping (e.g., the configuration relationship can record the correspondence between pipeline identifiers and group identifiers). It should also be noted that, as a possible implementation, when setting multiple data selectors, this application embodiment can implement the configuration relationship setting of pipelines, data selectors, and logic operation groups through the internal circuit connections of the processor.

[0082] In step S43, the logical operation results of each logical operation group are output.

[0083] After a logic operation group completes a logical operation on the data, it can output the result of the logical operation. In some embodiments, a pipeline can be configured with a corresponding result data bus. After a logic operation group completes a logical operation on the data, it can output the result of the logical operation to the result data bus corresponding to the configured pipeline.

[0084] In a further optional implementation, Figure 5C An exemplary diagram illustrates another optional system architecture for implementing instruction execution according to an embodiment of this application, in conjunction with... Figure 5B and Figure 5C As shown, in Figure 5C In the system architecture shown, multiple pipelines are configured with multiple result data buses 521 to 52n, with one pipeline corresponding to one result data bus. For example, pipeline 111 corresponds to result data bus 521, pipeline 112 corresponds to result data bus 522, and so on, with pipeline 11n corresponding to result data bus 52n. Thus, after a logic operation group completes the logical operation on the data, the logic operation group can output the result to the pipeline configured for that logic operation group. The corresponding result data bus; for example, after logic operation group 311 completes the logic operation of data 101, it can output the logic operation result to the result data bus 521 corresponding to pipeline 111. After logic operation group 312 completes the logic operation of data 102, it can output the logic operation result to the result data bus 522 corresponding to pipeline 112. And so on. After logic operation group 31n completes the logic operation of data 10n, it can output the logic operation result to the result data bus 52n corresponding to pipeline 11n.

[0085] The instruction execution method provided in this application can divide the logic operation unit in the execution engine into multiple logic operation groups, and each logic operation group can be configured for use by a single pipeline. Based on this, data for multiple instructions can be input into the execution engine through multiple pipelines, with one pipeline inputting data for one instruction. According to the configuration relationship between the pipelines and the logic operation groups, the data input to each pipeline can be selected for the logic operation group configured for that pipeline, so that each logic operation group can perform logical operations on the data input to each pipeline. Furthermore, this application embodiment can output the logical operation results of each logic operation group, thus completing instruction execution.

[0086] As can be seen, in the embodiments of this application, when the logic operation unit is divided into multiple logic operation groups, each pipeline in the processor that supports logic operations can use a single logic operation group to perform logic operations on the data. Therefore, after the data input to each pipeline is assigned to the corresponding configured logic operation group, multiple logic operation groups can process the data input to multiple pipelines in parallel. Moreover, different logic operation groups correspond to different data bit width ranges in the logic operation unit. Therefore, the data bit width resources of different ranges in the logic operation unit can be fully utilized by processing the data input to multiple pipelines in parallel, thereby reducing the degree of idle and wasted data bit width resources of the logic operation unit and improving the resource utilization rate of the logic operation unit.

[0087] It is understandable that, while maintaining the overall data width of the arithmetic unit, dividing the arithmetic unit into multiple arithmetic operation groups and configuring each arithmetic operation group for a single pipeline reduces the data width of the arithmetic unit that each pipeline can occupy. However, when the data width of the input data to a pipeline is lower than the overall data width of the arithmetic unit, the pipeline uses the corresponding configured arithmetic operation group to perform the logical operations on the data, while other arithmetic operation groups can be used by other pipelines for data operations. Therefore, it can avoid the waste of data width resources when the entire arithmetic unit is occupied by a single pipeline, and improve the resource utilization of the arithmetic unit. It can be seen that, by finely dividing the data width resources of the arithmetic unit and configuring multiple arithmetic operation groups used by multiple pipelines, the embodiments of this application can improve the overall data width resource utilization of the arithmetic unit, improve the throughput of the processor's arithmetic unit, and further improve instruction execution efficiency.

[0088] In one implementation example, assuming the data width of the logic unit is 256 bits, there are two pipelines supporting logic operations, and each pipeline takes two 128-bit data bits as input, this example is used. Figure 6 An exemplary implementation diagram of the instruction execution method according to an embodiment of this application is shown, such as... Figure 6 As shown, based on two pipelines that support logical operations (e.g., pipeline 111 and pipeline 112), a 256-bit logical operation unit can be divided into two 128-bit logical operation groups (e.g., logical operation groups 311 and 312).

[0089] In an optional implementation, based on the 32-bit data width of the unit execution unit in the logic operation unit, this embodiment of the application can combine four unit execution units with low data width in the logic operation unit into a low-bit logic operation group (e.g., logic operation group 311), thereby configuring a pipeline and a data selector for the low-bit logic operation group; and combine four unit execution units with high data width in the logic operation unit into a high-bit logic operation group (e.g., logic operation group 312), thereby configuring a pipeline and a data selector for the high-bit logic operation group; in this example, pipeline 111, data selector 511 and logic operation group 311 can be configured, and pipeline 112, data selector 512 and logic operation group 312 can be configured.

[0090] Furthermore, the data 101 input to pipeline 111 is 128 bits. Data selector 511 can transmit the 128-bit data 101 to the lower 128-bit logic operation group 311 for logic operation, so that the logic operation result of logic operation group 311 is output to the result data bus 521 corresponding to pipeline 111. Unlike the high 128-bit data width resources in the logic operation unit being idle and wasted, in this example, data selector 512 can transmit the 128-bit data 102 input to pipeline 112 to the high 128-bit logic operation group 312 for logic operation, so that the logic operation result of logic operation group 312 is output to the result data bus 522 corresponding to pipeline 112.

[0091] As can be seen from this example, the embodiments of this application can process data input from multiple pipelines in parallel by grouping multiple logic operations with different data bit width resources, thereby making full use of the data bit width resources of the logic operation unit and improving the resource utilization rate of the logic operation unit.

[0092] As an optional implementation, the data bit width of the pipeline input data and the data bit width of the logic operation group may differ as follows:

[0093] Scenario 1: The data width of the pipeline input data is smaller than the data width of the logic operation group. For example, the data width of the logic operation group is 128 bits, while the data width of the pipeline input data is 32 bits, 64 bits, etc. In this case, the logic operation groups configured for each pipeline can operate independently without affecting each other; that is, the data input to each pipeline can be processed by the logic operation groups configured for that pipeline. At this time, although there are some unused data width resources in each logic operation group, the logic operation unit can ensure resource utilization by processing the data input from multiple pipelines in parallel.

[0094] Scenario 2: The data width of the pipeline input is equal to the data width of the logic operation group. For example, the data width of the logic operation group is 128 bits, and the data width of the pipeline input is also 128 bits. In this case, the data input to each pipeline can be processed by the logic operation group configured for each pipeline, and the data width resources of each logic operation group are fully utilized. Therefore, the overall data width resources of the logic operation unit are fully utilized, which can greatly improve the resource utilization rate of the logic operation unit.

[0095] In one example, taking a logic operation group with a data width of 128 bits as an example, for cases one and two, when the logic operation unit performs 32-bit, 64-bit, and 128-bit single-precision floating-point logic operations (e.g., single-precision floating-point division), each pipeline inputs data less than or equal to 128 bits, which is then processed by the logic operation group configured for each pipeline. Furthermore, taking a logic operation unit with a data width of 256 bits as an example, the logic operation unit can simultaneously support logical operations on two single-precision floating-point data with a data width less than or equal to 128 bits. These two single-precision floating-point data can be used to initiate the operation using SIMD instructions for single-precision floating-point logic operations.

[0096] Scenario 3: The data width of the pipeline input data is greater than the data width of the logic operation group; for example, the data width of the logic operation group is 128 bits, while the data width of the pipeline input data is 256 bits. In this case, the logic operation group configured for the pipeline cannot complete the operation on the input data in one go, so the logic operation group configured for the pipeline needs to perform multiple logic operations on the data. In this case, the embodiments of this application can group the pipeline input data according to the data width of the logic operation group to obtain multiple data groups, wherein the data width of one data group is not greater than the data width of the logic operation group; then, the embodiments of this application can use the logic operation group configured for the pipeline to perform logic operations on multiple data groups sequentially, and concatenate the logic operation results of each data group to obtain the final logic operation result of the data.

[0097] For example, if the pipeline input data is 256 bits and the data width of the logic operation group is 128 bits, then the pipeline input data can be divided into two 128-bit data groups, such as a lower 128-bit data group and a higher 128-bit data group. Therefore, the corresponding logic operation group configured in the pipeline can be processed twice, performing logic operations on the lower 128-bit data group and the higher 128-bit data group sequentially to obtain the logic operation results for the lower 128-bit data group and the higher 128-bit data group, respectively. Finally, the logic operation results of the lower and higher 128-bit data groups are concatenated to obtain the final logic operation result.

[0098] Based on scenario three, as an optional implementation Figure 7 An exemplary flowchart of another optional instruction execution method provided in an embodiment of this application is shown. (Refer to...) Figure 7 The method process may include the following steps.

[0099] In step S71, data for multiple instructions are input into the execution engine through multiple pipelines. If the data bit width of the pipeline input data is greater than the data bit width of the corresponding configured logical operation group, then the pipeline input data includes multiple data groups, wherein the data bit width of one data group is not greater than the data bit width of the corresponding configured logical operation group of the pipeline.

[0100] In step S71 and Figure 4 The details related to step S41 shown are not repeated here. It should be noted that when the pipeline receives input data, if the data is larger than the data width of the corresponding configured logical operation group, the input data needs to be divided into multiple data groups, and the data width of each data group should not exceed the data width of the corresponding configured logical operation group. Alternatively, the pipeline can divide the data into multiple data groups according to the data width of the corresponding configured logical operation group, ensuring that the data width of each data group does not exceed the data width of the logical operation group.

[0101] In one example, if the pipeline input data is 256 bits, and the data width of the corresponding logic operation group configured for the pipeline is less than 256 bits (e.g., 128 bits, 64 bits, etc.), then the 256-bit pipeline input data can be divided into multiple data groups, each corresponding to a different data width range, with the data width of each data group not exceeding the data width of the logic operation group. For example, when the data width of the logic operation group is 128 bits, the 256-bit pipeline input data can be divided into two data groups: a lower 128-bit group and a higher 128-bit group. Or, when the data width of the logic operation group is 64 bits, the 256-bit pipeline input data can be divided into four data groups with sequentially increasing data widths, each data group being 64 bits. In an optional implementation, the pipeline input data can be grouped by the pipeline itself to obtain multiple data groups.

[0102] In step S72, the multiple data groups of the pipeline are sequentially selected by the logic operation groups configured for the pipeline, so that the logic operation groups configured for the pipeline perform logic operations on the multiple data groups in sequence.

[0103] When the pipeline input data includes multiple data groups, this embodiment of the application can select one data group at a time and assign it to the corresponding logic operation group configured for the pipeline, so that the logic operation group performs logic operations on one data group at a time (it can be understood that since the data bit width of a data group is not greater than the data bit width of the logic operation group, the logic operation group has sufficient data bit width resources to process one data group in one logic operation); furthermore, this embodiment of the application can select multiple data groups of the pipeline to the corresponding logic operation group multiple times, and the logic operation group performs logic operations on multiple data groups multiple times.

[0104] As an optional implementation, embodiments of this application can sequentially select multiple data groups to the logic operation group configured in the pipeline according to the data bit width order of multiple data groups, so that the logic operation group completes the logic operation of multiple data groups in sequence according to the data bit width order of multiple data groups, and performs the logic operation on one data group at a time.

[0105] In one example, assuming the data width of the logic operation group is 128 bits, and the 256 bits of data input to the pipeline are divided into two data groups of 128 bits and 128 bits respectively, then according to the data width order of the data groups, the lower 128 bits of data group can first select the logic operation group configured for the pipeline for logical operation. After the logic operation group completes the logical operation of the lower 128 bits of data group, the higher 128 bits of data group can then be selected for the logic operation group configured for the pipeline for logical operation.

[0106] As an optional implementation, pipeline data grouping can be achieved by inputting the logical operation grouping configured for the pipeline through a data selector (e.g., the data selector configured for the pipeline). For details on this, please refer to the description in the corresponding section above, which will not be repeated here.

[0107] In step S73, the logical operation results of multiple data groups obtained by logical operation grouping are concatenated to obtain the logical operation results of the pipeline input data, and the logical operation results of the output data are also output.

[0108] In some embodiments, after completing a logical operation on a data group, the logical operation group can temporarily store the logical operation result of that data group and obtain the next data group to be logically operated on from the data selector. Then, after the logical operation group completes logical operations on multiple data groups in the pipeline, it can concatenate the logical operation results of the multiple data groups to obtain the logical operation result of the data. Alternatively, in this embodiment, the logical operation results of multiple data groups can be concatenated sequentially according to the data bit width order of the data groups to obtain the logical operation result of the data.

[0109] Taking the sequential processing of two data blocks, the lower 128 bits and the higher 128 bits, by a 128-bit logic operation block as an example, after completing the logic operation on the lower 128 bits of the data block, the logic operation block can temporarily store the result of the logic operation on the lower 128 bits of the data block and obtain the next higher 128 bits of the data block to be logically operated on from the data selector; then, after the logic operation block completes the logic operation on the higher 128 bits of the data block, the results of the logic operation on the lower 128 bits and the higher 128 bits of the data block can be concatenated to obtain the final logic operation result of the pipeline input data.

[0110] Furthermore, the logical operation group can output the results of logical operations on the data to the result data bus configured accordingly in the pipeline.

[0111] As can be seen, in this embodiment of the application, when the logic operation unit is divided into multiple logic operation groups, and the data bit width of the pipeline input data is greater than the data bit width of the logic operation group, the pipeline input data can include multiple data groups, and the data bit width of one data group is not greater than the data bit width of the logic operation group. Furthermore, the logic operation group configured for the pipeline can sequentially process multiple data groups of the pipeline, and concatenate the logic operation results of multiple data groups to obtain the final logic operation result, thus realizing data processing when the data bit width of the input data is greater than that of the logic operation group. Since the data bit width of one data group is not greater than the data bit width of the logic operation group when the pipeline input data is divided into multiple data groups, when multiple logic operation groups process the input data of multiple pipelines in parallel, each logic operation group can have sufficient data bit width resources to process one data group of the pipeline in one operation, ensuring the normal progress of data operation, and at the same time, enabling the data bit width resources of each logic operation group to be used reasonably and efficiently.

[0112] In one implementation example, taking two pipelines and a 256-bit logic unit divided into two 128-bit logic operation groups as an example, when the pipeline input data is 256 bits, Figure 8 An exemplary diagram illustrating another implementation example of the instruction execution method provided in this application is shown, in conjunction with... Figure 6 and Figure 8 As shown, assuming that the input data 101 of pipeline 111 is 256 bits and the input data 102 of pipeline 112 is 256 bits, since the input data exceeds the computing resources of a 128-bit logical operation block, data 101 can be divided into a lower 128-bit data block 1011 and a higher 128-bit data block 1012 according to the 128-bit data width of the logical operation block; at the same time, data 102 can be divided into a lower 128-bit data block 1021 and a higher 128-bit data block 1022.

[0113] When performing logical operations on data 101, according to the data bit width order of data group 1011 and data group 1012, the data selector 511 configured in pipeline 111 can first transmit the lower 128 bits of data group 1011 to the corresponding logical operation group 311 configured in pipeline 111 for logical operation; after the logical operation group 311 completes the logical operation of data group 1011, it can temporarily store the logical operation result of data group 1011, and the data selector 511 can transmit the higher 128 bits of data group 1012 to the logical operation group 311 for logical operation.

[0114] It should be noted that the delay in processing data group 1012 by logic operation group 311 can be determined by the time it takes for logic operation group 311 to complete the logical operation and whether the logical operation can be piped. For example, if the logic operation group performs a division operation, and the completion time of the division operation is, for example, 11 clock cycles, and the logical operation of division cannot be piped, then after transmitting data group 1011 to logic operation group 311, data selector 511 needs to delay for 11 clock cycles before transmitting data group 1012 to logic operation group 311. It should be further noted that if the logical operation can be piped, the logic operation group can process the next data group after one clock cycle of executing the logical operation. However, logical operations such as division generally cannot be piped, so the logic operation group needs to process the next data group 11 clock cycles after completing the division operation. The 11 clock cycle delay for the divider to complete the division operation is only an example; different processor products and different operation instructions may result in different delays. In addition, compared to logical operations that can be executed in a pipelined manner, the solution provided in this application embodiment can achieve a higher resource utilization rate when logical operations cannot be executed in a pipelined manner.

[0115] Further integration Figure 6 and Figure 8 As shown, after completing the logical operation of data group 1012, logic operation group 311 can concatenate the logical operation results of data group 1011 and data group 1012, and then output them to the result data bus 521 configured in pipeline 111. It should be noted that when the logical operation is not pipelining, the delay of the logic operation group completing the logical operation of multiple data groups is determined by the number of multiple data groups and the time for the logic operation group to complete one logical operation (for example, the number of multiple data groups multiplied by the time for the logic operation group to complete one logical operation). Taking division as an example, when the logical operation is not pipelining, if it takes 11 clock cycles to complete one division operation, then the delay of one logic operation group completing the division operation of the lower 128-bit data group and the higher 128-bit data group is 22 clock cycles.

[0116] Further integration Figure 6 and Figure 8As shown, similarly, when performing logical operations on data 102, the data selector 512 configured in pipeline 112 can first transmit the lower 128 bits of data group 1021 to the corresponding logical operation group 312 configured in pipeline 112 for logical operation; after the logical operation group 312 completes the logical operation of data group 1021, it can temporarily store the logical operation result of data group 1021, and the data selector 512 can transmit the higher 128 bits of data group 1022 to the logical operation group 312 for logical operation; after the logical operation group 312 completes the logical operation of data group 1022, it can concatenate the logical operation results of data group 1021 and data group 1022, and then output them to the result data bus 522 configured in pipeline 112.

[0117] Furthermore, taking division as an example, based on the above implementation example, if the logical operation of division cannot be piped, then when performing a 256-bit single-precision floating-point division operation, the pipeline needs to divide the input data into low 128 bits and high 128 bits, and perform the division operation twice. First, the low 128 bits of data are controlled to the corresponding configured logical operation group for division. After a delay of one division operation (e.g., a delay of 11 clock cycles), the division result of the low 128 bits of data is temporarily stored, and the high 128 bits of data are controlled to the corresponding configured logical operation group for division. After a delay of one division operation, the division results of the low 128 bits and high 128 bits of data are concatenated to obtain the final division result, which is then output to the corresponding configured result data bus of the pipeline, thus completing the 256-bit single-precision floating-point division operation.

[0118] It should be noted that, in this embodiment of the application, when the data bit width of the pipeline input data is greater than the data bit width of the logic operation group, the logic operation group needs to perform logic operations multiple times. Although this increases the latency of data performing logic operations, this embodiment of the application can maintain the throughput of the logic operation unit unchanged when the data bit width of the input data is greater than the logic operation group; and can increase the throughput of the logic operation unit by a factor of two when the pipeline input data is not greater than the data bit width of the logic operation group.

[0119] Taking a 256-bit logic unit divided into two 128-bit logic operation groups as an example, for 32-bit, 64-bit, and 128-bit single-precision floating-point logic operations (such as single-precision floating-point division), the latency of completing the data operation in this embodiment is the time of one logic operation (e.g., 11 clock cycles to complete one division operation), and the throughput is 2 data bits, thus improving the throughput of the logic unit. For 256-bit single-precision floating-point logic operations, the latency of completing the data operation is the time of two logic operations, and the throughput is 2 data bits. Therefore, this embodiment can double the throughput of 32-bit, 64-bit, and 128-bit single-precision floating-point logic operations (i.e., when the pipeline input data is not greater than the data width of the logic operation group, the throughput of the logic unit and the utilization rate of data width resources are improved). For 256-bit single-precision floating-point logic operations, although the latency of data operation increases, the throughput of the logic unit remains unchanged within the latency period. As can be seen, the embodiments of this application can improve the utilization rate of data bit width resources of the logic operation unit, improve the throughput of the logic operation unit, and improve instruction execution efficiency.

[0120] To address the issue of wasted data bit width resources in logic operation units (ALUs), this application differs from the approach of using ALUs as a whole for different pipelines to use individually in different clock cycles. Instead, this embodiment divides the ALU into multiple ALU groups, and each ALU group is configured for a single pipeline. This allows multiple pipelines to simultaneously use their respective configured ALU groups for data processing, enabling multiple pipelines to reuse ALUs concurrently. This ensures that a pipeline only needs a portion of the ALU's data bit width resources for data processing, while the remaining data bit width resources in the ALU can be used by other pipelines simultaneously. This improves the utilization rate of the ALU's data bit width resources and enhances the processor's instruction parallel execution capability and instruction execution efficiency.

[0121] It should be further noted that the logic operation unit referred to in the embodiments of this application can be a circuit in a processor used to perform logic operations, such as an ALU (Arithmetic and Logic Unit). The ALU may be a divider, multiplier, adder, or other circuit device that performs different types of logic operations.

[0122] Based on the system architecture exemplified above, this application embodiment also provides an execution engine, which includes: a data selector and a logic operation unit; the logic operation unit is divided into multiple logic operation groups, and one logic operation group is configured for use by a pipeline alone;

[0123] The execution engine acquires data for multiple instructions input from multiple pipelines during the instruction issuance phase, with one instruction input per pipeline.

[0124] The data selector is used to select the data input from each pipeline and assign it to the corresponding logical operation group configured for each pipeline.

[0125] The logic operation group is used to obtain the corresponding pipeline input data from the data selector, perform logic operations on the corresponding pipeline input data, and output the logic operation result.

[0126] In some embodiments, multiple execution units may form a logic operation unit, and the multiple logic operation groups may be divided according to the number of multiple execution units and the number of logic operation groups; wherein the number of logic operation groups is less than or equal to the number of multiple pipelines.

[0127] As an optional implementation, a combination of a number of unit execution units can be combined to form a logical operation group, the number of combinations being determined based on the number of logical operation groups and the number of the multiple unit execution units; wherein, a unit execution unit supports logical operations on data of a unit bit width, the unit bit width being the data bit width of the unit execution unit, and the data bit width of a logical operation group being the sum of the data bit widths of the combined unit execution units.

[0128] In some embodiments, the data bit width of a pipeline input is less than or equal to the data bit width of the corresponding configured logical operation group; or, the data bit width of a pipeline input is greater than the data bit width of the corresponding configured logical operation group.

[0129] As an optional implementation, if the data bit width of the pipeline input data is greater than the data bit width of the corresponding configured logical operation group, then the pipeline input data includes multiple data groups, and the data bit width of one data group is not greater than the data bit width of the logical operation group; wherein, the pipeline input data is divided into multiple data groups according to the data bit width of the corresponding configured logical operation group;

[0130] In this case, the data selector is used to select the logical operation group configured for each pipeline from the input data of each pipeline. This may include: selecting the logical operation group configured for each pipeline from multiple data groups of the pipeline in sequence.

[0131] Logical operation groups are used to obtain data corresponding to the pipeline input from the data selector, and performing logical operations on the corresponding pipeline input data may include:

[0132] Multiple data groups corresponding to the pipeline are sequentially obtained from the data selector, and logical operations are performed on the multiple data groups sequentially; the logical operation results of the multiple data groups are concatenated to obtain the logical operation result of the pipeline input data; wherein, after completing the logical operation of a data group, the logical operation result of the data group is temporarily stored, and the next data group to be logically operated is obtained from the data selector.

[0133] In some embodiments, the data selector may include: multiple data selectors, with one data selector configured for each logic operation group; wherein, one data selector is used to obtain the pipeline input data corresponding to the logic operation group and pass the data to the corresponding logic operation group.

[0134] In some further embodiments, the execution engine may also be configured with multiple result data buses corresponding to the number of pipelines, wherein one pipeline corresponds to one result data bus; the logic operation group can output the logic operation result to the result data bus corresponding to the configured pipeline.

[0135] Furthermore, embodiments of this application also provide a processor (e.g., a superscalar processor), which may include the execution engine provided in embodiments of this application.

[0136] Furthermore, embodiments of this application also provide a chip, which may include the processor provided in embodiments of this application.

[0137] Furthermore, embodiments of this application also provide an electronic device, such as a terminal device or a server device, which may include the chip provided in embodiments of this application.

[0138] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0139] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A method for executing instructions, characterized in that, include: Multiple instruction data are input into the execution engine through multiple pipelines, with one instruction data input per pipeline. The execution engine's logic operation units are divided into multiple logic operation groups, and each logic operation group is assigned to a single pipeline. Each logic operation unit is formed by multiple execution units, and each execution unit supports logical operations on data with a unit bit width, where the unit bit width is the data bit width of the execution unit. A logic operation group is formed by combining several execution units, and the number of these multiple logic operation groups is less than or equal to the number of pipelines. Select the logical operation group configured for each pipeline's input data, so that each logical operation group can perform logical operations on the input data of each pipeline; Output the logical operation results of each logical operation group.

2. The method according to claim 1, characterized in that, Also includes: The logical operation unit is divided into multiple logical operation groups based on the multiple execution units that form the logical operation unit and the number of logical operation groups.

3. The method according to claim 2, characterized in that, The step of dividing the logical operation unit into multiple logical operation groups based on the multiple execution units forming the logical operation unit and the number of logical operation groups includes: Determine multiple execution units of the logical operation unit; Based on the number of logical operation groups, the unit execution units are combined to obtain multiple logical operation groups; wherein, the data bit width of a logical operation group is the sum of the data bit widths of the combined unit execution units.

4. The method according to claim 3, characterized in that, The step of combining unit execution units according to the number of logical operation groups to obtain multiple logical operation groups includes: The number of combinations of unit execution units corresponding to a logical operation group is determined based on the number of logical operation groups and the number of the multiple unit execution units. The number of unit execution units is combined into a logical operation group, so that multiple logical operation groups are obtained by combining the multiple unit execution units.

5. The method according to any one of claims 1-4, characterized in that, The data bit width of the input data of a pipeline is less than or equal to the data bit width of the corresponding configured logical operation group; or, the data bit width of the input data of a pipeline is greater than the data bit width of the corresponding configured logical operation group.

6. The method according to claim 5, characterized in that, If the data bit width of the pipeline input data is greater than the data bit width of the corresponding configured logical operation group, then the pipeline input data includes multiple data groups, and the data bit width of a data group is not greater than the data bit width of the logical operation group; wherein, the pipeline input data is divided into multiple data groups according to the data bit width of the corresponding configured logical operation group.

7. The method according to claim 6, characterized in that, The step of selecting the logical operation group configured for each pipeline's input data, so that each logical operation group can perform logical operations on the input data of each pipeline, includes: The pipeline selects the logical operation group configured for the pipeline in sequence from multiple data groups, so that the logical operation group configured for the pipeline performs logical operations on multiple data groups in sequence; wherein, after completing the logical operation on a data group, the logical operation group temporarily stores the logical operation result of the data group and obtains the next data group to be logically operated on. The logical operation results of each logical operation group output include: The logical operation results of multiple data groups obtained by logical operation grouping are concatenated to obtain the logical operation results of the pipeline input data and the logical operation results of the output data.

8. The method according to claim 5, characterized in that, The step of inputting data of multiple instructions into the execution engine through multiple pipelines includes: a data selector that inputs data of multiple instructions into the execution engine through multiple pipelines; The step of selecting the logical operation group configured for each pipeline input data includes: transmitting the data input from each pipeline to the logical operation group configured for each pipeline through a data selector; The output of the logical operation results of each logical operation group includes: outputting the logical operation results of the logical operation group to the result data bus corresponding to the corresponding configured pipeline; wherein, one pipeline corresponds to one configured result data bus.

9. The method according to claim 8, characterized in that, The data selector includes multiple data selectors, with one data selector configured for each logical operation group; The data selector that inputs data from multiple instructions into the execution engine through multiple pipelines includes: inputting data from each pipeline into the data selector corresponding to the logical operation group configured for each pipeline; The step of transmitting the input data from each pipeline to the logic operation group configured for each pipeline via the data selector includes: transmitting the input data to the logic operation group corresponding to each data selector via each data selector.

10. An execution engine, characterized in that, include: The system includes a data selector and a logic operation unit. The logic operation unit is divided into multiple logic operation groups, and each logic operation group is configured for use by a single pipeline. Each logic operation unit is formed by multiple execution units, and each execution unit supports logical operations on data with a unit bit width, where the unit bit width is the data bit width of the execution unit. A logic operation group is obtained by combining several execution units, and the number of these multiple logic operation groups is less than or equal to the number of pipelines. The execution engine acquires data for multiple instructions input from multiple pipelines during the instruction issuance phase, with one instruction input per pipeline. The data selector is used to select the data input from each pipeline and assign it to the corresponding logical operation group configured for each pipeline. The logic operation group is used to obtain the corresponding pipeline input data from the data selector, perform logic operations on the corresponding pipeline input data, and output the logic operation result.

11. The execution engine according to claim 10, characterized in that, The multiple logical operation groups are divided according to the multiple unit execution units and the number of logical operation groups.

12. The execution engine according to claim 11, characterized in that, A logical operation group is formed by combining a number of unit execution units, the number of combinations being determined based on the number of logical operation groups and the number of the multiple unit execution units; wherein, the data bit width of a logical operation group is the sum of the data bit widths of the combined unit execution units.

13. The execution engine according to any one of claims 10-12, characterized in that, If the data bit width of the pipeline input data is greater than the data bit width of the corresponding configured logical operation group, then the pipeline input data includes multiple data groups, and the data bit width of a data group is not greater than the data bit width of the logical operation group; wherein, the pipeline input data is divided into multiple data groups according to the data bit width of the corresponding configured logical operation group. The data selector is used to select the logical operation group corresponding to each pipeline from the input data of each pipeline, including: sequentially selecting the logical operation group configured for each pipeline from multiple data groups of the pipeline. The logical operation group is used to obtain data corresponding to the pipeline input from the data selector, and to perform logical operations on the corresponding pipeline input data, including: Multiple data groups corresponding to the pipeline are sequentially obtained from the data selector, and logical operations are performed on the multiple data groups sequentially; the logical operation results of the multiple data groups are concatenated to obtain the logical operation result of the pipeline input data; wherein, after completing the logical operation of a data group, the logical operation result of the data group is temporarily stored, and the next data group to be logically operated is obtained from the data selector.

14. The execution engine according to any one of claims 10-12, characterized in that, The data selector includes: multiple data selectors, with one data selector configured for each logic operation group; wherein, one data selector is used to obtain the pipeline input data corresponding to the logic operation group and pass the data to the corresponding logic operation group.

15. The execution engine according to any one of claims 10-12, characterized in that, Also includes: The number of result data buses corresponds to the number of pipelines, wherein one result data bus is configured for each pipeline; The logic operation group outputs the logic operation results to the result data bus corresponding to the configured pipeline.

16. A processor, characterized in that, Includes the execution engine as described in any one of claims 10-15.

17. A chip, characterized in that, Includes the processor as described in claim 16.

18. An electronic device, characterized in that, Includes the chip as described in claim 17.

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