Mask-based graphics processor pixel cache miss request merging system and method

Abstract

The present application relates to a kind of mask-based graphics processor pixel Cache miss request merging system and method.The system of the present application includes the detection and sequencing module of miss request's information to be merged, read mask miss merging processing module, read TAG miss merging processing module and write miss merging processing module, the detection and sequencing module of miss request's information to be merged is connected with read mask miss merging processing module, read TAG miss merging processing module, write miss merging processing module respectively, and the detection and sequencing module of miss request's information to be merged is used for the detection and sequencing of miss request's information to be merged, read mask miss merging processing module is used for the merging processing of read mask miss, read TAG miss merging processing module is used for the merging processing of read TAG miss, and write miss merging processing module is used for the merging processing of write miss.The present application can reduce miss replacement rate, reduce DDR bandwidth, and in the case of pipeline, fastest can reach one request in one clock cycle, very good improve GPU rendering performance.

Description

Technical Field

[0001] This invention relates to the field of computer hardware technology, and in particular to a mask-based system and method for merging pixel cache miss requests in a graphics processor. Background Technology

[0002] The graphics processing unit (GPU) contains multiple color buffers. Due to the large amount of data in these color buffers, it is impossible to store the data in on-chip SRAM. Therefore, the color buffers are stored in off-chip DDR memory and buffered by an internal pixel cache.

[0003] Pixel cache is an important unit in GPU. Ordinary cache can no longer meet the bandwidth requirements of GPU. Therefore, some modifications have been made to the cache write-back operation, and a pixel cache with mask has been proposed. When missing requests are made, they are merged, which greatly reduces the interaction with DDR and thus improves the rendering performance of GPU. Summary of the Invention

[0004] To address the technical problems existing in the background art, the present invention provides a mask-based system and method for merging missing requests in a graphics processor pixel cache, which can reduce the missing replacement rate, reduce DDR bandwidth, and achieve a minimum of one request per clock cycle in a pipelined manner, thereby significantly improving GPU rendering performance.

[0005] The technical solution of this invention is as follows: This invention is a mask-based system for merging missing requests in a graphics processor pixel cache. Its key feature is that the system includes a module for detecting and sorting missing request information to be merged, a module for processing missing requests by reading the mask, a module for processing missing requests by reading the TAG, and a module for processing missing requests by writing. The module for detecting and sorting missing request information to be merged is connected to the modules for processing missing requests by reading the mask, reading the TAG, and writing. The module for detecting and sorting missing request information to be merged is used for detecting and sorting the missing request information to be merged. The module for processing missing requests by reading the mask is used for merging missing requests by reading the mask. The module for processing missing requests by reading the TAG is used for merging missing requests by reading the TAG. The module for processing missing requests by writing is used for merging missing requests by writing.

[0006] Furthermore, the module for detecting and sorting missing requests needs to empty the PCache pipeline and stop accepting new requests before sorting. The sorting function refers to the function of sorting missing requests of the same block stored in MSHR according to the address mapping relationship within one clock cycle.

[0007] Furthermore, in the read mask missing merging module, since the read mask missing occurs on the basis of a TAG hit, the missing requests to be merged will not have write missing or read TAG missing, both of which are TAG missing. The merging process needs to pipeline the merging of data read from the DDR cache and the corresponding data stored in the Cache. During the merging process, the data is updated to the latest data according to the mask, and the data is pipelined to the Cache data storage.

[0008] Furthermore, in the read TAG missing merging module, the missing requests to be merged in MSHR that have the same read TAG missing as the currently processed block are divided into two categories: read TAG missing and write missing. In order to reduce the time occupied by update processing, the write-back of the replacement block with dirty bits, data update, merge of read missing and merge of write missing are processed synchronously. During the processing, it is only necessary to read the data of one block in the cache data storage one by one and then write it. Reading can be done one clock cycle earlier than writing. An address cannot be read and written at the same time.

[0009] Furthermore, in the write miss merging module, the missing requests to be merged in the MSHR for the same block as the currently processed write miss are divided into two categories: read TAG misses and write misses. If there is a read miss to be merged (referred to as a read after write), special handling is required. Because the write miss of the pixel cache does not involve a replacement operation, but directly writes the data with a mask, the data of the read miss of the current write miss block may not be in the cache data storage, which will result in the inability to read the data or the read data being incomplete. In order to ensure the correctness of the data, in the case of a read miss after a write miss, the write-merged data is written to DDR, and the read miss to be merged mark to be merged in the MSHR is cleared, and then it is reissued. At the same time, in the case of no read after write, in order to reduce the time occupied by write-back and write merging when replacing a block with dirty bits, the clock cycle required to read the data of a block is reduced to a maximum of half a clock cycle, and two adjacent data are read at one time.

[0010] A method for implementing the mask-based graphics processor pixel cache miss request merging system as described above, characterized in that the method includes the following steps:

[0011] 1) Detection and sorting of missing request information to be merged;

[0012] 2) Merging of missing read masks;

[0013] 3) Merging of missing tags;

[0014] 4) Write the merging process for missing data.

[0015] Furthermore, the specific method for step 1) is as follows:

[0016] 1.1) Before sorting, the PCache pipeline needs to be emptied and no new requests should be accepted. The sorting function is completed within one clock cycle.

[0017] 1.2) Compare the missing address registers in the 32 MSHR groups with the missing addresses currently being updated, and generate a 32-bit mask missing flag register, a 32-bit read TAG missing flag register, and a write missing flag register.

[0018] 1.3) Based on the flag in the flag register, extract the xy coordinate offset from the corresponding missing MSHR address, sort them from 0 to 15, and store the sorted MSHR addresses in the register. This facilitates reading data from the correct MSHR and updating the correct MSHR flag bit during subsequent sequential merging.

[0019] Furthermore, the specific method for step 2) is as follows:

[0020] 2.1) After sorting, 16 data items are read from the cache that reads data from DDR over 16 consecutive clock cycles;

[0021] 2.2) Simultaneously read 16 data points and the mask from the block of the data RAM marked by the TAG hit;

[0022] 2.3) Latch the read data and the mask, merge the latched data according to the mask, and write the latest data into the cache data storage after merging. The latest data is the merged data.

[0023] 2.4) During 16 consecutive clock cycles, based on the missing flag register of the read mask, if there is a case where the corresponding flag is 1, the merged data is output, the corresponding read address is output, and the flag bit of MSHR is updated to low.

[0024] 2.5) All 16 merged data are written to the Cache data storage. At this time, all read mask missing requests for the same Block as the current processing in MSHR are also returned. The current processing ends, and the corresponding marking information is updated. The corresponding marking information includes whether the 16 data in the Block are valid data and the Block mask missing mark.

[0025] Furthermore, the specific method for step 3) is as follows:

[0026] 3.1) After sorting is complete, the data to be written back is read from the replacement block of the cache data storage for 16 consecutive clock cycles. This step is performed when the block has dirty bits, and is omitted when there are no dirty bits.

[0027] 3.2) One clock cycle later than the previous step, 16 data entries are read from the cache that reads data from DDR for 16 consecutive clock cycles;

[0028] 3.3) Simultaneously monitor the flags in the write missing merge flag register. If the corresponding flag bit is high, use the address in the address register as the address to read MSHR, issue a read enable, read the write data and mask stored in MSHR, and update the corresponding flag in MSHR.

[0029] 3.4) The data read from the cache that reads data from DDR and the data read from MSHR are latched and merged and then written into the Cache data storage; if there is no write miss request to be merged, there is no need to read MSHR, and therefore no need to merge the data. The data read from the cache that reads data from DDR is directly latched and written into the Cache data storage.

[0030] 3.5) Two clock cycles later than step 3, continuously detect missing flags to be merged. If the corresponding flag bit is high, return the merged data and update the corresponding flag in MSHR with the corresponding return address and mask.

[0031] 3.6) Until all 16 data points have been processed, update the corresponding tagging information, which includes the TAG tag, dirty tag, and whether the 16 data points in the Block are valid data.

[0032] Furthermore, the specific method for step 4) is as follows:

[0033] 4.1) After sorting is complete, read two adjacent 512-bit data (0 and 1, 2 and 3, etc.) from the cache data storage in sequence. This step is performed when there are dirty bits in the block, and is skipped when there are no dirty bits.

[0034] 4.2) Monitor the adjacent two bits (0 and 1, 2 and 3, etc.) of the write missing merge flag register at the same time. If both bits are high, determine whether the two corresponding addresses in the address register are adjacent addresses (0 and 1, 2 and 3, etc.). If they are, use the address in the address register as the address to read MSHR and issue a read enable for one clock cycle to read the adjacent write data and mask stored in MSHR. If not, issue a read MSHR enable for two clock cycles respectively to read the write data and mask stored in MSHR. If one bit of the flag is high, read the corresponding write data and mask stored in MSHR. If both bits are low, do not perform a read operation; update the corresponding flag in MSHR.

[0035] 4.3) After latching the data and mask read from MSHR, write them into the Cache data storage and update the corresponding tag information. The corresponding tag information includes TAG tag, dirty bit tag, and tag indicating whether the 16 data in the Block is valid data.

[0036] 4.4) After sorting is complete, read two adjacent 512-bit data (0 and 1, 2 and 3, etc.) from the cache data storage in sequence. This step is performed when there are dirty bits in the block, and is skipped when there are no dirty bits.

[0037] 4.5) Monitor the write miss merge flag register, use the address register corresponding to the high-marked bit as the address to read MSHR, issue a read enable, and read the write address and mask stored in MSHR;

[0038] 4.6) Latch the read data and mask and write them to DDR;

[0039] 4.7) After the write merge process is completed, the address register corresponding to the high bit of the read missing merge flag register is used as the address to update MSHR, and the corresponding flag bit to be merged is updated to invalid flag;

[0040] 4.8) After processing, update the marking information, which includes TAG marking, dirty mark marking, and whether the 16 data in the Block are valid data marking.

[0041] The present invention provides a mask-based system and method for merging missing requests in a graphics processor pixel cache. This system adds a Missed Request Hierarchy Processor (MSHR) to a standard pipelined cache and employs various types of missing request merging processes when a missing request occurs. This masks the latency caused by waiting for cache and AXI interaction, effectively improving GPU rendering efficiency. Therefore, this invention can reduce the missing replacement rate, reduce DDR bandwidth, and, in a pipelined environment, achieve a minimum of one request per clock cycle, significantly improving GPU rendering performance. Attached Figure Description

[0042] Figure 1 This is a block diagram of the method of the present invention;

[0043] Figure 2 This is a flowchart illustrating the detection and sorting of missing request information to be merged in this invention;

[0044] Figure 3 This is a block diagram of the mask missing merging processing in this invention;

[0045] Figure 4 This is a flowchart of the TAG missing merging process in this invention;

[0046] Figure 5 This is a flowchart of the write missing merging process in this invention. Detailed Implementation

[0047] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0048] See Figure 1 The structure of a specific embodiment of the mask-based graphics processor pixel cache missing request merging system of the present invention includes a module for detecting and sorting missing request information to be merged, a module for reading mask missing requests and merging, a module for reading TAG missing requests and merging, and a module for writing missing requests and merging. The module for detecting and sorting missing request information to be merged is connected to the modules for reading mask missing requests and merging, reading TAG missing requests and merging, and writing missing requests and merging, respectively. The module for detecting and sorting missing request information to be merged is used for detecting and sorting the missing request information to be merged. The module for reading mask missing requests and merging, the module for reading TAG missing requests and merging, and the module for writing missing requests and merging, respectively, are used for reading mask missing requests and merging, and the module for writing missing requests and merging, respectively.

[0049] Before sorting the missing request information to be merged, the PCache pipeline needs to be emptied and no new requests should be accepted. The sorting function refers to the function of sorting the missing requests of the same block stored in MSHR according to the address mapping relationship within one clock cycle.

[0050] In the read mask missing merging module, since read mask missing occurs on the basis of TAG hit, the missing requests to be merged will not have write missing or read TAG missing, both of which are TAG missing. The merging process needs to pipeline the merging of data read from the DDR cache and the corresponding data stored in the cache. During the merging process, the data is updated to the latest data according to the mask, and the data is pipelined to the cache data storage.

[0051] In the read TAG missing merging module, missing requests in MSHR that have the same read TAG missing value as the currently being processed are divided into two categories: read TAG missing and write missing. In order to reduce the time occupied by update processing, the write-back of the replacement block with dirty bits, data update, merge of read missing and merge of write missing are processed synchronously. During the processing, it is only necessary to read the data of one block in the cache data storage one by one and then write it. Reading can be done one clock cycle earlier than writing. An address cannot be read and written at the same time.

[0052] In the write miss merging module, the missing requests to be merged in the MSHR for the same block as the currently processed write miss are divided into two categories: read TAG misses and write misses. If there is a read miss to be merged (referred to as a read after a write), special handling is required. Because the write miss in the pixel cache does not involve a replacement operation, but directly writes the data with a mask, the data of the read miss of the current write miss block may not be in the cache data storage, which will result in the inability to read the data or the read data being incomplete. In order to ensure the correctness of the data, in the case of a read miss after a write miss, the write-merged data is written to DDR, and then the read miss to be merged mark in the MSHR is cleared, and it is reissued. At the same time, in the case of no read after a write, in order to reduce the time occupied by write-back and write merging when replacing a block with dirty bits, the clock cycle required to read the data of a block is reduced to a maximum of half a clock cycle, and two adjacent data are read at a time.

[0053] In a specific embodiment of the present invention, a pixel cache used in a GPU is employed. The pixel cache is a masked cache with a size of 32KB and a block size of 16x512 bits. The cache is implemented using a non-blocking pipeline and is stored using 32 MSHR sets.

[0054] See Figure 2 When merging missing requests in the cache, a sorting process is first performed, as described below:

[0055] 1.1) Before sorting, the PCache pipeline needs to be emptied and no new requests should be accepted. The sorting function is completed within one clock cycle.

[0056] 1.2) Compare the missing address registers in the 32 MSHR groups with the missing addresses currently being updated, and generate a 32-bit mask missing flag register, a 32-bit read TAG missing flag register, and a write missing flag register.

[0057] 1.3) Based on the flag in the flag register, extract the xy coordinate offset from the corresponding missing MSHR address, sort them from 0 to 15, and store the sorted MSHR addresses in the register. This facilitates reading data from the correct MSHR and updating the correct MSHR flag bit during subsequent sequential merging.

[0058] See Figure 3 During the merging process for missing read masks, since the missing read mask occurs on top of a missing mask in a TAG match, the missing requests to be merged will not have write missing or read TAG missing (both types of missing requests are TAG missing); the specific description is as follows:

[0059] 2.1) After sorting, 16 data items are read from the cache that reads data from DDR over 16 consecutive clock cycles;

[0060] 2.2) Simultaneously read 16 data points and the mask from the block of the data RAM marked by the TAG hit;

[0061] 2.3) Latch the read data and the mask, merge the latched data according to the mask, and write the latest data into the cache data storage after merging. The latest data is the merged data.

[0062] 2.4) During 16 consecutive clock cycles, based on the missing flag register of the read mask, if there is a case where the corresponding flag is 1, the merged data is output, the corresponding read address is output, and the flag bit of MSHR is updated to low.

[0063] 2.5) All 16 merged data are written to the Cache data storage. At this time, all read mask missing requests for the same Block as the current processing in MSHR are also returned. The current processing ends, and the corresponding marking information is updated. The corresponding marking information includes whether the 16 data in the Block are valid data and the Block mask missing mark.

[0064] See Figure 4 During the read TAG missing merging process, missing requests in the MSHR that have the same read TAG missing value as the currently processed block are divided into two categories: read TAG missing and write missing. To reduce the time occupied by update processing, the write-back of the replacement block with dirty bits, data update, read missing merging, and write missing merging are processed synchronously. During the processing, only the data 0-15 of one block in the cache data storage needs to be read first and then written, with the read preceding the write by one clock cycle. Simultaneous read and write operations on the same address are not allowed. The specific description is as follows:

[0065] 3.1) After sorting is complete, the data to be written back is read from the replacement block of the cache data storage for 16 consecutive clock cycles; this step is performed when the block has dirty bits, and is omitted when there are no dirty bits.

[0066] 3.2) One clock cycle later than the previous step, 16 data entries are read from the cache that reads data from DDR for 16 consecutive clock cycles;

[0067] 3.3) Simultaneously monitor the flags in the write missing merge flag register. If the corresponding flag bit is high, use the address in the address register as the address to read MSHR, issue a read enable, read the write data and mask stored in MSHR, and update the corresponding flag in MSHR.

[0068] 3.4) The data read from the cache that reads data from DDR and the data read from MSHR are latched and merged and then written into the Cache data storage; if there is no write miss request to be merged, there is no need to read MSHR, and therefore no need to merge the data. The data read from the cache that reads data from DDR is directly latched and written into the Cache data storage.

[0069] 3.5) Two clock cycles later than step 3, continuously detect missing flags to be merged. If the corresponding flag bit is high, return the merged data and update the corresponding flag in MSHR with the corresponding return address and mask.

[0070] 3.6) Until all 16 data points have been processed, update the corresponding tagging information, which includes the TAG tag, dirty tag, and whether the 16 data points in the Block are valid data.

[0071] See Figure 5 During the write miss merging process, the missing requests in the MSHR for the same block as the currently processed write miss are divided into two categories: read TAG misses and write misses. If there is a read miss to be merged (referred to as a read after a write), special handling is required. Because write misses in the pixel cache do not involve a replacement operation, but directly write the data with a mask, the data for the read miss of the currently written miss block may not be in the cache data storage, which will result in no data being read or incomplete data being read. To ensure data correctness, in the case of a read miss following a write miss, the write-merged data is written to DDR, the read miss to be merged mark in the MSHR is cleared, and then it is reissued.

[0072] Meanwhile, without write-after-read, in order to reduce the time spent on write-back and write-merge when replacing blocks with dirty bits, the 16 clock cycles required to read 16 data bits of a block are reduced to a maximum of 8 clock cycles, allowing two adjacent 512 bits of data to be read at once.

[0073] The specific description of "write-after-read" is as follows:

[0074] 4.1) After sorting is complete, read two adjacent 512-bit data (0 and 1, 2 and 3, etc.) from the cache data storage in sequence. This step is performed when there are dirty bits in the block, and is skipped when there are no dirty bits.

[0075] 4.2) Monitor the adjacent two bits (0 and 1, 2 and 3, etc.) of the write missing merge flag register at the same time. If both bits are high, determine whether the two corresponding addresses in the address register are adjacent addresses (0 and 1, 2 and 3, etc.). If they are, use the address in the address register as the address to read MSHR and issue a read enable for one clock cycle to read the adjacent write data and mask stored in MSHR. If not, issue a read MSHR enable for two clock cycles respectively to read the write data and mask stored in MSHR. If one bit of the flag is high, read the corresponding write data and mask stored in MSHR. If both bits are low, do not perform a read operation; update the corresponding flag in MSHR.

[0076] 4.3) After latching the data and mask read from MSHR, write them into the Cache data storage and update the corresponding tag information. The tag information includes the TAG tag, dirty bit tag, and whether the 16 data in the Block is valid data.

[0077] The specific description of "writing followed by reading" is as follows:

[0078] 4.4) After sorting is complete, read two adjacent 256-bit and 512-bit data (0 and 1, 2 and 3, etc.) from the Cache data storage in sequence. This step is performed when there are dirty bits in the Block, and is skipped when there are no dirty bits.

[0079] 4.5) Monitor the write miss merge flag register, use the address register corresponding to the high-marked bit as the address to read MSHR, issue a read enable, and read the write address and mask stored in MSHR;

[0080] 4.6) Latch the read data and mask and write them to DDR;

[0081] 4.7) After the write merge process is completed, the address register corresponding to the high bit of the read missing merge flag register is used as the address to update MSHR, and the corresponding flag bit to be merged is updated to invalid flag;

[0082] 4.8) After processing, update the marking information, which includes TAG marking, dirty mark marking, and whether the 16 data in the Block are valid data marking.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A mask-based graphics processor pixel cache miss request merging method, characterized in that: The method comprises the following steps: 1) detection and ordering of missing requested information to be merged; 1.1) the pipeline of PCache needs to be emptied before ordering, and no new request is received, and the ordering function is completed within one clock cycle; 1.2) comparison of missing address registers in 32 groups of MSHRs with the missing address currently processed in the same Block, to generate a 32-bit read mask missing marker register, a 32-bit read TAG missing marker register and a write missing marker register; 1.3) according to the marker of the marker register, the offset of the xy coordinate is taken out from the corresponding MSHR missing address, and the MSHR address generated by ordering is stored in the register, so as to facilitate subsequent reading of data from the correct MSHR and updating of the correct MSHR marker bit according to the order during merging; 2) merging processing of read mask missing; 2.1) after ordering, 16 data are read out from the data buffer in the DDR in 16 consecutive clock cycles; 2.2) 16 data and a mask are read out from the Block of the data RAM of the TAG hit marker at the same time; 2.3) the read data and the mask are latched, and the latched data are merged according to the mask, and the latest data are written into the Cache data storage after data merging; 2.4) in the 16 consecutive clock cycles, according to the read mask missing marker register, if the corresponding 16 markers are 1, the merged data are output, the read address is output, and the marker bit of the MSHR is updated to low; 2.5) the 16 merged data are written into the Cache data storage, at this time, all read mask missing requests in the MSHR with the same Block as the current processing also return data, the current processing is ended, and the corresponding marker information is updated; 3) merging processing of read TAG missing; 4) merging processing of write missing.

2. The mask-based pixel cache miss request merging method of graphics processor according to claim 1, wherein: The specific method of step 3) is as follows: 3.1) after ordering, 16 data are read out from the replacement Block of the Cache data storage in 16 consecutive clock cycles, and this step is omitted when the Block has no dirty bit; 3.2) after one clock cycle later than the previous step, 16 data are read out from the data buffer in the DDR in 16 consecutive clock cycles; 3.3) at the same time, the marker of the write missing merging marker register is continuously monitored, if the corresponding marker bit is high, the address in the address register is taken as the address of the read MSHR, and the read enable is sent, the write data and the mask stored in the MSHR are read out, and the corresponding marker of the MSHR is updated; 3.4) the data read out from the data buffer in the DDR and the data read out from the MSHR are latched and merged, and then written into the Cache data storage; if there is no write missing request to be merged, the MSHR does not need to be read, and the data does not need to be merged, and the data read out from the data buffer in the DDR are latched and written into the Cache data storage; ​ 3.5) Continuously detect the read missing merge mark two clock cycles later than step 3.3), if the corresponding mark bit is high, return the merged data and the corresponding address and mask, and update the corresponding mark of MSHR; 3.6) Until all 16 data are processed, update the corresponding mark information.

3. The mask-based pixel cache miss request merging method of graphics processor according to claim 2, wherein: The specific method of step 4) is as follows: 4.1) After the sorting is completed, read the adjacent two 512 bits of data from the Cache data storage in sequence, and this step is performed when the Block has a dirty bit, and this step is removed when the Block has no dirty bit; 4.2) Monitor the adjacent two mark bits of the write missing merge mark register at the same time, if both mark bits are high, determine whether the two addresses in the address register are adjacent addresses, if yes, take the address in the address register as the address of the read MSHR, and issue a clock cycle of read enable, read out the adjacent stored write data and mask in the MSHR; if not, issue two clock cycles of read MSHR enable respectively, read out the stored write data and mask in the MSHR; if one mark bit is high, read out the stored write data and mask in the corresponding MSHR; if all mark bits are low, do not perform the read operation; update the corresponding mark of MSHR; 4.3) After the data and mask read out from the MSHR are latched, write them into the Cache data storage, and update the corresponding mark information; 4.4) After the sorting is completed, read the adjacent two 512 bits of data from the Cache data storage in sequence, and this step is performed when the Block has a dirty bit, and this step is removed when the Block has no dirty bit; 4.5) Monitor the write missing merge mark register, take the address register corresponding to the mark bit as high as the address of the read MSHR, and issue the read enable, read out the stored write address and mask in the MSHR; 4.6) Latch the read out data and mask and write them into the DDR; 4.7) After the write merge processing is completed, take the address register corresponding to the read missing merge mark register as high as the address of the update MSHR, and update the corresponding merge mark bit to the invalid mark; 4.8) Update the mark information after the processing is completed.

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