A graphics processor pipeline tile address conflict processing circuit and method

Abstract

This invention relates to a pipelined tile address conflict handling circuit and method for a graphics processor. The circuit includes a tile input data FIFO buffer circuit, a tile write judgment circuit, a tile information buffer circuit, a tile output selection circuit, and a tile address conflict detection circuit. The tile input data FIFO buffer circuit is connected to both the tile write judgment circuit and the tile information buffer circuit. The tile write judgment circuit is connected to the tile information buffer circuit. The tile information buffer circuit is connected to the tile address conflict detection circuit via the tile output selection circuit. The tile address conflict detection circuit is also connected to the tile information buffer circuit. This invention employs a FIFO input interface, which provides a clear interface and timing, is easy to integrate, and significantly improves the graphics processing performance in drawing scenarios where conflicting and non-conflicting addresses coexist.

Description

Technical Field

[0001] This invention belongs to the field of computer hardware technology, and in particular relates to a pipelined tile address conflict handling circuit and method for a graphics processor. Background Technology

[0002] In computer graphics processing units (GPUs), data processing is done via pipelines. When multiple pipelines process data in parallel, inconsistencies arise when data with the same address exists between pipelines. To avoid graphics rendering errors caused by this, a conflict detection unit is designed at the data input port to prevent data with the same address from entering the pipeline. Simultaneously, to ensure processing speed and improve performance, data with the same address is cached, allowing subsequent data with non-conflicting addresses to be sent without causing blockages. This caching design is feasible based on the assumption that there is no data dependency between different addresses. Summary of the Invention

[0003] To address the technical problems existing in the background art, the present invention provides a pipelined Tile address conflict handling circuit and method for graphics processors. It adopts a FIFO input interface, which has a clear interface and timing, is easy to integrate, and greatly improves the graphics processing performance of drawing scenes when conflicting and non-conflicting addresses exist at the same time.

[0004] The technical solution of this invention is as follows: This invention is a pipelined Tile address conflict handling circuit for a graphics processor, characterized in that: the circuit includes a Tile input data FIFO buffer circuit, a Tile write judgment circuit, a Tile information buffer circuit, a Tile output selection circuit, and a Tile address conflict detection circuit. The Tile input data FIFO buffer circuit is connected to the Tile write judgment circuit and the Tile information buffer circuit respectively. The Tile write judgment circuit is connected to the Tile information buffer circuit. The Tile information buffer circuit is connected to the Tile address conflict detection circuit through the Tile output selection circuit. The Tile address conflict detection circuit is connected to the Tile information buffer circuit.

[0005] Furthermore, the Tile information buffer circuit includes a register and RAM. The Tile write judgment circuit is connected to the register, the register is connected to the RAM, the RAM is connected to the Tile output selection circuit, the Tile input data FIFO buffer circuit is connected to the RAM, and the Tile address conflict detection circuit is connected to the register.

[0006] Furthermore, in the Tile input data FIFO buffer circuit, the address of the data to be written exists in the FIFO and can be viewed in advance.

[0007] Furthermore, the Tile information caching circuit uses 32 queues, each with a depth of 2, which can suspend 2 conflicting addresses, and can cache a total of 64 Tile requests. The address and flag bits are stored in registers, and the data is stored in RAM.

[0008] Furthermore, the Tile write judgment circuit determines the location where data is written to the conflict buffer; it compares the address of the data to be written with the address in the register, and if the queue can be written, it reads the data from the FIFO, writes it to the specified position in the queue, and completes the data update in RAM.

[0009] Furthermore, in the Tile write judgment circuit, the write position is divided into two types: one is writing to the same address, and the other is writing to an empty queue. Writing to the same address: there is a matching address, and there is an empty slot at the position of the matching address. Writing to an empty queue: there is no matching address, and there is an empty queue. The writing to the matching address is preferred. When there is no empty slot at the matching address, or there is no matching address and no empty queue, a block is formed, and the input data is not read. Buffer queue write update: according to the write position, find the write queue that needs to be updated. If vld0 is 0, the position of vld0 is written first, vld0 is marked as 1, and priority is marked as 0, and the data is written to the position of Data0. Otherwise, vld1 is marked as 1, priority is marked as 1, and the data is written to the position of Data1.

[0010] Furthermore, the Tile output selection circuit selects the output of data in the data buffer queue according to a grouped round-robin plus priority conflict address method: the round-robin starts from the maximum position, decrements by 1 each time, until it reaches 0, at which point the maximum value is obtained again; if a matching address is written during this process, the address is directly set to the position of the matching address; the selected position is then selected from two positions based on the priority flag bit for output; when selecting the maximum value, the queue is divided into 8 groups in order from 0 to 31, each group containing four queues, and if one of the four queues is valid, the group is considered valid; if the eighth group is valid, the maximum value is 31, if the seventh group is valid, the maximum value is 27, and so on, with the zeroth group having a valid maximum value of 3.

[0011] Furthermore, the Tile address conflict detection circuit monitors the pixel addresses of all pipeline data processing paths. If the coordinates of the current input tile and the monitored tile are the same, a conflict signal is fed back to retain the data in the buffer; otherwise, the information buffer queue is cleared.

[0012] Furthermore, in the Tile address conflict detection circuit, the input tile address is compared with the tile address that needs to be monitored within the pipeline. For timing considerations, the comparison circuit is divided into four parts: pipeline 1 address comparison, pipeline 2 address comparison, pipeline 3 address comparison, and pipeline 4 address comparison. Each part uses a flip-flop output, and finally, the results of the four parts are combined and output. The Tile address conflict detection circuit takes one clock cycle. The conflict signal is provided to the previous stage conflict buffer unit and serves as the switch signal for the output data of this unit. When the conflict signal is valid, the output data is invalid and discarded.

[0013] A method for using the above-described pipelined tile address conflict handling circuit of a graphics processor, characterized in that the method includes the following steps:

[0014] 1) The address of the data to be written exists in the Tile input data FIFO buffer circuit and can be viewed in advance;

[0015] 2) The Tile information caching circuit uses 32 queues, each with a depth of 2, which can suspend 2 conflicting addresses and cache a total of 64 Tile requests. The address and flag bits are stored in registers, and the data is stored in RAM.

[0016] 3) The Tile write judgment circuit compares the address of the data to be written with the address in the register. If the queue can be written, the data is read from the FIFO and then written to the specified position in the queue, and the data in the RAM is updated.

[0017] There are two types of write positions: writes to the same address and writes to an empty queue. Writes to the same address occur when there is a matching address and an empty slot at that address. Writes to an empty queue occur when there is no matching address and an empty queue exists. Writes to matching addresses are prioritized. When there is no empty slot at a matching address, or no matching address and no empty queue, a block occurs, and input data is not read. Cache queue write updates: Based on the write position, the write queue that needs updating is found. If vld0 is 0, the data is written to the position of vld0 first, vld0 is marked as 1, priority is marked as 0, and data is written to the position of Data0. Otherwise, vld1 is marked as 1, priority is marked as 1, and data is written to the position of Data1.

[0018] 4) The Tile output selection circuit selects the output of data in the data buffer queue using a grouped round-robin and priority conflict address method: the round-robin starts from the maximum position, decrements by 1 each time, until it reaches 0, at which point the maximum value is obtained again; if a matching address is written during this process, the address is directly set to the position of the matching address; the selected position is then selected from two positions based on the priority flag bit for output; when selecting the maximum value, the queue is divided into 8 groups in order from 0 to 31, each group containing four queues, and if one of the four queues is valid, the group is considered valid; if the eighth group is valid, the maximum value is 31, if the seventh group is valid, the maximum value is 27, and so on, with the zeroth group having a valid maximum value of 3;

[0019] 5) The Tile address conflict detection circuit monitors the pixel addresses of all pipeline data processing paths. If the coordinates of the current input tile and the monitored tile are the same, a conflict signal is fed back to retain the data in the buffer; otherwise, the information buffer queue is cleared.

[0020] Specifically, the input tile address is compared with the tile address that needs to be monitored within the pipeline. For timing considerations, the comparison circuit is divided into four parts: pipeline 1 address comparison, pipeline 2 address comparison, pipeline 3 address comparison, and pipeline 4 address comparison. Each part uses a flip-flop output, and the results of the four parts are finally combined and output. The tile address conflict detection circuit takes one clock cycle. The conflict signal is provided to the previous stage conflict buffer unit and serves as the switch signal for the output data of this unit. When the conflict signal is valid, the output data is invalid and the data is discarded.

[0021] This invention provides a pipelined tile address conflict handling circuit and method for a graphics processor. Its input interface is a FIFO interface, allowing output data to be previewed. If a condition is met, the data is read; otherwise, it is not read. This reduces the amount of control logic that cannot be processed after data is read. The tile information cache design uses 32 queues, each with a depth of 2, which can suspend 2 conflicting addresses, caching a total of 64 tile requests. The address and tag are stored in registers, while the data is stored in RAM. Therefore, this invention has the following advantages:

[0022] 1) This invention uses a FIFO input interface, which has a clear interface and timing, and is easy to integrate.

[0023] 2) This invention adopts a conflict suspension processing method and a single-shot pipeline circuit structure, which solves the problem of pipeline data read and write consistency in graphics processors and greatly improves the graphics processing performance of drawing scenes when conflicting addresses and non-conflicting addresses exist at the same time. Attached Figure Description

[0024] Figure 1 This is a circuit diagram of the present invention;

[0025] Figure 2 This is a specific application diagram of the Tile write judgment circuit in this invention;

[0026] Figure 3 This is a specific application diagram of the Tile output selection circuit in this invention;

[0027] Figure 4 This is a specific application diagram of the Tile address conflict detection circuit in this invention. Detailed Implementation

[0028] The technical solution of the present invention will be further described in detail below with reference to specific embodiments.

[0029] See Figure 1 The specific embodiment of the pipelined Tile address conflict handling circuit for the graphics processor of the present invention includes five parts: a Tile input data FIFO buffer circuit, a Tile write judgment circuit, a Tile information buffer circuit, a Tile output selection circuit, and a Tile address conflict detection circuit. These five parts complete the updating of the buffer queue and the output of data. The Tile input data FIFO buffer circuit is connected to both the Tile write judgment circuit and the Tile information buffer circuit. The Tile write judgment circuit is connected to the Tile information buffer circuit. The Tile information buffer circuit is connected to the Tile address conflict detection circuit through the Tile output selection circuit. The Tile address conflict detection circuit is also connected to the Tile information buffer circuit.

[0030] in:

[0031] The input interface of the Tile input data FIFO buffer circuit is a FIFO interface, allowing the output data to be previewed. If the conditions are met, the data is read; otherwise, it is not read. This reduces the control logic that could prevent subsequent pipelines from processing data if it is not received after the data has been read.

[0032] The tile information caching circuit includes registers and RAM. A tile write judgment circuit is connected to the registers, the registers are connected to the RAM, the RAM is connected to the tile output selection circuit, the tile input data FIFO caching circuit is connected to the RAM, and the tile address conflict detection circuit is connected to the registers. The caching design uses 32 queues, each with a depth of 2, which can suspend 2 conflicting addresses, for a total of 64 tile requests. Addresses and tags are stored in registers, while data is stored in RAM.

[0033] The Tile write detection circuit determines the location where data is written to the conflict buffer. The address of the data to be written exists in the FIFO and can be checked in advance. The address of the data to be written is compared with the address in the tag register. If the queue can be written, the data is read from the FIFO and then written to the specified position in the queue, and the data in RAM is updated.

[0034] The tile address conflict detection circuit monitors the pixel addresses of all pipeline data processing paths. If the coordinates of the current input tile and the monitored tile are the same, a conflict signal is fed back to retain the data in the buffer; otherwise, the information buffer queue is cleared.

[0035] See Figure 2 The Tile write judgment circuit categorizes write positions into two types: writes to the same address and writes to an empty queue. Writes to the same address occur when there is a matching address and an empty slot at that address. Writes to an empty queue occur when there is no matching address and an empty queue exists. Writes to matching addresses are prioritized. If there is no empty slot at a matching address, or no matching address and no empty queue, a block occurs, and input data is not read. Buffer queue write updates: Based on the write position, the write queue that needs updating is found. If vld0 is 0, the write to vld0 is prioritized, vld0 is marked as 1, priority is marked as 0, and data is written to Data0. Otherwise, vld1 is marked as 1, priority is marked as 1, and data is written to Data1.

[0036] See Figure 3 The Tile output selection circuit selects the output from the data buffer queue using a grouped round-robin approach with a priority conflict address method: The round-robin starts from the maximum position, decrementing by 1 each time until it reaches 0, at which point the maximum value is retrieved again. If a matching address is written during this process, the address is directly set to the position of the matching address. The selected position is then further divided into two based on the priority flag bit for output. For maximum value selection, the queue is divided into 8 groups from 0 to 31, with each group containing four queues. If one of the four queues is valid, the group is considered valid. If the eighth group is valid, the maximum value is 31; if the seventh group is valid, the maximum value is 27, and so on, with the zeroth group having a maximum value of 3.

[0037] See Figure 4The tile address collision detection circuit compares the input tile address with the tile addresses that need to be monitored within the pipeline. For timing considerations, the comparison circuit is divided into four parts: pipeline 1 address comparison, pipeline 2 address comparison, pipeline 3 address comparison, and pipeline 4 address comparison. Each part uses a flip-flop output, and the results of the four parts are finally combined and output. The tile collision circuit takes one clock cycle. The collision signal is provided to the previous stage collision buffer unit and serves as a switch signal for the output data of this unit. When the collision signal is valid, the output data is invalid and discarded.

[0038] This invention also provides a method for handling pipelined tile address conflicts in a graphics processor, the method specifically including the following steps:

[0039] 1) The address of the data to be written exists in the Tile input data FIFO buffer circuit and can be viewed in advance;

[0040] 2) The Tile information caching circuit uses 32 queues, each with a depth of 2, which can suspend 2 conflicting addresses and cache a total of 64 Tile requests. The address and flag bits are stored in registers, and the data is stored in RAM.

[0041] 3) The Tile write judgment circuit compares the address of the data to be written with the address in the register. If the queue can be written, the data is read from the FIFO and then written to the specified position in the queue, and the data in the RAM is updated.

[0042] There are two types of write positions: writes to the same address and writes to an empty queue. Writes to the same address occur when there is a matching address and an empty slot at that address. Writes to an empty queue occur when there is no matching address and an empty queue exists. Writes to matching addresses are prioritized. When there is no empty slot at a matching address, or no matching address and no empty queue, a block occurs, and input data is not read. Cache queue write updates: Based on the write position, the write queue that needs updating is found. If vld0 is 0, the data is written to the position of vld0 first, vld0 is marked as 1, priority is marked as 0, and data is written to the position of Data0. Otherwise, vld1 is marked as 1, priority is marked as 1, and data is written to the position of Data1.

[0043] 4) The Tile output selection circuit selects the output of data in the data buffer queue using a grouped round-robin and priority conflict address method: the round-robin starts from the maximum position, decrements by 1 each time, until it reaches 0, at which point the maximum value is obtained again; if a matching address is written during this process, the address is directly set to the position of the matching address; the selected position is then selected from two positions based on the priority flag bit for output; when selecting the maximum value, the queue is divided into 8 groups in order from 0 to 31, each group containing four queues, and if one of the four queues is valid, the group is considered valid; if the eighth group is valid, the maximum value is 31, if the seventh group is valid, the maximum value is 27, and so on, with the zeroth group having a valid maximum value of 3;

[0044] 5) The Tile address conflict detection circuit monitors the pixel addresses of all pipeline data processing paths. If the coordinates of the current input tile and the monitored tile are the same, a conflict signal is fed back to retain the data in the buffer; otherwise, the information buffer queue is cleared.

[0045] Specifically, the input tile address is compared with the tile address that needs to be monitored within the pipeline. For timing considerations, the comparison circuit is divided into four parts: pipeline 1 address comparison, pipeline 2 address comparison, pipeline 3 address comparison, and pipeline 4 address comparison. Each part uses a flip-flop output, and the results of the four parts are finally combined and output. The tile address conflict detection circuit takes one clock cycle. The conflict signal is provided to the previous stage conflict buffer unit and serves as the switch signal for the output data of this unit. When the conflict signal is valid, the output data is invalid and the data is discarded.

[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A pipelined tile address conflict handling circuit for a graphics processor, characterized in that: The circuit includes a Tile input data FIFO buffer circuit, a Tile write judgment circuit, a Tile information buffer circuit, a Tile output selection circuit, and a Tile address conflict detection circuit. The Tile input data FIFO buffer circuit is connected to the Tile write judgment circuit and the Tile information buffer circuit, respectively. The Tile write judgment circuit is connected to the Tile information buffer circuit. The Tile information buffer circuit is connected to the Tile address conflict detection circuit through the Tile output selection circuit. The Tile address conflict detection circuit is connected to the Tile information buffer circuit. The Tile output selection circuit selects data in the data buffer queue for output using a grouped round-robin plus priority conflict address method: the round-robin starts from the maximum position, decrements by 1 each time, until it reaches 0, at which point the maximum value is obtained again; if a matching address is written during this process, the address is directly set to the position of the matching address; the selected position is then selected from two options based on the priority flag bit for output; when selecting the maximum value, the queue is divided into 8 groups in order from 0 to 31, each... The group contains four queues. If any one of the four queues is valid, the group is considered valid. The maximum value for a valid group is 31, for the seventh group it is 27, and so on, with the zeroth group having a maximum value of 3. The Tile address conflict detection circuit monitors the pixel addresses of all pipeline data processing paths. If the coordinates of the current input tile and the monitored tile are the same, a conflict signal is fed back to retain the data in the buffer; otherwise, the information buffer queue is cleared. In the Tile address conflict detection circuit, the input tile address is compared with the tile address that needs to be monitored within the pipeline. For timing considerations, the comparison circuit is divided into four parts: pipeline 1 address comparison, pipeline 2 address comparison, pipeline 3 address comparison, and pipeline 4 address comparison. Each part uses a trigger output, and the results of the four parts are finally merged and output. The Tile address conflict detection circuit takes one clock cycle. The conflict signal is provided to the previous stage conflict buffer unit and serves as the switch signal for the output data of this unit. When the conflict signal is valid, the output data is invalid and discarded.

2. The pipelined tile address conflict handling circuit for a graphics processor according to claim 1, characterized in that: The Tile information caching circuit includes a register and RAM. The Tile write judgment circuit is connected to the register, the register is connected to the RAM, the RAM is connected to the Tile output selection circuit, the Tile input data FIFO caching circuit is connected to the RAM, and the Tile address conflict detection circuit is connected to the register.

3. The pipelined tile address conflict handling circuit for a graphics processor according to claim 2, characterized in that: In the Tile input data FIFO buffer circuit, the address of the data to be written exists in the FIFO and can be viewed in advance.

4. The pipelined tile address conflict handling circuit for a graphics processor according to claim 3, characterized in that: The Tile information caching circuit uses 32 queues, each with a depth of 2, which can suspend 2 conflicting addresses and cache a total of 64 Tile requests. The address and flag bits are stored in registers, and the data is stored in RAM.

5. The pipelined tile address conflict handling circuit for a graphics processor according to claim 4, characterized in that: The Tile write judgment circuit determines the location where data is written to the conflict buffer; it compares the address of the data to be written with the address in the register; if the queue can be written, the data is read from the FIFO and then written to the specified position in the queue, and the data in the RAM is updated.

6. The pipelined tile address conflict handling circuit for a graphics processor according to claim 5, characterized in that: In the Tile write judgment circuit, the write position is divided into two types: write to the same address and write to an empty queue. Write to the same address: there is a matching address and there is an empty slot at the matching address position. Write to an empty queue: there is no matching address and there is an empty queue. Write to the matching address is preferred. When there is no empty slot at the matching address, or no matching address and no empty queue, a block is formed and the input data is not read. Buffer queue write update: according to the write position, find the write queue that needs to be updated. If vld0 is 0, write to the position of vld0 first, mark vld0 as 1, mark priority as 0, and write the data to the position of Data0. Otherwise, mark vld1 as 1, mark priority as 1, and write the data to the position of Data1.

7. A method for applying the pipelined tile address conflict handling circuit of the graphics processor according to claim 1, characterized in that: The method includes the following steps: 1) The address of the data to be written exists in the Tile input data FIFO buffer circuit and can be viewed in advance; 2) The Tile information caching circuit uses 32 queues, each with a depth of 2, which can suspend 2 conflicting addresses, and can cache a total of 64 Tile requests. The address and flag bits are stored in registers, and the data is stored in RAM. 3) The Tile write judgment circuit compares the address of the data to be written with the address in the register. If the queue can be written, the data is read from the FIFO and then written to the specified position in the queue, and the data in the RAM is updated. There are two types of write positions: writes to the same address and writes to an empty queue. Writes to the same address occur when there is a matching address and an empty slot at that address. Writes to an empty queue occur when there is no matching address and an empty queue exists. Writes to matching addresses are prioritized. When there is no empty slot at a matching address, or no matching address and no empty queue, a block occurs, and input data is not read. Cache queue write updates: Based on the write position, the write queue that needs updating is found. If vld0 is 0, the data is written to the position of vld0 first, vld0 is marked as 1, priority is marked as 0, and data is written to the position of Data0. Otherwise, vld1 is marked as 1, priority is marked as 1, and data is written to the position of Data1. 4) The Tile output selection circuit selects the output of data in the data buffer queue using a grouped round-robin and priority conflict address method: the round-robin starts from the maximum position, decrements by 1 each time, until it reaches 0, at which point the maximum value is obtained again; if a matching address is written during this process, the address is directly set to the position of the matching address; the selected position is then selected from two positions based on the priority flag bit for output; when selecting the maximum value, the queue is divided into 8 groups in order from 0 to 31, each group containing four queues, and if one of the four queues is valid, the group is considered valid; if the eighth group is valid, the maximum value is 31, if the seventh group is valid, the maximum value is 27, and so on, with the zeroth group having a valid maximum value of 3; 5) The Tile address conflict detection circuit monitors the pixel addresses of all pipeline data processing paths. If the coordinates of the current input tile and the monitored tile are the same, a conflict signal is fed back to retain the data in the buffer; otherwise, the information buffer queue is cleared. Specifically, the input tile address is compared with the tile address that needs to be monitored within the pipeline. For timing considerations, the comparison circuit is divided into four parts: pipeline 1 address comparison, pipeline 2 address comparison, pipeline 3 address comparison, and pipeline 4 address comparison. Each part uses a flip-flop output, and the results of the four parts are finally combined and output. The tile address conflict detection circuit takes one clock cycle. The conflict signal is provided to the previous stage conflict buffer unit and serves as the switch signal for the output data of this unit. When the conflict signal is valid, the output data is invalid and the data is discarded.

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