An 18T radiation-resistant SRAM memory cell circuit

Abstract

The present invention discloses an 18T radiation-resistant SRAM memory cell circuit, which is composed of 10 Class I MOS transistors, 8 Class II MOS transistors, and 4 nodes. The 10 Class I MOS transistors are sequentially designated P1 to P10, the 8 Class II MOS transistors are sequentially designated N1 to N8, and the 4 nodes are sequentially designated a first storage node, a second storage node, a first redundant node, and a second redundant node. In the 18T radiation-resistant SRAM memory cell circuit of the present invention, the gate of Class I MOS transistor P5 is electrically connected to the drain of Class I MOS transistor P6, and the drain of Class I MOS transistor P5 is electrically connected to the gate of Class I MOS transistor P6, forming a cross-coupling structure that completely resists data flipping at a single node. Furthermore, because the first storage node and the second storage node utilize a dual pull-up and dual pull-down structure, and the pull-down transistors are controlled by different feedback loops, the dual nodes can still be restored to their initial state when data flipping occurs simultaneously.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to an 18T radiation-resistant SRAM storage unit circuit. Background Art

[0002] Static random-access memory (SRAM), an essential component in various processor chips, occupies an increasingly large area within the chip, significantly impacting processor performance. In recent years, CMOS technology has continuously advanced, reducing both size and supply voltage. This continuous increase in chip integration also presents numerous design challenges. For example, a drop in supply voltage reduces the critical charge of sensitive SRAM nodes, resulting in a corresponding decrease in the SRAM's static noise margin.

[0003] The continuous development of aerospace technology has also placed higher demands on the performance and reliability of integrated circuit design. The operation of spacecraft or space stations is inseparable from the core processor chip. Due to the limited size of lightweight satellites, they require high-density memory cells. SRAM memory cells are a favorable choice for this purpose due to their high packaging density and improved digital data processing and logic performance of satellite control systems.

[0004] However, low node charge SRAM memory cells are extremely susceptible to high-energy particles, and the space environment is rife with various radiation phenomena, such as galactic cosmic rays, aurora radiation, solar radiation, and X-rays. The large amount of high-energy particles brought by these radiations poses a great challenge to SRAM memory cells in electronic devices. When high-energy particles pass through the silicon substrate, they generate minority carriers, which can be diffused and collected by the source or drain. When the transistors around the storage node collect these carriers, they may cause changes in the storage node data. This phenomenon is called single event upset (SEU). If these changes are not corrected in time, it will cause the entire cell data to flip. This operation may change the data stored on the data node and may change the data integrity.

[0005] Therefore, in order to meet the radiation resistance requirements of integrated circuits in spacecraft and other applications, it is necessary to resolve the impact of SEU on SRAM cells and improve the ability of storage cells to resist SEU.

[0006] There are some technical solutions to this problem in the existing technology, but most of these solutions cannot completely restore the data flip of a single node caused by a single particle effect. Although some solutions can completely restore the data flip of a single node caused by a single particle effect, they are basically unable to recover when data flip occurs on two nodes at the same time. Summary of the Invention

[0007] In view of the above-mentioned shortcomings of the prior art, the present invention discloses an 18T radiation-resistant SRAM memory cell circuit, comprising:

[0008] There are 10 first-class MOS transistors, 8 second-class MOS transistors, and 4 nodes. The 10 first-class MOS transistors are sequentially recorded as P1 to P10, the 8 second-class MOS transistors are sequentially recorded as N1 to N8, and the 4 nodes are sequentially a first storage node, a second storage node, a first redundant node, and a second redundant node.

[0009] The gate of the first type of MOS transistor P5 is electrically connected to the drain of the first type of MOS transistor P6, and the drain of the first type of MOS transistor P5 is electrically connected to the gate of the first type of MOS transistor P6, forming a cross-coupling structure;

[0010] The first-type MOS transistors P3 and P7 are pull-up transistors on the first storage node, the second-type MOS transistors N3 and N7 are pull-down transistors on the first storage node, the first-type MOS transistors P4 and P8 are pull-up transistors on the second storage node, and the second-type MOS transistors N4 and N8 are pull-down transistors on the second storage node;

[0011] The first type MOS transistor P5 is a pull-up transistor on the first redundant node, the first type MOS transistors P9 and N5 are pull-down transistors on the first redundant storage node, the first type MOS transistor P6 is a pull-up transistor on the second redundant node, and the second type MOS transistors P10 and N6 are pull-down transistors on the second redundant node;

[0012] The gate of the first type of MOS transistor P1 is connected to the second word line, and the source of the first type of MOS transistor P1 is connected to the first bit line;

[0013] The gate of the first type of MOS transistor P2 is connected to the second word line, and the source of the first type of MOS transistor P2 is connected to the second bit line;

[0014] The gate of the second type MOS transistor N1 is connected to the first word line, and the source of the second type MOS transistor N1 is connected to the first bit line;

[0015] The gate of the second type MOS transistor N2 is connected to the first word line, and the source of the second type MOS transistor N2 is connected to the second bit line.

[0016] In an optional embodiment of the present invention, the specific connection relationship of each MOS transistor is as follows:

[0017] The drain of the first type MOS transistor P1 is electrically connected to the drain of the first type MOS transistor P5, the source of P9, the gate of P6, the gate of P8, the gate of the PMOS transistor P4, and the gate of the second type MOS transistor N6 and the gate of N4;

[0018] The drain of the first type MOS transistor P2 is electrically connected to the drain of the first type MOS transistor P6, the source of P10, the gate of P5, the gate of P7, the gate of P3, and the gate of the second type MOS transistor N5 and the gate of N3;

[0019] The drain of the first-class MOS transistor P3 is electrically connected to the source of P7, and the source of the first-class MOS transistor P3 and the sources of P4, P5, and P6 are all connected to the power supply VDD;

[0020] The drain of a type of MOS transistor P4 is electrically connected to the source of P8;

[0021] The drain of the first type MOS transistor P7, the gate of the first type MOS transistor P9, the drain of the second type MOS transistor N3, the gate of N8, and the drain of N1 are electrically connected to the first storage node Q;

[0022] The drain of the first type MOS transistor P8, the gate of the first type MOS transistor P10, and the drain of the second type MOS transistor N4, the gate of N7, and the drain of N2 are connected to the second storage node QB;

[0023] The drain of the first type MOS transistor P9 is electrically connected to the drain of the second type MOS transistor N5;

[0024] The drain of the first type MOS transistor P10 is electrically connected to the drain of the second type MOS transistor N6;

[0025] The source of the second type MOS transistor N3 is electrically connected to the drain of the second type MOS transistor N7;

[0026] The source of the second type MOS transistor N4 is electrically connected to the drain of the second type MOS transistor N8;

[0027] The source of the second type MOS transistor N5 and the sources of the second type MOS transistors N6 , N7 and N8 are all connected to GND.

[0028] In an optional embodiment of the present invention, in the data holding stage, the first word line is at a low level, and the second word line is at a high level.

[0029] In an optional embodiment of the present invention, in the data writing phase, the first word line is at a high level, and the second word line is at a low level.

[0030] In an optional embodiment of the present invention, in the data reading phase, the first bit line and the second bit line, the first word line WL, are at a high level, and the second word line WWL is at a low level.

[0031] In an optional embodiment of the present invention, the type-one MOS transistor P1 , the type-one MOS transistor P2 , the type-two MOS transistor N1 , and the type-two MOS transistor N2 are transmission transistors.

[0032] In an optional embodiment of the present invention, the gate length of the first type MOS transistor and the second type MOS transistor is 60-70 nm, and the gate width of the first type MOS transistor and the second type MOS transistor is 150-160 nm.

[0033] In an optional embodiment of the present invention, the gate lengths of the first type MOS transistor and the second type MOS transistor are both 62-68 nm, and the gate widths of the first type MOS transistor and the second type MOS transistor are 152-158 nm.

[0034] In an optional embodiment of the present invention, the type of MOS transistor is a PMOS transistor.

[0035] In an optional embodiment of the present invention, the second type of MOS transistor is an NMOS transistor.

[0036] Beneficial effects of the present invention:

[0037] In the 18T radiation-resistant SRAM storage cell circuit of the present invention, the gate of a type of MOS transistor P5 is electrically connected to the drain of a type of MOS transistor P6, and the drain of a type of MOS transistor P5 is electrically connected to the gate of a type of MOS transistor P6, forming a cross-coupling structure to completely resist data flipping at a single node. At the same time, because the first storage node and the second storage node utilize a dual pull-up transistor and dual pull-down transistor structure, and the pull-down transistors are respectively controlled by different feedback, the dual nodes can still be restored to their initial state when data flipping occurs simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 Schematic diagram of the structure of an 18T radiation-resistant SRAM memory cell circuit provided in an embodiment of the present invention.

[0039] Figure 2 This is a timing waveform diagram of the 18T radiation-resistant SRAM memory cell circuit provided by an embodiment of the present invention.

[0040] Figure 3 This is a transient waveform simulation diagram of a single node of the 18T radiation-resistant SRAM memory cell circuit provided by an embodiment of the present invention being injected with a double-exponential current pulse at different times.

[0041] Figure 4 This is a transient waveform simulation diagram of the first storage node Q and the second storage node QB of the 18T radiation-resistant SRAM memory cell circuit provided by an embodiment of the present invention being simultaneously injected with a double-exponential current pulse.

[0042] Figure 5 This is a comparison diagram of the anti-upset capability of the 18T radiation-resistant SRAM memory cell circuit provided by an embodiment of the present invention and the radiation-resistant memory cell circuit in the prior art. DETAILED DESCRIPTION

[0043] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0045] like Figure 1 As shown, this embodiment provides an 18T radiation-resistant SRAM memory cell circuit, including: 10 type-one MOS transistors and 8 type-two MOS transistors, the 10 type-one MOS transistors are sequentially denoted as P1 to P10, and the 8 type-two MOS transistors are sequentially denoted as N1 to N8, wherein:

[0046] The gate of the first type of MOS transistor P5 is electrically connected to the drain of the first type of MOS transistor P6, and the drain of the first type of MOS transistor P5 is electrically connected to the gate of the first type of MOS transistor P6, forming a cross-coupling structure;

[0047] The first-class MOS transistors P3 and P7 are pull-up transistors on the first storage node, the second-class MOS transistors N3 and N7 are pull-down transistors on the first storage node, the first-class MOS transistors P4 and P8 are pull-up transistors on the second storage node, and the second-class MOS transistors N4 and N8 are pull-down transistors on the second storage node;

[0048] The first type of MOS transistor P5 is a pull-up transistor on the first redundant node, the first type of MOS transistor P9 and N5 are pull-down transistors on the first redundant storage node, the first type of MOS transistor P6 is a pull-up transistor on the first redundant node, and the second type of MOS transistor P10 and N6 are pull-down transistors on the second redundant node;

[0049] The gate of the first type of MOS transistor P1 is connected to the second word line, and the source of the first type of MOS transistor P1 is connected to the first bit line;

[0050] The gate of the first type of MOS transistor P2 is connected to the second word line, and the source of the first type of MOS transistor P2 is connected to the second bit line;

[0051] The gate of the second type MOS transistor N1 is connected to the first word line, and the source of the second type MOS transistor N1 is connected to the first bit line;

[0052] The gate of the second type MOS transistor N2 is connected to the first word line, and the source of the second type MOS transistor N2 is connected to the second bit line.

[0053] In an optional embodiment, all 10 of the first type of MOS transistors are PMOS transistors, and all 8 of the second type of MOS transistors are NMOS transistors. The 18T radiation-resistant SRAM storage cell circuit of the present invention includes: PMOS transistor P1, PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5, PMOS transistor P6, PMOS transistor P7, PMOS transistor P8, PMOS transistor P9, PMOS transistor P10, NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, NMOS transistor N7, and NMOS transistor N8, wherein the PMOS transistor P1, PMOS transistor P2, NMOS transistor N1, and NMOS transistor N2 are transmission transistors.

[0054] See also Figure 1 As shown, Figure 1 The figure shows the specific connection relationship of each MOS transistor in the 18T radiation-resistant SRAM storage cell circuit of the present invention, wherein the first word line is marked as WL, the second word line is marked as WWL, the first bit line is marked as BL, the second bit line is marked as BLB, the first storage node is marked as Q, the second storage node is marked as QB, the first redundant node is marked as S0, the second redundant node is marked as S1, the power terminal is marked as VDD, and the ground terminal is marked as GND.

[0055] The drain of the PMOS transistor P1 is electrically connected to the drain of the PMOS transistor P5, the source of P9, the gate of P6, the gate of P8, the gate of the PMOS transistor P4, and the gate of the second type MOS transistor N6 and the gate of N4;

[0056] The drain of the PMOS transistor P2 is electrically connected to the drain of the PMOS transistor P6, the source of P10, the gate of P5, the gate of P7, the gate of P3, and the gate of the NMOS transistors N5 and N3;

[0057] The drain of the PMOS transistor P3 is electrically connected to the source of P7, and the source of the PMOS transistor P3, the source of P4, the source of P5, and the source of P6 are all connected to the power supply VDD;

[0058] The drain of the PMOS tube P4 is electrically connected to the source of P8;

[0059] The drain of the PMOS transistor P7, the gate of the PMOS transistor P9, the drain of the NMOS transistor N3, the gate of N8, and the drain of N1 are electrically connected to the first storage node Q;

[0060] The drain of the PMOS transistor P8, the gate of the PMOS transistor P10, and the drain of the NMOS transistor N4, the gate of N7, and the drain of N2 are connected to the second storage node QB;

[0061] The drain of the PMOS tube P9 is electrically connected to the drain of the NMOS tube N5;

[0062] The drain of the PMOS tube P10 is electrically connected to the drain of the NMOS tube N6;

[0063] The source of the NMOS transistor N3 is electrically connected to the drain of the NMOS transistor N7;

[0064] The source of the NMOS tube N4 is electrically connected to the drain of the NMOS tube N8;

[0065] The source of the NMOS transistor N5 and the sources of the NMOS transistors N6 , N7 , and N8 are all connected to GND.

[0066] Furthermore, in the 18T polarity-reinforced radiation-resistant SRAM memory cell circuit provided in an embodiment of the present invention, the gate lengths of all PMOS and NMOS tubes are 60-70 nm. Preferably, the gate lengths of the PMOS and NMOS tubes are 62-68 nm, such as 62 nm, 63 nm, 64 nm, 65 nm, 66 nm, 67 nm, and 68 nm. The gate widths of the PMOS and NMOS tubes are 150-160 nm. Preferably, the gate widths of the PMOS and NMOS tubes are 152-158 nm, such as 152 nm, 153 nm, 154 nm, 155 nm, 156 nm, 157 nm, and 158 nm.

[0067] The principle of the 18T radiation-resistant SRAM memory cell circuit provided by the embodiment of the present invention is as follows:

[0068] During the data retention phase:

[0069] The first word line WL is at a low level, and the second word line WWL is at a high level.

[0070] During the data writing phase:

[0071] The first word line WL is at a high level, and the NMOS transistors N1 and N2 are turned on. The second word line WWL is at a low level, and the PMOS transistors P1 and P2 are turned on.

[0072] If the first bit line BL is at a high level and the second bit line BLB is at a low level, then "1" is written to the first storage node Q through the NMOS transistor N1, "1" is written to the first redundant node S0 through the PMOS transistor P1, "0" is written to the second storage node QB through the NMOS transistor N2, and "0" is written to the second redundant node S1 through the PMOS transistor P2.

[0073] On the contrary, if the first bit line BL is at a low level and the second bit line BLB is at a high level, then "0" is written to the first storage node Q through the NMOS transistor N1, "0" is written to the first redundant node S0 through the PMOS transistor P1, "1" is written to the second storage node QB through the NMOS transistor N2, and "1" is written to the second redundant node S1 through the PMOS transistor P2.

[0074] During the data reading phase:

[0075] The first bit line BL and the second bit line BLB are both precharged to a high level, the first word line WL is at a high level, and the NMOS transistors N1 and N2 are turned on.

[0076] If the data stored in the unit circuit is "0", then "Q=S0=0, QB=S1=1", then the first bit line BL is discharged through discharge path 1: NMOS tubes N3 and N7, and discharge path 2: PMOS tube P9 and NMOS tube N5, and the voltage of the bit line BLB does not change, so that a voltage difference is generated between the first bit line BL and the second bit line BLB, and then the data is read out through the sense amplifier.

[0077] If the data stored in the unit circuit is "1", then "Q=S0=1, QB=S1=0", then the second bit line BLB is discharged to the ground through discharge path 1: NMOS transistors N4 and N8, and discharge path 2: PMOS transistor P10 and NMOS transistor N6, so that a voltage difference is generated between the first bit line BL and the second bit line BLB, and then the data is read out through the sense amplifier.

[0078] like Figure 2 As shown in FIG, the timing waveform diagram of the 18T radiation-resistant SRAM memory cell circuit provided by the embodiment of the present invention, the specific simulation conditions are: Corner: TT, Temperature: 25°C, VDD: 1.2V. Figure 2 It can be seen that the data "1" is written in 50-100ns, the data "1" is read out in 200-250ns, the data "0" is written in 350-400ns, and the data "0" is read out in 500-550ns. It can be seen that the 18T radiation-resistant SRAM storage cell circuit provided by the present invention can realize the operations of writing "1", reading "1", writing "0", and reading "0" on the storage node.

[0079] like Figure 3 As shown in FIG, a transient waveform simulation diagram of a single node of an 18T radiation-resistant SRAM memory cell circuit provided by an embodiment of the present invention being injected with a double exponential current pulse at different times. Figure 3As can be seen, at 100ns, the first storage node Q was struck by a single event, causing the data to flip from "0" to "1." Through the circuit feedback structure, the data was quickly restored. At 200ns, the first redundant node S0 was struck by a single event, causing the data to flip from "0" to "1." Through the circuit feedback structure, the data was quickly restored. At 300ns, the first redundant node QB was struck by a single event, causing the data to flip from "1" to "0." Through the circuit feedback structure, the data was quickly restored.

[0080] like Figure 4 As shown in FIG, a transient waveform simulation diagram of the first storage node Q and the second storage node QB of the 18T radiation-resistant SRAM memory cell circuit provided by the embodiment of the present invention is simultaneously injected with a double exponential current pulse. Figure 1 and Figure 4 Further analysis of this process:

[0081] When Q and QB are simultaneously injected with a double exponential current pulse, the voltage at Q suddenly rises, while the voltage at QB suddenly drops. The rise in the voltage at Q causes P9 to turn off transiently and N8 to turn on. The drop in the voltage at QB causes transistor P10 to turn on transiently and transistor N7 to turn off. However, the pull-up transistor P5 at P remains off, and the pull-up transistor P6 at S1 remains on, so the data at S1 and S0 remain unchanged. The pull-down transistor N8 at QB is temporarily turned on, but the pull-down transistor N4 remains off, and the pull-up transistor remains on, so the data at QB remains unchanged. The pull-down transistor N7 at Q is temporarily turned off, but the pull-up transistors P3 and P7 remain off. Since the data at QB remains unchanged, the temporarily turned-off transistor N7 returns to the on state, and the data stored in the entire SRAM remains unchanged.

[0082] It should be noted that this embodiment only takes the case where the first storage node Q and the second storage node QB are simultaneously injected with a double exponential current pulse as an example. It is understandable that when any two other nodes among the first storage node Q, the second storage node QB, the first redundant node S0, and the first redundant node S1 are injected with a double exponential current pulse, the analysis principle is similar to that when the first storage node Q and the second storage node QB are simultaneously injected with a double exponential current pulse, and thus will not be repeated here.

[0083] like Figure 5 As shown in the figure, the anti-flip capability comparison diagram of the 18T radiation-resistant SRAM memory cell circuit provided by the present invention and the radiation-resistant memory cell circuit in the prior art is shown. Figure 5 The SIMR) element circuit in the circuit has the best anti-flip capability.

[0084] It should be noted that the anti-rollover capability described in this article is obtained by the following formula:

[0085]

[0086] Among them, P s Represents the probability of recovery from SEU, P d represents the probability of recovery from DNU, HSNM represents the noise margin during the data hold phase, and Q c represents the critical charge, t ra Represents the data write delay time, t wa Represents the data reading delay time.

[0087] The SEU resistance of the 18T radiation-resistant SRAM memory cell circuit provided by the present invention is further described below:

[0088] The polarity hardening principle states that radiation-induced current can only flow from the n-type diffusion region to the p-type diffusion region through the pn junction due to its reverse bias. This means that if the sensitive node is composed only of PMOS transistors, the impact of radiation particles will not change the node voltage from "1" to "0"; vice versa, if only NMOS transistors are used, the node voltage cannot flip from "0" to "1".

[0089] Taking the storage state of "0" (i.e., Q="0", QB="1", S0="0", S1="1") as an example, since the second redundant node S1 is surrounded only by the PMOS transistor and its state is "1", the second redundant node S1 is not a sensitive node (a sensitive node refers to a node that can cause data flipping (logical value change) after a single event effect occurs, and the sensitive nodes are different in different storage states). Therefore, the sensitive nodes are the first storage node Q, the second storage node QB, and the first redundant node S0.

[0090] When the data of the first storage node Q deflects, that is, from state "0" to state "1". The data of the first storage node Q deflects from "0" to "1", causing N8 to be temporarily turned on and P9 to be temporarily turned off. Since the pull-up tube P5 of the first storage node S0 is controlled by the second redundant node S1 and remains closed, the temporary closing of P9 does not affect the data of the first redundant node S0. The pull-down tube N4 of the second storage node QB remains closed due to the unchanged data of the first redundant node S0 and does not affect the data of the storage node QB. The first storage node Q is connected to GND through the turned-on N3 and N7, thereby restoring to the logic value "0".

[0091] When the first redundant node S0 experiences a data transition, from state "0" to state "1," N4 and N6 are temporarily turned on, while P4, P6, and P8 are temporarily turned off. Because pull-down transistor N8 on the second storage node QB is controlled by the first storage node Q and remains off, the temporary turn-on of N4 does not affect the data on storage node QB. Pull-down transistor P10 on the second redundant node S1 remains off because the data on QB remains unchanged, so the data on PB remains unchanged. The first redundant node S0 is connected to GND via the turned-on P9 and N5, thereby restoring its logic value to "0."

[0092] When the second storage node QB experiences a data transition, from state "1" to state "0," N7 is temporarily turned off and P10 is temporarily turned on. Since the pull-down transistor N6 of the second redundant node S1 is controlled by the data node, the second redundant node S1, and remains off, the brief turn-on of P10 does not affect the data on the second redundant node S1. The pull-up transistor P7 of the first storage node Q remains off due to the unchanged second redundant node S1, so the brief turn-off of its pull-down transistor N7 does not affect its data. The second storage node QB is connected to the power supply VDD through the turned-on P4 and P8, thereby restoring its logic value to "1."

[0093] It should be noted that when the storage state is "1", the principle of combating SEU is similar and will not be repeated here.

[0094] In the description herein, numerous specific details, such as examples of components and / or methods, are provided to provide a complete understanding of the embodiments of the present invention. However, those skilled in the art will recognize that embodiments of the present invention may be practiced without one or more of the specific details or with other devices, systems, assemblies, methods, components, materials, parts, etc. In other cases, well-known structures, materials, or operations are not specifically shown or described in detail to avoid obscuring aspects of the embodiments of the present invention.

[0095] It should also be understood that one or more of the elements shown in the figures may also be implemented in a more separate or more integrated manner, or even removed because they are inoperable in certain circumstances or provided because they may be useful depending on the application.

[0096] In addition, unless otherwise expressly indicated, any marking arrows in the drawings should be regarded as illustrative only and not limiting. Furthermore, unless otherwise indicated, the term "or" as used herein is generally intended to mean "and / or." Where a term is unclear in providing separation or combination capabilities, the combination of components or steps will also be considered as indicated.

[0097] The above description of the illustrated embodiments of the present invention (including that described in the Abstract) is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. Although specific embodiments of the present invention and examples of the present invention are described herein for illustrative purposes only, as those skilled in the art will recognize and appreciate, various equivalent modifications are possible within the spirit and scope of the present invention. As noted, modifications may be made to the present invention in light of the above description of the illustrated embodiments of the present invention, and such modifications will be within the spirit and scope of the present invention.

[0098] Systems and methods have been generally described herein in detail to facilitate understanding of the present invention. In addition, various specific details have been given to provide an overall understanding of embodiments of the present invention. However, those skilled in the relevant art will recognize that embodiments of the present invention may be practiced without one or more of these specific details, or with other devices, systems, accessories, methods, components, materials, parts, etc. In other cases, well-known structures, materials, and / or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the present invention.

[0099] Thus, although the invention has been described herein with reference to specific embodiments thereof, freedom of modification, various changes and substitutions are contemplated within the foregoing disclosure, and it should be understood that in some cases, some features of the invention will be employed without the corresponding use of other features without departing from the scope and spirit of the claimed invention. Thus, many modifications may be made to adapt a particular environment or material to the true scope and spirit of the invention. The invention is not intended to be limited to the specific terminology used in the claims below and / or to the specific embodiments disclosed as the best mode contemplated for carrying out the invention, but the invention is intended to include any and all embodiments and equivalents falling within the scope of the appended claims. Thus, the scope of the invention will be determined solely by the appended claims.

Claims

1. An 18T radiation-resistant SRAM memory cell circuit, characterized in that: include: There are 10 first-class MOS transistors, 8 second-class MOS transistors, and 4 nodes. The 10 first-class MOS transistors are sequentially recorded as P1 to P10, the 8 second-class MOS transistors are sequentially recorded as N1 to N8, and the 4 nodes are sequentially a first storage node, a second storage node, a first redundant node, and a second redundant node. The gate of the first type of MOS transistor P5 is electrically connected to the drain of the first type of MOS transistor P6, and the drain of the first type of MOS transistor P5 is electrically connected to the gate of the first type of MOS transistor P6, forming a cross-coupling structure; The first-type MOS transistors P3 and P7 are pull-up transistors on the first storage node, the second-type MOS transistors N3 and N7 are pull-down transistors on the first storage node, the first-type MOS transistors P4 and P8 are pull-up transistors on the second storage node, and the second-type MOS transistors N4 and N8 are pull-down transistors on the second storage node; The first type MOS transistor P5 is a pull-up transistor on the first redundant node, the first type MOS transistors P9 and N5 are pull-down transistors on the first redundant storage node, the first type MOS transistor P6 is a pull-up transistor on the second redundant node, and the second type MOS transistors P10 and N6 are pull-down transistors on the second redundant node; The gate of the first type of MOS transistor P1 is connected to the second word line, and the source of the first type of MOS transistor P1 is connected to the first bit line; The gate of the first type of MOS transistor P2 is connected to the second word line, and the source of the first type of MOS transistor P2 is connected to the second bit line; The gate of the second type MOS transistor N1 is connected to the first word line, and the source of the second type MOS transistor N1 is connected to the first bit line; The gate of the second type MOS transistor N2 is connected to the first word line, and the source of the second type MOS transistor N2 is connected to the second bit line; Among them, the specific connection relationship of each MOS tube is: The drain of the first type MOS transistor P1 is electrically connected to the drain of the first type MOS transistor P5, the source of P9, the gate of P6, the gate of P8, the gate of the PMOS transistor P4, and the gate of the second type MOS transistor N6 and the gate of N4; The drain of the first type MOS transistor P2 is electrically connected to the drain of the first type MOS transistor P6, the source of P10, the gate of P5, the gate of P7, the gate of P3, and the gate of the second type MOS transistor N5 and the gate of N3; The drain of the first-class MOS transistor P3 is electrically connected to the source of P7, and the source of the first-class MOS transistor P3 and the sources of P4, P5, and P6 are all connected to the power supply VDD; The drain of a type of MOS transistor P4 is electrically connected to the source of P8; The drain of the first type MOS transistor P7, the gate of the first type MOS transistor P9, the drain of the second type MOS transistor N3, the gate of N8, and the drain of N1 are electrically connected to the first storage node Q; The drain of the first type MOS transistor P8, the gate of the first type MOS transistor P10, and the drain of the second type MOS transistor N4, the gate of N7, and the drain of N2 are connected to the second storage node QB; The drain of the first type MOS transistor P9 is electrically connected to the drain of the second type MOS transistor N5; The drain of the first type MOS transistor P10 is electrically connected to the drain of the second type MOS transistor N6; The source of the second type MOS transistor N3 is electrically connected to the drain of the second type MOS transistor N7; The source of the second type MOS transistor N4 is electrically connected to the drain of the second type MOS transistor N8; The source of the second type MOS transistor N5 and the sources of the second type MOS transistors N6 , N7 and N8 are all connected to GND.

2. The 18T radiation-resistant SRAM memory cell circuit according to claim 1, wherein: In the data holding phase, the first word line is at a low level, and the second word line is at a high level.

3. The 18T radiation-resistant SRAM memory cell circuit according to claim 1, characterized in that: During the data writing phase, the first word line is at a high level, and the second word line is at a low level.

4. The 18T radiation-resistant SRAM memory cell circuit according to claim 1, characterized in that: In the data reading phase, the first bit line and the second bit line, the first word line WL, are at a high level, and the second word line WWL is at a low level.

5. The 18T radiation-resistant SRAM memory cell circuit according to claim 1, wherein: The type 1 MOS transistor P1 , type 1 MOS transistor P2 , type 2 MOS transistor N1 and type 2 MOS transistor N2 are transmission transistors.

6. The 18T radiation-resistant SRAM memory cell circuit according to claim 1, wherein: The gate length of the first type MOS transistor and the second type MOS transistor is 60-70 nm, and the gate width of the first type MOS transistor and the second type MOS transistor is 150-160 nm.

7. The 18T radiation-resistant SRAM memory cell circuit according to claim 6, characterized in that: The gate lengths of the first-class MOS transistor and the second-class MOS transistor are both 62-68 nm, and the gate widths of the first-class MOS transistor and the second-class MOS transistor are 152-158 nm.

8. The 18T radiation-resistant SRAM memory cell circuit according to claim 1, wherein: The type of MOS transistor is a PMOS transistor.

9. The 18T radiation-resistant SRAM memory cell circuit according to claim 1, wherein: The second type of MOS transistor is an NMOS transistor.

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