A test structure and a method for forming the same

Abstract

A test structure and a method for forming the same, the test structure comprising: a plurality of metal wires extending along a first direction and arranged in parallel along a second direction, the metal wires comprising a test area, a first lead area located on one side of the test area, and a second lead area located on the other side of the test area along the first direction, the metal wires comprising a first metal wire and a second metal wire arranged alternately and spaced along the second direction; a partition layer penetrating the first metal wire at the junction of the second lead area and the test area, and the second metal wire at the junction of the first lead area and the test area, the partition layer being used to separate the first metal wire and the second metal wire in the first direction; a first through-hole interconnection structure located in the first lead area and at the top of the first metal wire, used as a test signal loading end for the first metal wire; a second through-hole interconnection structure located in the second lead area and at the top of the second metal wire, used as a test signal loading end for the second metal wire. The present invention improves the accuracy of the test results.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and particularly to a test structure and a method for forming the same. Background Art

[0002] In the process of manufacturing semiconductor devices, it is often necessary to test the reliability of the devices. Especially with the development of semiconductor process technology, semiconductor devices are becoming more and more integrated, the size of semiconductor devices is gradually shrinking proportionally, and their critical dimension (CD) is becoming smaller and smaller. For semiconductor devices with an increasingly small CD, the dielectric layer (Inter Layer Dielectric, ILD) in the BEOL (Back End of Line) will also become thinner and thinner, and it is also crucial to test the performance of the circuit structure manufactured by BEOL.

[0003] In this field, time-dependent dielectric breakdown (TDDB) testing is usually used for reliability testing. It can be used to predict the service life of semiconductor devices. Generally, a constant voltage is applied to the metal line to make the device in an accumulation state, which is the so-called TDDB. After a period of time, the dielectric material will be broken down, and the time elapsed from the start of applying a constant voltage to the metal line to the end of the breakdown of the dielectric material is the life of the dielectric material under this condition. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a test structure and a method for forming the same, which improve the accuracy of test results.

[0005] To solve the above problems, an embodiment of the present invention provides a test structure, including: multiple metal wires, the metal wires extend along a first direction and are arranged in parallel along a second direction, the second direction is perpendicular to the first direction, the metal wires include a test area along the first direction, a first lead area located on one side of the test area, and a second lead area located on the other side of the test area, both the first lead area and the second lead area are used to load test signals, the metal wires include first metal wires and second metal wires arranged alternately and at intervals along the second direction; an isolation layer, penetrating through the first metal wire at the junction of the second lead area and the test area, and the second metal wire at the junction of the first lead area and the test area, the isolation layer is used to divide the first metal wire and the second metal wire in the first direction; a first via interconnect structure, located in the first lead area and on top of the first metal wire, the first via interconnect structure is used as the test signal loading end of the first metal wire; a second via interconnect structure, located in the second lead area and on top of the second metal wire, the second via interconnect structure is used as the test signal loading end of the second metal wire.

[0006] Correspondingly, an embodiment of the present invention further provides a method for forming a test structure, including: providing a substrate, on which a first dielectric layer is formed. The first dielectric layer includes a test region, a first lead region located on one side of the test region, and a second lead region located on the other side of the test region along a first direction. Both the first lead region and the second lead region are used for loading test signals; forming a core layer covering the first dielectric layer; forming first trenches extending along the first direction and arranged in parallel along a second direction in the core layer. In the first direction, the first trenches in the second lead region and the test region are isolated from each other. The second direction is perpendicular to the first direction; forming second trenches extending along the first direction and arranged in parallel along the second direction in the core layer. In the first direction, the second trenches in the first lead region and the test region are isolated from each other, wherein the second trenches and the first trenches are alternately spaced along the second direction; etching the first dielectric layer at the bottoms of the first trenches and the second trenches to form interconnect openings, the interconnect openings including first interconnect openings and second interconnect openings alternately spaced along the second direction. The first interconnect openings correspond to the first trenches, and the second interconnect openings correspond to the second trenches; forming metal wires in the interconnect openings, wherein the metal wires in the first interconnect openings are first metal wires, and the metal wires in the second interconnect openings are second metal wires; after forming the metal wires, forming a second dielectric layer on the first dielectric layer; forming a first via interconnect structure in the second dielectric layer of the first lead region, the first via interconnect structure being located on top of the first metal wire and in contact with the first metal wire, and the first via interconnect structure being used as a test signal loading end of the first metal wire; forming a second via interconnect structure in the second dielectric layer of the second lead region, the second via interconnect structure being located on top of the second metal wire and in contact with the second metal wire, and the second via interconnect structure being used as a test signal loading end of the second metal wire.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] In the test structure provided by the embodiment of the present invention, the isolation layer penetrates through the first metal line at the junction of the second lead region and the test region, and the second metal line at the junction of the first lead region and the test region. The isolation layer located at the junction of the second lead region and the test region is used to divide the first metal line in the first direction, and the isolation layer located at the junction of the first lead region and the test region is used to divide the second metal line in the first direction; when the test structure of the embodiment of the present invention is used to test the time-dependent dielectric breakdown life (Time Dependent Dielectric Breakdown, TDDB) or the breakdown voltage (Breakdown Voltage, VBD), the dielectric breakdown life of the minimum pitch is used as the test life. Since at the junction of the first lead region and the test region, the isolation layer completely cuts off the second metal line, and at the junction of the second lead region and the test region, the isolation layer completely cuts off the first metal line, then during the test, the second metal line in the first lead region and the second metal line in the test region will not be connected, and the first metal line in the second lead region and the first metal line in the test region will not be connected. Therefore, when testing the dielectric breakdown life between adjacent first and second metal lines, the influence of the first via interconnect structure on the first metal line and the second via interconnect structure on the second metal line on the test structure is reduced, the probability of test error caused by the presence of the first via interconnect structure and the second via interconnect structure is reduced, and the accuracy of the test result is improved.

[0009] In the method for forming the test structure provided by the embodiment of the present invention, the first trenches located in the second lead region and the test region are isolated from each other, and the second trenches located in the first lead region and the test region are isolated from each other. The first dielectric layer at the bottoms of the first trenches and the second trenches is etched to form an interconnection opening, and a metal wire is formed in the interconnection opening. When the test structure formed by the embodiment of the present invention is used to test the time-dependent dielectric breakdown lifetime or the breakdown voltage, the dielectric breakdown lifetime of the minimum pitch is used as the test lifetime. Since the first trenches located in the second lead region and the test region are isolated from each other, and the second trenches located in the first lead region and the test region are isolated from each other, after etching the first dielectric layer at the bottoms of the first trenches and the second trenches, at the junction of the first lead region and the test region, the first dielectric layer is retained and can serve as a separation layer to completely isolate the second metal wire. At the junction of the second lead region and the test region, the first dielectric layer is also retained and can also serve as a separation layer to completely isolate the first metal wire. Then, during the test, the second metal wire in the first lead region and the second metal wire in the test region will not be connected, and the first metal wire in the second lead region and the first metal wire in the test region will not be connected. Thus, when testing the dielectric breakdown lifetime between adjacent first and second metal wires, the influence of the first vias interconnection structure on the first metal wire and the second vias interconnection structure on the second metal wire on the test result is reduced, the probability of test error caused by the existence of the first vias interconnection structure and the second vias interconnection structure is lowered, and the accuracy of the test result is improved. Description of the Drawings

[0010] Figure 1 is a top view of a test structure;

[0011] Figures 2 to 4 is a schematic structural diagram of an embodiment of the test structure of the present invention;

[0012] Figures 5 to 25 is a schematic structural diagram corresponding to each step in an embodiment of the method for forming the test structure of the present invention. Detailed Description of the Embodiment

[0013] Currently, in the case of continuous shrinking of the technology node, how to improve the accuracy of the test results has become a challenge, and the accuracy of the test results needs to be improved. The reason why the accuracy of the test results needs to be improved is analyzed in combination with a test structure.

[0014] Figure 1 is a top view corresponding to a test structure.

[0015] The test structure includes: a dielectric layer 10, and the dielectric layer 10 extends along a first direction (such as Figure 1In the X direction, it includes a test area 10T, a first lead area 10V1 located on one side of the test area 10T, and a second lead area 10V2 located on the other side of the test area 10T. Both the first lead area 10V1 and the second lead area 10V2 are used to load test signals; multiple metal lines (not labeled) are formed in the dielectric layer 10. The metal lines extend in a first direction and are arranged in parallel in a second direction (such as Figure 1 in the Y direction). The second direction is perpendicular to the first direction. The metal lines include first metal lines 21 and second metal lines 22 that are alternately and equally spaced along the second direction; a first via interconnect structure 31 is located at the top of the first metal line 21 in the first lead area 10V1 and is used as a test signal loading end for the first metal line 21; a second via interconnect structure 32 is located at the top of the second metal line 22 in the second lead area 10V2 and is used as a test signal loading end for the second metal line 22.

[0016] Generally, when forming the first via interconnect structure 31 and the second via interconnect structure 32, the sizes of the first via interconnect structure 31 and the second via interconnect structure 32 expand along the second direction, so that the distance w1 between the first via interconnect structure 31 at the top of the first metal line 21 and the adjacent second metal line 22 is less than the distance d1 between the adjacent first metal line 21 and the second metal line 22. Similarly, the distance w2 between the second via interconnect structure 32 on the second metal line 22 and the adjacent first metal line 21 is less than the distance d1 between the adjacent first metal line 21 and the second metal line 22. When the test structure is used to test the time-dependent dielectric breakdown lifetime or the breakdown voltage, the dielectric breakdown lifetime of the minimum distance is used as the test lifetime. Then, when testing the dielectric layer 10 between the adjacent first metal line 21 and the second metal line 22, due to the existence of both the distances w1 and w2 being less than the distance d1 between the adjacent first metal line 21 and the second metal line 22, it is difficult to accurately detect the breakdown lifetime of the dielectric layer 10 between the adjacent first metal line 21 and the second metal line 22, and it is easy to cause the actually detected breakdown lifetime to be the breakdown lifetime of the dielectric layer 10 between the first via interconnect structure 31 at the top of the first metal line 21 and the adjacent second metal line 22, or the breakdown lifetime of the dielectric layer 10 between the second via interconnect structure 32 on the second metal line 22 and the adjacent first metal line 21, thereby resulting in a large error in the test result and greatly affecting the accuracy of the test result.

[0017] To solve the above technical problems, an embodiment of the present invention provides a test structure, including: multiple metal lines, the metal lines extending along a first direction and arranged in parallel along a second direction, the second direction being perpendicular to the first direction, the metal lines including a test area, a first lead area located on one side of the test area, and a second lead area located on the other side of the test area along the first direction, both the first lead area and the second lead area being used to load test signals, the metal lines including first metal lines and second metal lines arranged alternately and at intervals along the second direction; an isolation layer penetrating through the first metal line at the junction of the second lead area and the test area, and the second metal line at the junction of the first lead area and the test area, the isolation layer being used to divide the first metal line and the second metal line in the first direction; a first via interconnect structure located in the first lead area and on top of the first metal line, the first via interconnect structure being used as a test signal loading end of the first metal line; a second via interconnect structure located in the second lead area and on top of the second metal line, the second via interconnect structure being used as a test signal loading end of the second metal line.

[0018] When the test structure of the embodiment of the present invention is used to test the time-dependent dielectric breakdown lifetime or the breakdown voltage, the dielectric breakdown lifetime of the minimum spacing is used as the test lifetime. Since at the junction of the first lead area and the test area, the isolation layer completely cuts off the second metal line, and at the junction of the second lead area and the test area, the isolation layer completely cuts off the first metal line, during the test, the second metal line in the first lead area and the second metal line in the test area will not be connected, and the first metal line in the second lead area and the first metal line in the test area will not be connected. Thus, when testing the dielectric breakdown lifetime between adjacent first metal lines and second metal lines, the influence of the first via interconnect structure on the first metal line and the second via interconnect structure on the second metal line on the test structure is reduced, the probability of test error caused by the existence of the first via interconnect structure and the second via interconnect structure is decreased, and the accuracy of the test result is improved.

[0019] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0020] Figures 2 to 4 is a schematic structural diagram of an embodiment of the test structure of the present invention, where, Figure 2 is a top view, Figure 3 a is Figure 2 a cross-sectional view along the BB direction, Figure 3 b is Figure 2 a cross-sectional view along the B’B’ direction, Figure 4 is Figure 2 a cross-sectional view along the CC direction.

[0021] The test structure includes: a plurality of metal wires (not shown), the metal wires are arranged along a first direction (such as Figure 2 X direction) and along the second direction (such as Figure 2 The second direction is perpendicular to the first direction. The metal wires along the first direction include a test area 101T, a first lead area 101V1 located on one side of the test area 101T, and a second lead area 101V2 located on the other side of the test area 101T. The first lead area 101V1 and the second lead area 101V2 are both used to load test signals. The metal wires along the second direction include first metal wires 211 and second metal wires 221 arranged alternately at intervals; an isolation layer 111, a first metal wire 211 passing through the boundary between the second lead area 101V2 and the test area 101T, and a first lead area 101V2 passing through the first metal wire 211 passing through the boundary between the second lead area 101V2 and the test area 101T. The second metal line 221 at the junction of the lead area 101V1 and the test area 101T, the isolation layer 111 is used to divide the first metal line 211 and the second metal line 221 in the first direction; the first through-hole interconnection structure 311 is located in the first lead area 101V1 and on the top of the first metal line 211, and the first through-hole interconnection structure 311 is used as the test signal loading end of the first metal line 211; the second through-hole interconnection structure 321 is located in the second lead area 101V2 and on the top of the second metal line 221, and the second through-hole interconnection structure 321 is used as the test signal loading end of the second metal line 221.

[0022] In this embodiment, the test structure includes a TDDB test structure or a VBD test structure.

[0023] The TDDB test structure is a time-dependent dielectric breakdown (TDDB) test structure, which is used to predict the service life of semiconductor devices. Usually, the breakdown life of dielectric materials is determined by detecting the breakdown time. A constant voltage is applied to the metal line to put the device in an accumulation state. After a period of time, the dielectric material will be broken down. The time from the beginning of applying the constant voltage to the end of the dielectric material breakdown is the life of the dielectric material under this condition. The VBD test structure is a breakdown voltage (VBD) test structure. The VBD test is a pre-test of the TDDB test, which is used to determine the breakdown life of dielectric materials by detecting the breakdown voltage. The voltage is increased in a step-by-step manner on the metal line. When a certain voltage is reached, the dielectric material will be broken down. The voltage applied when the dielectric material is broken down is the breakdown voltage of the dielectric material.

[0024] As an example, the test structure is a TDDB test structure.

[0025] In this embodiment, the test structure includes a substrate 131. The substrate 131 includes a substrate structure layer (not shown in the figure), and the substrate structure layer includes a substrate (not shown in the figure). Taking the semiconductor structure to be tested as a planar type as an example, the substrate is a planar substrate. Specifically, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate. In other embodiments, when the test structure is a three-dimensional semiconductor structure, the substrate may also be a substrate with fins.

[0026] The substrate structure layer may also include other structures. For example, a gate structure, a doped region, a shallow trench isolation (STI) structure, and a dielectric layer, etc. Devices (such as MOS transistors or SRAM devices, etc.) are formed in the substrate structure layer. Specifically, the substrate structure layer further includes an interlayer dielectric layer (not shown in the figure) formed on the substrate and contact plugs (CT) (not shown in the figure) formed in the interlayer dielectric layer.

[0027] In this embodiment, a dielectric layer 101 is formed on the substrate 131.

[0028] In this embodiment, the dielectric layer 101 is an inter metal dielectric (IMD) layer, and the dielectric layer 101 is used to achieve electrical isolation between metal interconnect structures in the back end of line (BEOL) process.

[0029] For this purpose, the material of the dielectric layer 101 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6). In this embodiment, the material of the dielectric layer 101 includes one or more of SiOC, SiOCH, SiC, SiCN, SiO 2 , SiN, and SiON. In this embodiment, the material of the dielectric layer 101 is an ultra-low-k dielectric material, so as to reduce the parasitic capacitance between the back-end metal interconnect structures, and thus reduce the back-end RC delay. Specifically, the ultra-low-k dielectric material may be SiOCH.

[0030] Correspondingly, in this embodiment, the metal wire is located in the dielectric layer 101, and along the second direction, the adjacent first metal wire 211 and second metal wire 221 are spaced apart by the dielectric layer 101.

[0031] It should be noted that the first metal line 211 and the second metal interconnection line 221 are metal interconnection lines on the same layer.

[0032] In this embodiment, the metal line includes a test area 101T along the first direction, a first lead area 101V1 on one side of the test area 101T, and a second lead area 101V2 on the other side of the test area 101T. The first lead area 101V1 and the second lead area 101V2 are both used to load test signals, and the first metal line 211 and the second metal line 221 are arranged alternately at intervals.

[0033] In this embodiment, when the test structure is used for testing, test signals are respectively loaded on the first metal line 211 in the first lead area 101V1 and the second metal line 221 in the second lead area 101V2, and the dielectric breakdown life between adjacent first metal line 211 and second metal line 221 in the test area 101T is detected, so as to realize the reliability test.

[0034] In this embodiment, the intervals between adjacent first metal line 211 and second metal line 221 are equal.

[0035] Since when the test structure is used to test the time-dependent dielectric breakdown life, the dielectric breakdown life of the minimum spacing is used as the TDDB test life. In this embodiment, the intervals between adjacent first metal line 211 and second metal line 221 are equal. Then, when performing the TDDB test, the dielectric breakdown life between adjacent first metal line 211 and second metal line 221 can be detected more accurately, and the situation that the detection result has a large error due to different spacing sizes between adjacent first metal line 211 and second metal line 221 can be avoided to a large extent.

[0036] In this embodiment, the material of the first metal line 211 includes one or more of copper, aluminum, and copper alloy, and the material of the second metal line 221 includes one or more of copper, aluminum, and copper alloy, so that the first metal line 211 and the second metal line 221 are used to achieve better electrical conductivity.

[0037] In this embodiment, the first metal line 211 and the second metal interconnection line 221 are metal interconnection lines on the same layer. Therefore, the materials of the first metal line 211 and the second metal interconnection line 221 are the same.

[0038] The isolation layer 111 is used to divide the second metal line 221 in the first lead region 101V1 and the test region 101T in the first direction, so as to achieve physical isolation and electrical isolation between the second metal lines 221 in the first lead region 101V1 and the test region 101T. The isolation layer 111 is also used to divide the first metal line 211 in the second lead region 101V2 and the test region 101T in the first direction, so as to achieve physical isolation and electrical isolation between the first metal lines 211 in the second lead region 101V2 and the test region 101T.

[0039] When the test structure of this embodiment is used to test the time-dependent dielectric breakdown lifetime or the breakdown voltage, the dielectric breakdown lifetime of the minimum spacing is used as the test lifetime. Since at the junction of the first lead region 101V1 and the test region 101T, the isolation layer 111 completely cuts off the second metal line 221, and at the junction of the second lead region 101V2 and the test region 101T, the isolation layer 111 completely cuts off the first metal line 211. Then, during the test, the second metal line 221 in the first lead region 101V1 and the second metal line 221 in the test region 101T will not be connected, and the first metal line 211 in the second lead region 101V2 and the first metal line 211 in the test region 101T will not be connected. Thus, when testing the dielectric breakdown lifetime between adjacent first metal line 211 and second metal line 221, the influence of the first vias interconnect structure 311 on the first metal line 211 and the second vias interconnect structure 321 on the second metal line 221 on the test structure is reduced, the probability of test error caused by the existence of the first vias interconnect structure 311 and the second vias interconnect structure 321 is reduced, and the accuracy of the test result is improved.

[0040] In this embodiment, the isolation layer 111 in the first metal line 211 also extends along the second direction to the side walls of the second metal line 221 on both sides, which is beneficial to ensuring that the isolation layer 111 completely divides the first metal line 211 in the second lead region 101V2 and the test region 101T.

[0041] In this embodiment, the isolation layer 111 in the second metal line 221 also extends along the second direction to the side walls of the first metal line 211 on both sides, which is beneficial to ensuring that the isolation layer 111 completely divides the second metal line 221 in the first lead region 101V1 and the test region 101T, so as to improve the isolation effect of the isolation layer 111.

[0042] In this embodiment, the material of the isolation layer 111 includes one or more of SiOC, SiOCH, SiC, SiCN, SiO 2 、SiN and SiON.

[0043] In this embodiment, the isolation layer 111 and the dielectric layer 101 are of an integral structure.

[0044] In this embodiment, during the formation of the test structure, the first metal line 211 and the second metal line 221 are formed in corresponding interconnect openings which are formed in the dielectric layer 101. Usually, trenches are first formed in the core layer above the dielectric layer 101, and then the pattern of the trenches is transferred to the dielectric layer 101 to form the interconnect openings; the isolation layer 111 and the interconnect openings are formed in the same step by transferring the pattern of the trenches to the dielectric layer 101. That is to say, usually an etching mask is formed on the top of the dielectric layer 101 at the position corresponding to the isolation layer 111, so that the dielectric layer 101 at the position corresponding to the isolation layer 111 can be retained after etching. Therefore, the isolation layer 111 and the dielectric layer 101 are of an integral structure. Moreover, during the formation of the test structure, there is no need to separately perform the step of forming the isolation layer 111, which reduces the process complexity and improves the process efficiency.

[0045] Therefore, in this embodiment, the isolation layer 111 and the dielectric layer 101 are made of the same material.

[0046] In other embodiments, the isolation layer and the dielectric layer may also be independent structures.

[0047] It should be noted that the line width dimension of the isolation layer 111 in the first direction should not be too small or too large. If the line width dimension of the isolation layer 111 in the first direction is too small, the isolation effect of the isolation layer 111 is weakened, and thus it is difficult for the isolation layer 111 to completely isolate the first metal line 211 and the second metal line 221; if the line width dimension of the isolation layer 111 in the first direction is too large, the isolation layer 111 occupies too much space of the first metal line 211 and the second metal line 221, affecting the formation quality and performance of the first metal line 211 and the second metal line 221. At the same time, the too large line width dimension of the isolation layer 111 also causes unnecessary process waste. For this reason, in this embodiment, the line width dimension of the isolation layer 111 in the first direction is 20 nm to 35 nm.

[0048] In this embodiment, the dielectric layer 101 is defined as the first dielectric layer 101, and a second dielectric layer 301 covering the metal lines is further formed on the first dielectric layer 101.

[0049] The second dielectric layer 301 is also used to achieve electrical isolation between metal interconnect structures in the back-end process.

[0050] To this end, the material of the second dielectric layer 301 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6). In this embodiment, the material of the second dielectric layer 301 includes one or more of SiOC, SiOCH, SiC, SiCN, SiO 2 , SiN, and SiON. In this embodiment, the material of the second dielectric layer 301 is an ultra-low-k dielectric material, so as to reduce the parasitic capacitance between the back-end metal interconnect structures, and further reduce the back-end RC delay. Specifically, the ultra-low-k dielectric material can be SiOCH.

[0051] Correspondingly, the first vias interconnect structure 311 and the second vias interconnect structure 321 are located in the second dielectric layer 301.

[0052] The first vias interconnect structure 311 is used as the test signal loading end of the first metal line 211, and the second vias interconnect structure 321 is used as the test signal loading end of the second metal line 221.

[0053] Generally, when forming the first vias interconnect structure 311 and the second vias interconnect structure 321, the sizes of the first vias interconnect structure 311 and the second vias interconnect structure 321 will expand along the second direction.

[0054] Therefore, in this embodiment, along the second direction, the width dimension of the first vias interconnect structure 311 is greater than the width dimension of the first metal line 211. Similarly, along the second direction, the width dimension of the second vias interconnect structure 321 is greater than the width dimension of the second metal line 221.

[0055] That is to say, the distance w1 between the first vias interconnect structure 311 on the top of the first metal line 211 and the adjacent second metal line 221 is less than the distance d1 between the adjacent first metal line 211 and the second metal line 221. Similarly, the distance w2 between the second vias interconnect structure 321 on the second metal line 221 and the adjacent first metal line 211 is less than the distance d1 between the adjacent first metal line 211 and the second metal line 221.

[0056] Since the isolation layer 111 realizes physical isolation and electrical isolation between the first lead region 101V1 and the second metal wire 221 in the test region 101T, and also realizes physical isolation and electrical isolation between the second lead region 101V2 and the first metal wire 211 in the test region 101T, therefore, even when there are cases where both the spacing w1 and w2 are less than the spacing d1 between adjacent first and second metal wires, when testing the dielectric breakdown life between adjacent first metal wire 211 and second metal wire 221 in the TDDB test, the probability of test error caused by the existence of the spacing w1 and w2 being less than the spacing d1 between adjacent first and second metal wires is reduced.

[0057] It should be noted that on top of each first metal wire 211, in the first lead region 101V1 or the second lead region 101V2, the number of the first vias interconnecting structures 311 should not be too many or too few. If the number of the first vias interconnecting structures 311 is too many and the characteristic dimensions of the test structure are getting smaller and smaller, it is easy to increase the process difficulty of forming the first vias interconnecting structures 311 and cause unnecessary process waste at the same time; if the number of the first vias interconnecting structures 311 is too few, the probability of the first vias interconnecting structures 311 failing to connect is likely to increase. Therefore, in this embodiment, on top of each first metal wire 211, in the first lead region 101V1 or the second lead region 101V2, the number of the first vias interconnecting structures 311 is 2 to 5.

[0058] In this embodiment, on top of each first metal wire 211, in the first lead region 101V1 or the second lead region 101V2, the number of the first vias interconnecting structures 311 is 3. Under the condition of ensuring a simple forming process, as long as one of the first vias interconnecting structures 311 is successfully electrically connected, the first metal wire 211 is successfully electrically connected. Therefore, by using 3 first vias interconnecting structures 311, the successful loading of the test signal of the first metal wire 211 can be guaranteed to a large extent.

[0059] In this embodiment, the material of the first vias interconnecting structures 311 is a metal material. The metal material has good electrical conductivity, which is beneficial to improving the electrical connection performance between the first metal wire 211 and the external interconnecting structure, and correspondingly beneficial to improving the accuracy of the test results.

[0060] In this embodiment, the material of the first vias interconnecting structures 311 includes one or more of copper, aluminum, and copper alloy.

[0061] In this embodiment, on top of each second metal wire 221, in the first lead region 101V1 or the second lead region 101V2, the number of the second vias interconnecting structures 221 is 1 to 5.

[0062] In this embodiment, at the top of each of the second metal lines 221, in the first lead region 101V1 or the second lead region 101V2, the number of the second via interconnect structures 221 is two.

[0063] In this embodiment, the situation of the second via interconnect structure 221 is similar to that of the foregoing first via interconnect structure 211, and will not be elaborated here.

[0064] Figures 5 to 25 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a test structure of the present invention.

[0065] Reference Figure 5 , a substrate 130 is provided, and a first dielectric layer 100 is formed on the substrate 130. The first dielectric layer 100 includes a test region 100T, a first lead region 100V1 located on one side of the test region 100T, and a second lead region 100V2 located on the other side of the test region 100T along a first direction (such as Figure 5 the X direction in

[0066] In this embodiment, the test structure includes a TDDB test structure or a VBD test structure.

[0067] As an example, the test structure is a TDDB test structure.

[0068] In this embodiment, the substrate 130 includes a substrate structure layer (not shown in the figure), and the substrate structure layer includes a substrate (not shown in the figure). Taking the tested structure as a planar semiconductor structure as an example, the substrate is a planar substrate. Specifically, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. In other embodiments, when the test structure is a three-dimensional semiconductor structure, the substrate may also be a substrate with fins.

[0069] The substrate structure layer may further include other structures. For example, a gate structure, a doped region, a shallow trench isolation (STI) structure, and a dielectric layer, etc. Devices (such as MOS transistors or SRAM devices, etc.) are formed in the substrate structure layer. Specifically, the substrate structure layer further includes a second dielectric layer (not shown in the figure) formed on the substrate and a contact plug (CT) (not shown in the figure) formed in the second dielectric layer.

[0070] In this embodiment, a first dielectric layer 100 is formed on the substrate 130.

[0071] In this embodiment, the first dielectric layer 100 is an inter metal dielectric (IMD) layer, and the first dielectric layer 100 is used to achieve electrical isolation between metal interconnect structures in the back end of line (BEOL) process.

[0072] For this purpose, the material of the first dielectric layer 100 is a low-k dielectric material or an ultra-low-k dielectric material. In this embodiment, the material of the first dielectric layer 100 includes one or more of SiOC, SiOCH, SiC, SiCN, SiO 2 , SiN, and SiON. In this embodiment, the material of the first dielectric layer 100 is an ultra-low-k dielectric material, so as to reduce the parasitic capacitance between the back-end metal interconnect structures, and further reduce the back-end RC delay. Specifically, the ultra-low-k dielectric material can be SiOCH.

[0073] The test area 100T serves as a TDDB test area, and both the first lead area 100V1 and the second lead area 100V2 are used to load test signals.

[0074] Specifically, subsequently, metal lines are formed in the first dielectric layer 100. When performing the TDDB test, test signals are loaded on the metal lines in the first lead area 100V1 and the second lead area 100V2, and the dielectric breakdown lifetime between adjacent metal lines in the test area 100T is tested.

[0075] Reference Figure 6 , a core layer 400 covering the first dielectric layer 100 is formed.

[0076] The core layer 400 is used to provide a process platform for subsequently forming a first trench and a second trench, so as to transfer the pattern downward by using the patterned core layer 400. Among them, the first trench is used to define the pattern and position of the first interconnect opening formed subsequently, and the second trench is used to define the pattern and position of the second interconnect opening formed subsequently, which is correspondingly beneficial to improving the pattern accuracy of the first interconnect opening and the second interconnect opening.

[0077] In addition, sidewalls will be formed on the sidewalls of the core layer 400 subsequently, and the core layer 400 also provides support for forming the sidewalls.

[0078] Subsequently, the core layer 400 will also be removed. Therefore, the material of the core layer 400 is a material that is easy to be removed, thereby reducing the difficulty of removing the core layer 400 and minimizing the damage to other film layers located below the core layer 400. Therefore, the material of the core layer 400 includes one or more of amorphous silicon, polysilicon, single-crystalline silicon, silicon oxide, advanced patterning film (APF) material, spin on carbon (SOC), and silicon carbide. In this embodiment, the core layer 400 is amorphous silicon (a-Si).

[0079] With reference to Figures 7 to 16 , first trenches 410 extending along the first direction (such as the X direction shown in Figure 16 ) and arranged parallel to each other along the second direction (such as the Y direction shown in Figure 16 ) are formed in the core layer 400. In the first direction, the first trenches 410 located in the second lead region 100V2 and the test region 100T are isolated from each other. The second direction is perpendicular to the first direction. Second trenches 420 extending along the first direction and arranged parallel to each other along the second direction are formed in the core layer 400. In the first direction, the second trenches 420 located in the first lead region 100V1 and the test region 100T are isolated from each other. Among them, the second trenches 420 and the first trenches 410 are alternately arranged at intervals along the second direction.

[0080] When the test structure formed in the embodiment of the present invention is used to test the time-dependent dielectric breakdown lifetime or the breakdown voltage, the dielectric breakdown lifetime of the minimum pitch is used as the test lifetime. Since the first trenches 410 located in the second lead region 100V2 and the test region 100T are isolated from each other, and the second trenches 410 located in the first lead region 100V1 and the test region 100T are isolated from each other, after the first dielectric layer 100 is patterned, at the junction of the first lead region 100V1 and the test region 100T, the first dielectric layer 100 is retained, which can serve as a separation layer to completely isolate the second metal line. At the junction of the second lead region 100V2 and the test region 100T, the first dielectric layer 100 is also retained, which can also serve as a separation layer to completely isolate the first metal line. Then, during the test, the second metal line in the first lead region 100V1 and the second metal line in the test region 100T will not be connected, and the first metal line in the second lead region 100V2 and the first metal line in the test region 100T will not be connected. Thus, when testing the dielectric breakdown lifetime between adjacent first and second metal lines, the influence of the first vias interconnect structure on the first metal line and the second vias interconnect structure on the second metal line on the test results is reduced, and the probability of test errors caused by the existence of the first vias interconnect structure and the second vias interconnect structure is decreased, improving the accuracy of the test results.

[0081] The following will be described in detail in conjunction with the reference Figures 7 to 16 , the steps of forming the first trench 410 and the second trench 420.

[0082] In conjunction with the reference Figure 7 and Figure 8 , Figure 7 is a top view, Figure 8 is Figure 7 a cross-sectional view along the B’B’ direction. At the junction of the second lead region 100V2 and the test region 100T, a first partition structure 710 is formed in the core layer 400.

[0083] The first partition structure 710 is used as a mask for etching the first dielectric layer 100 when transferring the patterns of the second trench 420 and the first trench 410 to the first dielectric layer 100 subsequently.

[0084] In this embodiment, the material of the first partition structure 710 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. In this embodiment, the material of the first partition structure 710 is titanium oxide.

[0085] The steps of forming the first partition structure 710 include: forming a first mask layer 601 on the first dielectric layer 100, and a first mask opening 610 is formed in the first mask layer 601, and the first mask opening 610 exposes the core layer 400 at the junction of the second lead region 100V2 and the test region 100T.

[0086] The first mask layer 601 is used as a mask for forming the first partition structure 710.

[0087] The material of the first mask layer 601 is a material that is easy to remove, and the process of removing the first mask layer 601 causes less damage to other film layers. In this embodiment, the material of the first mask layer 601 is spin-on carbon (SOC) material. In other embodiments, the material of the first mask layer may also be ODL (organic dielectric layer) material or BARC (Bottom Anti-Reflective Coating) material.

[0088] In this embodiment, the core layer 400 exposed by the first mask opening 610 is removed, and a first groove (not shown) is formed in the core layer 400.

[0089] In this embodiment, a first partition structure 710 is formed in the first groove.

[0090] Compared with the solution of directly patterning the core layer 400, forming the first mask opening 610 first is beneficial to improving the pattern size accuracy and position accuracy of the first mask opening 610. Correspondingly, forming the first partition structure 710 in the first groove corresponding to the first mask opening 610 is beneficial to improving the pattern size accuracy and position accuracy of the first partition structure 710.

[0091] Specifically, the step of forming the first partition structure in the first groove includes: filling the first partition material into the first mask opening 610, and the first partition material also covers the top of the first mask layer 601; performing a re-etching process (for example, a dry etching process) on the first partition material, and retaining the first partition material located in the first mask opening 610 as the first partition structure 710.

[0092] Since the first partition structure 710 is formed in the first mask opening 610, by reasonably setting the thickness of the first partition material and the etching amount of the first partition material, it is easy to make the height of the first partition structure 710 meet the process requirements, and the process flexibility is relatively high.

[0093] In this embodiment, after forming the first partition structure 710, the first mask layer 601 is removed.

[0094] Removing the first mask layer 601 prepares for subsequent process steps.

[0095] Combined with reference to Figure 9 and Figure 10 , Figure 9 is a top view, Figure 10 is Figure 9 a cross-sectional view along the BB direction. At the junction of the first lead region 100V1 and the test region 100T, a second partition structure 720 is formed in the core layer 400, and the first partition structure 710 and the second partition structure 720 are alternately arranged along the second direction.

[0096] When the second trench 420 and the first trench 410 are subsequently transferred to the first dielectric layer 100, the second partition structure 720 is used together with the first partition structure 710 as a mask for etching the first dielectric layer 100.

[0097] In this embodiment, the material of the second partition structure 720 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. In this embodiment, the material of the second partition structure 720 is titanium oxide.

[0098] The steps of forming the second partition structure 720 include: forming a second mask layer 602 on the first dielectric layer 100, with a second mask opening 620 formed in the second mask layer 602, and the second mask opening 620 exposing the core layer 400 at the junction of the first lead region 100V1 and the test region 100T.

[0099] The second mask layer 602 is used as a mask for forming the second partition structure 720.

[0100] The material of the second mask layer 602 is a material that is easy to remove, and the process of removing the second mask layer 602 causes less damage to other film layers. In this embodiment, the material of the second mask layer 602 is spin-on carbon (SOC) material. In other embodiments, the material of the second mask layer can also be ODL (organic dielectric layer) material or BARC (Bottom Anti-Reflective Coating) material.

[0101] In this embodiment, the core layer 400 exposed by the second mask opening 620 is removed, and a second groove (not shown) is formed in the core layer 400.

[0102] In this embodiment, a second partition structure 720 is formed in the second groove.

[0103] Compared with the solution of directly patterning the core layer 400, by first forming the second mask opening 620, it is beneficial to improve the pattern size accuracy and position accuracy of the second mask opening 620. Correspondingly, forming the second partition structure 720 in the second groove corresponding to the second mask opening 620 is beneficial to improve the pattern size accuracy and position accuracy of the second partition structure 720.

[0104] Specifically, the steps of forming the second partition structure 720 in the second groove include: filling the second mask opening 620 with a second partition material, and the second partition material also covering the top of the second mask layer 602; performing a re-etching process (e.g., dry etching process) on the second partition material, and retaining the second partition material located in the second mask opening 620 as the second partition structure 720.

[0105] The second partition structure 720 is formed in the second mask opening 620. Therefore, by reasonably setting the thickness of the second partition material and the etching amount of the second partition material, it is easy to make the height of the second partition structure 720 meet the process requirements, and the process flexibility is relatively high.

[0106] In this embodiment, after forming the second partition structure 720, the second mask layer 602 is removed.

[0107] It should be noted that in this embodiment, the first partition structure 710 and the second partition structure 720 are formed in different steps, and the order of forming the first partition structure 710 and the second partition structure 720 is not limited.

[0108] With reference to Figure 11 and Figure 12 , Figure 11 is a top view, Figure 12 is Figure 11 a cross-sectional view based on the AA direction. After forming the first partition structure 710 and the second partition structure 720, a first trench 410 extending along the first direction and arranged in parallel along the second direction is formed in the core layer 400. The first partition structure 710 divides the first trench 410 along the first direction, and at the second direction, the first trench 410 exposes the end of the second isolation structure 720.

[0109] The first trench 410 is used to define the pattern and position of the subsequently formed first interconnect opening, which is beneficial to improving the pattern accuracy of the first interconnect opening.

[0110] With reference to Figures 13 to 15 , Figure 13 is a cross-sectional view based on Figure 12 , Figure 14 is a top view, Figure 15 is Figure 14 a cross-sectional view based on the AA direction. A mask sidewall 510 is formed on the sidewall of the first trench 410.

[0111] The mask sidewall 510 is used to subsequently isolate the second trench from the first trench 410, prevent the second trench from penetrating the first trench 410, and ensure that the distance between adjacent second trenches and the first trench 410 meets the designed minimum space. Moreover, when transferring the patterns of the second trench and the first trench 410 to the first dielectric layer 100 subsequently, the mask sidewall 510 serves as a mask for etching the first dielectric layer 100. In addition, the mask sidewall 510 is used to adjust the distance between the second trench and the first trench 410 in the second direction.

[0112] The mask sidewall 510 is made of a material that has an etching selectivity with respect to the core layer 400. The material of the mask sidewall 510 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. In this embodiment, the material of the mask sidewall 510 is titanium oxide.

[0113] It should be noted that only a partial length along the first direction and a partial number along the second direction of the mask sidewall 510 and the first trench 410 are shown in this embodiment. That is to say, in actual situations, along the second direction, there will also be included, for example, Figure 10 the core layer 400 and the mask sidewall 510 arranged in an extended manner in the Y direction in

[0114] Reference Figure 13 , the steps of forming the mask sidewall 510 include: forming a mask sidewall material layer 500 that conformally covers the top of the core layer 400, as well as the bottom and sidewalls of the first trench 410.

[0115] The mask sidewall material layer 500 is used to form the mask sidewall 510.

[0116] In this embodiment, the mask sidewall material layer 500 is formed by an atomic layer deposition process.

[0117] The mask sidewall material layer 500 formed by the atomic layer deposition process has good thickness uniformity and good step coverage ability, so that the mask sidewall material layer 500 can conformally cover the top of the core layer 400, as well as the bottom and sidewalls of the first trench 410 well.

[0118] In this embodiment, the material of the mask sidewall material layer 500 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide, and is used to directly form the mask sidewall 510.

[0119] Combined with reference to Figure 14 and Figure 15 , the mask sidewall material layer 500 located on the top of the core layer 400 and the bottom of the first trench 410 is removed, and the mask sidewall material layer 500 located on the sidewalls of the first trench 410 is retained as the mask sidewall 510.

[0120] Removing the mask sidewall material layer 500 located on the top of the core layer 400 and the bottom of the first trench 410 can better expose the top surface of the core layer 400, thereby reducing the process difficulty of removing the core layer 400 subsequently and preparing for transferring the pattern with the mask sidewall 510 as an etching mask in the future.

[0121] In this embodiment, a dry etching process is used to remove the mask sidewall material layer 500 located on the top of the core layer 400 and the bottom of the first trench 410.

[0122] The dry etching process has the characteristic of anisotropic etching. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the mask sidewall 510 and the first dielectric layer 100. At the same time, the dry etching has more etching directionality, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the mask sidewall 510.

[0123] Combined with reference Figure 16 and Figure 18 , Figure 16 is a top view, Figure 17 is Figure 16 a cross-sectional view based on the AA direction, Figure 18 a is Figure 16 a cross-sectional view based on the BB direction, Figure 18 b is Figure 16 a cross-sectional view based on the B’B’ direction. After forming the mask sidewall 510, the core layer 400 is removed to form the second trench 420. The second partition structure 720 divides the second trench 420 along the first direction, and the adjacent second trench 420 and the first trench 410 are isolated by the mask sidewall 510.

[0124] The second trench 420 is used to define the shape, size, and position of the second interconnect opening formed in the first dielectric layer 100 subsequently. In this embodiment, by first forming the first trench 410 in the core layer 400 and then forming the second trench 420 using the mask sidewall 510, the pattern accuracy of the first trench 410 and the second trench 420 is improved, thereby improving the pattern accuracy of the first interconnect opening and the second interconnect opening formed subsequently, and correspondingly improving the pattern transfer accuracy.

[0125] In addition, in this embodiment, the first trench 410 and the second trench 420 are formed separately, which is beneficial to improving the process window for forming the first trench 410 and the second trench 420 (for example: improving the optical proximity effect or alleviating the resolution limitation of the lithography process), ensuring the pattern accuracy of the first trench 410 and the second trench 420, and being beneficial to reducing the interval between the adjacent first trench 410 and the second trench 420.

[0126] In this embodiment, the core layer 400 is removed by using a maskless etching process. The etching selectivity between the core layer 400 and the mask sidewall 510, as well as the first dielectric layer 100, is relatively high. Therefore, during the process of removing the core layer 400, the damage to other film layers is relatively small. Correspondingly, the core layer 400 can be removed by using a maskless etching process, thereby simplifying the process steps and reducing the cost. Moreover, by selecting the maskless etching process, the process window for forming the second trench 420 is also significantly increased.

[0127] In this embodiment, the wet etching process is used to remove the core layer 400. The wet etching process removes the core layer 400 through a chemical reaction, which is beneficial to reducing the damage to the mask sidewall 510 and the first dielectric layer 100, and is also beneficial to completely removing the core layer 400. In this embodiment, the material of the core layer 400 is amorphous silicon, and the etching solution used in the wet etching process is a mixed solution of Cl 2 and HBr or a TMAH solution.

[0128] In this embodiment, the first trench 410 and the second trench 420 are formed in different steps, and the order of formation of the first trench 410 and the second trench 420 is not limited.

[0129] In this embodiment, the first partition structure 710 and the second partition structure 720 are formed first, and then the first trench 410 and the second trench 420 are formed. Forming the first partition structure 710 and the second partition structure 720 in the core layer 400 with higher flatness first is beneficial to making the quality of the formed first partition structure 710 and second partition structure 720 better and the position more accurate, so as to be beneficial to more precisely patterning the first dielectric layer 100 as a mask subsequently.

[0130] In other embodiments, the first partition structure and the second partition structure can also be formed in the first trench and the second trench respectively after forming the first trench and the second trench; or, after forming the first trench, the first partition structure is formed in the first trench, after forming the first partition structure, the second trench is formed, and after forming the second trench, the second partition structure is formed in the second trench; or, after forming the first partition structure, the first trench is formed, after forming the first trench, the second partition structure is formed, and after forming the second partition structure, the second trench is formed.

[0131] It should be noted that in other embodiments, when forming the first partition trench and the second trench, the specific steps of forming the first trench and the second trench are similar to the way of forming the first trench and the second trench in this embodiment. Correspondingly, the descriptions of the first mask layer and the second mask layer can be referred to in combination with the relevant descriptions of the mask layer in this embodiment, which will not be elaborated here.

[0132] Combined reference Figure 19 and Figure 20 , Figure 19 is a top view, Figure 20 a is Figure 19 a cross-sectional view based on the BB direction, Figure 20 b is Figure 19In a cross-sectional view based on the B’B’ direction, etch the first dielectric layer 100 at the bottoms of the first trench 410 and the second trench 420 to form interconnect openings, where the interconnect openings include first interconnect openings 230 and second interconnect openings 240 that are alternately spaced along the second direction. The first interconnect openings 230 correspond to the first trench 410, and the second interconnect openings 240 correspond to the second trench 420.

[0133] In this embodiment, in the step of etching the first dielectric layer 100 at the bottoms of the first trench 410 and the second trench 420, use the mask sidewall 510, the first partition structure 710, and the second partition structure 720 as masks to etch the first dielectric layer 100.

[0134] In this embodiment, the interconnect opening corresponding to the first trench 410 is the first interconnect opening 230, the interconnect opening corresponding to the second trench 420 is the second interconnect opening 240, the portion of the first dielectric layer 100 that the first partition structure 710 correspondingly retains is the first partition layer 110, and the portion of the first dielectric layer 100 that the second partition structure 720 correspondingly retains is the second partition layer 120.

[0135] That is to say, in this embodiment, the first partition layer 110 and the second partition layer 120 and the first dielectric layer 100 are of an integral structure, and there is no need to perform the steps of forming the first partition layer 110 and the second partition layer 120, which simplifies the process flow and improves the process efficiency.

[0136] In this embodiment, in the first direction, the first interconnect openings 230 of the second lead region 100V2 and the test region 100T are isolated by the first partition layer 110, and the second interconnect openings 240 of the first lead region 100V1 and the test region 100T are isolated by the second partition layer 120.

[0137] Such as Figure 19 shown, Figure 19 the dashed boxes in represent the outlines of the first partition layer 110 and the second partition layer 120.

[0138] The first interconnect openings 230 and the second interconnect openings 240 are used to provide spatial positions for the formation of metal interconnect lines.

[0139] In this embodiment, the morphological quality, dimensional accuracy, and positional accuracy of the first trench 310 and the second trench 320 are relatively high, thereby improving the accuracy of pattern transfer, correspondingly improving the pattern accuracy of the interconnect openings, enabling the morphology and layout of the subsequent formed metal lines to meet the design requirements, and correspondingly improving the performance of the metal lines.

[0140] In this embodiment, using the mask sidewall 510, the first partition structure 710, and the second partition structure 720 as masks, the first dielectric layer 100 is etched to form an interconnect opening. Compared with the solution of directly forming an interconnect opening in the first dielectric layer 100, this solution is easy to form a mask sidewall 510 with a smaller size in the second direction, and the dimensions and positions of the mask sidewall 510, the first partition structure 710, and the second partition structure 720 have higher precision, which correspondingly facilitates the precise control of the pattern precision of the interconnect opening and correspondingly improves the pattern transfer precision.

[0141] In this embodiment, the dry etching process is used to etch the first dielectric layer 100 at the bottoms of the first trench 410 and the second trench 420 to form an interconnect opening.

[0142] The dry etching process has the characteristics of anisotropic etching. Therefore, the dry etching has more etching directionality, which is beneficial to improving the sidewall topography quality and dimensional accuracy of the interconnect opening.

[0143] With reference to Figure 21 and Figure 22 , where Figure 21 is a top view, Figure 22 a is Figure 21 a cross-sectional view along the BB direction, Figure 22 b is Figure 21 a cross-sectional view along the B’B’ direction. Metal lines are formed in the interconnect opening. Among them, the first metal line 210 is located in the first interconnect opening 230, and the second metal line 220 is located in the second interconnect opening 240.

[0144] In this embodiment, the material of the first metal line 210 includes one or more of copper, aluminum, and copper alloy, which is used to achieve better electrical conductivity. The material of the second metal line 220 includes one or more of copper, aluminum, and copper alloy, which is used to achieve better electrical conductivity.

[0145] In this embodiment, the first metal line 210 and the second metal interconnect line 220 are metal interconnect lines of the same layer. Therefore, the materials of the first metal line 210 and the second metal interconnect line 220 are the same.

[0146] In this embodiment, the remaining first dielectric layer 100 between the adjacent first metal line 210 and the second metal line 220 is transferred through the mask sidewall 510, so the sizes of the intervals d1 between the adjacent first metal line 210 and the second metal line 220 are equal.

[0147] Since the dielectric breakdown lifetime of the minimum spacing is used as the test lifetime when the test structure is used to test the time-related dielectric breakdown lifetime or the breakdown voltage, in this embodiment, the intervals d1 between adjacent first metal lines 210 and second metal lines 220 are equal. Therefore, during the test, the dielectric breakdown lifetime between adjacent first metal lines 210 and second metal lines 220 can be detected more accurately, and the situation of large errors in the detection results caused by different spacing sizes of the intervals between adjacent first metal lines 210 and second metal lines 220 can be avoided to a large extent.

[0148] With reference to Figures 23 to 25 , where Figure 23 is a top view, Figure 24 a is Figure 23 a cross-sectional view along the BB direction, Figure 24 b is Figure 23 a cross-sectional view along the B’B’ direction, Figure 25 is Figure 23 a cross-sectional view along the CC direction. After forming the metal lines, a second dielectric layer 300 is formed on the first dielectric layer 100.

[0149] The second dielectric layer 300 is used to achieve electrical isolation between metal interconnect structures (e.g., a first via interconnect structure 310 and a second via interconnect structure 320) in the subsequent process.

[0150] For the description of the material of the second dielectric layer 300, reference can be made to the relevant description of the first dielectric layer 100 above, which will not be elaborated here.

[0151] Continuing with reference to Figures 23 to 25 , a first via interconnect structure 310 is formed in the second dielectric layer 300 of the first lead region 100V1. The first via interconnect structure 310 is located on top of the first metal line 210 and is in contact with the first metal line 210. The first via interconnect structure 310 is used as the test signal loading end of the first metal line 210. A second via interconnect structure 320 is formed in the second dielectric layer 300 of the second lead region 100V2. The second via interconnect structure 320 is located on top of the second metal line 220 and is in contact with the second metal line 220. The second via interconnect structure 320 is used as the test signal loading end of the second metal line 220.

[0152] In this embodiment, the first via interconnect structure 310 and the second via interconnect structure 320 are formed in the same step, which simplifies the process steps and improves the process efficiency.

[0153] Generally, when forming the first vias interconnect structure 310 and the second vias interconnect structure 320, the sizes of the first vias interconnect structure 310 and the second vias interconnect structure 320 will expand along the second direction.

[0154] Therefore, in this embodiment, along the second direction, the width dimension of the first vias interconnect structure 310 is greater than the width dimension of the first metal line 210. Similarly, along the second direction, the width dimension of the second vias interconnect structure 320 is greater than the width dimension of the second metal line 220.

[0155] That is to say, the distance w1 between the first vias interconnect structure 310 on top of the first metal line 210 and the adjacent second metal line 220 is less than the distance d1 between the adjacent first metal line 210 and the second metal line 220. Similarly, the distance w2 between the second vias interconnect structure 321 on the second metal line 220 and the adjacent first metal line 210 is less than the distance d1 between the adjacent first metal line 210 and the second metal line 220.

[0156] Since the isolation layer 110 realizes physical isolation and electrical isolation between the second metal line 220 in the first lead region 100V1 and the test region 100T, and also realizes physical isolation and electrical isolation between the first metal line 210 in the second lead region 100V2 and the test region 100T, therefore, even when there are situations where both the distances w1 and w2 are less than the distance d1 between the adjacent first metal line and the second metal line, when testing the dielectric breakdown life between the adjacent first metal line 210 and the second metal line 220, the probability of test error caused by the existence of the distances w1 and w2 being less than the distance d1 between the adjacent first metal line and the second metal line is reduced.

[0157] In this embodiment, on top of each first metal line 210, in the first lead region 100V1 or the second lead region 100V2, the number of the first vias interconnect structures 310 is from 1 to 5. The analysis of the number of the first vias interconnect structures 310 can refer to the corresponding description in the foregoing embodiments and will not be elaborated here.

[0158] In this embodiment, on top of each first metal line 210, in the first lead region 100V1 or the second lead region 100V2, the number of the first vias interconnect structures 310 is 3. Under the condition of ensuring a simple forming process, as long as one of the first vias interconnect structures 310 is successfully electrically connected, then the first metal line 210 is successfully electrically connected. Therefore, by using 3 first vias interconnect structures 310, the successful loading of the test signal of the first metal line 210 can be guaranteed to a large extent.

[0159] In this embodiment, the material of the first via interconnect structure 310 is a metal material. The metal material has good electrical conductivity, which is beneficial to improving the electrical connection performance between the first metal wire 210 and the external interconnect structure, and correspondingly beneficial to improving the accuracy of the test results.

[0160] In this embodiment, the material of the first via interconnect structure 310 includes one or more of copper, aluminum, and copper alloy.

[0161] In this embodiment, at the top of each of the second metal wires 220, in the first lead region 100V1 or the second lead region 100V2, the number of the second via interconnect structures 220 is 2 to 5.

[0162] In this embodiment, at the top of each of the second metal wires 220, in the first lead region 100V1 or the second lead region 100V2, the number of the second via interconnect structures 220 is 3.

[0163] In this embodiment, the situation of the second via interconnect structure 220 is similar to that of the foregoing first via interconnect structure 210 and will not be elaborated here.

[0164] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A test structure, characterized in that: include: A plurality of metal wires, the metal wires extending along a first direction and arranged in parallel along a second direction, the second direction being perpendicular to the first direction, the metal wires including a test area, a first lead area located on one side of the test area, and a second lead area located on the other side of the test area along the first direction, the first lead area and the second lead area both being used to load a test signal, and the metal wires including first metal wires and second metal wires arranged alternately along the second direction; a dielectric isolation layer, which passes through the first metal line at the junction of the second lead area and the test area, and the second metal line at the junction of the first lead area and the test area, the dielectric isolation layer at the junction of the second lead area and the test area is used to divide the first metal line in the first direction, and the dielectric isolation layer at the junction of the first lead area and the test area is used to divide the second metal line in the first direction; A first through-hole interconnection structure is located in the first lead area and on the top of the first metal line, and the first through-hole interconnection structure is used as a test signal loading end of the first metal line; The second through-hole interconnection structure is located in the second lead area and on the top of the second metal line. The second through-hole interconnection structure is used as a test signal loading end of the second metal line.

2. The test structure according to claim 1, characterized in that The test structure also includes a dielectric layer; The metal lines are located in the dielectric layer, and along the second direction, adjacent first metal lines and second metal lines are spaced apart by the dielectric layer.

3. The test structure according to claim 2, characterized in that: The dielectric isolation layer and the dielectric layer are an integral structure.

4. The test structure according to claim 1, characterized in that: The dielectric isolation layer located in the first metal line also extends to both sides along the second direction to the sidewalls of the second metal line; The dielectric isolation layer located in the second metal line further extends to both sides along the second direction to the sidewalls of the first metal line.

5. The test structure according to claim 1, characterized in that: At the top of each of the first metal lines, in the first lead area or the second lead area, the number of the first through-hole interconnect structures is 2 to 5; At the top of each of the second metal lines, in the first lead area or the second lead area, the number of the second through-hole interconnection structures is 2 to 5.

6. The test structure according to claim 1, characterized in that: Along the second direction, the width dimension of the first through-hole interconnect structure is greater than the width dimension of the first metal line; Along the second direction, a width dimension of the second through-hole interconnect structure is greater than a width dimension of the second metal line.

7. The test structure according to claim 1, characterized in that: Along the first direction, the line width of the dielectric isolation layer is 20 nm to 35 nm.

8. The test structure according to claim 1, characterized in that: The intervals between adjacent first metal lines and second metal lines are equal.

9. The test structure according to claim 1, characterized in that: The material of the dielectric isolation layer includes one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN and SiON.

10. The test structure according to claim 3, characterized in that: The material of the dielectric layer includes one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN and SiON.

11. The test structure according to claim 1, characterized in that: The material of the first metal wire includes one or more of copper, aluminum and a copper alloy, and the material of the second metal wire includes one or more of copper, aluminum and a copper alloy.

12. The test structure according to claim 1, characterized in that: The test structure includes a TDDB test structure or a VBD test structure.

13. A method for forming a test structure, characterized in that: include: Providing a substrate, on which a first dielectric layer is formed, wherein the first dielectric layer includes a test area, a first lead area located on one side of the test area, and a second lead area located on the other side of the test area along a first direction, wherein the first lead area and the second lead area are both used to load a test signal; forming a core layer covering the first dielectric layer; Forming first grooves extending along the first direction and arranged in parallel along a second direction in the core layer, wherein the first grooves located in the second lead area and the test area are isolated from each other in the first direction, and the second direction is perpendicular to the first direction; forming second grooves extending along the first direction and arranged in parallel along the second direction in the core layer, wherein the second grooves located in the first lead area and the test area are isolated from each other in the first direction, wherein the second grooves and the first grooves are arranged alternately and spaced apart along the second direction; Etching the first dielectric layer at the bottom of the first trench and the second trench to form interconnect openings, wherein the interconnect openings include first interconnect openings and second interconnect openings alternately arranged along the second direction, the first interconnect openings corresponding to the first trench, and the second interconnect openings corresponding to the second trench; forming metal lines in the interconnect openings, wherein the first metal line is located in the first interconnect opening, and the second metal line is located in the second interconnect opening; After forming the metal line, forming a second dielectric layer on the first dielectric layer; forming a first through-hole interconnect structure in the second dielectric layer of the first lead area, the first through-hole interconnect structure being located on top of the first metal line and in contact with the first metal line, the first through-hole interconnect structure being used as a test signal loading terminal of the first metal line; A second through-hole interconnect structure is formed in the second dielectric layer of the second lead area. The second through-hole interconnect structure is located on top of the second metal line and contacts the second metal line. The second through-hole interconnect structure is used as a test signal loading end of the second metal line.

14. The method for forming a test structure according to claim 13, wherein: The steps of forming the first groove and the second groove include: forming a first partition structure in the core layer at the junction of the second lead area and the test area; At the junction of the first lead area and the test area, a second partition structure is formed in the core layer, and the first partition structure and the second partition structure are alternately arranged along the second direction; After forming the first partition structure and the second partition structure, forming first grooves extending along the first direction and arranged in parallel along the second direction in the core layer, the first partition structure dividing the first grooves along the first direction, and in the second direction, the first grooves expose the ends of the second partition structure; forming a mask sidewall on the sidewall of the first trench; After forming the mask sidewalls, removing the core layer to form second trenches, wherein the second partition structure divides the second trenches along the first direction, and adjacent second trenches and first trenches are isolated from each other by the mask sidewalls; In the step of etching the first dielectric layer at the bottom of the first trench and the second trench, the first dielectric layer is etched using the mask sidewalls, the first partition structure and the second partition structure as masks.

15. The method for forming a test structure according to claim 14, wherein: In different steps, the first partition structure and the second partition structure are formed respectively, and the step of forming the first partition structure includes: forming a first mask layer on the first dielectric layer, wherein a first mask opening is formed in the first mask layer, and the first mask opening exposes the core layer at the junction of the second lead area and the test area; removing the core layer exposed by the first mask opening, and forming a first groove in the core layer; forming a first partition structure in the first groove; After forming the first partition structure, the first mask layer is removed.

16. The method for forming a test structure according to claim 14, wherein: In different steps, the first partition structure and the second partition structure are formed respectively, and the step of forming the second partition structure includes: forming a second mask layer on the first dielectric layer, a second mask opening is formed in the second mask layer, and the second mask opening exposes the core layer at the junction of the first lead area and the test area; removing the core layer exposed by the second mask opening, and forming a second groove in the core layer; forming a second partition structure in the second groove; After the second partition structure is formed, the second mask layer is removed.

17. The method for forming a test structure according to claim 13, wherein: In the same step, the first through-via interconnection structure and the second through-via interconnection structure are formed.

18. The method for forming a test structure according to claim 13, wherein: The first dielectric layer at the bottom of the first trench and the second trench is etched by a dry etching process to form an interconnect opening. 19 . The method for forming a test structure according to claim 13 , wherein the test structure comprises a TDDB test structure or a VBD test structure.

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