MOSFET device and preparation method

Abstract

The present invention provides a MOSFET device and a preparation method thereof. By introducing a double-layer epitaxial structure with different doping concentrations and a deeper trench gate structure with gate dielectric layers of different thicknesses, the MOSFET device can achieve a higher withstand voltage under a certain trench depth, and significantly reduce the on-resistance and reverse recovery time. In the trench gate structure, a composite trench gate structure with gate dielectric layers of different thicknesses and gate conductive layers of the same plane is formed, and the preparation process is simple, easy to manufacture, and has low manufacturing cost. By introducing defect centers in the epitaxial structure, the reverse recovery time of the MOSFET device can be further reduced, thereby significantly improving the rectification efficiency of the power supply system. At the same time, the double-layer epitaxial structure provides soft reverse recovery characteristics, significantly reducing the voltage and current spikes of the system, and improving the system reliability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a MOSFET device and a preparation method thereof. Background Art

[0002] The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a field-effect transistor that can be widely used in analog and digital circuits. Due to its simple drive circuit, low drive power, fast switching speed, and high operating frequency, it is an important component in medium and low voltage synchronous rectification power supplies.

[0003] To increase component density, existing MOSFET devices often utilize a vertical structure. For example, trench MOSFETs typically feature a source located on the surface, connected to the silicon via a via. The gate is formed in the trench and connected to the silicon via gate polysilicon. The drain is located on the backside of the substrate. To achieve higher withstand voltages, particularly for medium-voltage applications, these trench MOSFETs typically utilize thick epitaxial layers. This results in high epitaxial resistance, high on-resistance, and long reverse recovery time, leading to low rectification efficiency.

[0004] However, modern high-power power systems are experiencing increasingly higher switching frequencies, higher output voltages, and larger currents. This requires secondary synchronous rectification MOSFETs to have high withstand voltages, low on-resistance, and fast reverse recovery speeds. Consequently, existing MOSFETs are no longer sufficient.

[0005] Therefore, it is necessary to provide a MOSFET device and a preparation method thereof. Summary of the Invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a MOSFET device and a preparation method thereof, so as to solve the problem that the MOSFET device in the prior art is difficult to meet the requirements of high-efficiency rectification.

[0007] To achieve the above-mentioned and other related objectives, the present invention provides a MOSFET device, comprising:

[0008] An epitaxial structure having a first conductivity type, the epitaxial structure comprising a first epitaxial layer and a second epitaxial layer stacked together, wherein the doping concentration of the first epitaxial layer is greater than the doping concentration of the second epitaxial layer;

[0009] a trench gate structure disposed in the epitaxial structure, comprising a first trench gate structure and a second trench gate structure, wherein the first trench gate structure comprises a first gate dielectric layer and a first gate conductive layer, the second trench gate structure comprises a second gate dielectric layer and a second gate conductive layer, and the second trench gate structure is located on the first gate dielectric layer and is located at a periphery of a portion of the first gate conductive layer;

[0010] a body region having a second conductivity type, the body region being disposed in the second epitaxial layer between the trench gate structures, the second conductivity type being opposite to the first conductivity type;

[0011] A source region of a first conductivity type is provided on the body region.

[0012] Optionally, the epitaxial structure is an epitaxial structure having a defect center, and a substance forming the defect center includes one or a combination of lithium, iron and copper.

[0013] Optionally, the thickness of the epitaxial structure ranges from 8 μm to 20 μm; the depth of the trench gate structure is from 5 μm to 10 μm, and the trench gate structure penetrates the second epitaxial layer; and the thickness of the first gate dielectric layer is from 500 μm to 1000 μm.

[0014] Optionally, a surface of the second gate conductive layer and a surface of the first gate conductive layer are located in the same plane.

[0015] Optionally, the first gate dielectric layer and the second gate dielectric layer are both silicon oxide; and the first gate conductive layer and the second gate conductive layer are both polysilicon.

[0016] The present invention also provides a method for preparing a MOSFET device, characterized by comprising the following steps:

[0017] forming an epitaxial structure having a first conductivity type, the epitaxial structure comprising a first epitaxial layer and a second epitaxial layer stacked together, wherein the doping concentration of the first epitaxial layer is greater than the doping concentration of the second epitaxial layer;

[0018] forming a trench gate structure in the epitaxial structure, the trench gate structure comprising a first trench gate structure and a second trench gate structure, wherein the first trench gate structure comprises a first gate dielectric layer and a first gate conductive layer, the second trench gate structure comprises a second gate dielectric layer and a second gate conductive layer, and the second trench gate structure is located on the first gate dielectric layer and is located around a portion of the first gate conductive layer;

[0019] forming a body region of a second conductivity type in the second epitaxial layer between the trench gate structures, the second conductivity type being opposite to the first conductivity type;

[0020] A source region having a first conductivity type is formed in the body region.

[0021] Optionally, the method further includes a step of forming a defect center in the epitaxial structure, wherein the material forming the defect center includes one or a combination of lithium, iron and copper.

[0022] Optionally, the thickness of the formed epitaxial structure ranges from 8μm to 20μm; the depth of the formed trench gate structure is 5μm to 10μm, and the trench gate structure penetrates the second epitaxial layer; the thickness of the first gate dielectric layer is 500μm to 1000μm.

[0023] Optionally, the step of forming the trench gate structure includes:

[0024] Patterning the epitaxial structure to form a trench, wherein the trench exposes the first epitaxial layer;

[0025] forming a first gate dielectric layer in the trench and a first gate conductive layer filling the trench;

[0026] removing a portion of the first gate dielectric layer to form a groove;

[0027] A second gate dielectric layer and a second gate conductive layer filling the groove are formed in the groove, and a surface of the second gate conductive layer and a surface of the first gate conductive layer are located in the same plane.

[0028] Optionally, the step of forming the trench gate structure includes:

[0029] Patterning the epitaxial structure to form a trench, wherein the trench exposes the first epitaxial layer;

[0030] forming a first gate dielectric layer in the trench and a first gate conductive layer filling the trench;

[0031] patterning the first gate dielectric layer to form a groove;

[0032] A second gate conductive layer is formed to fill the groove, and a surface of the second gate conductive layer and a surface of the first gate conductive layer are located in the same plane.

[0033] As described above, the MOSFET device and preparation method of the present invention introduce a double-layer epitaxial structure with different doping concentrations and a deeper trench gate structure with gate dielectric layers of different thicknesses, which can enable the MOSFET device to achieve a higher withstand voltage under a certain trench depth and significantly reduce the on-resistance and reverse recovery time; in the trench gate structure, the composite trench gate structure with gate dielectric layers of different thicknesses and gate conductive layers of the same plane is formed, and the preparation process is simple, easy to manufacture, and has low manufacturing cost; introducing defect centers in the epitaxial structure can further reduce the reverse recovery time of the MOSFET device, thereby greatly improving the rectification efficiency of the power supply system. At the same time, the double-layer epitaxial structure provides soft reverse recovery characteristics, significantly reducing the voltage and current spikes of the system and improving the system reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Shown is a schematic diagram of the process flow for preparing a MOSFET device in an embodiment of the present invention.

[0035] Figure 2 Shown is a schematic structural diagram of a patterned epitaxial structure after trenches are formed in an embodiment of the present invention.

[0036] Figure 3 It is a schematic structural diagram showing the structure after forming a first gate dielectric layer and a first gate conductive layer in the trench according to an embodiment of the present invention.

[0037] Figure 4 It is a schematic structural diagram showing the formation of a second gate dielectric layer and a second gate conductive layer in an embodiment of the present invention.

[0038] Figure 5 It is a schematic diagram of the structure after the body region and the source region are formed in an embodiment of the present invention.

[0039] Figure 6 Shown is a schematic structural diagram after a defect center is formed in an embodiment of the present invention.

[0040] Figure 7 It is a schematic diagram of the structure after forming the metal conductive layer in an embodiment of the present invention.

[0041] Component number description

[0042] 100 semiconductor substrate

[0043] 200 epitaxial structure

[0044] 210 First epitaxial layer

[0045] 220 Second epitaxial layer

[0046] 300 grooves

[0047] 400 trench gate structure

[0048] 410 first trench gate structure

[0049] 411 first gate dielectric layer

[0050] 412 first gate conductive layer

[0051] 420 second trench gate structure

[0052] 421 second gate dielectric layer

[0053] 422 second gate conductive layer

[0054] 500 Body Area

[0055] 600 Source Area

[0056] 700 Defect Center

[0057] 800 dielectric layer

[0058] 900 Metal conductive layer DETAILED DESCRIPTION

[0059] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0060] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0061] For ease of description, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may be present. As used herein, "between" is inclusive of both endpoints.

[0062] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0063] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0064] like Figure 7 The cross-sectional view of the MOSFET device of this embodiment is shown, which includes an epitaxial structure 200 having a first conductivity type, a trench gate structure 400 , a body region 500 having a second conductivity type, and a source region 600 having a first conductivity type.

[0065] In this embodiment, the first conductivity type is N-type, and the second conductivity type is opposite to the first conductivity type, so that the corresponding second conductivity type is P-type, but it is not limited to this. In another embodiment, the first conductivity type may also be N-type, and the corresponding second conductivity type may also be P-type.

[0066] Specifically, the epitaxial structure 200 includes a first epitaxial layer 210 and a second epitaxial layer 220 stacked together, and the doping concentration of the first epitaxial layer 210 is greater than the doping concentration of the second epitaxial layer 220. The trench gate structure 400 is disposed in the epitaxial structure 200 and includes a first trench gate structure 410 and a second trench gate structure 420. The first trench gate structure 410 includes a first gate dielectric layer 411 and a first gate conductive layer 412, and the second trench gate structure 420 includes a second gate dielectric layer 421 and a second gate conductive layer 422. The second trench gate structure 420 is located on the first gate dielectric layer 411 and is located around a portion of the first gate conductive layer 411. The body region 500 is disposed in the second epitaxial layer 220 between the trench gate structures 400, and the source region 600 is disposed on the body region 500.

[0067] This embodiment introduces a double-layer epitaxial structure with different doping concentrations and a trench gate structure with gate dielectric layers of different thicknesses, which can enable the MOSFET device to achieve a higher withstand voltage under a certain trench depth and significantly reduce the on-resistance and reverse recovery time; in the trench gate structure, the composite trench gate structure with gate dielectric layers of different thicknesses and gate conductive layers of the same plane is formed, and the preparation process is simple, easy to manufacture, and has low manufacturing cost; at the same time, the double-layer epitaxial structure provides soft reverse recovery characteristics, significantly reducing the voltage and current spikes of the system and improving the system reliability.

[0068] like Figure 7 The MOSFET device further comprises a semiconductor substrate 100, a dielectric layer 800, and a metal conductive layer 900. Furthermore, in this embodiment, the epitaxial structure 200 further comprises a defect center 700, which reduces the reverse recovery time of the MOSFET device through the defect center 700, thereby significantly improving the rectification efficiency of the power supply system.

[0069] The following describes the manufacturing process of the MOSFET device with reference to the accompanying drawings.

[0070] See Figure 1 This embodiment provides a method for preparing a MOSFET device, which may specifically include:

[0071] First, see Figure 2 , forming the epitaxial structure 200 with a first conductivity type, the epitaxial structure 200 includes a first epitaxial layer 210 and a second epitaxial layer 220 stacked together, and the doping concentration of the first epitaxial layer 210 is greater than the doping concentration of the second epitaxial layer 220.

[0072] Specifically, a semiconductor substrate 100 may be provided. The semiconductor substrate 100 may be a silicon substrate of the first conductivity type. Alternatively, the semiconductor substrate 100 may be made of a doped semiconductor material such as silicon germanium (SiGe), gallium nitride (GaN), or silicon carbide (SiC). Because the semiconductor substrate 100 is doped with the first conductivity type, it can serve as the drain region of the MOSFET device. Next, an epitaxial structure 200 having different doping concentrations may be formed on the semiconductor substrate 100 through ion implantation. The concentration of first conductivity type carriers in the epitaxial structure 200 is lower than that in the semiconductor substrate 100, and it can serve as the drift region of the MOSFET device. Furthermore, the doping concentration of the first epitaxial layer 210 adjacent to the semiconductor substrate 100 in the epitaxial structure 200 is greater than the doping concentration of the second epitaxial layer 220. This ensures that, given a certain trench depth, the MOSFET device can achieve a high withstand voltage. Furthermore, the double-layer epitaxial structure provides soft reverse recovery characteristics, significantly reducing voltage and current spikes in the system and improving system reliability.

[0073] Then, if Figures 2 to 4 The trench gate structure 400 is formed in the epitaxial structure 200. The trench gate structure 400 includes a first trench gate structure 410 and a second trench gate structure 420. The first trench gate structure 410 includes a first gate dielectric layer 411 and a first gate conductive layer 412, and the second trench gate structure 420 includes a second gate dielectric layer 421 and a second gate conductive layer 422. The second trench gate structure 420 is located on the first gate dielectric layer 411 and is located around a portion of the first gate conductive layer 412. Thus, in the trench gate structure 400, the thickness of the first gate dielectric layer 411 located at the top is greater than the thickness of the second gate dielectric layer 421 located at the bottom, and the surface of the second gate conductive layer 422 is coplanar with the surface of the first gate conductive layer 412, thereby forming a composite trench gate structure. This preparation process is simple, easy to manufacture, and has low manufacturing costs.

[0074] As an example, the thickness of the formed epitaxial structure 200 may range from 8 μm to 20 μm, such as 8 μm, 10 μm, 15 μm, 20 μm, etc. The depth of the formed trench gate structure 400 may range from 5 μm to 10 μm, such as 5 μm, 8 μm, 10 μm, etc., and the trench gate structure 400 may penetrate the second epitaxial layer 220; the thickness of the first gate dielectric layer 411 may range from 500 μm to 1000 μm, such as 500 μm, 800 μm, 1000 μm, etc.

[0075] As an example, the first gate dielectric layer 411 and the second gate dielectric layer 421 can both be made of silicon oxide, such as silicon oxide formed by a thermal oxidation process. Alternatively, they can be made of a material having a dielectric constant greater than that of silicon oxide, such as an oxide, nitride, or oxynitride having a relatively large dielectric constant. The first gate conductive layer 412 and the second gate conductive layer 422 can both be made of polysilicon. Alternatively, they can be made of a metal layer or a stacked gate conductive layer including a metal layer and a polysilicon layer.

[0076] As an example, the step of forming the trench gate structure 400 may include:

[0077] The epitaxial structure 200 is patterned to form a trench 300, wherein the trench 300 exposes the first epitaxial layer 210. Figure 2 ;

[0078] A first gate dielectric layer 411 and a first gate conductive layer 412 filling the trench 300 are formed in the trench 300. Figure 3 ;

[0079] removing a portion of the first gate dielectric layer 410 to form a groove (not shown);

[0080] A second gate dielectric layer 421 and a second gate conductive layer 422 filling the groove are formed in the groove, and the surface 422 of the second gate conductive layer and the surface of the first gate conductive layer 412 are located in the same plane. Figure 4 .

[0081] In another embodiment, the step of forming the trench gate structure 400 may further include:

[0082] The epitaxial structure 200 is patterned to form a trench 300, wherein the trench 300 exposes the first epitaxial layer 210. Figure 2 ;

[0083] A first gate dielectric layer 411 and a first gate conductive layer 412 filling the trench 300 are formed in the trench 300. Figure 3 ;

[0084] patterning the first gate dielectric layer to form a groove;

[0085] A second gate conductive layer 422 is formed to fill the groove, and the surface of the second gate conductive layer 422 is located in the same plane as the surface of the first gate conductive layer 421. Figure 4 , that is, the formed first gate conductive layer 421 can be directly used as the gate dielectric layer of the second trench gate structure 420 to reduce process complexity.

[0086] Then, if Figure 5A body region 500 of the second conductivity type is formed in the second epitaxial layer 220 between the trench gate structures 400 , and a source region 600 of the first conductivity type is formed in the body region 500 .

[0087] Specifically, conventional body implantation techniques may be used to form the body region 500 and the source region 600 surrounding the trench gate structure 400. For example, a first ion implantation may be performed to form the body region 500 of the second conductivity type in the upper region of the second epitaxial layer 220 adjacent to the trench gate structure 400. Subsequently, a second ion implantation may be performed to form the source region 600 of the first conductivity type in the body region 500.

[0088] Then, if Figure 6 , may also include the step of forming a defect center 700 in the epitaxial structure 200, so that when the reverse freewheeling diode is turned off, the minority carrier holes can recombine with the defect center on the spot, shortening the recombination time, so as to reduce the reverse recovery time of the MOSFET device through the defect center 700, thereby greatly improving the rectification efficiency of the power supply system. Wherein, the material forming the defect center 700 may include one or a combination of lithium, iron and copper. The defect center 700 is preferably evenly distributed in the first epitaxial layer 210 and the second epitaxial layer 220. Then, as Figure 7 , forming a dielectric layer 800 and a metal conductive layer 900 located above the source region 600.

[0089] Specifically, the dielectric layer 800 is first formed to cover the source region 600 and the top surface of the trench gate structure 400, and then a conductive channel penetrating the dielectric layer 800 and the source region 600 is formed through a known etching process, and then the metal conductive layer 900 is formed above the dielectric layer 800, so that the metal conductive layer 900 is connected to the body region 500 through the conductive channel. The metal conductive layer 900 may include a metal material such as aluminum or copper.

[0090] In summary, the MOSFET device and preparation method of the present invention introduce a double-layer epitaxial structure with different doping concentrations and a deeper trench gate structure with gate dielectric layers of different thicknesses, which can enable the MOSFET device to achieve a higher withstand voltage under a certain trench depth and significantly reduce the on-resistance and reverse recovery time; in the trench gate structure, the composite trench gate structure with gate dielectric layers of different thicknesses and gate conductive layers of the same plane is formed, and the preparation process is simple, easy to manufacture, and has low manufacturing cost; introducing defect centers in the epitaxial structure can further reduce the reverse recovery time of the MOSFET device, thereby greatly improving the rectification efficiency of the power supply system. At the same time, the double-layer epitaxial structure provides soft reverse recovery characteristics, significantly reducing the voltage and current spikes of the system and improving the system reliability.

[0091] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A MOSFET device, characterized in that: The MOSFET device comprises: An epitaxial structure having a first conductivity type, the epitaxial structure comprising a first epitaxial layer and a second epitaxial layer stacked together, the doping concentration of the first epitaxial layer being greater than the doping concentration of the second epitaxial layer, the epitaxial structure being an epitaxial structure having defect centers, the material forming the defect centers comprising one or a combination of lithium, iron, and copper, and the defect centers being uniformly distributed in the first epitaxial layer and the second epitaxial layer; a trench gate structure disposed in the epitaxial structure, comprising a first trench gate structure and a second trench gate structure, wherein the first trench gate structure comprises a first gate dielectric layer and a first gate conductive layer, the second trench gate structure comprises a second gate dielectric layer and a second gate conductive layer, the second trench gate structure is located on the first gate dielectric layer and is located around a portion of the first gate conductive layer, and the first gate dielectric layer is directly used as the second gate dielectric layer in the second trench gate structure; a body region having a second conductivity type, the body region being disposed in the second epitaxial layer between the trench gate structures, the second conductivity type being opposite to the first conductivity type; A source region of a first conductivity type is provided on the body region.

2. The MOSFET device according to claim 1, wherein: The thickness of the epitaxial structure ranges from 8 μm to 20 μm; the depth of the trench gate structure is from 5 μm to 10 μm, and the trench gate structure penetrates the second epitaxial layer; the thickness of the first gate dielectric layer is from 500 μm to 1000 μm.

3. The MOSFET device according to claim 1, wherein: A surface of the second gate conductive layer and a surface of the first gate conductive layer are located in the same plane.

4. The MOSFET device according to claim 1, wherein: The first gate dielectric layer and the second gate dielectric layer are both silicon oxide; the first gate conductive layer and the second gate conductive layer are both polysilicon.

5. A method for preparing a MOSFET device, characterized in that: The following steps are involved: forming an epitaxial structure having a first conductivity type, the epitaxial structure comprising a first epitaxial layer and a second epitaxial layer stacked together, wherein the doping concentration of the first epitaxial layer is greater than the doping concentration of the second epitaxial layer; A trench gate structure is formed in the epitaxial structure, wherein the trench gate structure includes a first trench gate structure and a second trench gate structure, wherein the first trench gate structure includes a first gate dielectric layer and a first gate conductive layer, and the second trench gate structure includes a second gate dielectric layer and a second gate conductive layer, and the second trench gate structure is located on the first gate dielectric layer and is located at the periphery of a portion of the first gate conductive layer; wherein the step of forming the trench gate structure includes: Patterning the epitaxial structure to form a trench, wherein the trench exposes the first epitaxial layer; forming a first gate dielectric layer in the trench and a first gate conductive layer filling the trench; patterning the first gate dielectric layer to form a groove; forming a second gate conductive layer filling the groove, and directly applying the first gate dielectric layer as the second gate dielectric layer in the second trench gate structure; forming a body region of a second conductivity type in the second epitaxial layer between the trench gate structures, the second conductivity type being opposite to the first conductivity type; forming a source region having a first conductivity type in the body region; The method further includes forming a defect center in the epitaxial structure, wherein the material forming the defect center includes one or a combination of lithium, iron and copper, and the defect center is uniformly distributed in the first epitaxial layer and the second epitaxial layer.

6. The method for preparing a MOSFET device according to claim 5, wherein: The thickness of the formed epitaxial structure ranges from 8 μm to 20 μm; the depth of the formed trench gate structure is from 5 μm to 10 μm, and the trench gate structure penetrates the second epitaxial layer; the thickness of the first gate dielectric layer is from 500 μm to 1000 μm.

7. The method for preparing a MOSFET device according to claim 5, wherein: A surface of the second gate conductive layer and a surface of the first gate conductive layer are located in the same plane.

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