Digital counting method and circuit with hysteresis
By using a digital counting method and circuit with hysteresis, the problem of unstable counting results was solved. By increasing the period value of the last counting cycle during the counting process, the stability of the counting results and the accuracy of the system were achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-08-31
- Publication Date
- 2026-04-10
AI Technical Summary
Existing digital counting methods produce unstable counting results when the input signal duration is between two clock cycles, leading to system misjudgments.
A digital counting method with hysteresis is adopted. Counting starts at the first moment, and the count signal is stored at the second moment and it is judged whether its value is equal to the output signal value. If they are equal, the period value of the last counting cycle is increased. The hysteresis function is realized by using a counter, a clock signal generation circuit, a register and a digital comparator.
This achieves stability of the counting results when the effective duration of the input signal is uncertain, avoids fluctuations in the counting results, and ensures the accuracy of the system.
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Figure CN115395946B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to an electronic circuit, and more particularly, to a digital counting method and circuit with hysteresis. BACKGROUND
[0002] In digital circuit, it is often to record the effective duration of a signal by digital counting. By simple counting, the duration of a signal can be digitalized. For example, when the input signal is high, the counter starts counting from zero to the clock signal, and the counter increases by one every time the clock signal passes a period. When the input signal becomes low, the counter stops counting and records the digital signal representing the counting result into a register.
[0003] The above implementation is simple, but it has a problem: when counting the input signal with equal duration for each period, if the duration of the input signal is just between two clock signal periods, the counting result may be different every time due to the clock jitter. That is, for the input signal with equal duration for each period, the counting value is different: more or less.
[0004] As shown in FIG. 1, the effective duration of the input signal Signal-IN needs to be counted. Assume that the counter counts once at the rising edge of each clock signal. When the end time of the effective duration of the input signal Signal-IN (the falling edge of the input signal Signal-IN) is in the middle of the clock signal period, as shown in the clock signal CLK0, the counter will not make a mistake, for example, Cn. However, when the end time of the effective duration of the input signal Signal-IN is between two clock signal periods, as shown in the clock signal CLK1, the counter will cause the counting value to swing between two adjacent numbers Cn and Cn+1 due to its inherent jitter. This will result in a stable input signal corresponding to a group of jumping and unstable output digital signals, and further cause the system to make a mistake. Figure 1 SUMMARY The present disclosure relates to an electronic circuit, and more particularly, to a digital counting method and circuit with hysteresis.
[0005] The present disclosure aims to solve the above problems in the prior art and proposes a digital counting method and circuit with hysteresis.
[0006] The present disclosure proposes a digital counting method with hysteresis, which includes: starting counting the period of the clock signal at a first time and generating a counting signal; registering the value of the counting signal at a second time and generating an output signal; determining whether the value of the counting signal is equal to the value of the output signal; and when the value of the counting signal is equal to the value of the output signal, increasing the period value of the last counted period of the clock signal between the first time and the second time.
[0007] The present disclosure further provides a digital counting circuit with hysteresis, comprising: a counter having an enable terminal, an input terminal and an output terminal, the enable terminal of the counter receiving an input signal, the input terminal of the counter receiving a clock signal, at the first active edge of the input signal, the counter starts and counts the clock signal to generate a counting signal at the output terminal of the counter; a clock signal generation circuit having a control terminal and an output terminal, the control terminal receiving a period adjustment signal, the clock signal generation circuit generating the clock signal at the output terminal, wherein the period adjustment signal is used to adjust the period of the clock signal; a register receiving the counting signal and generating an output signal at the second active edge while storing the value of the counting signal at the time; and a digital comparator comparing the counting signal and the output signal and generating the period adjustment signal.
[0008] The digital counting circuit and method with hysteresis provided by the present disclosure have simple implementation, and the hysteresis function of the counting circuit can be realized without complex digital signal processing process, so that the counting result is stable. BRIEF DESCRIPTION OF DRAWINGS
[0009] Figure 1 Fig. 1 shows a waveform diagram of an existing counting circuit;
[0010] Figure 2 Fig. 2 shows a digital counting method with hysteresis according to an embodiment of the present disclosure;
[0011] Figure 3 Fig. 3 shows a waveform diagram of the digital counting method with hysteresis according to an embodiment of the present disclosure;
[0012] Figure 4 Fig. 4 shows a schematic block diagram of a digital counting circuit 100 with hysteresis according to an embodiment of the present disclosure.
[0013] Figure 5 Fig. 5 shows a digital counting circuit with hysteresis according to an embodiment of the present disclosure; Figure 4 Fig. 6 shows a circuit schematic diagram of the clock signal generation circuit 12 in the embodiment.
[0014] As shown in the drawings, the same reference numerals refer to the same parts in all different views. The drawings provided herein are for the purpose of illustrating the embodiments, principles, concepts, etc., and are not drawn to scale. DETAILED DESCRIPTION
[0015] Non-limiting descriptions of specific embodiments of the present disclosure will be provided with reference to the drawings. Throughout the specification, "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. The terms "comprising," "having," "including," and "containing" are used interchangeably in this disclosure. Unless otherwise noted, features of subject matter outlined herein can be combined with each other in any combination. Throughout the document, the use of "a," "an," or "one" to describe a particular feature, structure, or characteristic is not intended to waive the possibility of more than one of the features, structures, or characteristics. Further, the described features, structures, or characteristics can be combined in one or more embodiments in any suitable manner. Unless otherwise indicated, the term "connected" is used to designate a direct electrical connection between circuit elements, while the term "coupled" is used to designate an electrical connection between circuit elements, which can be direct or via one or more other elements. In contrast, when an element is said to be "directly connected to" or "directly coupled to" another element, there are no intervening elements. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. When referring to a voltage of a node or terminal, it is considered that the voltage is the voltage between the node and a reference potential (typically ground), unless otherwise indicated. Furthermore, when referring to a potential of a node or terminal, it is considered that the potential refers to a reference potential, unless otherwise indicated. The voltage and the potential of a given node or a given terminal will be further designated with the same reference sign. A signal that alternates between a first logic state (e.g., a logic low state) and a second logic state (e.g., a logic high state) is referred to as a "logic signal." The high and low states of different logic signals of the same electronic circuit can be different. In particular, the high and low states of a logic signal can correspond to voltages or currents that can not be completely constant in the high or low state.
[0016] Figure 2 A method of digital counting with hysteresis is shown according to one embodiment of the present disclosure. The method of digital counting with hysteresis includes steps S1-S4.
[0017] Step S1: Counting the clock signal periods and generating a count signal is started at a first time instant. In one embodiment, the first time instant includes an input signal (e.g., a clock signal) being asserted. The count signal is generated by a counter (e.g., a digital counter) that is coupled to the clock signal. Figure 4The first active edge of the input signal is the time at which the input signal changes from the first logic level to the second logic level. In one embodiment, the input signal is a pulse width modulated signal, the first logic level of the input signal is a logic low level, the second logic level of the input signal is a logic high level, and the first active edge is the time at which the input signal changes from the logic low level to the logic high level, i.e., the time at which the input signal rises.
[0018] In other embodiments, the first logic level of the input signal can also be a logic high level, and the second logic level of the input signal is a logic low level. In this case, the first active edge is the time at which the input signal falls.
[0019] Step S2: stopping counting the clock signal at a second time and outputting the value of the count signal as an output signal (e.g., Signal-OUT) at the second time. Figure 4 In one embodiment, the second time includes the time of a second active edge of the input signal. In one embodiment, a register is used to store the value of the count signal at the time of the second active edge of the input signal in each cycle of the input signal, and the register is refreshed at the time of the second active edge of the input signal in each cycle of the input signal. In one embodiment, the first active edge and the second active edge are edges in opposite directions, i.e., the time of the second active edge is the time at which the input signal changes from the second logic level to the first logic level. That is, when the first active edge is a rising edge, the second active edge is a falling edge, and vice versa. In one embodiment, the time of the second active edge is the time at which the input signal changes from the logic high level to the logic low level, i.e., the time of the falling edge of the input signal in each cycle. The time period between the time of the first active edge and the time of the second active edge is the active time of the input signal, and is also the counting time of the clock signal. The output signal Signal-OUT represents the counting value of the clock signal between the time of the first active edge and the time of the second active edge of the input signal. In one embodiment, the output signal Signal-OUT has a fixed value.
[0020] Step S3: determining whether the value of the count signal is equal to the value of the output signal Signal-OUT. If yes, go to step S4, otherwise, continue step S3.
[0021] Step S4: Increase the period value of the last counted cycle of the clock signal between the first and second time points.
[0022] Figure 3 The diagram shown is a waveform representation of a hysteresis-based digital counting method according to an embodiment of this disclosure. Figure 3 As shown, assume the counter counts once at the rising edge of each clock signal CLK1. Even if the effective duration of the input signal Signal-IN ends at the falling edge of the input signal Signal-IN between two cycles of the clock signal CLK1, because... Figure 2 The disclosed method extends the period value of the last cycle Tn of the clock signal CLK1 between the times of the first and second effective edges when the counting signal equals the output signal. Therefore, the output signal Signal-OUT will not oscillate between two adjacent count values Cn and Cn+1 due to the inherent jitter of the counter itself, but will be fixed at Cn. Figure 3 The waveforms of CLK2 and CLK3 are shown in the diagram. In the last period between the rising edge and the falling edge of the input signal Signal-IN, the original clock signal CLK1 increases from Tn to Tn+Δt1. In one embodiment, Δt1 = 0.5 × Tn.
[0023] Those skilled in the art will readily understand that changing the period value of the last cycle Tn of the clock signal CLK1 can be achieved by increasing the duration of the logic low level (as shown in the CLK2 waveform) or by increasing the duration of the logic low level (as shown in the CLK3 waveform), which will not be elaborated here.
[0024] Figure 4 The diagram shown is a schematic block diagram of a hysteresis-enabled digital counting circuit 100 according to an embodiment of the present disclosure. Figure 4 The counting circuit shown can achieve Figure 2 The counting method is shown. (As shown in the example...) Figure 4 As shown, the digital counting circuit 100 includes a counter 11, a clock signal generation circuit 12, a single pulse generator 13, a register 14, and a digital comparator 15.
[0025] The counter 11 includes an enable terminal, an input terminal and an output terminal. The enable terminal of the counter 11 receives the input signal Signal-IN. The input terminal of the counter 11 receives the clock signal CLK. At the time of the first active edge of the input signal Signal-IN, the input signal Signal-IN starts the counter 11, the counter 11 counts the clock signal CLK and outputs a count signal COUNT at its output terminal. At the time of the second active edge of the input signal Signal-IN, the input signal Signal-IN resets the counter 11, the counter 11 waits for the time of the first active edge of the next cycle of the input signal Signal-IN and counts the clock signal CLK again.
[0026] In one embodiment, the count signal COUNT is a real-time count signal of the clock signal CLK, representing the number of real-time cycles of the clock signal CLK, the count signal COUNT has a value that varies with time.
[0027] The clock signal generating circuit 12 includes a control terminal and an output terminal, the control terminal receives the cycle adjustment signal CTL. The clock signal generating circuit 12 generates the clock signal CLK at the output terminal, the cycle adjustment signal CTL is used to adjust the cycle of the clock signal CLK.
[0028] The one-shot generator 13 receives the input signal Signal-IN and generates a one-shot signal PLS at the time of the second active edge of the input signal Signal-IN. In one embodiment, the time of the second active edge is the time of the falling edge of the input signal Signal-IN.
[0029] The register 14 has an enable terminal, an input terminal and an output terminal. The enable terminal of the register 14 receives the one-shot signal PLS. The input terminal of the register 14 receives the count signal COUNT. The one-shot signal PLS enables the register 14 to register the value of the count signal COUNT and generate an output signal Signal-OUT. The value registered by the register 14 will be refreshed after the arrival of each one-shot. In one embodiment, the output signal Signal-OUT has a fixed value that does not vary with time within one cycle.
[0030] The digital comparator 15 compares the count signal COUNT and the output signal Signal-OUT and generates the cycle adjustment signal CTL. In one embodiment, when the value of the count signal COUNT is equal to the output signal Signal-OUT, the cycle adjustment signal CTL will increase the cycle value of the clock signal CLK for the last counted cycle between the first active edge and the second active edge of the input signal Signal-IN.
[0031] Figure 5 An embodiment of the present disclosure is shown.Figure 4 a circuit schematic diagram of the clock signal generating circuit 12 in the embodiment. As shown in the figure, the clock signal generating circuit 12 includes a current source IB, a capacitor CI, a switch tube Ml, a first comparison circuit 121, a second comparison circuit 122, and a logic circuit 123. Figure 5
[0032] The current source IB has a first end, a second end, and a control end. The first end of the current source IB is coupled to a power supply VCC. The control end of the current source IB receives a period adjustment signal CTL.
[0033] The capacitor CI is coupled between the second end of the current source IB and a reference ground.
[0034] The first comparison circuit 121 has a first end, a second end, and an output end. The first end of the first comparison circuit 121 receives a voltage signal VC1 on the capacitor CI. The second end of the first comparison circuit 121 receives a first reference voltage signal Vmax. The first comparison circuit 121 compares the voltage signal VC1 and the first reference voltage signal Vmax, and generates a set signal SET. In one embodiment, the first comparison circuit 121 includes a voltage comparator CA1 having a non-inverting input end and an inverting input end. The non-inverting input end of the voltage comparator CA1 receives the voltage signal VC1. The inverting input end of the voltage comparator CA1 receives the first reference voltage signal Vmax.
[0035] The second comparison circuit 122 has a first end, a second end, and an output end. The first end of the second comparison circuit 122 receives the voltage signal VC1. The second end of the second comparison circuit 122 receives a second reference voltage signal Vmin. The second comparison circuit 122 compares the voltage signal VC1 and the second reference voltage signal Vmin, and generates a reset signal RESET. In one embodiment, the second reference voltage signal Vmin is less than the first reference voltage signal Vmax. In one embodiment, the second comparison circuit 122 includes a voltage comparator CA2 having a non-inverting input end and an inverting input end. The inverting input end of the voltage comparator CA2 receives the voltage signal VC1. The non-inverting input end of the voltage comparator CA2 receives the second reference voltage signal Vmin.
[0036] The switch tube Ml has a first end, a second end, and a control end. The first end of the switch tube Ml is coupled to a common node of the current source IB and the capacitor CI. The second end of the switch tube Ml is connected to the reference ground. The control end of the switch tube Ml receives a clock signal CLK.
[0037] The logic circuit 123 receives the set signal SET and the reset signal RESET. The logic circuit 123 performs a logic operation on the set signal SET and the reset signal RESET, and generates the clock signal CLK. In one embodiment, the logic circuit 123 includes an RS flip-flop. The set end S of the RS flip-flop receives the set signal SET. The reset end R of the RS flip-flop receives the reset signal RESET. The RS flip-flop outputs the clock signal CLK at the output end Q.
[0038] In Figure 5 In the embodiment shown, the set signal SET is used to set the rising edge of the clock signal CLK, and the reset signal RESET is used to set the falling edge of the clock signal CLK. The cycle adjustment signal CTL is used to adjust the value of the current source IB. In one embodiment, when the cycle adjustment signal CTL is invalid, i.e. the value of the count signal COUNT has not reached the value of the output signal Signal-OUT, the value of the current source IB remains unchanged; when the cycle adjustment signal CTL is valid, i.e. the value of the count signal COUNT is equal to the value of the output signal Signal-OUT, the cycle adjustment signal CTL is used to reduce the value of the current source IB, thereby increasing the period of the clock signal CLK.
[0039] Although the present disclosure has been described with reference to several exemplary embodiments, it is understood that the terms used in the disclosed embodiments of the present disclosure are illustrative and exemplary only and are not to be construed as limiting the present disclosure. It is to be understood that in an alternative embodiment, unless it is specifically excluded (i.e., is unambiguously contradicted by context), the term "comprising" can be replaced with the term "consisting of." Furthermore, the words "comprise", "comprising", "including", "including", "has", "have", "containing", "containing" or the like are to be construed in their inclusive sense as opposed to an exclusive or exhaustive sense, unless these words are specifically followed by the terms "consist only of" or "consisting only of". Additionally, the words "herein," "above," and "below" and words of similar import mean in reference to this application as a whole, unless the context clearly indicates otherwise. Moreover, the words "primarily," "substantially," "approximately," and "about" mean "plus or minus 10% of the stated magnitude", unless otherwise stated. Furthermore, the words "contact" and "engage" mean "direct contact" or "direct engagement", unless otherwise stated.
Claims
1. A method of digital counting with hysteresis, characterized by, include: The clock signal cycles are counted starting from the first moment, and a counting signal is generated. The value of the counting signal is registered at the second time and an output signal is generated. The first time includes the time of the first effective edge of the input signal in each cycle, and the second time includes the time of the second effective edge of the input signal in each cycle. The first effective edge and the second effective edge are edges with opposite directions. Determine whether the value of the counting signal is equal to the value of the output signal; and When the value of the counting signal equals the value of the output signal, increase the period value of the last counted cycle of the clock signal between the first and second moments.
2. A digital counting circuit with hysteresis, characterized by The counting circuit includes: A counter has an enable terminal, an input terminal, and an output terminal. The enable terminal of the counter receives an input signal, and the input terminal of the counter receives a clock signal. At the moment of the first valid edge of the input signal, the counter starts and counts the clock signal and generates a count signal at the output terminal of the counter. The moment of the first valid edge is the moment when the input signal changes from a first logic level to a second logic level. A clock signal generating circuit has a control terminal and an output terminal. The control terminal receives a period adjustment signal, and the clock signal generating circuit generates a clock signal at its output terminal. The period adjustment signal is used to adjust the period of the clock signal. A register is used to receive the counting signal and store the value of the counting signal at the second valid edge while simultaneously generating an output signal. The second valid edge is the moment when the input signal changes from a second logic level to a first logic level. A digital comparator is used to compare a counting signal and an output signal and generate the period adjustment signal, wherein when the value of the counting signal is equal to the output signal, the period adjustment signal increases the period value of the last counted cycle of the clock signal between the time of the first effective edge and the time of the second effective edge of the input signal.
3. The counting circuit of claim 2, wherein, The counting circuit further includes a single pulse generator; the single pulse generator receives an input signal and generates a single pulse signal at the second effective edge of the input signal; wherein, the register further receives the single pulse signal and stores the value of the counting signal at the moment the single pulse signal arrives to generate an output signal.
4. The counting circuit of claim 3, wherein, The digital counting circuit further includes an inverter; the inverter receives an input signal and performs an inverted logic operation on the input signal to generate an inverted signal of the input signal; wherein the inverted signal of the input signal is sent to the enable terminal of the counter.
5. The counting circuit of claim 3, wherein, The first and second effective edges are edges in opposite directions.
6. The counting circuit of claim 3, wherein, The clock signal generation circuit includes: A controllable current source has a first terminal, a second terminal, and a control terminal. The first terminal of the controllable current source is coupled to the power supply, and the control terminal of the controllable current source receives a periodic adjustment signal. A capacitor is coupled between the second terminal of the controllable current source and a reference ground. A first comparator circuit has a first terminal, a second terminal and an output terminal. The first terminal of the first comparator circuit receives a voltage signal on the capacitor, and the second terminal of the first comparator circuit receives a first reference voltage signal. The first comparator circuit compares the voltage signal on the capacitor with the first reference voltage signal to generate a set signal. a second comparison circuit having a first end, a second end and an output end, the first end of the second comparison circuit receiving the voltage signal on the capacitor, the second end of the second comparison circuit receiving a second reference voltage signal, the second comparison circuit comparing the voltage signal on the capacitor and the second reference voltage signal to generate a reset signal; a logic circuit performing a logic operation on the set signal and the reset signal to generate a clock signal; and a switch tube having a first end, a second end and a control end, the first end of the switch tube being coupled to the common node of the controllable current source and the capacitor, the second end of the switch tube being connected to a reference ground, the control end of the switch tube receiving the clock signal.
7. The counting circuit of claim 6, wherein, The second reference voltage signal is less than the first reference voltage signal.
8. The counting circuit of claim 6, wherein, The period adjustment signal is used to reduce the output current of the controllable current source when the count signal is equal to the output signal.
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