Neuromorphic memory devices and methods

Abstract

Devices and methods are disclosed, including memory devices and systems. Example memory devices, systems, and methods include a memory die stack, a controller die, and a buffer. Example memory devices, systems, and methods include one or more neuromorphic layers logically coupled between a host interface of one or more dies in the memory die stack and the controller die.

Description

[0001] Priority requirements

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 62 / 954,186, filed on December 27, 2019, entitled “Neuromorphic Memory Device and Method,” which is hereby incorporated herein by reference in its entirety. Background Technology

[0003] A memory device is a semiconductor circuit that provides electronic storage for data to a host system (such as a computer or other electronic device). Memory devices can be volatile or non-volatile. Volatile memory requires power to maintain data and includes devices such as random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM). Non-volatile memory retains stored data when no power is supplied and includes devices such as flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), or magnetoresistive random access memory (MRAM).

[0004] A host system typically includes a host processor, a first number of main memories (e.g., typically volatile memory, such as DRAM) supporting the host processor, and one or more storage systems (e.g., typically non-volatile memory, such as flash memory), which provide additional storage devices for retaining data as a supplement to the main memory or separately from the main memory.

[0005] Storage systems such as solid-state drives (SSDs) may include a memory controller and one or more memory devices, comprising several dies or logic units (LUNs). In some instances, each die may include several memory arrays and peripheral circuitry, such as die logic or die processors. The memory controller may include interface circuitry configured to communicate with a host device (e.g., a host processor or interface circuitry) via a communication interface (e.g., a bidirectional parallel or serial communication interface). The memory controller may receive commands or operations associated with memory operations or instructions from the host system, such as read or write operations transferring data (e.g., user data and associated integrity data, such as error data or address data) between the memory device and the host device, erase operations erasing data from the memory device, and drive management operations (e.g., data migration, garbage collection, block deregistration), etc.

[0006] The goal is to provide improved main memory, such as DRAM. The characteristics of the desired improved main memory include, but are not limited to, higher capacity, higher speed, and reduced cost. Attached Figure Description

[0007] In the accompanying drawings, which are not necessarily drawn to scale, similar designations may describe similar components in different views. Similar designations with different letter suffixes may indicate different examples of similar components. The accompanying drawings illustrate, by way of example but not in a limiting sense, the various embodiments discussed in this document.

[0008] Figure 1A A system including a memory device is shown according to some example embodiments.

[0009] Figure 1B Another system including a memory device is shown according to some example embodiments.

[0010] Figure 2 An example memory system according to some example embodiments is shown.

[0011] Figure 3A A memory system in block diagram form according to some example embodiments is shown.

[0012] Figure 3B Another memory system is shown in block diagram form according to some example embodiments.

[0013] Figure 3C A buffer die is shown in block diagram form according to some example embodiments.

[0014] Figure 4 Another memory device according to some example embodiments is shown.

[0015] Figure 5A Another memory device according to some example embodiments is shown.

[0016] Figure 5B Another memory device according to some example embodiments is shown.

[0017] Figure 5C Another memory device according to some example embodiments is shown.

[0018] Figure 5D Another memory device according to some example embodiments is shown.

[0019] Figure 6 Another memory device according to some example embodiments is shown.

[0020] Figure 7 Another memory device according to some example embodiments is shown.

[0021] Figure 8A Another memory device according to some example embodiments is shown.

[0022] Figure 8B Another memory device according to some example embodiments is shown.

[0023] Figure 9A A DRAM die configuration according to some example embodiments is shown.

[0024] Figure 9B Another DRAM die configuration according to some example embodiments is shown.

[0025] Figure 9C Another DRAM die configuration according to some example embodiments is shown.

[0026] Figure 10 An example neuromorphic layer is shown according to some example embodiments.

[0027] Figure 11 Another example neuromorphic layer is shown according to some example embodiments.

[0028] Figure 12 A DIMM memory according to some example embodiments is shown.

[0029] Figure 13 A flowchart of an example method according to some example embodiments is shown.

[0030] Figure 14 An example block diagram of an information processing system according to some example embodiments is shown. Detailed Implementation

[0031] The following description and accompanying drawings fully illustrate specific embodiments, enabling those skilled in the art to practice these specific embodiments. Other embodiments may be included with structural, logical, electrical, technological, and other variations. Parts and features of some embodiments may be incorporated into or replace those parts and features of other embodiments. The embodiments set forth in the claims cover all available equivalents of those claims.

[0032] Figure 1A An electronic system 100 is shown, having a processor 106 coupled to a substrate 102. In some instances, the substrate 102 may be a system motherboard, or in other instances, the substrate 102 may be coupled to another substrate, such as a motherboard. The electronic system 100 also includes a first memory device and second memory devices 120A, 120B. The memory devices 120A, 120B are also shown as being supported by the substrate 102 adjacent to the processor 106, but in the example configuration are depicted as being coupled to a secondary substrate 124. In other instances, the memory devices 120A, 120B may be directly coupled to the same substrate 102 as the processor 106.

[0033] Memory devices 120A and 120B each include a controller die 128, which includes buffer circuitry coupled to a secondary substrate 124. Memory devices 120A and 120B each include a corresponding memory device stack 122. For the purposes of this specification, the stacked memory devices will be described as an example configuration, wherein the devices are dynamic random access memory (DRAM) dies 122A and 122B, each coupled to a secondary substrate 124. Other types of memory devices may be used instead of DRAM, including, for example, FeRAM, phase-change memory (PCM), 3D XPoint, etc. TM Memory, NAND memory, or NOR memory, or a combination thereof. In some cases, a single memory device may include a first memory die using a first memory technology (e.g., DRAM) and a second memory die using a second memory technology different from the first memory technology (e.g., SRAM, FeRAM, etc.).

[0034] DRAM die stack 122 in Figure 1A The diagram is shown in block form. Other figures described below illustrate die stacking and various stacking configurations in more detail. Figure 1AIn one example, several wire bonds 126 are shown coupled to a DRAM die stack 122. Additional circuitry (not shown) is contained on or within a substrate 124. This additional circuitry completes the connections between the DRAM die stacks 122 to buffer dies 120 via the wire bonds 126. Selected examples may include through-silicon vias (TSVs) instead of wire bonds 126, as will be described in more detail in subsequent figures.

[0035] Substrate wiring 104 is shown as coupling memory device 120A to processor 106. Figure 1B In the example, an additional memory device 120B is shown. Although two memory devices 120A and 120B are shown for the illustrated example, a single memory structure can be used, or more than two memory devices can be used. The examples of memory devices described in this disclosure increase the capacity near the memory, improve speed, and reduce manufacturing costs.

[0036] Figure 1B An electronic system 150 is shown, having a processor 156 coupled to a substrate 152. System 150 also includes a first memory device and second memory devices 160A and 160B. Compared to Figure 1A ,exist Figure 1B In this configuration, the first and second memory devices 160A and 160B are directly connected to the same substrate 102 as the processor 156, without any intermediate substrate or interposer. This configuration provides superior performance compared to... Figure 1A The instance provides additional speed and reduces component usage. Similar to... Figure 1A As an example, the controller die 168 containing the buffer is shown adjacent to the DRAM die stack 162. Wire bonding 166 is shown as an example interconnect structure; however, other interconnect structures such as TSV can be used.

[0037] Figure 2 It shows something similar to Figure 1A System 120A, 120B or Figure 1B The memory system 200 of systems 160A and 160B includes a controller die 202 coupled to a substrate 204. In one example, the controller die 202 includes a buffer as described in the examples above. The memory device 200 also includes a DRAM die stack 210 coupled to the substrate 204. Figure 2 In one example, individual dies in the DRAM die stack 210 are laterally offset from one or more vertically adjacent dies; specifically, in the depicted example, each die is laterally offset from two vertically adjacent dies. For example, the dies may be staggered in at least one stepped configuration. Figure 2The example illustrates two different staggered orientations in a stepped DRAM die stack 210. In the illustrated dual-step configuration, the exposed surface portion 212 of each die is used for several wire-bonded interconnects.

[0038] Multiple wire-bonded interconnects 214, 216 are shown from the dies in the DRAM die stack 210 to the substrate 204. Additional conductors (not shown) on or within the substrate 204 further couple the wire-bonded interconnects 214, 216 to the controller die 202. The controller die 202 is shown coupled to the substrate 204 using one or more solder interconnects 203, such as a solder ball array. Several substrate solder interconnects 206 are further shown on the bottom side of the substrate 204 to further transmit signals and data from the controller die 202 to the substrate 102, and ultimately to the processor 106, as shown. Figure 1B As shown.

[0039] Figure 3A A top block diagram of a memory device 300 having a memory die stack 310 is shown. In one example, the memory die stack 310 includes DRAM dies. The die stack is shown coupled to a substrate 303. The memory die stack 310 is coupled to a controller die 302 via conductive traces 301. Figure 3A In one example, controller die 302 includes buffer 350 and neuromorphic device 380. In another example, the neuromorphic device is coupled between one or more dies in the memory die stack 310 and buffer 350. It is desirable to perform computational operations, such as neuromorphic commuting, closer to the memory die 310 where data is stored. The close physical proximity of the neuromorphic device 380 to the memory die 310 reduces the physical distance that data must travel during computation. The shorter distance improves computation time and reduces the power required to send data signals back and forth between the processor (e.g., processor 106 of FIG. 1) and the memory dies in the memory device.

[0040] exist Figure 3AIn the configuration shown, buffer 350 allows for different data speeds between controller die 302 and die stack 310, compared to the data speed between controller die 302 and the host device or processor such as processor 106. This configuration can enhance the neuromorphic device's ability to process large amounts of data without causing undesirable lag between memory device 300 and the host device or processor such as processor 106. For example, a wider, slower data interface might be more suitable for interaction between memory die stack 310 and neuromorphic device 380, while a faster, narrower data interface might be more suitable for interaction between controller die 302 and the host device or processor such as processor 106. In one example, buffer 350 of controller die 302 performs this function. The following section discusses... Figure 10 and 11 Examples of neuromorphic device structures are discussed in more detail.

[0041] Figure 3B A side block view of a memory device 330 with a die stack 331 is shown. In one example, the die stack 331 includes DRAM dies. The die stack is shown as coupled to a substrate 333. Figure 3B In one example, the die stack 331 includes a memory die 334 and at least one die 332 containing one or more neuromorphic layers. The memory die stack 331 is coupled to a controller die 336 via a conductive trace 338. Figure 3B In this example, controller die 336 includes buffer 337. One or more neuromorphic layers of die 332 are coupled between memory die 334 and controller die 336. Similar to... Figure 3A The operation of the memory device 300 is enhanced by a configuration that can improve the ability of one or more neuromorphic layers to process large amounts of data from the memory die 334 using a wider and slower channel on one side of the buffer 337, while maintaining a faster and narrower interface on the other side of the buffer 337 between the memory device 330 and the host device or a processor such as the processor 106.

[0042] Figure 3A and 3B Two example locations of the neuromorphic layer are shown; however, the invention is not limited thereto. Other physical locations of the neuromorphic layer are possible, wherein the neuromorphic layer is situated between one or more dies in a memory die stack and a host interface on the controller. Other possibilities include, but are not limited to, dies separated from the controller die or die stack, wherein the separated dies are situated on a substrate such as substrate 303 or substrate 333.

[0043] The selected instance may contain only a single neuromorphic layer. Other instances may contain multiple neuromorphic layers. In one instance, multiple neuromorphic layers may contain 30 to 100 neuromorphic layers. Example devices, such as image recognition systems for autonomous vehicle navigation, may utilize multiple layers in the range of 30 to 100. In one instance, a single die may contain multiple neuromorphic layers. In one instance, multiple dies may contain multiple neuromorphic layers.

[0044] Figure 3C Examples are shown Figure 3A Buffer 350 or Figure 3B A block diagram of buffers such as buffer 337. In one example, a memory device incorporating buffers as described in the examples below is more conducive to the incorporation of local neuromorphic processing. For example, a slower and wider interface 354 may be more suitable for handling slower and wider data from neuromorphic operations performed between the memory die stack and the buffer. After the results computed from one or more neuromorphic layers are available, the results can be transferred via buffer to a narrower, higher-speed host interface, such as... Figure 3C Interface 352.

[0045] The host device interface 352 and memory interface 354 are shown. Additional circuitry components for buffer 350 may include controller and switching logic 356, row address selection (RAS) logic 357, and built-in self-test (BIST) login 358. Communication from buffer 350 to the memory die stack is indicated by arrow 360. Communication from buffer 350 to the host device is indicated by arrows 362 and 364. Figure 3B In the diagram, arrow 364 indicates communication from the Command / Address (CA) pin, and arrow 362 indicates communication from the Data (DQ) pin. The example numbers of CA and DQ pins are provided only as examples, as host device interfaces can have generally more or fewer of either CA or DQ pins, or both. The required number of pins of either type can vary depending on the width of the interface's channels, the provisioning of extra bits (e.g., ECC bits), and many other variables. In many instances, the host device interface will be an industry-standard memory interface (explicitly defined by the standards-setting organization or the actual standard adopted in the industry).

[0046] In one instance, all CA pins 364 are used as a single channel, and all data pins 362 are used as a single channel. In another instance, all CA pins 364 service all data pins 362. In yet another instance, CA pins 364 are subdivided into multiple sub-channels. In yet another instance, data pins 362 are subdivided into multiple sub-channels. One configuration may include a portion of CA pins 364 serviceing a portion of data pins 362. In a particular instance, as a sub-combination of CA pins and data pins, 8 CA pins service 9 data pins. For example, multiple sub-combinations such as an 8 CA pin / 9 data pin instance may be included in a memory device.

[0047] In operation, the potential data rate from the host device may exceed the processing speed of the interconnect components to the memory die (e.g., traces, TSVs, wire bonds, etc.). Adding buffers, for example... Figure 3A Buffer 350, Figure 3B The buffer 337 or other forms of buffer components allow for buffering of rapid data interactions from the host device. Figure 3C In one instance, host interface 352 is configured to operate at a first data rate. In another instance, the first data rate may match the delivery speed at which the host device is capable of delivering data.

[0048] In one instance, memory interface 354 is configured to operate at a second data rate slower than the first data rate. In another instance, memory interface 534 is configured to be slower and wider than host interface 352. In operation, a buffer can convert high-speed data interactions on the host interface 352 side to slower, wider data interactions on the memory interface 354 side. Furthermore, as further described below, in order to maintain a data throughput at least approximating the data throughput of the host interface, in some instances, the buffer can reallocate connections of the host interface to multiple sub-channels associated with the respective memory interface. The slower, wider memory interface 354 can be configured to substantially match the capacity of the narrower, higher-speed host interface 352. In this way, the more limited interconnect components to the memory die (e.g., traces, TSVs, wire bonding, etc.) can handle the capacity of interactions supplied from a faster host device. Although an example host interface (with both CA and DQ pins) to buffer 350 is shown, buffer 350 may contain multiple host interfaces for separate data paths, each of which is reassigned to multiple DRAM interfaces in a similar manner via buffer 350.

[0049] In one instance, host device interface 352 includes a first number of data paths, and memory interface 354 includes a second number of data paths, which is greater than the first number. In one instance, circuitry in buffer 350 maps data and commands from the first number of data paths to the second number of data paths. In this configuration, the second number of data paths provides a slower and wider interface, as described above.

[0050] In one instance, the command / address pins 364 of the host device interface 352 include a first number of command / address paths, and on the corresponding memory interface 354 side of the buffer 350, the memory interface 354 includes a second number of command / address paths greater than the first number. In one instance, the second number of command / address paths is twice the first number. In one instance, the second number of command / address paths is more than twice the first number. In one instance, the second number of command / address paths is four times the first number. In one instance, the second number of command / address paths is eight times the first number.

[0051] In one instance, a given command / address path on the memory interface 354 side of buffer 350 communicates with only a single DRAM die. In another instance, a given command / address path on the memory interface 354 side of buffer 350 communicates with multiple DRAM dies. In yet another instance, a given command / address path on the memory interface 354 side of buffer 350 communicates with four DRAM dies. In yet another instance, a given command / address path on the memory interface 354 side of buffer 350 communicates with sixteen DRAM dies.

[0052] In one example, the data pins 362 of the host device interface 352 include a first number of data paths, and on the corresponding memory interface 354 side of the buffer 350, the memory interface 354 includes a second number of data paths greater than the first number of data paths. In one example, the second number of data paths is twice the first number of data paths. In one example, the second number of data paths is more than twice the first number of data paths. In one example, the second number of data paths is four times the first number of data paths. In one example, the second number of data paths is eight times the first number of data paths.

[0053] In one instance, the data path on the memory interface 354 side of buffer 350 communicates with only a single DRAM die. In another instance, a given data path on the memory interface 354 side of buffer 350 communicates with multiple DRAM dies. In yet another instance, a given data path on the memory interface 354 side of buffer 350 communicates with four DRAM dies. In yet another instance, a given data path on the memory interface 354 side of buffer 350 communicates with sixteen DRAM dies.

[0054] In one example, host interface 352 includes different speeds for command / address pin 364 and data pin 362. In one example, the data pin 362 of the host interface is configured to operate at 6.4 Gb / s. In one example, the command / address pin 364 of the host interface is configured to operate at 3.2 Gb / s.

[0055] In one instance, the memory interface 354 of buffer 350 slows down and widens communication from the host interface 352 side of buffer 350. In one instance, with a given command / address path from host interface 352 mapped to two command / address paths on memory interface 354, the speed at host interface is 3.2 Gb / s and the speed at memory interface 354 is 1.6 Gb / s.

[0056] In one example, with a given data path from host interface 352 mapped to two data paths on memory interface 354, the speed at the host interface is 6.4 Gb / s and the speed at memory interface 354 is 3.2 Gb / s, where each data path communicates with a single DRAM die in the DRAM die stack. In another example, with a given data path from host interface 352 mapped to four data paths on memory interface 354, the speed at the host interface is 6.4 Gb / s and the speed at memory interface 354 is 1.6 Gb / s, where each data path communicates with four DRAM dies in the DRAM die stack. In yet another example, with a given data path from host interface 352 mapped to eight data paths on memory interface 354, the speed at the host interface is 6.4 Gb / s and the speed at memory interface 354 is 0.8 Gb / s, where each data path communicates with 16 DRAM dies in the DRAM die stack.

[0057] In one example, a Pulse Amplitude Modulation (PAM) protocol is used for communication on the memory interface 354 side of buffer 350. In one example, the PAM protocol includes PAM-4, but other PAM protocols are within the scope of this invention. In one example, the PAM protocol increases data bandwidth. In one example, with a given data path from host interface 352 mapped to four data paths on memory interface 354, the speed at the host interface is 6.4 Gb / s, and the speed at memory interface 354 is 0.8 Gb / s using the PAM protocol, where each data path communicates with four DRAM dies in the DRAM die stack. In one example, with a given data path from host interface 352 mapped to eight data paths on memory interface 364, the speed at the host interface is 6.4 Gb / s, and the speed at memory interface 354 is 0.4 Gb / s using the PAM protocol, where each data path communicates with 16 DRAM dies in the DRAM die stack.

[0058] The number of pins required for communication between buffer 350 and the 16 DRAM dies in Example 16 varies depending on the number of command / address paths on the memory interface 354 side of buffer 350 and the number of DRAM dies coupled to each data path. Several non-limiting examples of pin counts and corresponding command / address path configurations are shown below.

[0059]

[0060] The number of pins required for communication between buffer 350 and the 16 DRAM dies in Example 16 varies depending on the number of data paths on the memory interface 354 side of buffer 350 and the number of DRAM dies coupled to each data path. Several non-limiting examples of pin counts and corresponding data path configurations are shown below.

[0061]

[0062] As illustrated in the examples selected below, the pins in the table above can be coupled to DRAM dies in a DRAM die stack in several different ways. In one example, wire bonding is used to couple from the pins to several DRAM dies. In another example, TSV is used to couple from the pins to several DRAM dies. Although wire bonding and TSV are used as examples, other communication paths besides wire bonding and TSV are also within the scope of this invention.

[0063] Figure 4Another example of a memory device 400 is shown. The memory device 400 includes a controller die 402 coupled to a substrate 404, which includes a buffer as described above. The memory device 400 also includes a DRAM die stack 410 coupled to the substrate 404. Figure 4 In one instance, the DRAM die stack 410 is staggered in at least one stepped configuration. Figure 4 The example illustrates two different staggered directions in a stepped DRAM die stack 410. Similar to... Figure 2 In the stepped configuration shown, the exposed surface portion 412 is used for several wire-bonded interconnects.

[0064] Multiple wire-bonded interconnects 414, 416 are shown from the dies in the DRAM die stack 410 to the substrate 404. Additional conductors (not shown) on or within the substrate 404 further couple the wire-bonded interconnects 414, 416 to the controller die 402. The controller die 402 is shown coupled to the substrate 404 using one or more solder interconnects, such as a solder ball array. Several substrate solder interconnects 406 are further shown on the bottom side of the substrate 404 to further transmit signals and data from the buffer die to the motherboard and ultimately to the host device.

[0065] exist Figure 4 In one example, multiple wire-bonded interconnects 414, 416 are connected in series upwards along multiple stacked DRAM dies. In the selected example, a single wire bond can drive a load in more than one DRAM die. In such examples, the wire-bonded interconnects can be connected in series, such as... Figure 4 As shown in the illustration. In one example, a single wire bond can be cascaded to four DRAM dies. In another example, a single wire bond can be cascaded to eight DRAM dies. In yet another example, a single wire bond can be cascaded to sixteen DRAM dies. Other numbers of cascaded DRAM dies are also within the scope of this invention. Additionally, the DRAM interface CA can be connected to a first number of DRAM dies, while the DRAM interface DQ can be correspondingly connected to a second number of DRAM dies, different from the first number.

[0066] Figure 5A Another example of a memory device 500 is shown. The memory device 500 includes a controller die 502 coupled to a substrate 504, which includes a buffer as described above. The memory device 500 also includes a DRAM die stack 510 coupled to the substrate 504. Figure 5AIn this example, the DRAM die stack 510 is staggered in at least one stepped configuration. An example in Figure 5 illustrates two different staggering directions in the stepped DRAM die stack 510. In the illustrated stepped configuration, exposed surface portions 512 are used for several wire-bonded interconnects.

[0067] Multiple wire-bonded interconnects 514, 516 are shown from the dies in the DRAM die stack 410 to the substrate 404. Additional conductors (not shown) on or within the substrate 504 further couple the wire-bonded interconnects 514, 516 to the controller die 502. The controller die 502 is shown coupled to the substrate 504 using one or more solder interconnects, such as a solder ball array. Several substrate solder interconnects 506 are further shown on the bottom side of the substrate 504 to further transmit signals and data from the buffer die to the motherboard and ultimately to the host device.

[0068] exist Figure 5A In one example, the controller die 502 is at least partially located beneath the DRAM die stack 510. In another example, the encapsulation 503 at least partially surrounds the controller die 502. Figure 5A This further reduces the footprint of the memory device 500. Additionally, the interconnect distance between the DRAM die stack 510 and the controller die 502 is reduced.

[0069] Figure 5B Another example of memory device 520 is shown. Memory device 520 includes a controller die 522 coupled to a substrate 524, which includes a buffer as described above. Memory device 520 also includes a DRAM die stack 530 coupled to the substrate 524. Multiple wire-bonded interconnects 534, 536 are shown from the dies in the DRAM die stack 530 to the substrate 524. Figure 5B In one example, multiple wire-bonded interconnects 534, 536 are connected in series upwards along multiple stacked DRAM dies. In one example, a single wire bond may be connected in series to four DRAM dies. In one example, a single wire bond may be connected in series to eight DRAM dies. In one example, a single wire bond may be connected in series to sixteen DRAM dies. Other numbers of DRAM dies connected in series are also within the scope of this invention.

[0070] Figure 5C A top view of a memory device 540, similar to memory devices 500 and 520, is shown. Figure 5C In one example, a controller die 542 containing a buffer as described above is shown coupled to a substrate 544 and is located entirely beneath a DRAM die stack 550. Figure 5DA top view of a memory device 560, similar to memory devices 500 and 520, is shown. Figure 5D In this configuration, the controller die 562 is coupled to the substrate 564 and is partially located beneath a portion of the first DRAM die stack 570 and the second DRAM die stack 572. In one example, shorter DRAM die stacks provide shorter interconnect paths and higher manufacturing yields. In the chosen example, multiple shorter DRAM die stacks may be necessary for these reasons. One trade-off of multiple shorter DRAM die stacks is a larger footprint for the memory device 560.

[0071] Figure 6 Another example of a memory device 600 is shown. The memory device 600 includes a controller die 602 coupled to a substrate 604, which includes a buffer as described above. The memory device 600 also includes a DRAM die stack 610 coupled to the substrate 604. Figure 6 In one instance, the DRAM die stack 610 is staggered in at least one stepped configuration. Figure 6 The example shows four interleavings in two different interleaving directions in a stepped DRAM die stack 610. Figure 6 The DRAM die stack 610 in the example contains 16 DRAM dies, but the invention is not limited thereto. Similar to... Figure 6 Other stepped configurations shown have exposed surface portions 612 for several wire-bonded interconnects.

[0072] Multiple wire-bonded interconnects 614, 616 are shown from the die in the DRAM die stack 610 to the substrate 604. Additional conductors (not shown) on or within the substrate 604 further couple the wire-bonded interconnects 614, 616 to the controller die 602. The controller die 602 is shown coupled to the substrate 604 using one or more solder interconnects, such as a solder ball array. Several substrate solder interconnects 606 are further shown on the bottom side of the substrate 604 to further transmit signals and data from the controller die to the motherboard and ultimately to the host device.

[0073] Figure 7 Another example of a memory device 700 is shown. The memory device 700 includes a controller die 702 coupled to a substrate 704, which includes a buffer as described above. The memory device 700 also includes a DRAM die stack 710 coupled to the substrate 704. Figure 7 In one instance, the DRAM die stack 710 is staggered in at least one stepped configuration. Figure 7 The example shows four interleavings in two different interleaving directions in a stepped DRAM die stack 710. Figure 7The DRAM die stack 710 in the example contains 16 DRAM dies, but the invention is not limited thereto. Similar to... Figure 7 Other stepped configurations shown have exposed surface portions 712 for several wire-bonded interconnects.

[0074] Multiple wire-bonded interconnects 714, 716 are shown from the die in the DRAM die stack 710 to the substrate 704. Additional conductors (not shown) on or within the substrate 704 further couple the wire-bonded interconnects 714, 716 to the controller die 702. The controller die 702 is shown coupled to the substrate 704 using one or more solder interconnects, such as a solder ball array. Several substrate solder interconnects 706 are further shown on the bottom side of the substrate 704 to further transmit signals and data from the controller die to the motherboard and ultimately to the host device.

[0075] exist Figure 7 In one example, the controller die 702 is at least partially located beneath the DRAM die stack 710. In another example, the encapsulation 703 at least partially surrounds the controller die 702. Figure 7 This further reduces the footprint of the memory device 700. Additionally, the interconnect distance between the DRAM die stack 710 and the controller die 702 is reduced.

[0076] Figure 8A Another example of a memory device 800 is shown. The memory device 800 includes a controller die 802 coupled to a substrate 804, which includes a buffer as described above. The memory device 800 also includes a DRAM die stack 810 coupled to the substrate 804. Figure 8A In this example, the DRAM die stack 810 is vertically aligned. Figure 8A The DRAM die stack 810 in the invention contains eight DRAM dies, but the invention is not limited thereto.

[0077] Multiple TSV interconnects 812 are shown, which pass through and communicate with one or more dies in the DRAM die stack 810 to reach a substrate 804. Additional conductors (not shown) on or within the substrate 804 further couple the TSVs 812 to a controller die 802. The controller die 802 is shown coupled to the substrate 804 using one or more solder interconnects, such as a solder ball array. Several substrate solder interconnects 806 are further shown on the bottom side of the substrate 804 to further transmit signals and data from the controller die to the motherboard and ultimately to the host device.

[0078] Figure 8BAnother example of memory device 820 is shown. Memory device 820 includes a controller die 822 coupled to a substrate 824, which includes a buffer as described above. Memory device 820 also includes a DRAM die stack 830 coupled to the substrate 824. Figure 8B In this example, the DRAM die stacks are vertically aligned in an 830 configuration. Figure 8B The DRAM die stack 830 in the invention contains 16 DRAM dies, but the invention is not limited thereto.

[0079] Multiple TSV interconnects 832 are shown, which pass through and communicate with one or more dies in the DRAM die stack 830 to reach a substrate 824. Additional conductors (not shown) on or within the substrate 824 further couple the TSVs 832 to a controller die 822. The controller die 822 is shown coupled to the substrate 824 using one or more solder interconnects, such as a solder ball array. Several substrate solder interconnects 826 are further shown on the bottom side of the substrate 824 to further transmit signals and data from the controller die to the motherboard and ultimately to the host device.

[0080] Figure 9A A block diagram is shown of a single DRAM die 900 that may be contained in a stack of memory dies according to any embodiment of this disclosure. Figure 9A In this embodiment, the DRAM die 900 includes a memory region 902 having an array of memory cells. A first data I / O stripe 904 is shown extending from a first side 901 to a second side 903 of the DRAM die 900. In one example, contacts may be formed on one or both sides 901, 903 of the first data I / O stripe 904 at the edge of the first data I / O stripe 904. The contacts may be connected to wire bonding as described in the examples above. In other examples, TSVs may be coupled to the first data I / O stripe 904 at sides 901, 903 or at other locations along the first data I / O stripe 904.

[0081] Figure 9A The second data I / O stripe 906 is further illustrated. In one example, the second data I / O stripe 906 is substantially the same as the first data I / O stripe 904. Figure 9A In this example, each data I / O strip contains 36 contacts for connection to wire bonds on either side. With two data I / O strips, each with two sides, the DRAM die 900 contains connections for 144 wire bonds or TSVs.

[0082] Figure 9AThe diagram further illustrates a command / address strip 910. In the illustrated example, the command / address strip 910 includes 30 contacts for connection to wire bonds or TSVs. In one example, one or more DRAM dies may include a redistribution layer that redistributes the connections of one or more of the data I / O stripes 904, 906, 910 to a second location for wire bonding, for example, redistributing them to wire bonding pads along one or more rows of the die edge (as depicted relative to the example wire bonding stack configuration discussed earlier herein).

[0083] Figure 9B A block diagram of four DRAM die stacks 920 that may be included in a DRAM die stack according to any embodiment of this disclosure is shown. Figure 9B In the stack 920, each die includes a memory region 922 with an array of memory cells. A first data I / O stripe 924 is shown extending from a first side 921 to a second side 923 of the stack 920. In one example, contacts may be formed on one or both sides 921, 923 of the first data I / O stripe 924 at its edge. The contacts may be connected to wire bonding as described in the examples above. In other examples, TSVs may be coupled to the first data I / O stripe 924 at sides 921, 923 or at other locations along the first data I / O stripe 924.

[0084] Figure 9B The second data I / O stripe 926 is further illustrated. In one example, the second data I / O stripe 926 is substantially the same as the first data I / O stripe 924. Figure 9B In one example, each data I / O stripe contains nine contacts for connection to wire bonds on either side. In the case of two data I / O stripes and two sides, each DRAM die in the stack 920 contains connections for 36 wire bonds or TSVs. In one example, all four dies in the stack 920 are driven by a single data path as described in the example above.

[0085] Figure 9B The command / address strip 930 is further illustrated. In the example shown, the command / address strip 930 includes 30 contacts for connection to wire bonding or TSV.

[0086] Figure 9C A block diagram of four DRAM die stacks 940 that may be included in a memory die stack according to any embodiment of this disclosure is shown. Figure 9CIn this stack 940, each die contains a memory region 942 with an array of memory cells. A single data I / O stripe 944 is shown extending from a first side 941 to a second side 943 of the stack 940. In one example, contacts may be formed on one or both sides 941, 943 of the data I / O stripe 944 at the edge of the data I / O stripe 944. The contacts may be connected to wire bonding as described in the examples above. In other examples, TSVs may be coupled to the data I / O stripe 944 at sides 941, 943 or at other locations along the first data I / O stripe 944.

[0087] exist Figure 9C In one example, a single data I / O stripe 944 contains 18 contacts for connection to wire bonds on either side. In the case of two sides, each DRAM die in the stack 940 contains connections for 36 wire bonds or TSVs. In one example, all four dies in the stack 940 are driven by a single data path as described in the example above.

[0088] Figure 9B The command / address strip 950 is further illustrated. In the example shown, the command / address strip 950 includes 30 contacts for connection to wire bonding or TSV.

[0089] The above-described contents include Figure 4-8B In the example memory device, one or more neuromorphic layers are coupled between one or more dies in a die stack and the host interface of an associated controller die. As described above, buffers better facilitate the operation of one or more neuromorphic layers. In each of the described configurations, several different locations for one or more neuromorphic layers are possible. Example locations include locations within the controller die, locations within the memory die stack, or other locations along the transport path between the memory die stack and the host interface of the associated controller die.

[0090] Figure 10 An example architecture of a neuromorphic layer 1000, which may be a layer in a neuromorphic device according to one embodiment, is shown. The neuromorphic layer 1000 includes an input line array 1002 and an output line array 1004. A plurality of logic weighting devices 1010 are coupled between the input line array 1002 and the output line array 1004.

[0091] Examples of the logic weighting device 1010 may include analog weighting devices, digital weighting devices, or hybrid analog and digital weighting devices. Examples of the logic weighting device 1010 include, but are not limited to, memristors, ReRAM, phase-change cells, multilayer memory devices, flash memory, etc. In one example, the logic weighting device 1010 is capable of accumulating logic weights representing a variable number of inputs from the input line array 1002. When the logic weighting device 1010 accumulates weights, they are configured to transfer their relative weights to the output line array 1004. After a learning or training process, the array of weighting devices 1010 is capable of recognizing patterns.

[0092] In one instance, several neuromorphic layers, such as layer 1000, are logically coupled together to process information and pass information from the first layer to subsequent layers. Weight patterns in individual units within each successive layer produce results processed in a neuromorphic manner. Examples of these results include, for example, image recognition or speech recognition used for autonomous driving.

[0093] Figure 11 An example of a hybrid digital and analog neuromorphic layer 1100, which may be a layer in a neuromorphic device according to one embodiment, is shown. An input line array 1104 and an output line array 1106 are shown. Several logic weighting devices 1110 are coupled between the input line array 1104 and the output line array 1106. Figure 11 In one example, several access devices 1112 and access lines 1102 for selectively activating the access devices 1112 are shown. In one example, the access device 1112 includes a transistor. The operation of the logic weighting device 1110 is similar to... Figure 10 Examples described herein. Instances of the logic weighting device 1110 may include analog weighting devices, digital weighting devices, or hybrid analog and digital weighting devices. Instances of the logic weighting device 1110 include, but are not limited to, memristors, ReRAM, phase-change cells, multilayer memory devices, flash memory, etc. When the logic weighting devices 1110 accumulate weights, they are configured to transfer their relative weights to the output line array 1106. After the learning or training process, the array of weighting devices 1110 is able to recognize patterns.

[0094] exist Figure 11In this example, several digital-to-analog converters (DACs) 1120 are shown at their junction with the input line array 1104. Several analog-to-digital converters (ADCs) 1122 are further shown at their junction with the output line array 1106. In this way, digital signals can reach the DACs 1120 and be converted into analog signals. The analog signals can be added to the weighting device 1110 depending on the input. The analog signals modified by the weighting device 1110 can then be passed down along the output line 1106 and converted back into weighted digital signals at the ADCs 1122.

[0095] Figure 12 An example of a DIMM memory 1200 is shown, including aspects of the neuromorphic devices and buffers as described above. The DIMM memory 1200 includes a substrate 1202 and one or more memory devices 1210. In one example, each memory device 1210 may include a memory die stack, a controller die, a buffer, and one or more neuromorphic layers, as described in the example above. The DIMM memory 1200 further includes a plurality of pins 1220, including CA / CS pins 1224 and DQ pins 1222 as described in the example configuration above. Using a commonly accepted industry format for DIMM slots may be advantageous. In this way, the advantages of localized processing using one or more neuromorphic layers can be applied to existing memory formats to improve processing power and speed.

[0096] Figure 13 A block diagram of an operational method according to an embodiment of the present invention is shown. In operation 1302, a neuromorphic device located in a memory device is trained. Examples of training include, but are not limited to, providing a first line of recognition using human input, such as basic image configuration components or audio components. The process of using introductory-level human training makes computer recognition more efficient and / or effective. One example of training includes an Internet verification procedure used to check whether a user is human. One example includes indicating which images contain fire hydrants or buses. The act of a human typing this input can be used to train the computer to more easily recognize objects, such as fire hydrants or buses.

[0097] In operation 1304, data is transferred from one or more dies in a die stack in the memory device to a neuromorphic device at a first data rate. In operation 1306, the data from the die stack is locally processed using the neuromorphic device, and in operation 1308, the processed data is transferred to a host device via a buffer located in the memory device, wherein the buffer is configured to provide a second data rate faster than the first data rate.

[0098] Figure 14A block diagram of an example machine (e.g., a host system) 1400, which may include one or more memory devices and / or systems as described above, is shown. In alternative embodiments, machine 1400 may be used as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, machine 1400 may be used as a server machine, a client machine, or both in a server-client network environment. In an example, machine 1400 may be used as a peer-to-peer (P2P) (or other distributed) network environment. Machine 1400 may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network appliance, IoT device, automotive system, or any machine capable of executing (sequentially or otherwise) instructions specifying actions to be taken by said machine. Furthermore, although only a single machine is shown, the term "machine" should also be considered as encompassing any collection of machines that individually or collectively execute a set of instructions (or more sets of instructions) to perform any of the methods discussed herein (e.g., cloud computing, Software as a Service (SaaS), other computer cluster configurations).

[0099] As described herein, an instance may comprise, or be operable through, logic, components, devices, packages, or mechanisms. A circuit system is an assembly (e.g., a collection) of circuits implemented in a tangible entity containing hardware (e.g., simple circuits, gates, logic, etc.). Circuit system members can be flexible over time and as the underlying hardware changes. A circuit system contains components that can perform a specified task individually or in combination during operation. In an instance, the hardware of the circuit system may be perpetually designed to perform a specific operation (e.g., hardwired). In an instance, the hardware of the circuit system may contain physically connected components (e.g., execution units, transistors, simple circuits, etc.) and computer-readable media that are physically modified (e.g., the magnetism, electricity, movable placement, etc. of unchanging aggregated particles) to encode instructions for a specific operation. When connecting physical components, the underlying electrical properties of the hardware structure change, for example, from an insulator to a conductor, or from a conductor to an insulator. Instructions enable participating hardware (e.g., execution units or loading mechanisms) to form portions of the circuit system components in the hardware via variable connections to perform a specific task during operation. Therefore, during device operation, the computer-readable medium is communicatively coupled to other components of the circuit system. In an example, any of the physical components can be used in more than one component of more than one circuit system. For instance, during operation, an execution unit can be used at one point in time in a first circuit of a first circuit system and reused at different times by a second circuit in the first circuit system or by a third circuit in the second circuit system.

[0100] Machine (e.g., computer system, host system, etc.) 1400 may include processing device 1402 (e.g., hardware processor, central processing unit (CPU), graphics processing unit (GPU), hardware processor core, or any combination thereof), main memory 1404 (e.g., read-only memory (ROM), dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static memory 1406 (e.g., static random access memory (SRAM), etc.), and storage system 1418. Some or all of the above components may communicate with each other via a communication interface (e.g., bus) 1430. In one example, main memory 1404 includes one or more memory devices as described in the examples above.

[0101] Processing device 1402 may represent one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or a combination of instruction sets. Processing device 1402 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1402 may be configured to execute instructions 1426 for performing the operations and steps discussed herein. Computer system 1400 may further include a network interface device 1408 communicating via network 1420.

[0102] Storage system 1418 may include machine-readable storage media (also referred to as computer-readable media) on which one or more instruction sets 1426 or software embodying any one or more methods or functions described herein are stored. Instructions 1426 may also reside wholly or at least partially in main memory 1404 or processing device 1402 during execution by computer system 1400, which also constitute machine-readable storage media.

[0103] The term "machine-readable storage medium" should be understood to include a single medium or multiple media storing one or more sets of instructions, or any medium capable of storing or encoding sets of instructions for machine execution and causing the machine to perform any one or more methods of this disclosure. Therefore, the term "machine-readable storage medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media. In examples, aggregated machine-readable media includes machine-readable media having multiple particles with invariant (e.g., rest) mass. Thus, aggregated machine-readable media are non-transitory propagating signals. Specific examples of aggregated machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0104] Machine 1400 may further include a display unit, an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device (e.g., a mouse). In an example, one or more of the display unit, input device, or UI navigation device may be a touchscreen display. The machine is a signal generating device (e.g., a speaker), or one or more sensors, such as a Global Positioning System (GPS) sensor, a compass, an accelerometer, or one or more other sensors. Machine 1400 may include an output controller, such as serial (e.g., Universal Serial Bus (USB)), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection, to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0105] Instructions 1426 (e.g., software, programs, operating systems (OS), etc.) or other data stored on storage system 1418 may be accessed by main memory 1404 for use by processing device 1402. Main memory 1404 (e.g., DRAM) is typically fast but volatile, and therefore belongs to a different type of storage device compared to storage system 1418 (e.g., SSD), which is designed for long-term storage, including long-term storage when in a "shutdown" condition. Instructions 1426 or data for use by the user or machine 1400 are typically loaded into main memory 1404 for use by processing device 1402. When main memory 1404 is full, virtual space from storage system 1418 may be allocated to supplement main memory 1404; however, because storage system 1418 devices are typically slower than main memory 1404, and write speeds are typically at least twice as slow as read speeds, the use of virtual memory can significantly degrade the user experience due to storage system latency (compared to main memory 1404, such as DRAM). Furthermore, using storage system 1418 for virtual memory can significantly shorten the usable lifespan of storage system 1418.

[0106] Instruction 1424 can further utilize any of a plurality of transport protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.) to transmit or receive on network 1420 via network interface device 1408 using a transport medium. Example communication networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), conventional telephone (POTS) networks, and wireless data networks (e.g., referred to as…). The Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards, known as The network interface device 1408 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connection to the network 1420. In an example, the network interface device 1408 may include multiple antennas for wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" should be considered as any intangible medium capable of storing, encoding, or transmitting instructions for execution by machine 1400 and containing digital or analog communication signals, or other intangible media used to facilitate communication of this software.

[0107] The detailed description above includes reference to the accompanying drawings, which form a part of the detailed description. The drawings illustrate, by means of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements other than those shown or described. However, the inventors also contemplate that only examples of those elements shown or described are provided herein. Furthermore, the inventors also contemplate examples (or aspects thereof) using any combination or arrangement of those elements shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0108] All publications, patents, and patent documents referenced in this document are incorporated herein by full reference as if individually cited. In the event of any inconsistency in usage between this document and those documents incorporated by reference, the usage in the incorporated references shall be considered supplementary to the usage in this document; in the case of irreconcilable inconsistencies, the usage in this document shall prevail.

[0109] In this document, as is common in patent documents, the term "a / an" is used to include one or more, regardless of any other instance or use of "at least one" or "one or more". In this document, unless otherwise stated, the term "or" is used to refer to non-exclusivity or to cause "A or B" to include "A but not B", "B but not A", and "A and B". In the appended claims, the terms "comprising" and "in which" are used as common equivalents to the corresponding terms "including" and "wherein". Furthermore, in the appended claims, the terms "comprising" and "including" are open-ended, meaning that a system, apparatus, article, or process that includes elements other than those listed in the claims following such terms is still considered to be within the scope of the claims. Additionally, in the appended claims, the terms "first", "second", and "third", etc., are used merely as labels and are not intended to impose numerical requirements on their objects.

[0110] In various instances, the components, controllers, processors, units, engines, or tables described herein may include, in particular, physical circuitry systems or firmware stored on a physical device. As used herein, "processor" means any type of computing circuitry, such as, but not limited to, microprocessors, microcontrollers, graphics processors, digital signal processors (DSPs), or any other type of processor or processing circuitry, including processors or groups of multi-core devices.

[0111] As used in this document, the term "horizontal" is defined as a plane parallel to a conventional plane or surface of the substrate, such as a plane or surface beneath a wafer or die, regardless of the actual orientation of the substrate at any given time. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. Prepositions such as "above," "above," and "below" are defined with respect to a conventional plane or surface on top of or exposed on the substrate, regardless of the substrate's orientation; and "above" is intended to indicate direct contact between one structure and another structure located "above" it (unless otherwise explicitly indicated); the terms "above" and "below" are intended to explicitly indicate the relative placement of structures (or layers, features, etc.), which explicitly includes—but is not limited to—direct contact between the indicated structures, unless specifically indicated as such. Similarly, the terms "on" and "below" are not limited to horizontal orientation, because if a structure is the outermost part of the construction under discussion at a given time, then this structure may be "on" the reference structure even if it extends vertically relative to the reference structure rather than in a horizontal orientation.

[0112] The terms “wafer” and “substrate” are used herein to generally refer to any structure on which an integrated circuit is formed, and also to such structures during the various stages of integrated circuit manufacturing. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of the various embodiments is defined only by the full scope of the appended claims together with their equivalents.

[0113] Various embodiments according to this disclosure and described herein include memories utilizing vertical structures of memory cells (e.g., NAND strings of memory cells). As used herein, directional adjectives relative to the surface of the substrate on which the memory cells are formed will be used (i.e., the vertical structure will be considered as extending away from the substrate surface, the bottom end of the vertical structure will be considered as the end closest to the substrate surface, and the top end of the vertical structure will be considered as the end furthest from the substrate surface).

[0114] As used herein, directional adjectives such as horizontal, vertical, orthogonal, parallel, and perpendicular may refer to relative orientation and, unless otherwise indicated, are not intended to require strict adherence to specific geometric properties. For example, as used herein, a vertical structure need not be precisely perpendicular to the surface of the substrate, but may instead be substantially perpendicular to the surface of the substrate and may form an acute angle with the surface of the substrate (e.g., between 60 and 120 degrees).

[0115] In some embodiments described herein, different doping configurations may be applied to the Selective Gate Source (SGS), Control Gate (CG), and Selective Gate Drain (SGD), each of which in this example may be formed of or at least comprise polysilicon, resulting in these layers (e.g., polysilicon, etc.) having different etch rates when exposed to an etch solution. For example, during the formation of a monomer pillar in a 3D semiconductor device, SGS and CG may form a depression, while SGD may retain less or no depression. These doping configurations can therefore achieve selective etching into different layers (e.g., SGS, CG, and SGD) in the 3D semiconductor device using an etch solution (e.g., tetramethylammonium hydroxide (TMCH)).

[0116] As used herein, operating a memory cell includes reading from, writing to, or erasing the memory cell. The operation of placing a memory cell in a predetermined state is referred to herein as “programming” and may include both writing to and erasing from the memory cell (i.e., the memory cell may be programmed into an erased state).

[0117] According to one or more embodiments of this disclosure, a memory controller (e.g., processor, controller, firmware, etc.) located inside or outside the memory device can determine (e.g., select, set, adjust, calculate, change, clear, transfer, adapt, derive, limit, utilize, modify, apply, etc.) a certain number of wear cycles or wear states (e.g., record wear cycles, count operations on the memory device when they occur, track the memory device operations that started them, evaluate memory device characteristics corresponding to wear states, etc.).

[0118] According to one or more embodiments of this disclosure, a memory access device may be configured to provide wear cycle information for each memory operation to the memory device. A memory device control circuitry (e.g., control logic) may be programmed to compensate for memory device performance variations corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0119] It should be understood that when an element is referred to as "on another element," "connected to another element," or "coupled to another element," it may be directly on, directly connected to, or coupled to the other element, or there may be intermediate elements. In contrast, when an element is referred to as "directly on another element," "directly connected to another element," or "directly coupled to another element," there are no intermediate elements or layers. If two elements are shown in the figures as connected by a line, then unless otherwise specified, the two elements may be coupled or directly coupled.

[0120] The methods described herein can be implemented, at least in part, by a machine or computer. Some examples may include computer-readable or machine-readable media encoded with instructions that can be used to configure an electronic device to perform the methods as described in the examples above. Implementations of such methods may include code, such as microcode, assembly language code, high-level language code, etc. Such code may contain computer-readable instructions for performing various methods. The code may form part of a computer program product. Additionally, the code may be tangibly stored, for example, during execution or at other times, on one or more volatile or non-volatile tangible computer-readable media. Examples of such tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical discs (e.g., optical discs and digital video discs), magnetic tape cassettes, memory cards or memory sticks, random access memory (RAM), read-only memory (ROM), etc.

[0121] To better illustrate the methods and apparatus disclosed herein, a non-limiting list of embodiments is provided herein:

[0122] Example 1 is a memory system. The memory system includes a controller die coupled to a substrate, the controller die including a buffer, the buffer including a host interface and a die stack interface, wherein the host interface includes at least one channel, and the die stack interface includes two or more sub-channels. The memory system includes a die stack supported by the substrate and coupled to the two or more sub-channels. The memory system includes control logic that reallocates connections for the at least one channel to at least two sub-channels; and one or more neuromorphic layers logically coupled between the one or more dies in the die stack and the host interface.

[0123] In Example 2, the object described in Example 1 is optionally configured such that the one or more neuromorphic layers are physically located within the controller die.

[0124] In Example 3, the object according to any one of Examples 1 to 2 is optionally configured such that the buffer is configured to control the data rate to the one or more neuromorphic layers.

[0125] In Example 4, the subject matter according to any one of Examples 1 to 3 is optionally configured to further include circuitry in the controller die, the circuitry being configured to operate the host interface at a first data rate and the die stack interface at a second data rate slower than the first data rate.

[0126] In Example 5, the object according to any one of Examples 1 to 4 is optionally configured such that the one or more neuromorphic layers comprise digital neuromorphic layers.

[0127] In Example 6, the object according to any one of Examples 1 to 5 is optionally configured such that the one or more neuromorphic layers include an analog multiply-accumulate (MAC) neuromorphic layer.

[0128] In Example 7, the subject matter according to any one of Examples 1 to 6 is optionally configured such that the one or more neuromorphic layers comprise both digital and analog portions.

[0129] In Example 8, the subject matter according to any one of Examples 1 to 7 is optionally configured such that the die stack contains DRAM dies.

[0130] In Example 9, the object according to any one of Examples 1 to 8 is optionally configured such that the one or more neuromorphic layers include phase transition units.

[0131] In Example 10, the object according to any one of Examples 1 to 9 is optionally configured such that the one or more neuromorphic layers include memristor units.

[0132] In Example 11, the object according to any one of Examples 1 to 10 is optionally configured such that the substrate is a motherboard.

[0133] In Example 12, the subject matter according to any one of Examples 1 to 11 is optionally configured such that the substrate is a dual in-line memory (DIMM) substrate.

[0134] In Example 13, the object according to any one of Examples 1 to 12 is optionally configured such that the substrate is an intermediate substrate coupled to the motherboard.

[0135] Example 14 is a memory system. The memory system includes a controller die coupled to a substrate, the controller die including a buffer, the buffer including a host interface and a die stack interface, wherein the host interface includes at least one channel, and the die stack interface includes two or more sub-channels. The memory system includes a die stack supported by the substrate and coupled to the two or more sub-channels. The memory system includes control logic that reallocates connections for the at least one channel to at least two sub-channels; and one or more neuromorphic layers logically coupled between the one or more dies in the die stack and the host interface; and logic in the controller die for programming one or more neuromorphic weights into the one or more neuromorphic layers.

[0136] In Example 15, the object described in Example 14 is optionally configured such that the one or more neuromorphic layers are physically located within the controller die.

[0137] In Example 16, the object according to any one of Examples 14 to 15 is optionally configured such that the buffer is configured to control the data rate to the one or more neuromorphic layers.

[0138] In Example 17, the subject matter according to any one of Examples 14 to 16 is optionally configured to further include circuitry in the controller die, the circuitry being configured to operate the host interface at a first data rate and the die stack interface at a second data rate slower than the first data rate.

[0139] In Example 18, the subject matter according to any one of Examples 14 to 17 is optionally configured such that the one or more neuromorphic layers comprise multiple layers in a single bare sheet.

[0140] In Example 19, the subject matter according to any one of Examples 14 to 18 is optionally configured such that the one or more neuromorphic layers comprise multiple layers in multiple dies.

[0141] In Example 20, the subject matter according to any one of Examples 14 to 19 is optionally configured such that the die stack supported by the substrate includes one or more wire bonding connections to the substrate.

[0142] In Example 21, the subject matter according to any one of Examples 14 to 20 is optionally configured such that the die stack supported by the substrate includes one or more through-silicon via (TSV) connections to the substrate.

[0143] In Example 22, the subject matter according to any one of Examples 14 to 21 is optionally configured such that the one or more neuromorphic layers comprise 30 to 100 digital neuromorphic layers.

[0144] In Example 23, the subject matter according to any one of Examples 14 to 22 is optionally configured such that a plurality of die stacks are contained on a dual in-line memory (DIMM) substrate.

[0145] In Example 24, the object according to any one of Examples 14 to 23 is optionally configured such that each of the plurality of die stacks is associated with a separate controller die.

[0146] Example 25 is a method. The method includes: training a neuromorphic device located in a memory device; transferring data from one or more dies in a die stack in a memory system to the neuromorphic device at a first data rate; locally processing the data from the die stack using the neuromorphic device; and transferring the processed data to a host device via a buffer located in the memory system, wherein the buffer is configured to provide a second data rate faster than the first data rate.

[0147] In Example 26, the object according to Example 25 is optionally configured such that transmitting data from one or more dies in a die stack of the memory system to the neuromorphic device comprises transmitting data from one or more dies to a neuromorphic device located within the die stack.

[0148] In Example 27, the subject matter according to any one of Examples 25 to 26 is optionally configured such that transmitting data from one or more dies in the die stack of the memory system to the neuromorphic device includes transmitting data from the one or more dies to a controller die that includes both the neuromorphic device and the buffer.

[0149] The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used by one of ordinary skill in the art upon review of the above description. An abstract is provided to conform to 37C.FR §1.72(b) to allow the reader to quickly determine the nature of the technical disclosure. It should be understood that the embodiments described are not intended to construe or limit the scope or meaning of the claims. Furthermore, in the above detailed description, various features may be grouped together to simplify this disclosure. This should not be construed as expecting that any unclaimed disclosed features are necessary for any claim. Rather, the subject matter of the invention may consist of fewer features than all of the particular disclosed embodiments. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim exists independently as a separate embodiment, and such embodiments are considered to be combined or arranged in various ways. The scope of the invention should be determined by reference to the appended claims and the full scope of the equivalents granted by such claims.

Claims

1. A memory system comprising: A controller die coupled to a substrate, the controller die including a buffer, the buffer including a host interface and a die stacking interface, wherein the host interface includes at least one channel and the die stacking interface includes two or more sub-channels; A stack of bare dies, supported by the substrate and coupled to the two or more sub-channels; The circuitry in the controller die is configured to operate the host interface at a first data rate and at a second data rate slower than the first data rate, operating the two or more sub-channels coupled to the die stack. Control logic that reallocates connections used for the at least one channel to at least two sub-channels; as well as One or more neuromorphic layers, which are logically coupled between one or more dies in the die stack and the host interface.

2. The memory system of claim 1, wherein the one or more neuromorphic layers are physically located within the controller die.

3. The memory system of claim 1, wherein the buffer is configured to control the data rate to the one or more neuromorphic layers.

4. The memory system of claim 1, wherein the one or more neuromorphic layers comprise digital neuromorphic layers.

5. The memory system of claim 1, wherein the one or more neuromorphic layers comprise an analog multiply-accumulate (MAC) neuromorphic layer.

6. The memory system of claim 1, wherein the one or more neuromorphic layers comprise both digital and analog portions.

7. The memory system of claim 1, wherein the die stack comprises DRAM dies.

8. The memory system of claim 1, wherein the one or more neuromorphic layers comprise phase transition units.

9. The memory system of claim 1, wherein the one or more neuromorphic layers comprise memristor units.

10. The memory system of claim 1, wherein the substrate is a motherboard.

11. The memory system of claim 1, wherein the substrate is a dual in-line memory (DIMM) substrate.

12. The memory system of claim 1, wherein the substrate is an intermediate substrate coupled to the motherboard.

13. A memory system comprising: A controller die coupled to a substrate, the controller die including a buffer, the buffer including a host interface and a die stacking interface, wherein the host interface includes at least one channel and the die stacking interface includes two or more sub-channels; A stack of bare dies, supported by the substrate and coupled to the two or more sub-channels; The circuitry in the controller die is configured to operate the host interface at a first data rate and at a second data rate slower than the first data rate, operating the two or more sub-channels coupled to the die stack. Control logic that reallocates connections used for the at least one channel to at least two sub-channels; as well as One or more neuromorphic layers, logically coupled between one or more dies in the die stack and the host interface; and The logic in the controller die is used to program one or more neuromorphic weights into the one or more neuromorphic layers.

14. The memory system of claim 13, wherein the one or more neuromorphic layers are physically located within the controller die.

15. The memory system of claim 13, wherein the buffer is configured to control the data rate to the one or more neuromorphic layers.

16. The memory system of claim 13, wherein the one or more neuromorphic layers comprise multiple layers in a single die.

17. The memory system of claim 13, wherein the one or more neuromorphic layers comprise multiple layers in multiple dies.

18. The memory system of claim 13, wherein the die stack supported by the substrate includes one or more wire bonding connections to the substrate.

19. The memory system of claim 13, wherein the die stack supported by the substrate includes one or more through-silicon via (TSV) connections to the substrate.

20. The memory system of claim 13, wherein the one or more neuromorphic layers comprise 30 to 100 neuromorphic layers.

21. The memory system of claim 13, wherein a plurality of dies are stacked on a dual in-line memory (DIMM) substrate.

22. The memory system of claim 21, wherein each of the plurality of die stacks is associated with a separate controller die.

23. A method comprising: Training a neuromorphic device located in a memory device; Data is transmitted from one or more dies in a die stack in the memory system to the neuromorphic device at a first data rate; The data from the stack of bare dies is processed locally using the neuromorphic device. Processed data is transmitted to a host device via a buffer located in the memory system, wherein the buffer is configured to provide a second data rate that is faster than the first data rate.

24. The method of claim 23, wherein transmitting data from one or more dies in a die stack of the memory system to the neuromorphic device comprises transmitting data from one or more dies to a neuromorphic device located within the die stack.

25. The method of claim 23, wherein transmitting data from one or more dies in a die stack of the memory system to the neuromorphic device comprises transmitting data from the one or more dies to a controller die comprising both the neuromorphic device and the buffer.

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