Fuzzy retrieval circuit

Abstract

The need to search for "which of the data stored inside the storage circuit is most similar to the input information from the outside" is increasing, and the storage circuit itself has high hopes for such memory technology, which is considered to be an indispensable technology for computers to respond to information from the outside more flexibly. In order to realize such technology, the storage circuit needs to have a built-in function to measure the similarity between the stored data and the input data from the outside. The present invention inputs the input data into the memory matrix in the form of a "time series of pulse signals", so that the memory matrix of the existing storage circuit functions as a data conversion circuit for calculating the inner product distance between the stored data and the input data. In addition, the output of the circuit that measures the inner product of the mixed stored data and input data in real time is used to output the position of the stored data with the largest inner product value to the outside, thereby forming a fuzzy retrieval circuit.

Description

Technical Field

[0001] The present invention relates to a circuit architecture, which determines which of the internal information stored in an internally mounted memory circuit is the best content based on external information, performs fuzzy retrieval on the entire memory circuit, and makes an autonomous response based on the determination. Background Art

[0002] Reference Figure 1 to Figure 3 The outline of the existing content-addressable memory technology is described. The existing content-addressable memory technology is characterized in that in addition to the operations performed by a general memory such as the read operation and the write operation to the cells in the cell matrix, a search operation is also performed. As a content-addressable memory cell, such as Figure 1 As shown, various methods are known.

[0003] The storage circuit (or storage element) of the content addressable memory unit stores storage data to be searched. Input data that becomes a search key during search is transmitted to the content addressable memory unit via a search line (or a search line and bit line).

[0004] The content-addressable memory cells ((A) to (D)) using SRAM store storage data in the FF (Flip-Flop) serving as a storage circuit, the content-addressable memory cells (E) using DRAM store storage data in the parasitic capacitance of a node in a floating state, and the content-addressable memory cells (F) using resistance variable elements store storage data in resistance variable elements.

[0005] An element is provided which conducts current from the match line in any case according to the stored data and the potential input from the search line.

[0006] The content-addressable memory cell ((A)~(D)) using SRAM controls the conduction or cutoff of two series-connected transistor columns according to the storage data stored in the FF (Flip-Flop) serving as the storage circuit and the potential input from the search line. When turned on, current is conducted from the matching line.

[0007] A content addressable memory cell (E) using DRAM conducts current from a match line according to storage data stored in a parasitic capacitance of a node in a floating state and a potential input from a search line.

[0008] A content-addressable memory cell (F) using a resistance change element conducts current from a match line according to storage data stored in the resistance change element and a potential input from a search line.

[0009] In the case of a ternary content addressable memory cell using an SRAM, as in (C) and (D), a bit line and a search line are often used for writing, reading, and searching operations.

[0010] Generally speaking, a binary type content addressable memory cell has one storage circuit (or storage element), and a ternary type content addressable memory cell has two storage circuits (or storage elements). The reason why there are many ternary type storage circuits (or storage elements) is that as data, not only a value of 1 or a value of 0 is stored, but also a mask state called ignore (Don't Care) is stored.

[0011] Hereinafter, a conventional example will be described based on a case where a ternary content addressable memory cell ((C) or (D)) using an SRAM is used.

[0012] Figure 2 This is a block diagram of a ternary type content addressable memory (CAM) based on SRAM, in which cells are arranged in a matrix of M rows×N columns. Figure 2 Only the four corners of the M-row×N-column matrix are shown.

[0013] During the search operation, the search keyword (input data) input from the outside is transmitted to each row of the content-addressable memory cells in the cell matrix via the search line. In each content-addressable memory cell, when the stored data of the FF of the content-addressable memory cell and the input signal transmitted by the search line become inverted, it is interpreted as the two data "consistent (or matching)". The stored data and the input data "consistent (or matching)" when they are inverted like High and Low or Low and High.

[0014] There are two transistors connected in series in the content-addressable memory cell, and the storage data and input data of the FF are supplied as potentials in the gate electrodes of the two transistors. When indicating "consistency (or match)", any one of the two transistors connected in series becomes cut off and does not conduct current to the matching line.

[0015] When the stored data is "inconsistent" with the input data, the same-phase input is applied to the two gate electrodes of the two series-connected transistors in the content-addressable memory cell, such as High and High or Low and Low. However, since there are two groups of two series-connected transistors in the content-addressable memory cell, any group can become conductive, and therefore current can be conducted to the matching line through any group.

[0016] Although two sets of two transistors connected in series are sometimes considered to have an exclusive-NOR logic in each cell, they do not conduct current when they are “consistent” and conduct current when they are “inconsistent”.

[0017] One bit of a content addressable memory cell includes two FFs as storage circuits, so whether in a read operation or a write operation, the paired search line and bit line need to perform at least two cycles of operation. Both the read data and the write data are 2N bits.

[0018] Hereinafter, a portion of a row consisting of N bits of a content addressable memory cell to which a corresponding match determination circuit is added is referred to as a word circuit. A word circuit includes one match line and two word lines.

[0019] Figure 3 Shown by N Figure 1 (C) shows the structure and operation of the word circuit composed of the ternary type content addressable memory cell based on SRAM. The labels of cell [3] to cell [N-2] are omitted. In addition, in this figure, only the search action is explained, so the display of the access transistor (transistor that conducts current between the bit line and the storage circuit) used when performing the reading action and the writing action on the storage circuit (FF) in the cell is also omitted.

[0020] In each cell, a pair of left and right transistors connected in series do not conduct current when the stored data and the input data are “consistent”, and conduct current when they are “inconsistent”.

[0021] The match line sums the currents conducted by each cell in the word circuit and sends the sum to the match determination circuit.

[0022] The match determination circuit generally includes a transistor for setting the voltage of the match line to a RESET potential before match determination and a control signal (RESET_bar) for this purpose.

[0023] When there is no mismatch bit in the word, no current is conducted by the content-addressable memory cell in the match line, and there is no potential change, so the potential level (RESET potential) before the input data is transmitted is maintained.

[0024] When there is a single mismatch bit within a word, a current that is conducted by the content-addressable memory cell is generated in the match line, causing the potential of the match line to change.

[0025] In order to detect the potential change indicating the mismatch, an intermediate potential between the potential when no potential change occurs in the matching line and the potential when the minimum current is conducted is generated by a threshold potential generating circuit and supplied to the matching determination circuit as a threshold potential. (For example, refer to Patent Document 1)

[0026] like Figure 3 As shown in (B), in the prior art, if the input data and the stored data are in opposite phases, they are consistent, and when all cells are consistent, no current is conducted, and no potential change occurs in the match line. On the contrary, if the input data and the stored data are in phase, they are inconsistent, and even when only one bit is inconsistent, current is conducted, and a potential change occurs in the match line.

[0027] like Figure 1 As shown, the output of the match determination circuit is sent to the address encoder circuit, and the physical address of the match determination circuit that detected the match is generated and output as a "match address output".

[0028] Such content-addressable memories are used for packet data processing within network routers, memory management in parallel computers, etc.

[0029] The existing content addressable memory technology can be mathematically explained as the case where the Hamming distance between the inversion of the input data and the stored data is 0 is regarded as a coincidence.

[0030] Background Art Literature

[0031] Patent Literature

[0032] Patent Document 1: Japanese Patent No. 5480986

[0033] Patent Document 2: Japanese Patent No. 5893465

[0034] Patent Document 3: Japanese Patent No. 5800422

[0035] Patent Document 4: Japanese Patent Application No. 2019-517138

[0036] Patent Document 5: Japanese Patent Application No. 2014-504401

[0037] Patent Document 6: Japanese Patent Application Laid-Open No. 2020-017281

[0038] Patent Document 7: Japanese Patent Application Laid-Open No. 2019-185784

[0039] Non-patent literature

[0040] Non-patent document 1: K.Pagiamtzis and A.Sheikholeslami, "Content-addressablememory(CAM)circuits and architectures:A tutorial and survey," IEEEJ.Solid-State Circuits, vol.41, no.3, Mar.2006, pp.712727.

[0041] Non-patent document 2: Akiko Mochizuki and Takashi Omori, "PATON: A dynamic neural network model expressing contextual dependencies", Journal of the Japanese Society of Neural Networks, Vol. 3, No. 3 (1996), 81-89 Summary of the invention

[0042] Problem that the invention aims to solve

[0043] In recognition applications such as handwritten text recognition, it is often impossible to find consistency when the Hamming distance is 0. In this case, some inconsistencies are allowed, and it is required to determine words that can be regarded as "consistent to a certain extent" and detect the corresponding words.

[0044] By using a plurality of rows (words) with the "Don't Care" setting changed, "partial coincidence" can be detected even by an existing ternary content addressable memory (Ternary CAM), but a plurality of rows (words) is required, which is not cost-effective.

[0045] The need to consider something as “consistent to a certain extent” and to make judgments and detections also exists when constructing a neural network circuit that mimics the operations of neurons.

[0046] In neural network circuits, there is the following problem: input data and reference data are generally considered as multidimensional vectors, and the consistency is measured based on the inner product between the two vectors. However, the maximum value of the inner product is not a fixed value and may be different for each reference data. Therefore, the existing ternary content addressable memory (Ternary CAM) cannot cope with this problem.

[0047] In the prior art, when input data and stored data are considered "inconsistent" for each content-addressable unit, current is conducted to the matching line. However, if the data registered in the content-addressable memory becomes larger, then at least in word units, the "inconsistency" cases account for the vast majority compared to the "consistency" cases, so there is a problem in power consumption.

[0048] In applications such as handwritten character recognition using the above-mentioned neural network circuit, if the word length becomes longer even as individual bits, the number of bits having a value of 1 tends to decrease compared to the number of bits having a value of 0.

[0049] Therefore, a structure is required that conducts current between a content-addressable memory cell and a match line when there is "coincidence" rather than "inconsistency" and detects "certain consistency" without requiring a plurality of rows (words).

[0050] While the process of “finding storage data that is consistent with input data from a large amount of storage data stored on an integrated circuit or in a storage device” is called “retrieval”, the process of “finding storage data that is consistent with input data to a certain extent” is sometimes called “fuzzy retrieval”.

[0051] The present invention is such a "circuit architecture for implementing fuzzy retrieval", and relates to a data processing circuit that uses the circuit architecture to determine which of the internally stored information is the best content or the best response program based on external information, and responds and acts based on the determination.

[0052] Means of solving the problem

[0053] When "determining which of the internally stored information is the best content, data or best response program based on external information", it is necessary to concretize a circuit component that realizes the function of accurately measuring the similarity between the inconsistent "external information" and "information stored internally".

[0054] In the present invention, if Figure 6 As shown, in each activation line (90[0]~[m-1]) of a matrix circuit having a memory cell (10) for storing data, a group input of an input signal weighted by the number of pulse signals in a unit time is input, and the number of pulse signals conducted to each activation line according to the data of the memory cell (10) is totaled by a detection line (70[0]~[k-1]), and counted by a sensing circuit (101) and a counting circuit (207) connected to the detection line.

[0055] In a unit time, since the number of pulse signals counted by the counting circuit (207) approximates the inner product value between the input information (90) and the storage data of the memory unit (10), it is assumed that the "similarity" is measured, and the circuit that performs such an action is set as a main component based on the "consistency judgment circuit".

[0056] In determining the "similarity", a determination circuit (290) compares the expected number of pulses stored in the "second storage circuit (200)" with the number of pulses counted by a counting circuit (207). When the measured number of pulses exceeds the value of the "second storage circuit", a "signal indicating high similarity" is output from an output terminal (260).

[0057] And, if Figure 6 As shown, based on the "matching degree determination circuit", a "fuzzy search circuit" is constructed to evaluate and search for the similarity between each "information stored in the interior" and the "input signal from the exterior". Since it is generally believed that the "signal indicating high similarity" is outputted earlier from the output terminal (260) when the similarity is high, the "matching degree determination circuit" that outputs the "signal indicating high similarity" earliest is regarded as the "most consistent".

[0058] Furthermore, based on the function of "fuzzy search", a circuit is constructed by using "fuzzy search circuit" as a basic circuit to construct an "autonomous response circuit that determines which of the information stored in the internal part is the best content or the best response program based on external information, and starts a subroutine to respond based on the result.

[0059] Fig.25 The basic structure of the "autonomous response circuit (801)" of the present invention is shown. The "autonomous response circuit" adds a "fuzzy search circuit (701)", a "memory circuit (735)" and a "data compression circuit (745, 755)" to the usual "data processing circuit (725)", and "for input information from external information, it determines which of the information stored inside is the best content or the best response program, and starts and responds to the program according to the result."

[0060] Effects of the Invention

[0061] This invention is a breakthrough in the development of "electronic circuits that are most suitable for fuzzy retrieval". The technology of "quantifying the definition of similarity and inferring the content that is most similar to the input information from the outside from the registered information" is a necessary technology for processing that relies on similarity to retrieve fuzzy but possible information and make correct judgments probabilistically, and it will have a great impact on future data processing hardware.

[0062] The "first storage circuit" appearing in the figure of the embodiment of the present invention classifies various situations currently recognized, and "stimulates" the most similar data in the registered data in descending order of similarity by sending an "activation signal" as an input signal from the outside to the memory cell array. Based on this "stimulation" pattern, a response program is started.

[0063] This technology can be expected to be applied to devices that can autonomously recognize situations and perform responsive actions, similar to the human brain. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 is an example of an existing content-addressable memory cell.

[0065] Figure 2 It is an existing content addressable memory circuit.

[0066] Figure 3 It is a word circuit of an existing content-addressable memory.

[0067] FIG. 4 is a diagram showing a configuration example of a read circuit.

[0068] FIG. 5 is a diagram showing a first embodiment of the present invention.

[0069] Figure 6 It is a diagram of a second embodiment of the present invention.

[0070] Figure 7 It is a diagram of a third embodiment of the present invention.

[0071] Figure 8 It is a diagram of a fourth embodiment of the present invention.

[0072] Fig. 9 It is a diagram of a fifth embodiment of the present invention.

[0073] Fig.10 It is a diagram of a sixth embodiment of the present invention.

[0074] Fig.11 It is a diagram of a seventh embodiment of the present invention.

[0075] Fig.12 It is a diagram of an eighth embodiment of the present invention.

[0076] Fig.13 It is a diagram of a ninth embodiment of the present invention.

[0077] Fig.14 It is a diagram of the tenth embodiment of the present invention.

[0078] Fig.15 It is a diagram of the eleventh embodiment of the present invention.

[0079] Fig.16 This is a configuration example of a counting circuit using a shift register circuit.

[0080] Fig.17 This is an example of the structure of a shift register and a determination circuit.

[0081] Fig.18This is a configuration example of a second storage circuit.

[0082] Fig.19 This is a configuration example of a counting circuit using a counter circuit.

[0083] Fig. 20 This is a configuration example of a counter circuit.

[0084] Fig.21 This is an example of the configuration of a determination threshold storage circuit when a counter circuit is used.

[0085] FIG. 22 is a conceptual diagram of a fuzzy search circuit that outputs time-series information.

[0086] Fig.23 This is the description of the fuzzy retrieval circuit generating a time series signal Figure 1 .

[0087] Fig.24 This is the description of the fuzzy retrieval circuit generating a time series signal Figure 2 .

[0088] Fig.25 It is a diagram of a twelfth embodiment of the present invention.

[0089] Fig.26 It is a diagram of a thirteenth embodiment of the present invention.

[0090] FIG27 is an abstract model of a complex fuzzy retrieval circuit.

[0091] Fig.28 It is a diagram of a fourteenth embodiment of the present invention.

[0092] Figure 29 shows the connection between the fuzzy retrieval circuit and the maintenance bus.

[0093] Fig.30 It is a diagram of a fifteenth embodiment of the present invention.

[0094] Simple description of symbols

[0095] 1: Consistency determination circuit #1

[0096] 2: Consistency determination circuit #2

[0097] 3: Consistency determination circuit #3

[0098] 4: Consistency determination circuit #4

[0099] 5: Consistency determination circuit #5

[0100] 6: Consistency determination circuit #6

[0101] 11: Fuzzy search circuit #1

[0102] 12: Fuzzy search circuit #2

[0103] 13: Fuzzy search circuit #3

[0104] 14: Fuzzy search circuit #4

[0105] 15: Fuzzy retrieval circuit #5

[0106] 16: Fuzzy search circuit #6

[0107] 17: Fuzzy retrieval circuit #7

[0108] 10: Content-addressable memory unit

[0109] 20: Memory unit

[0110] 30: Intersection unit

[0111] 40: First storage circuit

[0112] 42: Fifth storage circuit

[0113] 45: The third storage circuit

[0114] 46: Output data storage circuit

[0115] 47: Fourth storage circuit

[0116] 48: Word line selection circuit of the fourth storage circuit

[0117] 49: Reading circuit of the fourth storage circuit

[0118] 50: Detection unit circuit

[0119] 55: Unit storage circuit

[0120] 61: First test line

[0121] 62: Second test line

[0122] 70: Detection line

[0123] 71: Second test line

[0124] 80: Input line

[0125] 81: Second input line

[0126] 85: External activation signal sent to the activation line driver circuit

[0127] 86: Information on the number of activation pulses sent to the activation line signal generation circuit

[0128] 87: Activation control signal sent to the activation signal control circuit

[0129] 90: Activation signal input line

[0130] 91: Second activation signal input line

[0131] 99: Determination result output

[0132] 101: Detection line current reading circuit

[0133] 102: Second detection line current reading circuit

[0134] 111: First threshold information generator

[0135] 112: Threshold bias 1

[0136] 113: Third threshold information generator

[0137] 114: Threshold bias 3

[0138] 115: Bias voltage

[0139] 116: Timer Circuit

[0140] 117: Fourth control circuit

[0141] 118: Third control circuit

[0142] 119: Second control circuit

[0143] 120: First control circuit

[0144] 151: Sequence selection indication signal

[0145] 152: Sequence selection control signal

[0146] 153: Control signal input from the outside

[0147] 155: Activate line drive circuit

[0148] 156: Activation line signal generation circuit

[0149] 157: Activate the number of control circuits

[0150] 158: Activate the number of control circuits B

[0151] 200: Second storage circuit

[0152] 201: Count input

[0153] 202: Shift register

[0154] 203: Shift register control circuit

[0155] 204: Unit circuit of shift register

[0156] 206: Second counting circuit

[0157] 207: Counting circuit

[0158] 208: Counting circuit pre-stage

[0159] 209: Counting circuit backstage

[0160] 210: Second read / write signal (D2)

[0161] 211: IO circuit of the second storage circuit

[0162] 212: Control input to the IO circuit of the second storage circuit 260: Determination result output

[0163] 270: Output of the data storage circuit

[0164] 288: Read control signal

[0165] 289: Write control signal

[0166] 290: Decision circuit

[0167] 291: Shift-Forward at Odd Cycle

[0168] 292: Shift-Forward at Even Cycle

[0169] 293:Shift-Reversely at Odd Cycle

[0170] 294:Shift-Reversely at Even Cycle

[0171] 305: Threshold Information Memory Access Global

[0172] 306: Shift Register Access Global

[0173] 307: Reset Content Global

[0174] 308: Write TIM to SR Global

[0175] 309: Write SR To TIM Global

[0176] 404: Read Write & Reset Control Circuit (Read Write & Reset)

[0177] 405: Write TIM to SR Local

[0178] 407: Reset Content Local

[0179] 408: Shift Register Access Local

[0180] 409: Threshold Information Memory Access Local

[0181] 506: Write SR To TIM Local

[0182] 510: Integrated flash signal

[0183] 521: Control signal of the fourth storage circuit

[0184] 522: Fourth write signal

[0185] 523: Fourth read signal

[0186] 530: Excitation unit

[0187] 531: Vertical detection line

[0188] 532: Vertical direction detection line reading circuit

[0189] 533: Comprehensive excitation signal

[0190] 534: Vertical output detection circuit

[0191] 535: Pulse generating circuit

[0192] 540: Counter control circuit

[0193] 543: Determination circuit B

[0194] 560: Counter Circuit

[0195] 570: Reading and writing circuit of the second storage circuit

[0196] 571: Input and output IO circuit of the fourth storage

[0197] 572: Control signal from outside the fourth storage circuit

[0198] 573: Write signal from the outside of the fourth storage circuit

[0199] 574: external read signal sent to the fourth storage circuit

[0200] 575: Fourth storage circuit

[0201] 580: Output of fuzzy search circuit #8

[0202] 581: Second write signal

[0203] 582: Second read signal

[0204] 585: Flag output signal

[0205] 590: Address output

[0206] 591: Address encoder circuit

[0207] 592: Address encoder unit circuit

[0208] 593: Address output circuit

[0209] 598: Forward shift

[0210] 599: Reverse shift

[0211] 604: Read Write & Reset control circuit B

[0212] 610: Second storage circuit in counter mode

[0213] 690: In-word peripheral circuits

[0214] 701: Fuzzy retrieval circuit A

[0215] 702: Fuzzy retrieval circuit B

[0216] 703: Fuzzy retrieval circuit C

[0217] 704: Synthetic Circuits

[0218] 710: Input data of input signal conversion circuit

[0219] 715: Input signal conversion circuit

[0220] 720: Input signal

[0221] 725: Data processing circuit

[0222] 735: Memory circuit A

[0223] 736: Memory circuit B

[0224] 737: Memory Circuit C

[0225] 738: Output of memory circuit B

[0226] 739: Output of memory circuit C

[0227] 740: Output data of the data processing circuit (725)

[0228] 745: First data compression circuit

[0229] 750: Status signal output of the data processing circuit (725)

[0230] 755: Second data compression circuit

[0231] 760: Response output

[0232] 765: Output of memory circuit A

[0233] 770: Differential corresponding control signal

[0234] 775: Output of input signal conversion circuit (715)

[0235] 780: Response signal 2

[0236] 785: Control signal

[0237] 795: Output of fuzzy retrieval circuit B

[0238] 801: Autonomous Response Circuit #1

[0239] 802: Autonomous Response Circuit #2

[0240] 803: Autonomous Response Circuit #3

[0241] 811: Address signal

[0242] 812: Word selection circuit

[0243] 813: Blank control bit

[0244] 821: Read and write signal [system A]

[0245] 822: Read and write signal [system B]

[0246] 826: Read and Write Circuit [System A]

[0247] 827: Read and Write Circuits [System B]

[0248] 831: Read and write signal [system FB]

[0249] 836: Read and write circuit [system FB]

[0250] 841: Read and write signal of the fourth storage circuit

[0251] 851: Address line

[0252] 852: Control signal line

[0253] 853: Data Bus

[0254] 861: Fuzzy retrieval input signal [system A]

[0255] 862: Fuzzy retrieval input signal [system B]

[0256] 863: Fuzzy search result response output bus

[0257] 871: CPU

[0258] 872: Backup memory

[0259] 873: Data Processing Circuit

[0260] 880: Extension of fuzzy retrieval circuit: 880

[0261] 881: CPU, backup memory, synthesis circuit, IO circuit

[0262] 882: Register

[0263] 883: FIFO

[0264] 888: Fuzzy retrieval circuit + fourth storage circuit

[0265] 891: Fuzzy Retrieval Bus

[0266] 892: Maintenance bus DETAILED DESCRIPTION

[0267] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0268] In the description, as long as the space allows, reference numerals are indicated in parentheses () or between colons ":" at the end of the names of the circuit elements. The numerals in the reference numerals in the description correspond to those in the drawings.

[0269] In the case of a circuit element that emphasizes the existence of multiple components, basically, the number of alphanumeric characters or a mathematical formula enclosed in brackets [ ] is marked in the place of the name of the circuit element or the figure mark representing the circuit element, and this serves as a note (サヒックス) to indicate the number or number of circuit elements.

[0270] In order to avoid unclear boundaries between the names of circuit components and the description content, the names of circuit components in the description content are enclosed in quotation marks "".

[0271] However, when the drawings are too complicated when the number of constituent elements is expressed in general terms, the number of constituent elements that exist is limited, for example, it is assumed to be three and illustrated in the drawings, and it is also explained in the specification. When it is clear that the number of constituent elements or the number of lines is plural, the number of constituent elements or the number of lines is omitted by the number of alphanumeric characters enclosed in brackets [], mathematical formulas, etc.

[0272] In the descriptions related to the memory circuit, the circuit blocks related to the conventionally known read circuit, write circuit, power supply circuit, etc., which are independent of the present invention, or the signal lines associated therewith are omitted from the description, expression, and description. Therefore, in many descriptions, the content-addressable memory cells and the bit lines and word lines connected to the memory cells are not described. The structures and functions of these circuits and wirings are also based on the application of the typical and modified prior art of the conventionally known content-addressable memory and memory when the present invention is applied.

[0273] On the contrary, by adding circuits other than the memory matrix of the embodiment of the present invention to a conventionally known memory circuit, the functions of "matching degree determination" and "fuzzy search" are added to the existing memory circuit.

[0274] In the description content and illustrations, the expression "fuzzy search" is often used, for which the appropriate term has not yet been established. This expression means inputting input data as an input signal and "searching for stored data with a smaller distance based on a certain definition" from the stored data. It expresses the search for an object equivalent to what is said in everyday language as "high consistency" or "high similarity".

[0275] In technologies related to content-addressable memory circuits, the terms “retrieval”, “search”, and “Search” are often used, but these are terms indicating “strict consistency” and have different meanings from the “fuzzy consistency” in the present invention.

[0276] When processing digital signals, the storage value of the storage circuit and the level of the signal line are sometimes expressed as value 1, value 0, High Level, and Low Level. However, there are differences in the polarity of the signal and the potential level of the digital signal, and value 1 does not necessarily mean High Level.

[0277] Unless otherwise specified, modifications with different polarities are always included in the technology in the embodiments.

[0278] Variations of different internal configurations and arrangements of the content-addressable memory cells, memory cells, sense amplifiers, storage circuits, write circuits, read circuits, control circuits, and the like may also be expressed as the same embodiments.

[0279] In the description and the explanatory drawings, the terms “signal” and “data” may have different meanings such as physical layer information and logical layer information, but are basically used with the same meaning.

[0280] In any embodiment of the present invention, the "memory cell (10)" used is a "memory cell having the function of controlling whether to conduct current to a detection line or a bit line or not based on data stored therein", but such a function is generally common to known memory cells, and the present invention does not select the form or method of the memory cell.

[0281] In any embodiment of the present invention, a unit of a circuit in which a storage circuit expresses a binary number is referred to as a "unit storage circuit (55)". The "unit storage circuit (55)" is composed of one or more memory cells (10). Each memory cell (10) in the "unit storage circuit (55)" shares an "activation signal input line (90)" and transmits the conduction current generated in response to the signal from the "activation signal input line (90)" to different detection lines (70).

[0282] In the illustration of any embodiment of the present invention, other variants are represented by using any example using memory cell technology.

[0283] In describing the embodiments of the present invention, input signals to the consistency determination circuit, the fuzzy search circuit, and the autonomous response circuit are often "signal sequences in which the time series of applied pulse signals each have a certain meaning as data."

[0284] For example, the data transmitted in the group of m "activation signal input lines", namely "90[0:m-1]", basically has a time series meaning. The signal value at a certain time (t=t0) is only data and does not have a meaning as data.

[0285] The data include the following parameters of the pulse signal during the lapse of a predetermined time.

[0286] The density of pulse signals per “specified time”

[0287] Timing of switching the density of pulse signals from sparse to dense

[0288] Timing of switching the density of pulse signals from dense to sparse

[0289] These three types of information are used to express the numerical value at a certain timing.

[0290] If the "prescribed time" as the observation period is too short, the density of the pulse signal cannot be measured, and therefore the timing of the density change of the pulse signal cannot be understood. On the other hand, if the "prescribed time" as the observation period is too long, the density of the pulse signal may be averaged.

[0291] The “predetermined time” can depend on the “width of the pulse signal”, but both the “predetermined time” and the “width of the pulse signal” are parameters that depend on the application.

[0292] Hereinafter, an appropriate “predetermined time” will be referred to as a “unit time”.

[0293] Regarding the “width of the pulse signal”, it is required to be a “width” that is difficult to be superimposed on “pulse signals” from other signal lines. However, this also depends largely on the manufacturing technology of the mounting circuit, so there is no special definition.

[0294] Example

[0295] Matching degree determination circuit #1 according to the first embodiment of the present invention

[0296] 5 and Figure 6 , the “matching degree determination circuit #1” of the “first embodiment” of the present invention and the “matching degree determination circuit #2” of the “second embodiment” of the present invention are described.

[0297] Figure 5A This is a block diagram conceptually showing the structure of the consistency determination circuit #1.

[0298] exist Figure 5B In FIG. 1 , only the input and output of these consistency determination circuits are illustrated.

[0299] Figure 6 This is a block diagram conceptually showing the structure of the consistency determination circuit #2.

[0300] For the "consistency determination circuit #1" of the first embodiment of the present invention, since there is a special case in which the number of rows (m) of the memory cell matrix of the "consistency determination circuit #2" of the second embodiment is 1 and the value of the "preset weighting coefficient" is "1", first, the following will be Figure 6 The “Consistency determination circuit #2 of the second embodiment” is described below.

[0301] The consistency determination circuit #2 includes a first storage circuit (40) formed of a memory cell matrix, a counting circuit (207), a second storage circuit (200), and a determination circuit (290).

[0302] The circuits for controlling the reading and writing of the first storage circuit (40) and the second storage circuit (200), and the bit lines and word lines used at this time have a generally known structure, and therefore are not described in this figure to avoid complicating the figure. On the contrary, by adding circuits other than the memory matrix of the embodiment of the present invention to the conventionally known memory circuit, the functions of "consistency determination" and "fuzzy search" are added to the memory circuit.

[0303] The input signal applied to the "activation signal input line (90)" of the consistency determination circuit #2 is a signal sequence in which the time series of the pulse signals applied to each "activation signal input line (90)" each have a certain meaning as data. That is, the data transmitted in the group of m "activation signal input lines", i.e., "90[0:m-1]", basically have a meaning in terms of time series, and the signal value at a certain time (t=t0) does not have a meaning as data, but has a time series of pulse signals during the passage of a unit time.

[0304] The density of pulse signals per “unit time”

[0305] Timing of switching the density of pulse signals from sparse to dense

[0306] Timing of switching the density of pulse signals from dense to sparse

[0307] These three types of information are used to express a signal sequence of numerical values ​​at a certain timing.

[0308] In the consistency determination circuit #2, the first storage circuit (40) converts the serial pulse signal information input from the column of the activation signal input line (90[0:m-1]), the counting circuit (207) accumulates the number of pulse signals of the k rows of the detection line (70[0:k-1]) transmitted as a group of serial pulse signals, and the determination circuit (290) determines in turn whether the generated value exceeds the threshold value set in the second storage circuit (200), and outputs a signal indicating the excess when the threshold value is exceeded.

[0309] In the "conversion performed by the storage circuit (40)", an on-current pulse is generated that is equivalent to the cumulative value of the input activation signal (90[0:m-1]) and the "storage value of the memory cell of the storage circuit (40)". It can be said that the detection line (70) sums the number of pulse signals generated by each activation signal input line (90[0:m-1]) within a "unit time".

[0310] To be precise, the pulse signals generated by the activation signal input lines (90[0:m-1]) may be superimposed, and the number of pulse signals may decrease, but at least it is close to the sum of the number of pulse signals.

[0311] Such conversion similar to matrix operation based on accumulation and summation (product sum) is "conversion performed by the storage circuit (40)".

[0312] When the "determination circuit (290)" determines that the product-sum value exceeds the "storage value of the second storage circuit (200)", a "signal indicating high similarity" is output from the output terminal (260). This operation is the most basic operation related to the consistency determination of the "consistency determination circuit".

[0313] Operation of consistency judgment loop #1

[0314] Next, refer to Figure 5A , the operation of the consistency determination circuit #1 is described in more detail.

[0315] The m memory cells (10) sharing the detection line (70) constitute a detection unit circuit (50) and receive activation signals input from m "activation signal input lines (90)". The activation signal is a pulse signal, and the timing of the rise / fall of the pulse is basically not synchronized with each other.

[0316] In addition, the pulse signal transmitted in the "activation signal input line (90)" conveys information indicating the number of pulses transmitted within a "unit time" which is a relatively short time interval.

[0317] For example, if the number of pulses transmitted within a "unit time" is three, it represents a value of "3", if the number of pulses transmitted within a "unit time" is seven, it represents a value of "7", and so on.

[0318] The "m memory cells (10)" respectively conduct current pulses to the "detection line (70)" according to the storage value in the memory cell and the pulse signal transmitted in the "activation signal input line (90)".

[0319] For example, when the storage value in the memory cell is "value 1", if a pulse signal is transmitted from the "activation signal input line (90)", a current pulse is conducted to the "detection line (70)", but when the storage value in the memory cell is "value 0", even if a pulse signal is transmitted from the "activation signal input line (90)", no current pulse is conducted to the "detection line (70)".

[0320] Therefore, in the consistency determination circuit #1, the "detection unit circuit (50)" conducts a maximum number of pulse currents equal to the sum of the number of on-current pulses transmitted from each of the m "activation signal input lines (90)" to the "detection line (70)", and transmits it to the "counting circuit (207)" via the "detection line current reading circuit (101)".

[0321] In order to make the number of current pulses generated in the detection line (70) equal to the number of pulses transmitted from each input line (90), it is effective to prevent the pulses transmitted from each "activation signal input line (90)" from being superimposed.

[0322] In order to count the number of pulsed on-currents generated in the detection line (70), the sensing circuit (101) generally converts the pulsed on-current changes into a "digital pulse signal constituting a time series" so that the value becomes 1 when the current value is above the current defined by the threshold (112), and becomes 0 when the current value is below the current defined by the threshold (112), and the number of digital pulse signals is counted by the counting circuit of the next stage.

[0323] However, the provision of the sensing circuit (101) and the threshold value (112) is necessary depending on the circuit scale and the type of memory cell selected, and is not necessarily required in the present invention.

[0324] Since the number of digital pulse signals is counted in "unit time", the counted number is a finite value.

[0325] A general memory cell is activated by the word line when reading and conducts current to the bit line, so this assumption is very common and can also be assumed to be volatile memories such as SRAM and DRAM, non-volatile memories such as EPROM, EEPROM, MASK-ROM, and various memories such as FeRAM, ReRAM, PCM, MRAM, etc., which are sometimes called new material memories.

[0326] In the case of these memory cells, Figure 5A The "activation signal input line (90)" in the embodiment is generally referred to as a word line. Figure 5A The detection line (70) in is generally referred to as a bit line.

[0327] Typically, in circuit diagrams of various memories, word lines are shown as lines extending in the horizontal direction, and bit lines are shown as lines extending in the vertical direction, so please note that the circuits in the figures showing the embodiments of the present invention are expressed as circuit diagrams of conventional memories or as circuit diagrams rotated 90 degrees to the left.

[0328] As an embodiment of the present invention, the following can be used: Figure 5A The memory unit for Binary content addressable memory and the Half unit for Ternary content addressable memory are shown. In the case of using the memory unit for content addressable memory, Figure 5A The "activation signal input line (90)" in the figure corresponds to the Search Line that transmits a signal constituting a part of the search keyword during the search, and the "detection line (70)" corresponds to the Match Line.

[0329] The circuit representation in each figure showing the embodiment of the present invention has the same vertical and horizontal arrangement as the circuit diagram of a memory cell for a general content-addressable memory, and is not rotated 90 degrees to the left.

[0330] Similarity Count

[0331] Hereinafter, the concept of “counting of similarities” in the present invention will be described in more detail.

[0332] When S(i) pulse signals are applied per unit time to the "activation signal input line (90[i])" supplied to the i-th memory unit (10[i]), the memory unit (10[i]) controls whether current is conducted or not conducted to the detection line (70) according to the data stored inside.

[0333] Without loss of generality, the storage value of the memory cell (10[i]) that conducts current to the detection line (70) is called "value 1", and the storage value that does not conduct current is called "value 0". If the names of the storage values ​​are reversed, the description becomes slightly complicated, so this setting is used for the description.

[0334] Therefore, when the storage value of the memory cell (10[i]) is "value 1" and S(i) pulse signals are applied to the "activation signal input line (90[i])" per unit time, the memory cell (10[i]) may conduct a maximum of S(i) currents in a pulsed manner to the detection line (70).

[0335] When the memory unit (10[i]) is turned on at the timing when other memory units (10) are not conducting current, the number of current pulses conducted by the memory unit (10[i]) is the largest. When the pulse signals transmitted by the "activation signal input line (90)" are not superimposed, the memory unit (10[i]) conducts the same number of current pulses as the number of input pulses to the detection line (70).

[0336] On the other hand, when the storage value of the memory cell (10[i]) is "value 0", the number of current pulse signals conducted by the memory cell (10[i]) to the detection line (70) is 0.

[0337] Therefore, if the number of current pulse signals that the i-th memory cell (10[i]) conducts to the detection line (70) in a unit time is "D", then

[0338] D≤S(i)×(storage value of the memory cell).

[0339] This calculation is valid for all memory cells connected to the detection line (70).

[0340] That is, if the total number of current pulse signals conducted to the detection line (70) is set to "D[0]", then "D[0]" can be used as the number of pulse signals {S[i]} transmitted by the activation signal input line (90[i]) per unit time,

[0341] It is expressed as D[0]≤∑{S[i]×{data value of the memory cell connected to the detection line (70)}}.

[0342] (Note: Σ is the sum of i=0~(m-1))

[0343] The equality holds true when the signal pulses transmitted by the "activation signal input line (90[i], i=0 to (m-1))" do not overlap each other.

[0344] Here, if the signal pulse transmitted by the "activation signal input line (90[i], i=0~(m-1))" is convex, that is, it becomes "value 1" when activated and becomes "value 0" when not activated, then the expression becomes easy. Therefore, in the future, the signal pulse transmitted by the "activation signal input line (90[i], i=0~(m-1))" will be convex without losing generality.

[0345] That is, in the circuit using the architecture of the present invention, the counting circuit approximates the following calculation: the inner product value between a vector "S" whose components are a value consisting of the number of pulse values ​​of the time series of the "activation signal input line (90[i], i=0~(m-1))" within a unit time and a vector (this vector is set to "M") whose components are the data values ​​of the memory cells connected to the detection line (70) is taken.

[0346] When the inner product value obtained between the input data expressed by the "time series of the pulse signal applied to the activation signal line (90)" which is the output value of the counting circuit (207) and the data stored in the "first storage circuit (40)" exceeds the "storage value of the second storage circuit", the "determination circuit" outputs a "signal indicating high similarity" from the output terminal (260).

[0347] Hereinafter, the output of "a signal indicating a high degree of similarity" from the output terminal (260) of the consistency determination circuit will be referred to as "excitation".

[0348] Operation of consistency judgment loop #2

[0349] Below, refer to Figure 6 , the consistency determination circuit #2 of the “second embodiment” of the present invention is described.

[0350] In the consistency determination circuit #1, each component of the vector "S" is an integer value, but each component of the vector "M" is also a single-digit number as a binary number and can only take two values, "value 0" or "value 1".

[0351] In the consistency determination circuit #2 of the present invention, the k value is an integer value of k≥2, and each component of the vector "M" is expressed by a "unit storage circuit (55)" composed of a plurality of memory cells, and the storage circuit is a unit of a circuit that expresses a binary number. Each memory cell (10) in the "unit storage circuit (55)" shares a common "activation signal input line (90)", and transmits the conduction current generated in response to the signal from the "activation signal input line (90)" to different detection lines (70).

[0352] That is, the first storage circuit has "a plurality of detection lines [j]; j=0 to (k-1)", and transmits signals from the plurality of detection lines to the counting circuit. [Claim 1]

[0353] If the number of pulses detected from these multiple detection lines per unit time is set to "D[j]",

[0354] Then D[j]≤∑{S[i]×{data value of the memory cell connected to the detection line [j]}}.

[0355] (Note: Σ is the sum of i=0~(m-1))

[0356] If the counting circuit multiplies D[j] by "2 to the power of j; 2 j " is used to perform product and sum calculation, then the output "P" of the counting circuit is,

[0357] P≤{∑{S[i]×{(data value of the memory cell connected to the detection line [j]}×(2j)}}}. (Note: ∑ is the double sum of i=0~(m-1) and j=0~(k-1))

[0358] "2 to the power of j; 2 j " is equivalent to the "predetermined weighting coefficient" in claim 2, but the present invention does not deny the selection of "2 to the jth power; 2 j ” counts outside of the .

[0359] However, by adding “2 to the power of j; 2 j " is multiplied by the coefficients of the vector "M", and the "unit storage circuit (55)" expresses a binary number, so it is convenient to use the usual digital calculation framework.

[0360] As mentioned above, Figure 6 The counting circuit of the "consistency judgment circuit #2" of the present invention shown has the function and ability to count and output the signal of the inner product value between the vector data that can represent the "time series of the pulse-shaped input signal group" and the vector data stored in the memory cell array.

[0361] Determination circuit action

[0362] In both "coincidence determination circuit #1" and "coincidence determination circuit #2", the output of the counting circuit (207) is compared with the value stored in the second storage circuit (200) via the determination circuit (290).

[0363] By storing the expected inner product value within the unit time in advance in the second storage circuit, the output from the determination circuit becomes a signal indicating whether the inner product value as the output value of the counting circuit is greater than or equal to the expected value.

[0364] In the description of the present invention, when “the inner product value as the output value of the counter circuit is a value greater than or equal to the expected value stored in the second storage circuit”, the description is given of outputting “value 1” without loss of generality.

[0365] In addition, the state in which "the coincidence determination circuit #1 or #2" outputs "value 1" is referred to as "activation".

[0366] That is, the "counting circuit" of the "consistency judgment circuit #1" and the "consistency judgment circuit #2" of the present invention calculates the inner product as the distance, calculates the distance between the vector data that can be represented by the "time series of the pulse-shaped input signal group" and the vector data stored in the memory cell array, and the "judgment circuit" determines whether the calculated distance is greater than the value stored in the "second storage circuit". If it is "above", a signal indicating "excitation" is output.

[0367] The inner product value representing the distance is regarded as the “similarity.” Therefore, the “match determination circuit” is activated when receiving input data having a “similarity” higher than the value stored in the “second storage circuit.”

[0368] Matching degree determination circuit #3 according to the third embodiment of the present invention

[0369] Figure 7 This is a block diagram schematically showing a "fuzzy search circuit #3" according to the third embodiment of the present invention.

[0370] In this embodiment, a Flash EEPROM is used as a memory cell of the first storage circuit, but the memory cell of this embodiment may be any other memory cell as long as it is a "memory cell having a function of conducting current from a bit line by selecting a word line" including DRAM or SRAM.

[0371] In this embodiment, the "activation signal input line (90)" corresponds to the "word line" of the Flash EEPROM memory cell, and the "detection line

[70] " is the "bit line".

[0372] The "word line" is connected to the gate terminal of the memory cell (Flash EEPROM in this embodiment), and the "bit line" is connected to the drain terminal of the memory cell. [Claim 3]

[0373] The circuit for controlling the reading and writing of the memory cells of the Flash EEPROM, and the bit lines and word lines used in this process are generally known technologies, and therefore are not illustrated in this figure to avoid complication.

[0374] Matching degree determination circuit #4 according to the fourth embodiment of the present invention

[0375] Figure 8 This is a block diagram schematically showing a “matching degree determination circuit # 4 ” according to the fourth embodiment of the present invention.

[0376] The output data storage circuit receives the signal (260) indicating the exceeding outputted by the "matching degree determination circuit #4" and the determination circuit, and sequentially outputs the stored data of the output data storage circuit. [Claim 4]

[0377] Fuzzy search circuit #1 according to the fifth embodiment of the present invention

[0378] Fig. 9 This is a block diagram schematically showing a "fuzzy search circuit #1" according to the fifth embodiment of the present invention.

[0379] The fuzzy search circuit #1 (11) has n sets of consistency determination circuits #1, #2, or #3, and further has an "activation line drive circuit (155)", "first threshold value generating circuit (111)", "first control circuit (120)", and "reading and writing circuit (570) of the second storage circuit" as common circuits. [Claim 4]

[0380] Fig. 9 The consistency determination circuit (9) in the embodiment refers to consistency determination circuit #1, consistency determination circuit #2 or consistency determination circuit #3.

[0381] The “activation line driving circuit 155” input from the outside generates a signal of the “activation signal input line 90” based on the “input signal 80”, and sends it as an input signal to each coincidence determination circuit.

[0382] The "first threshold value generating circuit (111)" sets the threshold value (112) of the "detection line current reading circuit (101)" of each consistency determination circuit.

[0383] The "reading and writing circuit (570) of the second storage circuit" receives a signal from the "first control circuit (120)" and reads and writes data from the "second storage circuit (200)" of each consistency determination circuit.

[0384] The "first control circuit (120)" also controls the counting operation of the "counting circuit (207)". In addition, it controls the "counting circuit (207)", the "second storage circuit (200)", and the "reading and writing circuit (570) of the second storage circuit" to set and control the overall operation mode of the fuzzy search circuit #1 (11).

[0385] in addition, Fig. 9 The block diagram of the interior of the degree of consistency determination circuit shown is a block diagram of the degree of consistency determination circuit #2.

[0386] In addition, Fig. 9 In order to avoid making the drawings complicated, the circuit for controlling the reading and writing of the "first storage circuit 40" and the bit lines and word lines used at this time are not described. The circuit for controlling the reading and writing of the "first storage circuit (40)" and the bit lines and word lines used at this time have a generally known structure and are not the essence of the present invention.

[0387] Each consistency judgment circuit receives the signal from the common "activation signal input line (90[i], i=0~(m-1))", is activated when the count is received as input data with a "similarity" higher than the value stored in each "second storage circuit", and outputs a "signal indicating high similarity" to the "judgment result output (260)".

[0388] Since the signal input from the "activation signal input line (90[i], i=0~(m-1))" sends the "number of pulses per unit time" of the signal as data, for each "consistency judgment circuit", according to the difference between the data of the "first storage circuit" and the data of the "second storage circuit", the "inner product value" representing the "similarity" is different, resulting in a difference between a circuit that increases faster to be excited and a circuit that increases slowly to be excited.

[0389] Based on the difference in the firing timing, the "determination result output (260[0] to 260[n-1])" indicates which circuit in the entire signal group is the "matching degree determination circuit" with the highest similarity among the "fuzzy search circuits".

[0390] [Claim 5]

[0391] Setting mode (for setting the value of the second storage circuit)

[0392] The consistency determination circuit and the fuzzy search circuit have at least a "setting mode", a "measurement mode" and a "maintenance mode" controlled by a first control circuit (120) that operates based on an external control signal input (153). In the "maintenance mode", the data stored in the first storage circuit (40), the second storage circuit (200) and the excitation unit (530) are read or written.

[0393] In the operation modes of "setting mode" and "measurement mode", the operations of "counting circuit (207)" and "second storage circuit (200)" are different. [Claim 13]

[0394] The "setting mode" is an action of setting data in the storage circuit of the "second storage circuit (200)", and the setting method includes at least two methods. In the first method, the data of the "second read / write signal (210)" provided from the outside is written into the "second storage circuit (200)" under the control of the "first control circuit (120)". When writing, the written data passes through the "read / write circuit (570) of the second storage circuit".

[0395] That is, the control circuit (120) selects the counting circuit (207) and the second storage circuit (200) of any consistency judgment circuit, and writes the input data from the "second read-write signal (210)" into the "second storage circuit (200)" by sending control signals to the second storage circuit (200) and the counting circuit (207), as well as the read-write circuit (570) of the second storage circuit. In addition, by sending other control signals, the storage data of the "second storage circuit (200)" is output to the terminal of the "second read-write signal (210)".

[0396] In the setting mode of the second method, the following operation flow is assumed.

[0397] In the first stage, a pulse signal is applied from the outside to an input line of a first storage circuit (40) at a timing that is not sequentially superimposed.

[0398] In the second stage, as a result of the first stage, the current pulses or voltage pulses generated in the detection line are counted by the counting circuit (207).

[0399] In the third stage, the counting result is written into the second storage circuit (200).

[0400] The first to third stages mentioned above do not mean a segmented state like an assembly line action. The expression "stage" only expresses the action flow.

[0401] Through the above-mentioned operation flow, the counting result based on the number of cells of "value 1" in the memory cell (10) of the first storage circuit (40) is stored in the "second storage circuit (200)". The counting result is the count value counted when each of the m activation signal lines (90) is activated once, and is the number of memory cells (10) connected to the detection line (70) storing "value 1".

[0402] Measurement Mode

[0403] In the measurement mode, the pulse signal applied to the "activation signal input line (90)" is counted by the "measurement circuit (207)", and the value generated based on the numerical value is compared with the value stored in the "second memory circuit (200)" by the "determination circuit (290)" at any time, and the determination result is output.

[0404] The "determination circuit (290)" may use the value of the "second storage circuit (200)" itself, or a numerical value generated based on the value, as a threshold value to perform determination.

[0405] Structure of counting circuit

[0406] Fig.16This is a block diagram showing the internal structure of the "counting circuit (207)" which is the main component circuit of the matching degree determination circuit of the present invention, and the connection relationship between it and other circuits connected to the counting circuit.

[0407] exist Fig.16 In the figure, it is assumed that the "k value" representing the number of detection unit circuits (50), detection lines (70), and detection line current reading circuits (101) constituting the first storage circuit (40) is "3".

[0408] In addition, the value corresponding to the "weighting coefficient pre-set for each detection line" of claim 2 is "1" for detection line (70[0]), "2" for detection line (70[1]), and "4" for detection line (70[2]).

[0409] The counting circuit (207) is composed of a counting circuit front stage circuit (208) and other counting circuit rear stage circuits. The counting circuit front stage circuit (208) has the following functions:

[0410] [1] receiving the output (70[0], 70[1], 70[2]) of the “detection line current reading circuit (101)” for reading the pulse signal transmitted in the detection line,

[0411] [2] The number of pulses transmitted from these signals is counted using counter circuits (508, 509, 511) and converted into binary numbers of 3 digits, 2 digits, and 1 digit, respectively.

[0412] [3] The high-order two digits of the binary number generated from 70[0], the two digits of the binary number generated from 70[1], and the one digit of the binary number generated from 70[2] are stored in a register consisting of five flip-flops (512, 513, 514, 515, 516).

[0413] [4] Furthermore, the Adder circuits (517, 518, 519) sum the values ​​stored in the registers and store them in the next registers (527, 528, 529), and the "value of the highest digit that becomes the carry" is applied to the shift register circuit (202) as a 1-bit signal.

[0414] [5] Whenever the input "value of the most significant digit that becomes a carry" is switched and the counted value increases, the shift register circuit (202) shifts the internal register value toward the higher digit.

[0415] In the above-mentioned stages [3] to [4], for the three-digit, two-digit, and one-digit binary numbers counted by the counter circuits (508, 509, 511), the values ​​of the second digits of the number of pulses transmitted from 70[2] and the number of pulses transmitted from 70[1] are summed, and the values ​​of the second and third digits of the number of pulses transmitted from 70[1] and the number of pulses transmitted from 70[0] are summed.

[0416] Thus, in the preceding circuit (208) of the counting circuit, the number of pulses counted based on the signal from 70[2] is multiplied by a coefficient of 4, the number of pulses counted based on the signal from 70[1] is multiplied by a coefficient of 2, and the number of pulses counted based on the signal from 70[0] is multiplied by a coefficient of 1, and the sum of these is taken. [Claim 2]

[0417] In addition, in the final stage of the above-mentioned [4], the "value of the number of bits that become the highest bit of the carry" is applied to the shift register circuit (202) as a 1-bit signal, but thereby the value of the number of bits other than the highest bit of the preceding circuit (208) of the counting circuit is discarded.

[0418] This has the effect of reducing the circuit scale of the subsequent stage circuit (209) of the measurement circuit.

[0419] Structure of shift register circuit and determination circuit

[0420] Fig.17 and Fig.18 This is a block diagram showing the internal structure of the main circuits constituting the "counting circuit (207)", namely the "shift register circuit (202)", the "determination circuit (290)" and the "second storage circuit (200)", which are the main components of the consistency determination circuit of the present invention.

[0421] from Fig.17 The "counting input (201)" inputted at the left end is the output of the "counting circuit front stage circuit (208)",

[0422] When the forward shift (598) is "value 1" and the reverse shift (599) is "value 0", the data of the Flip-Flop (FF) in the SRU composed of SRU[0]~SRU[x-1] is shifted from the left side of the figure to the right side, and a new "value 1" appears in the FF of the SRU at the left end.

[0423] In the case of a Flip-Flop (FF in SRU[0]) composed of G213 and G214, the "value 1" of the FF of the SRU is in a state where the right node (212) becomes a High level and the left node (211) becomes a Low level.

[0424] in addition,

[0425] When the forward shift (598) is "value 0" and the reverse shift (599) is "value 0", the data of the FF in the SRU composed of SRU[0]~SRU[x-1] is shifted from the right side of the figure to the left side, and "value 0" is set in the FF of the SRU at the right end, namely SRU[X-1].

[0426] However, the value of Flip-Flop (FF) in the "shift register circuit (202)" may be written into the value of the "second storage circuit (200)".

[0427] For example, if the data value when resetting the "second storage circuit (200)" is set to "All 0", the right nodes of all Flip-Flops become Low level, so if this value is written into the shift register (202), all FFs in the shift register circuit are also set to "value 0".

[0428] If the data value when resetting the "second storage circuit (200)" is set to "All 0" and the data is written to the "shift register (202)", all the FFs in the shift register will also become "value 0". In this state, if the forward shift (598) is set to "value 1", the reverse shift (599) is set to "value 0", and the triggering of the "count input (201)" is started, then in the FFs of SRU[0]~SRU[x-1], when left-aligned, only the counted number is arranged as "value 1", and "value 0" is arranged on its right.

[0429] That is, the "shift register (202)" is incremented and the count value is stored.

[0430] The determination circuit (290) has a delay circuit composed of a 2-input NAND and an inverter, but in the portion of the shift register corresponding to "value 1", the 2-input NAND functions as an inverter, and in the boundary portion between "value 1" and "value 0", a low-level signal is received from the 2-input NAND from the shift register (202), and a high-level signal is received in other areas, so a low level appears in the "determination result output (260)".

[0431] Therefore, the number of pulses counted in the setting mode is stored in Fig.18After the data is written into the "second storage circuit (200)" of the shift register, if the forward shift (598) is set to "value 0", the reverse shift (599) is set to "value 1", and the triggering of the "count input (201)" is started, when the triggering is repeated for the number of times written into the second storage circuit (200), all the FFs of the shift register (202) return to "value 0", and a High level appears in the "judgment result output (260)". [Claim 14]

[0432] This state is regarded as “excited”, and is a signal reporting information that “the similarity has reached the value set in the second storage circuit” to the outside.

[0433] Structure of measurement circuit based on counter circuit

[0434] Fig.19 This is an embodiment of a counter circuit used to constitute a subsequent circuit of a counting circuit of the "counting circuit (207)" which is a main constituent circuit of the coincidence determination circuit of the present invention.

[0435] Fig.16 The "structural example of a counting circuit using a shift register circuit" in the embodiment is the same as the "counting circuit front stage circuit (208)", but the constituent elements of the "counting circuit rear stage circuit (209)" are different. Fig.16 The "Counter Circuit" shown and Fig.17 The structure of the "second storage circuit when using a counter circuit" shown in FIG.

[0436] Fig. 20 This is a configuration example of a counter circuit.

[0437] Below, refer to Fig. 20 and Fig.21 , the operation of the counter circuit in the setting mode and the operation mode is explained.

[0438] and Fig.16 Similarly, here, the “k value” indicating the number of detection unit circuits (50), detection lines (70), and detection line current reading circuits (101) constituting the first storage circuit (40) is set to “3” for description.

[0439] In a counter circuit, in Y counter units (CU[0] to CU[Y-1]), a maximum binary number of Y bits can be expressed as a large value of "2 to the power of (Y)", but in order to construct it so that it can count up and down, the number of components increases, so there are both advantages and disadvantages.

[0440] In the setting mode, first, a "reset control signal (307)" is sent from the "control circuit (120)" to write the reset value into the "second storage circuit (610)".

[0441] When the reset value is All-0 (binary number, 0000...0) or All-1 (binary number, 1111...1), the operation becomes simple and can basically be any value. In order to simplify the description, the reset value is set to All-0 (binary number, 0000...0) in the following description.

[0442] Next, the "write signal (308)" is sent from the "control circuit (120)" to the "second storage circuit for the counter circuit (610)", and the values ​​of each unit (TIMBU[0]~TIMBU[Y-1]) of the second storage circuit (610) are written into the Flip-Flop (FF) in each counter circuit (CU[0]~CU[Y-1]).

[0443] Therefore, the FFs in the counter circuits (CU[0] to CU[Y-1]) also become All-0 (binary number, 0000...0).

[0444] Next, pulse signals are applied to the "activation signal input lines (90)" one by one in a non-superimposed manner, and at the same time, a "Shift Foward" signal is sent from the "control circuit (120)" to the "counter circuit (560)".

[0445] Through the processing of the "counting circuit front stage circuit (208)", the number of pulses counted based on the signal from 70[2] is multiplied by a coefficient of 4, the number of pulses counted based on the signal from 70[1] is multiplied by a coefficient of 2, and the number of pulses counted based on the signal from 70[0] is multiplied by a coefficient of 1, and the sum of these is taken. However, in the final stage of the processing of the "counting circuit front stage circuit (208)", only the "value of the most significant digit of the carry" of the 1-bit signal (524) is used as the input signal for the counter circuit (560), that is, the count input (201). Therefore, the value of the digits other than the most significant digit of the 4-digit binary number generated in the "counting circuit front stage circuit (208)" is discarded.

[0446] In the "counter circuit (560)", a "Shift-Foward (598)" signal is sent from the "control circuit (120)", so that the count is incremented every time a pulse signal is applied to the count input (201).

[0447] After the sequential selection of all the "activation signal input lines (90)" is completed, the current pulses from the memory cell connected to the last "activation signal input line (90)" are counted. When the counting of the "counter circuit (560)" is completed, a control signal (309) is sent from the "control circuit (120)" to write the values ​​of all the "counter circuits (560)" into the "second storage circuit (610)", and the values ​​of all the counters in the "counter circuit (560)" are written into the "second storage circuit (610)".

[0448] Thus, the setting mode ends.

[0449] Measurement Mode

[0450] Next, refer to Fig.19 and Fig. 20 , the operation of the measurement mode is explained.

[0451] In the measurement mode, first, a control signal (309) is sent from the "control circuit (120)" to write the value of Flop-Flop (FF) in the "second storage circuit (610)" into the Flop-Flop (FF) in the corresponding "counter circuit (560)", and the value of the "second storage circuit (610)" is written into the corresponding "counter circuit (560)".

[0452] However, at this time, unlike the setting mode, the "Shift Reversely (599)" signal is sent from the "control circuit (120)" to indicate a count-down operation, so the counter enters a reverse rotation state.

[0453] Next, an input signal from the outside is applied to the "input line (80)", and a pulse signal is sent to the "counting circuit front stage circuit (208)" through the "activation signal input line (90)" and the "detection line (70)". In the counter circuit, a pulse signal is transmitted to the counting input (201), but unlike the setting mode, the value gradually decreases from the value written in the second storage circuit (610) because the counter is reversed.

[0454] If a pulse signal for only the number of values ​​written from the "second storage circuit (610)" is transmitted from the "counting circuit front stage circuit (208)" to the "counter circuit 560", the value of the counter circuit returns to the initial value All-0 (binary number, 0000···0).

[0455] That is, the same number of "value 1" as that detected in the setting mode is detected in the operation mode.

[0456] If the value of the counter circuit returns to the initial value All-0 (binary number, 0000...0), the determination circuit (543) switches the output from a Low level to a High level, and outputs "input data represented by the time series of an activation signal input from the outside and a signal indicating a high degree of similarity with the storage data of the first storage circuit" from the "determination result output terminal (260)".

[0457] In the above description, in the "counting circuit front stage circuit (208)", since the values ​​up to the third digit of the number after multiplication with the coefficient and summing are ignored, a maximum difference of up to "value 7" may occur in the counting values ​​in the setting mode and the counting mode, but this difference is considered to be an error within the allowable range.

[0458] Fuzzy search circuit #2 according to the sixth embodiment of the present invention

[0459] Fig.10 It is a block diagram schematically showing a "fuzzy search circuit #2" according to the sixth embodiment of the present invention.

[0460] The "fuzzy retrieval circuit #2" is provided with a "vertical output detection circuit (534)" and a "timer circuit (116)" based on the "fuzzy retrieval circuit #1", and the control circuit carried is changed from the "control circuit (120)" to the "control circuit (119)".

[0461] The circuit for controlling the reading and writing of the first storage circuit (40), the bit lines and word lines used in this case have generally known structures, and therefore are not described in this figure to avoid complicating the figure.

[0462] As an embodiment, the mounted consistency determination circuit is shown as an example of consistency determination circuit #2, but it may also be consistency determination circuit #1 or consistency determination circuit #3.

[0463] Operation of the control circuit based on the signal from the vertical output detection circuit

[0464] The "vertical direction output detection circuit (524)" is connected to the "excitation unit (530)" of each of the "determination result output (260)" which is the output of the consistency determination circuit #2. When any of the "excitation units (530)" is excited, a High level is output to the "integrated excitation signal (533)" through the "vertical direction detection line (531)" and the "vertical direction detection line reading circuit (532)".

[0465] The output "comprehensive excitation signal (533)" becomes a High level, which means that any one of the matching degree determination circuits constituting the fuzzy search circuit #2 has output a "signal indicating a high similarity".

[0466] When any of the "firing units (530)" is not excited, the "comprehensive excitation signal (533)" is at a Low level.

[0467] Regarding the control of the counting action based on the control of the "control circuit (119)" when the "comprehensive excitation signal (533)" becomes a High level indicating "excitation", there are multiple "setting options" as shown below through the setting of the "control signal input (153) from the outside".

[0468] [1] When the "control circuit (119)" receives a "comprehensive excitation signal (533)" that becomes a High level signal indicating "excitation", or receives a signal indicating timeout from the "timer circuit (116)", the count value of the counting circuit is reset by rewriting the storage value of the FF in the "shift register circuit (202)" of all consistency judgment circuits to the storage value of the "second storage circuit", and the "prescribed period" is started again.

[0469] [Claim 6]

[0470] [2] When the "control circuit (119)" receives a signal indicating that the "comprehensive excitation signal (533)" is a High level signal indicating "excitation", or receives a signal indicating a timeout from the "timer circuit (116)", it instructs the count value of all consistency determination circuits to be forcibly reduced by one step. [Claim 6]

[0471] [3] The "control circuit (119)" does not require the "vertical direction output detection circuit" and the "timer circuit", and controls the "unit time" according to the signal of the "control signal input (153) from the outside".

[0472] The signal of the "control signal input (153) from the outside" may be a multi-bit signal, or may be a signal receiving an excitation signal of other fuzzy search circuits. [Claim 15]

[0473] This is because the "vertical direction output detection circuit (534)" has a structure of a consistency determination circuit.

[0474] The "firing unit (530)" is a circuit having the same structure as the "memory unit (10)", which can program the non-use of a specific consistency determination circuit by forcibly maintaining the "non-firing" state based on the data stored in the "firing unit (530)".

[0475] In any of the drawings of the embodiments of the present invention, circuits and connections related to reading and writing of the "excitation unit (530)" are not described.

[0476] The "vertical direction detection line reading circuit (532)" is the same as the detection line reading circuit, and is a general sense amplifier circuit as shown in FIG4. The circuit for setting the threshold value (114) is the "third threshold value circuit (113)".

[0477] Fuzzy search circuit #3 according to the seventh embodiment of the present invention

[0478] Fig.11 This is a block diagram schematically showing a "fuzzy search circuit #3" according to the seventh embodiment of the present invention.

[0479] In the "fuzzy search circuit #3" of this embodiment, the "fuzzy search circuit #2 ( Fig. 9 )” is switched to the “activation line signal generating circuit (156)”, and a “pulse generating circuit (535)” is added between the output of the “uniformity determining circuit (2)” and the “excitation unit (530)”. In addition, the input signal from the outside is switched from the “input signal (80[0] to 80[m-1])” to the “activation control signal (85[0] to 85[Z-1])”, and a function of controlling the “activation line signal generating circuit (156)” is added to the “control circuit (118)”. [Claim 12]

[0480] The circuit for controlling reading and writing with respect to the first storage circuit (40), and the bit lines and word lines used at this time have generally known structures, and therefore, they are not described in this figure to avoid complexity.

[0481] In the fuzzy search circuit #3 as an embodiment accompanying these changes, a pulse signal is not assumed as an input signal from the outside, but a pulse signal provided to the "activation line (90[0] to 90[m-1])" is generated by the "activation line signal generation circuit (156)".

[0482] The "pulse generating circuit (535)" is composed of a delay circuit and a logic circuit.

[0483] This is a known technique for constructing a pulse generating circuit having a pulse width corresponding to a delay circuit by obtaining a NAND logic or a NOR logic between a signal before delay and a signal after delay.

[0484] The "activation line signal generation circuit (156)" also uses the same pulse generation circuit when generating the "activation line signal (80)".

[0485] The signals of the "activation signal input line (90)" are qualitatively respectively:

[0486] Pulse density information per “unit time”

[0487] Timing of switching the density of pulse signals from sparse to dense

[0488] Timing of switching the density of pulse signals from dense to sparse

[0489] These three types of information are equivalent to "input data represented by the time series of activation signals input from the outside".

[0490] Therefore, the signal input to the "activation line signal generating circuit (156)", namely the "activation control signal (85[0]~85[Z-1])", must have all the information required by the "activation signal input line (90[0]~90[m-1])". Generally speaking, the number of "activation control signals (85)" is greater than the number of "activation signal input lines (90)".

[0491] However, since much information is transmitted not through serial signals but through parallel input signals, the operation of "Fuzzy Search Circuit #3" has the advantage of being able to operate at high speed compared to other embodiments.

[0492] Fuzzy search circuit #4 according to the eighth embodiment of the present invention

[0493] Fig.12 This is a block diagram schematically showing a "fuzzy search circuit #4" according to the eighth embodiment of the present invention.

[0494] Fig.12 Schematically shows Fig.16 , Fig.17 and Fig.18 The connection relationship between the control signal line between the "second control circuit (119)" and the "measurement circuit (207)" of the "consistency judgment circuit (2)", the signal line (TIM-GBL) used when transferring data between the "read-write circuit of the second storage circuit" and the "consistency judgment circuit", and the signal line (TIM-LBL) used when transferring data between the "second storage circuit" and the "judgment circuit" in the "consistency judgment circuit".

[0495] In addition, in this embodiment, a cross-point memory cell is used as the memory cell of the “first storage circuit 40 ”.

[0496] like Fig.12 As shown, if it is a cross-point cell capable of bidirectional operation, it has the advantage of being able to use the "activation signal input line (90)" as the bit line when reading the cell, and allowing the "detection line (70)" to function as the word line when reading.

[0497] The control signal lines between the "second control circuit (119)" and the "measurement circuit (207)" of the "matching degree determination circuit (2)" are as follows.

[0498] 305 controls access to the second storage circuit (200 or 610).

[0499] · 306 controls access to the shift register circuit (202) or the counter circuit (560).

[0500] ·307 Reset the storage data of the second storage circuit.

[0501] 308 indicates writing the storage data of the second storage circuit into the shift register circuit (or counter circuit).

[0502] 309 indicates writing the data of the shift register circuit (or counter circuit) into the second storage circuit.

[0503] 288 indicates reading the storage data of the second storage circuit (200 or 610) to the "read-write circuit (570) of the second storage circuit".

[0504] 289 indicates writing the storage data of the “read-write circuit (570) of the second storage circuit” into the second storage circuit (200 or 610).

[0505] 598 indicates to "move up or count up" the data of the shift register circuit (or counter circuit).

[0506] 599 indicates to "shift or count down" the data of the shift register circuit (or counter circuit).

[0507] Fuzzy search circuit #5 according to the ninth embodiment of the present invention

[0508] Fig.13 It is a block diagram schematically showing "fuzzy search circuit #5" according to the ninth embodiment of the present invention.

[0509] This embodiment and Fig.11 Compared to the "fuzzy retrieval circuit #3" shown in the figure, in addition to the "first storage circuit (40)" and "second storage circuit (200)", a "third storage circuit (45)", "activation signal line (91) to the third storage circuit", "activation line drive circuit 2 (155[1])" and "detection line (71)" are added to replace the "first threshold generating circuit (111)" to the "detection line current reading circuit (101)".

[0510] In addition, since the memory matrix and detection line (71) of the third storage circuit (45) are added to the consistency detection circuit constituting the "fuzzy search circuit #5", the name becomes "consistency detection circuit #5 (5)". Since the circuits related to the reading and writing of the memory cells of the "first storage circuit (40)" and the "third storage circuit (45)" are well known, the description is omitted.

[0511] If an activation pulse is applied to some activation signal lines (90[0]~90[m2-1]) of the "third storage circuit (45)", a current pulse can be conducted to the detection line (71) of the third storage circuit based on the storage data of the memory cell of the third storage circuit (45). However, since this current pulse has an inhibitory function with respect to the "detection of the current pulse from the first storage circuit" of the "detection line current reading circuit (101)", it has the effect of forcibly suppressing the similarity detection of the "consistency detection circuit #3(3)".

[0512] This function is useful in emulating the action of a neuron circuit. [Claim 15]

[0513] The "detection line current reading circuit (101)" of the "consistency detection circuit #3 (3)) needs to adopt a circuit structure that detects the current difference between the "detection line (70)" and the "detection line (71)", for example, Figure 4B The “differential current sense amplifier” illustrated in FIG. 1 is used in the “detection line current reading circuit ( 101 )”.

[0514] The effect of suppressing the detection of the current pulse from the first storage circuit by the current of the second detection line (71) is Figure 4B The transistor size ratio of Q41 and Q42 in the read circuit in the embodiment of the present invention changes greatly. In the case of simulating the operation of a neuron circuit, the gate width of the transistor of Q42 is smaller than the gate width of Q41.

[0515] Fuzzy search circuit #6 according to the tenth embodiment of the present invention

[0516] Fig.14 This is a block diagram schematically showing a "fuzzy search circuit #6" according to the tenth embodiment of the present invention.

[0517] This embodiment and Fig.13 Compared with the "Fuzzy Search Circuit #5" shown in the figure,

[0518] A "second detection line current reading circuit (102)" for detecting a pulse current from a "detection line (71)" of a memory matrix of a "third storage circuit (45)" is added.

[0519] a "counting circuit (207)" for counting the number of pulse signals output by the "second detection line current reading circuit (102)",

[0520] a circuit for encoding and outputting the physical address of the "matching detection circuit" that outputs the "signal indicating high similarity" from the "output terminal (260)", namely, an "address encoder circuit (591)" and its output circuit (593),

[0521] "IO circuit (211) for data of the second storage circuit".

[0522] In addition, since a "second detection line current reading circuit (102)" for detecting a pulse current from a "detection line (71)" of a memory matrix of a "third storage circuit (45)" is added to the consistency detection circuit constituting the fuzzy search circuit #6, the name becomes "consistency detection circuit #6 (6)". Since the circuits related to the reading and writing of the memory cells of the first storage circuit (40) and the third storage circuit (45) are well known, the description thereof is omitted.

[0523] In fuzzy retrieval circuit #6, a "second detection line current reading circuit (102)" is added for detecting the pulse current of the "detection line (71)" of the memory matrix of the "third storage circuit (45)", and the counting operation is performed by inputting the difference between the two into the shift register circuit.

[0524] The number of pulses from the "Detect Line Current Reading Circuit (101)" contributes to the increment count or "ShiftForward",

[0525] The number of pulses from the "Second Detection Line Current Reading Circuit (102)" contributes to the count down or "ShiftReversely".

[0526] In addition, in the fuzzy search circuit #6, since the physical address of the "matching detection circuit #4" that issues the "signal indicating high similarity" is encoded and output, if the "second storage circuit (200 or 610)" is accessed from the "IO circuit (211) of the second storage circuit" using the address output from the address output circuit (593), the data stored in the second storage circuit (200 or 610) is read. [Claim 17]

[0527] Fuzzy search circuit #7 according to the eleventh embodiment of the present invention

[0528] Fig.15 This is a block diagram schematically showing a "fuzzy search circuit #7" according to the eleventh embodiment of the present invention.

[0529] This embodiment and Fig.13 Compared with the "Fuzzy Search Circuit #5" shown in the figure,

[0530] The first storage circuit is Fig.18 There is 1 group in Fig.15 There are three groups (40[0], 40[1], 40[2]), and at the same time, the activation line driving circuit also has three circuits (155[0], 155[1], 155[2]).

[0531] In addition, each unit of the consistency determination circuit has a blank setting bit (813). The storage circuit (813) for blank setting is a storage bit that stops the operation of the consistency detection circuit and does not forcibly output a signal indicating excitation from the determination circuit (290). (Claim 23)

[0532] Along with these changes, the name of the third storage circuit relative to the activation line driver circuit is changed to activation line driver circuit D (155[3]).

[0533] Not available Fig.14 The "vertical direction output detection circuit (534)" of the "fuzzy retrieval circuit #6" is not used, but the "fuzzy retrieval circuit #4 (14)" detects the excitation of the "determination circuit A (290)" and feeds back to the "control circuit (120)".

[0534] "Fuzzy retrieval circuit #4 (14)" is composed of "activation line driving circuit E", "first storage circuit E (40[4])", "detection line current reading circuit E", "counting circuit E (207)", "second storage circuit E (200)", "determination circuit E (155)" and "vertical direction detection E (534)".

[0535] The information of the excitation of the "determination circuit A (290)" detected by the "fuzzy retrieval circuit #4 (14)" is transmitted through the "activation line drive circuit C (156[2])" and the "activation line drive circuit D (156[3])", and the counting action cycle of the "counting circuit A (207)" is ended by operating the "first storage circuit C (40[2])" and the "first storage circuit D (40[3])". However, since the output of the "fuzzy retrieval circuit #4 (14)" is input to the "fuzzy retrieval circuit #8" again, the next fuzzy retrieval action is started under new input conditions containing the information of the "input signal [system A]" and the "input signal [system B]" at that moment.

[0536] In the fuzzy search of the "fuzzy search circuit #4 (14)", based on the output of the "determination circuit E (290)" with the highest similarity, the word line of the memory matrix of the "fourth storage circuit (47)" is selected, and the data of the selected memory cell is output as the final "output (580) of the fuzzy search circuit #8" via the "reading circuit (49)". [Claim 19]

[0537] In addition, in order to avoid complicating the drawings, common circuits such as the control circuit of the "fuzzy retrieval circuit #4 (14)", the "read and write circuit of the second storage circuit" of the "fuzzy retrieval circuit #4 (14)", the "read and write circuit of the second storage circuit" of the "fuzzy retrieval circuit #8 (18)", and the read and write circuits for each "first storage circuit (40)" are not recorded.

[0538] Independently of the "vertical output detection circuit (534)", by adding and mixing the "fuzzy retrieval circuit #4 (14)", the "signal indicating high similarity" from the "determination circuit A (290)" is detected and a response signal is output. The "fuzzy retrieval circuit #7" of this embodiment repeatedly performs fuzzy retrieval based on the input information of the time series from the "input signal [system A]" and the "input signal [system B]" and the feedback information of the fuzzy retrieval result of the previous cycle (92[0]~92[m3-1]), and outputs the time series information.

[0539] [Conceptual diagram of a fuzzy search circuit that outputs time-series information]

[0540] Refer to Figure 22. Fig.23 , Fig.24 The generation of a time series signal by a fuzzy search circuit is described.

[0541] FIG. 22 is a conceptual diagram of a fuzzy search circuit that outputs time-series information.

[0542] In order to simplify the description, in the fuzzy search circuit of FIG22, there is no "third storage circuit" for suppressing the action, and only three sides of the "first storage circuit (40)" are shown. In addition, regarding the three sides of the "first storage circuit (40)", two sides are 16 rows × 6 columns, and the other side is 16 rows × 16 columns, and feedback input is performed on the 16 rows × 16 columns.

[0543] Here, the minimum unit of the matrix constituting each surface is not a memory cell but a "counting unit circuit (55)".

[0544] DL[0]~DL

[15] do not refer to detection lines, but schematically illustrate the connection between the "unit storage circuit (55)" of the "detection line group (detection line [0]~detection line [k-1])" possessed by the "counting unit circuit (55)" and the "detection line current reading circuit [0]~detection line current reading circuit [k-1]".

[0545] Therefore, the total number of detection lines expressed in Fig. 22 is (16×k), and the number of detection line groups is 16. The total number of output signal lines (99[0] to

[15] ) is 16.

[0546] In addition, since FIG22 is a conceptual diagram, peripheral circuits such as a counting circuit, a second storage circuit, a determination circuit, and a threshold generation circuit are not described. However, a "first storage circuit" having three sides, a read / write circuit to the second storage circuit, and a word selection circuit (812) for determining a memory cell when reading or writing are described.

[0547] There are various configurations of the circuits in the conceptual diagram of FIG. 22 , and FIG. 22 represents the configurations that depend on the layout of the circuits as representatives.

[0548] A composite memory circuit having a feedback input structure as shown in the conceptual diagram of FIG. 22 generally has the following functions: outputting a time-series signal, or holding or repeating the output by appropriately setting the data stored in each "first storage circuit".

[0549] Fig.23 is an example showing the reproduction of time series data caused by the feedback input structure.

[0550] and Fig.23 Similarly, the matrix sizes of the first storage circuit [system A], the first storage circuit [system B], and the first storage circuit [system FB] are 16 rows×6 columns, 16 rows×6 columns, and 16 rows×16 columns, respectively.

[0551] The smallest unit of the matrix is ​​not a memory cell but a "unit storage circuit (55)".

[0552] "Unit storage circuits" having "numbers large to a certain extent" in the storage data in the memory matrix having three surfaces are marked with symbols such as "M", "N", "A", "B" ..., "H", and other "unit storage circuits" are assumed to have smaller values ​​and are marked with the symbol "·".

[0553] Information represented by the time series of pulses input through the activation signal input line, that is, “the number of pulses per unit time” is shown above the matrix showing the first storage circuits.

[0554] "P" and "Q" are numbers that are large to a certain extent, and "·" refers to smaller numbers.

[0555] Since the "input signal (90[2])" and "input signal (91[4])" have a larger inner product value with the detection line group (DL[2]) than with other detection line groups, a "high similarity" signal is output as time passes. This output signal is displayed as "value 1" in the DL[2] row of the Step=1 column in the right half of the figure.

[0556] This condition is referred to as "detection line group (DL[2])" excitation.

[0557] When a pulse generating circuit (535) is installed, the output signal continues for a certain period of time.

[0558] The excitation of the input detection line group (DL[2]) is fed back via the signal input line (99[2]), and the activation signal is sent to the "first storage circuit [system FB]". Since there is a number "A" that is large to a certain extent in the storage data of the "unit storage circuit (55)" where the signal input line (99[2]) and the detection line group (DL[9]) intersect, the detection line group (DL

[12] ) may also be excited. At this moment, if the amount of the pulse signal of the input signal line (90[2]) and the input signal line (91[4]), which were originally input signals with larger values, decreases, only the detection line group (DL[9]) is excited.

[0559] The excitation of the detection line group (DL[9]) is fed back again, and then, according to the value of "B" in the matrix, the detection line group (DL

[14] ) is excited, and then,

[0560] Depending on the value of "C" in the matrix, the detection line group (DL[3]) is excited.

[0561] Depending on the value of "D" in the matrix, the detection line group (DL[5]) is excited.

[0562] According to the value of "E" in the matrix, the detection line group (DL

[12] ) is excited.

[0563] According to the value of "F" in the matrix, the detection line group (DL[7]) is excited.

[0564] According to the value of "G" in the matrix, the detection line group (DL

[15] ) is excited.

[0565] After that,

[0566] According to the value of "H" in the matrix, the detection line group (DL[2]) is excited again, and the excitation from A to H is repeated.

[0567] In the above case, the excitation action is set to be cyclic according to the value of "H" in the matrix, but if the value of the "H" part is sufficiently small or 0, it is very likely that the subsequent excitation will not be carried out. Whether the excitation is actually performed depends on the "unit time setting" and the size of the actual storage value of the "unit storage circuit 55" marked with "·".

[0568] As described above, the fuzzy search circuit can perform an operation of changing the output terminal to be activated over time based on a signal input from the outside.

[0569] If the signals 99[0] to 99

[15] are instruction signals for different subroutine operations, respectively, then an embodiment of the present invention in which this signal sequence is applied to program control is the "twelfth embodiment of the present invention."

[0570] Fig.24 This is another expression of the "conceptual diagram of the fuzzy search circuit that outputs time-series information" shown in FIG. 22.

[0571] DL[0] to DL

[15] arranged on the periphery are 16 "detection line groups". In each "detection line group", two system signal inputs (90[0] to 90[5]) and (91[0] to 91[5]) are received from the outside, and an output 99[j] (j = any value from 0 to 15) is output to the outside.

[0572] Although the common "90[0]~90[5]) and (91[0]~91[5]) are input into all "detection line groups", if it is expressed that "90[0]~90[5]) and (91[0]~91[5]) are the same regardless of which "detection line group" they are sent to, the diagram will become very complicated, so the line connecting them is not expressed.

[0573] The dotted and solid lines connecting the "detection line groups" on the inner side of the circle refer to the "unit storage circuits (55)" of 16 rows x 16 columns of the "first storage circuit [system FB]". Since each dotted line and each solid line has a direction, it should actually be represented by two lines in opposite directions, but in order to avoid complicating the drawing, only one line is recorded.

[0574] The lines representing "unit storage circuits" having "numbers large to a certain extent", namely "A", "B" ..., "H", are shown with thick solid lines, and the figure marks of "A", "B" ..., "H" are marked in the circle symbol.

[0575] It can be seen from the figure that when the "detection line group" of DL[2] is excited, the excitation of the input detection line group (DL[9]) is fed back in sequence according to the "unit storage circuit" namely "A", "B" ..., "H", and then, according to the value of "B" in the matrix, the excitation of DL

[14] , DL[3], DL[5], DL

[12] , DL[7], DL

[15] , and DL[2] is carried out continuously.

[0576] That is, the connection of the "conceptual diagram of the fuzzy retrieval circuit that outputs time-series information" in FIG. 22 is a network similar to a fully connected neural network.

[0577] Twelfth embodiment of the present invention

[0578] Fig.25 It is a block diagram schematically showing “autonomous response circuit # 1 ” according to the twelfth embodiment of the present invention. Fig.25 The block diagram of the fuzzy retrieval circuit is referenced using Fig. 22B The "symbol map" defined in .

[0579] The "autonomous response circuit #1 (801)" is composed of a fuzzy search circuit A (701), a memory circuit A (735), a data processing circuit (725), a first compression circuit (745) and a second compression circuit (755).

[0580] The fuzzy search circuit A (701) refers to a fuzzy search circuit or a search circuit constructed based on the "fuzzy search circuit #1" to "fuzzy search circuit #7" of the embodiment of the present invention and the "matching degree determination circuit #1" to "matching degree determination circuit #6" of the embodiment of the present invention. Which embodiment is adopted depends on the scale and type of data processed by the "autonomous response circuit #1 (801)" and the required response accuracy.

[0581] The memory circuit A (735) is a well-known concept that receives an address signal as input and outputs data, and is a memory circuit such as SRAM, DRAM, Flash-Memory, etc., which has become a well-known technology.

[0582] The data processing circuit (725) is a logic circuit based on known data processing technologies including CPU, MPU, PLA, FPGA, and ASIC, and processes input data and outputs output data based on a program written to a memory circuit A mounted inside.

[0583] The first compression circuit (745) and the second compression circuit (755) are circuits of a type that generate data input to the fuzzy retrieval circuit A (701), and refer to fuzzy retrieval circuits constructed based on the embodiments of the present invention illustrated by "fuzzy retrieval circuit #1" to "fuzzy retrieval circuit #8", the embodiments of the present invention illustrated by "consistency determination circuit #1" to "consistency determination circuit #5", or publicly known retrieval circuits and data compression circuits.

[0584] The implementation method to be adopted depends on the size and type of data processed by "autonomous response circuit #1 (801)" and the required response accuracy.

[0585] The "fuzzy search circuit A (701)" mounted in the "autonomous response circuit #1 (801)" receives inputs from three systems.

[0586] The input of the first system is the output of the first compression circuit (745), that is, the "input signal: 720", and the data that forms the basis of the first compression circuit (745) is the "input data (710)" input from the outside, the data obtained by pre-processing the "input data (710)" input from the outside by the "input signal conversion circuit (715)", or a part of these signals. Which data or signal is used as the "input signal: 720" depends on the implementation method.

[0587] Fig.25 The case where the "input signal conversion circuit (715)" is inserted is shown.

[0588] The input of the second system is the "output (740 and 750) of the data processing circuit (725)". The output of the data processing circuit (725) is generally a signal (750) indicating the status of the "data processing circuit (725)", which is often given a name such as "Status signal" or "Flag signal", and the output after processing by the "data processing circuit (725)", that is, "output data (740)", which can be the "Status signal" in most cases. Fig.25 Both "Output Data (740)" and "Status Signal (750)" are shown as inputs to the second system.

[0589] The input of the third system is a "control signal (785)" input from the outside.

[0590] The "control signal (785)" is essentially the "control signal input (153) from the outside" of the "fuzzy retrieval circuit A (701)", which writes, reads, sets and resets the data of the storage circuit in the "fuzzy retrieval circuit A (701)" and controls the counting circuit.

[0591] In addition, although Fig.25 Although not shown, when the "fuzzy retrieval circuit" of the present invention constitutes the "first compression circuit" and the "second compression circuit", it is necessary to provide an external signal equivalent to the "control signal (153) from the outside" to the "fuzzy retrieval circuit".

[0592] The "fuzzy retrieval circuit A (701)" internally has at least one or more "first storage circuits" of the fuzzy retrieval circuit of the present invention, which compares a combination of a "data group" consisting of a content generated by a "first data compression circuit" based on "input information (720)" input from the outside and a content generated by a "second data compression circuit" based on "response signal 2 (780)" with the content stored inside the "fuzzy retrieval circuit A (701)", outputs the most similar content and the most similar information in the stored "data group" as a "response output (760)", and transmits it to the "memory circuit A (735)".

[0593] That is, the "autonomous response circuit #1 (801)" fuzzily searches the past condition that is most similar to the combination of the "input signal: 710" representing the external condition and the "response signal 2" represented by the output of the "autonomous response circuit #1 (801)" at that moment from the "first storage circuit" in the "fuzzy retrieval circuit A (701)", outputs the response determined to be the most similar "past condition" as the "response output: 760", and instructs the data processing circuit (725) through the memory circuit A (735).

[0594] The information transmission from the "fuzzy search circuit A (701)" to the "memory circuit A (735)" may be a case where the physical address of the "matching determination device" in the "fuzzy search circuit A (701)" is encoded and transmitted to the "memory circuit A (735)", or an installation method in which the physical address of the "matching determination device" is not encoded and each "matching determination device" has an "output data storage circuit (46)". [Claim 19], [Claim 4]

[0595] Thirteenth embodiment of the present invention

[0596] Fig.26 13 is a block diagram schematically showing an “autonomous response circuit # 2 ” according to a thirteenth embodiment of the present invention.

[0597] Fig.26 The block diagram of the fuzzy retrieval circuit is referenced using Fig. 22B The "symbol map" defined in .

[0598] The "autonomous response circuit #2 (802)" is composed of a fuzzy retrieval circuit A (701), a fuzzy retrieval circuit B (702), a fuzzy retrieval circuit C (703), a memory circuit A (735), a memory circuit B (736), a memory circuit C (737) and a synthesis circuit (704).

[0599] Fuzzy search circuit A (701), fuzzy search circuit B (702) and fuzzy search circuit C (703) refer to fuzzy search circuits, search circuits, or content addressable memory circuits exemplified by "fuzzy search circuit #1" to "fuzzy search circuit #8" of the embodiment of the present invention and "consistency determination circuit #1" to "consistency determination circuit #5" of the embodiment of the present invention. Which embodiment is adopted depends on the scale and type of data processed by "autonomous response circuit #1 (801)" and the required response accuracy.

[0600] Memory circuit A (735), memory circuit B (736) and memory circuit C (737) are well-known concepts that take address signals as input and output data, and are memory circuits that have become well-known technologies.

[0601] The data processing circuit (725) is a logic circuit based on known data processing technologies including CPU, MPU, PLA, FPGA, and ASIC, and processes input data and outputs output data based on a program written to an internal memory.

[0602] "Fuzzy retrieval circuit A (701)", "fuzzy retrieval circuit B (702)" and "fuzzy retrieval circuit C (703)" each have at least one or more "first storage circuits" of the fuzzy retrieval circuit of the present invention inside, which compare the combination of information input from the outside with the content stored inside, and output information on which is the most similar content.

[0603] The "synthesis circuit (704)" receives a plurality of inputs and synthesizes data representing a control signal for the "data processing circuit (725)". Specifically, the data is a program start signal, a control code to be sent at this time.

[0604] Data pre-written into the fuzzy search circuit and memory circuit

[0605] In the "fuzzy search circuit A (701)", possible data combinations of the "response signal 2 (780)" and the "input signal (720)" are stored in advance with a certain accuracy or granularity. In addition, in the "memory circuit #A (735)", control signals to be sent to the data processing circuit are stored in advance for each of these combinations.

[0606] In the "fuzzy search circuit B (702)", possible combinations of the "input signal (720)" and the "response signal (760)" are stored with a certain accuracy or granularity. In addition, in the "memory circuit #B (736)", for each of these combinations, the "value expected in the next step regarding the input signal (720)" is stored accordingly.

[0607] In the "fuzzy search circuit C (703)", possible combinations of "input signal (720)" and "values ​​predicted by the fuzzy search circuit B (702) in the next step with respect to the input signal (720)" are stored with a certain accuracy or a certain granularity. In addition, in the "memory circuit #C (737)", "correction values ​​with respect to the output of the fuzzy search circuit A" are stored correspondingly for each of these combinations.

[0608] Action of autonomous response circuit #2

[0609] In this way, the storage data of each fuzzy search circuit and each memory circuit are set, and the following operation is performed.

[0610] First, in step #1,

[0611] On this basis, the "fuzzy search circuit A" is fuzzily searched according to the current "response signal 2 (780)" and the "input signal indicating the external condition (720)". The "fuzzy search circuit A" is activated for the combination with the highest similarity among the input combinations, and a control signal to be sent to the data processing circuit is generated through the "memory circuit #A (735)".

[0612] In step #2, through the "fuzzy search circuit B (702)" and the "memory circuit B (736)", the "input signal expected in the next step" is output based on the past combination of the "input signal (720)" and the "response signal (760)".

[0613] In step #3, through the "fuzzy retrieval circuit C (703)" and the "memory circuit C (737)", based on the combination of the "input signal expected in the next step" and the "input signal actually generated", the difference between the two is understood, and the "differential corresponding control signal (770)" required at this time is generated.

[0614] In step #4, the control signal sent to the "data processing circuit (725)" is synthesized with the control signal that should be sent to the "data processing circuit (725)" inferred by the "fuzzy retrieval circuit A" through the "synthesis circuit (704)" based on the "differential corresponding control signal (770)" determined by the "fuzzy retrieval circuit C (703)".

[0615] Abstract Model of Complex Fuzzy Retrieval Circuit

[0616] FIG. 27 is a block diagram showing a model that abstractly expresses an embodiment of the fuzzy search circuit of the present invention when the systems of the input signal are two systems (system A and system B).

[0617] Since the circuit blocks and signals constituting the fuzzy search circuit of the present invention are very numerous, this model will be used to explain the expansion method of the fuzzy search circuit in the embodiment of the present invention and the maintenance operation of the storage data of each storage circuit.

[0618] The model of FIG27 includes the structure of the fuzzy search circuit in which the input signal system shown in FIG22 is two systems, and further includes a fourth storage circuit (47) Fig.15 The structure of the fuzzy retrieval circuit in.

[0619] The "feedback storage circuit [FB]) in the model of FIG. 27 is equivalent to Fig.15 The “third storage circuit (45)” in FIG.

[0620] Fig.15 The function of the "fuzzy retrieval circuit #4 (14)" in FIG. 27 is equivalent to the "vertical direction output detection circuit (534)" in FIG. 27.

[0621] When the action mode is "counting mode", the signal for fuzzy retrieval is input from the "input signal (system A)" and the "input signal (system B)", and the excitation signal as the fuzzy retrieval result is output from the "output signal (99) of the fuzzy retrieval circuit", and the word of the "fourth storage circuit (47)" is selected based on this signal, and the read output as its content is output as the "output signal (580)".

[0622] The signal that transmits these "input signal (system A)", "input signal (system B)" and "output signal (580)" that are valid in the "counting mode" is called the "fuzzy retrieval bus (891)".

[0623] On the other hand, in the "maintenance mode", based on the "address selection signal 811", the storage data of the storage circuit corresponding to each signal is read or written through the "read-write signal (system A: 821)", "read-write signal (system B: 822)", "signal of the second storage circuit (210)", "read-write signal (FB system: 831)", or "read-write signal of the fourth storage circuit (841)".

[0624] The signal that transmits the "address selection signal (811)", "read-write signal (system A: 821)", "read-write signal (system B: 822)", "second storage circuit signal (210)", "read-write signal (FB system: 831)", and "read-write signal (841) of the fourth storage circuit" that is valid in "maintenance mode" is called the "maintenance bus (892)".

[0625] The control of the "action mode" and the control of the reading and writing actions are performed by the "control circuit", and for this purpose, the "control signal (153)" is input into the control circuit.

[0626] Thus, the actions in the "counting mode" and the actions in the "maintenance mode" use input and output signals of different systems.

[0627] Fourteenth embodiment of the present invention

[0628] Fig.28 29 is a block diagram illustrating an outline of “autonomous response circuit # 4 ” according to the fourteenth embodiment of the present invention. Fig.28 and Fig.29A The block diagram of the fuzzy retrieval circuit is referenced using Fig.27B The "symbol map" defined in .

[0629] Fig.28 It is a block diagram schematically showing an “autonomous response circuit # 4 ” according to a fourteenth embodiment of the present invention.

[0630] The "autonomous response circuit #4" is mainly composed of a "data processing circuit (725)" that has the function of a "measurement mode" for performing fuzzy retrieval operations, a "CPU (871)" that maintains the storage circuits of each fuzzy retrieval circuit, and a "backup memory (872)".

[0631] "Autonomous response circuit #4" is a technology of "expansion of fuzzy retrieval circuit (880)" equipped with multiple fuzzy retrieval circuits. The signals of the input system and the signals of the output system used in the signal transmission under the maintenance mode of these multiple fuzzy retrieval circuits are connected to the maintenance bus.

[0632] In maintenance mode, under the control of "CPU (871)", the data of the storage circuit carried by each fuzzy retrieval circuit [0: (S-1)] is read into the "backup memory (872)", and after the relationship between its physical address and data is optimized, the data is written back to the storage circuit of each fuzzy retrieval circuit.

[0633] In the "measurement mode", the search data is sent from the "data processing circuit (725)" to each fuzzy search circuit [0: (S-1)] through the "fuzzy search bus", and the "excitation" information from these "data processing circuits (725)" is received. In the case of responding to multiple excitation information, the earliest response has the highest similarity.

[0634] The connection method between fuzzy retrieval circuit and bus

[0635] Figure 29 shows that Fig.28 The details of "the connection between the fuzzy retrieval circuit and the maintenance bus and the fuzzy retrieval bus" are omitted.

[0636] When the fuzzy search circuit is connected to the maintenance bus, by interposing the register and the FIFO, the fuzzy search circuit outputs the output data to the maintenance bus only when the maintenance bus is idle.

[0637] Likewise, when the fuzzy search circuit is connected to the fuzzy search bus, by interposing the register and the FIFO, the fuzzy search circuit outputs output data to the fuzzy search bus only when the fuzzy search bus is idle.

[0638] Since the maintenance bus and the fuzzy search bus both constitute a ring bus that transfers data in only one direction, each register can be operated at a high speed.

[0639] Fifteenth embodiment of the present invention

[0640] Fig.30 The "autonomous response circuit #4" according to the fifteenth embodiment of the present invention will be described.

[0641] Fig.30 This is an example showing the outline of an algorithm of “autonomous response circuit #4” representing the fifteenth embodiment of the present invention.

[0642] By conducting Fig.28 As for the “expansion of the fuzzy retrieval circuit” shown in FIG. 29 , the output data can be sent to the “fuzzy retrieval circuit + fourth storage circuit” of the destination address recorded in the “fourth storage circuit”, so that the data can be autonomously sent to multiple fuzzy retrieval circuits according to the data of each storage circuit.

[0643] The fuzzy retrieval circuit in the block diagram is referenced using Fig. 22B The "symbol map" defined in .

[0644] For example, in Fig.30In the case of the algorithm of the "autonomous response circuit #4" of the fifteenth embodiment of the present invention, a plurality of input data (710) are sent to the "fuzzy search circuit A (701)" and the "fuzzy search circuit B (702)" via each "input signal conversion circuit (715)" and each "first data compression circuit (745)". Fig.29B The schematic diagram corresponds to the following actions: data from the "data processing circuit (725") is input to the fuzzy retrieval circuit A (701), fuzzy retrieval circuit B (702) and fuzzy retrieval circuit C (703) via the "CPU, backup memory, synthesis circuit, IO circuit (881)" through the ring bus.

[0645] Since the destination address of the output data is also stored in memory circuit A, memory circuit B and memory circuit C, the destination of the output of each of memory circuit A, memory circuit B and memory circuit C is other fuzzy retrieval circuits in the ring bus, or "CPU, backup memory, synthesis circuit, IO circuit (881)".

[0646] When the fuzzy search process is completed, the result is returned to the "data processing circuit (725)" via the "CPU, backup memory, synthesis circuit, IO circuit (881)".

[0647] Industrial Applicability

[0648] The present invention is very different from the existing electronic circuit technology in that data is sent to the memory matrix in the form of a "time series of pulse signals" and the memory matrix is ​​used as a data conversion circuit. Therefore, for practical use, it is necessary to wait for the emergence of some related technologies.

[0649] The advantage of serial communication is that the number of wires is small, but on the other hand, it has a disadvantage that the processing speed of the entire circuit is slowed down because the delay time required for data transmission increases.

[0650] In the technical method of the present invention, transmitting data in the form of "time series of pulse signals" may also be a disadvantage in terms of delay and processing speed, but by "full parallelization of the inner product calculation between the stored data and the input data in a very parallel manner in the memory chip" and "integration of the storage circuit and the operation circuit" to compensate for this disadvantage, the advantages will outweigh the disadvantages. The balance of advantages and disadvantages can of course depend on the application, but in applications such as artificial intelligence that require constant mobilization of stored data, it is considered to be very advantageous.

[0651] In electronic circuits, the logical causal relationship between input data and output data has been completely clear in the past, but the "fuzzy search" of the present invention, or fuzzy data processing, has become a fundamental challenge in the industrial-based culture. This may also be an obstacle to conservative applications because it requires the emergence of some related technologies.

[0652] However, electronic circuits have always been a challenge to the capabilities of the human brain. In addition, due to the increase in the number of random processes in many applications that have developed rapidly in recent years and the increasing number of situations that require uncertain predictions and anticipations, the challenges faced by the practical use of the present invention can be said to be an obstacle that cannot be avoided and needs to be overcome for the evolution and deepening of all future electronic circuit technologies.

[0653] This technology is the development direction of future electronic circuit technology.

Claims

1. A fuzzy retrieval circuit, characterized in that: have: Multiple (n groups) of consistency determination circuits, The consistency determination circuit comprises: A first storage circuit (40) having a plurality of memory cells (10) arranged in a matrix having at least m columns x k rows, where m is an integer greater than 2 and k is an integer greater than 2; m or m pairs of activation signal input lines (90) which transmit a signal input from the outside to the memory unit; k detection lines (70) which conduct current when the memory cell is activated; A counting circuit (207) having a function of multiplying information related to the number of signals transmitted from each of the detection lines by a weighting coefficient preset for each detection line, calculating the sum and outputting the result; A second storage circuit (200) storing threshold information for determining the number information; as well as A determination circuit (290), Wherein, within a specified time, the counting circuit generates information of the number of pulse signals that conduct to each of the detection lines via the signal of the activation signal input line transmitted to the memory unit of the first storage circuit and multiplied by a weighting coefficient preset for each detection line and then summing the information, and transmits at least a part of the information to the determination circuit at any time, Thus, it is determined in sequence whether the similarity between the input data represented by the time series of the activation signal input from the outside and the storage data of the first storage circuit is higher or lower than the threshold information stored in the second storage circuit, and when it is higher than the threshold information, an excitation signal representing the result is output from the determination circuit. In which, the fuzzy retrieval circuit outputs a group of outputs from each consistency judgment circuit by inputting a common serial pulse signal information into the activation signal input line of each consistency judgment circuit, and sequentially outputs information indicating which consistency judgment circuit exceeds the threshold set in the second storage circuit, or which consistency judgment circuit's first storage circuit has storage information most similar to the information of the numerical group represented by the input signal group (90[0:m-1]).

2. The fuzzy search circuit according to claim 1, characterized in that: The fuzzy search circuit further comprises at least a vertical output detection circuit (534) and a control circuit (119). When the vertical output detection circuit (534) detects that a signal indicating a high similarity is sent from any one of the consistency determination circuits, The count value of the counting circuit (207) is reset to an initial value, or the count value of the counting circuit is reduced by a certain amount.

3. The fuzzy search circuit according to claim 1, characterized in that: The fuzzy search circuit further comprises at least a timing circuit (116) and a control circuit (119). When the timing circuit sends a signal indicating that the operation of the fuzzy search circuit has elapsed for a predetermined time, The count value of the counting circuit (207) is reset to an initial value, or the count value of the counting circuit is reduced by a certain amount.

4. The fuzzy search circuit according to claim 1, characterized in that: The initial value of the counter circuit (207) is set to a value generated by the data of the second storage circuit (200).

5. The fuzzy search circuit according to claim 1, characterized in that: The fuzzy search circuit further comprises a pulse generating circuit (535) in each of the consistency determination circuits. When the determination circuit of the consistency determination circuit performs an excitation output, a pulse signal is generated to replace the excitation signal of the determination circuit, and the output of the pulse generating circuit is used as the output of the consistency determination circuit.

6. The fuzzy search circuit according to claim 5, characterized in that: The pulse generating circuit (535) provided in each of the consistency determination circuits further receives the storage value of the second storage circuit (200) as input. When the determination circuit (290) of the consistency determination circuit outputs an excitation signal, a pulse signal having a number based on the storage value of the second storage circuit (200) is generated to replace the excitation signal of the determination circuit, and the output of the pulse generating circuit is output as the output of the fuzzy retrieval circuit.

7. A fuzzy retrieval circuit, characterized in that ， The fuzzy search circuit according to claim 1 further comprises: A pulse generating circuit (535) receiving the storage value of the second storage circuit (200) as an input signal; A vertical output detection circuit (534); as well as a control circuit (118), When the vertical output detection circuit detects that any one of the determination circuits of the consistency determination circuit has issued an excitation signal, Decrease the count value of the counting circuit by a certain amount, and The pulse generating circuit of the match degree determination circuit outputs a pulse signal of a number of times corresponding to the storage value of the second storage circuit as an output of the match degree determination circuit.

8. A fuzzy search circuit, characterized in that ， The fuzzy search circuit according to claim 1 further comprises: The activation line signal generating circuit (156) generates a time series of output pulse signals in a manner that pulses are not superimposed on each other based on information of a plurality of external input signals (80[0] to 80[z-1]). The output of the activation line signal generating circuit is used as the activation signal (90).

9. A fuzzy retrieval circuit, characterized in that ， The fuzzy search circuit according to claim 1 further comprises: A control circuit (118, 119 or 120) having a function of switching the operation mode of each of the consistency determination circuits to a setting mode (first operation mode), a counting mode (second operation mode) or a read / write mode based on an external control signal input (153), Wherein, in the setting mode, the pulse signal transmitted through the activation signal input line or the word line is sequentially applied to the first storage circuit (40), and based on the number of pulse signals transmitted through the detection line (70), the number of memory cells with a value of 1 or a value of 0 in the first storage circuit is counted by the counting circuit (207), and a value generated based on the value is written into the second storage circuit (200), In the counting mode, the pulse signals transmitted through the activation signal input line or the word line are sequentially applied to the first storage circuit (40), the counting circuit (207) is used to count the number of pulse signals transmitted through the detection line (70), and the determination circuit (290) is used to compare the value generated based on the value with the value stored in the second storage circuit, thereby outputting an excitation signal indicating a high degree of similarity with the stored data of the first storage circuit, In the read-write mode, a reading or writing operation is performed on data stored in at least a portion of the first storage circuit (40), the second storage circuit (200), and the excitation unit (530).

10. A fuzzy retrieval circuit, characterized in that ， The counting circuit according to claim 9 includes a shift register circuit or a counter circuit inside. According to the control signal of the control circuit, In the setting mode, first, the shift register circuit or the counter circuit is reset to a predetermined reset value and starts operation, and the counting circuit is made to perform counting operation in ascending order (or descending order), and a value generated based on a count value of the number of pulse signals transmitted from the detection line (70) is written into the second memory circuit (200), In the count mode, first, by writing a value generated based on the value stored in the second memory circuit into the shift register circuit or the counter circuit, a counting operation is performed in descending order (or ascending order) opposite to the setting mode.

11. The fuzzy search circuit according to claim 10, characterized in that: The reset value is a binary number in which all digits are 0 or 1.

12. A fuzzy retrieval circuit, characterized in that ， The consistency determination circuit of the fuzzy search circuit according to claim 10 further comprises: a third storage circuit (45) composed of a plurality of second activation signal lines (91), a plurality of second detection lines (71) and a plurality of unit storage circuits (55); A plurality of detection line current reading circuits (101); and the driving circuit (155[1]) of the second activation signal line, When counting the number of pulses of the signal that the memory unit (10) of the first storage circuit (40) conducts to the detection line (70) via the activation signal input line (90), The counting circuit (207) A signal generated by the output of a detection line current reading circuit (101) using as a reference current an on-current caused by the memory cell (10) of the second storage circuit (55) in the second detection line (71) via the second activation signal line (91) is used.

13. A fuzzy retrieval circuit, characterized in that ， The consistency determination circuit of the fuzzy search circuit according to claim 12 further comprises: a plurality of second detection line current reading circuits (102) paired with the plurality of detection line current reading circuits (101), and a second counting circuit (206), The consistency determination circuit includes: when counting the number of pulses of the signal that the memory unit (10) of the first storage circuit (40) conducts to the detection line (70) via the activation signal input line (90), the counting circuit (207) counts, When counting the number of pulses of the signal that the memory unit (10) of the second storage circuit (55) conducts to the second detection line (71) via the second activation signal line (91), the counting circuit (206) counts, and, As an input value of the shift register circuit (202) or an input value of the counter circuit (560), a difference between an accumulated number of the counting circuit (207) and an accumulated number of the counting circuit (206) is used.

14. A fuzzy retrieval circuit, characterized in that ， The fuzzy search circuit according to claim 1 further comprises: A physical address encoding circuit (591), When any one of the match degree determination circuits outputs a signal indicating that the similarity is high, the physical address of the match degree determination circuit that issued the output is output.

15. A fuzzy retrieval circuit, characterized in that: A plurality of the fuzzy search circuits according to claim 1 are provided, and the output and the input are connected in series with each other, and All or part of the output of the fuzzy search circuit at the subsequent stage is used as all or part of the input signal of the fuzzy search circuit at the preceding stage.

16. A fuzzy retrieval circuit, characterized in that ， The fuzzy search circuit according to claim 9 performs the operation of the setting mode at a predetermined frequency.

17. A fuzzy retrieval circuit, characterized in that ， The consistency detection circuit mounted in the fuzzy search circuit according to claim 1 further comprises a storage circuit (813) of at least one bit for blank setting, and When the coincidence detection circuit is not used, the operation of the coincidence detection circuit is stopped by setting the storage circuit for blank setting, and the signal indicating activation is not forcibly output from the determination circuit (290).

18. A data processing circuit, characterized in that: The operation of the program is controlled by the fuzzy search circuit according to claim 1.

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