Group III nitride-based transistor devices

Abstract

A transistor device based on group III nitrides is provided, which has a gate-drain capacitance (C GD ), drain-source capacitance (C) DS ) and drain-source on-resistance (RDSon). Drain-source voltage (V DS The gate-drain capacitance (C) when it is 0V GD That is, C GD (0V) and V DS Gate-drain capacitance C when the value is >0V GD That is, C GD The ratio of V is at least 3:1, where V DS Less than 15V.

Description

Background Technology

[0001] To date, transistors used in power electronics applications have typically been fabricated using silicon (Si) semiconductor materials. Common transistor devices for power applications include Si CoolMOS®, Si power MOSFETs, and Si insulated-gate bipolar transistors (IGBTs). Recently, silicon carbide (SiC) power devices have been considered. Group III-N semiconductor devices, such as gallium nitride (GaN) devices, are now emerging as attractive candidates for carrying high currents, supporting high voltages, and providing extremely low on-resistance and fast switching times.

[0002] Gallium nitride (GaN) devices are also attractive candidates for power amplifiers used in communication systems. In terms of efficiency and power density, group III-nitride materials offer advantages over silicon-based devices, such as high breakdown field strength, saturation velocity, and low field mobility.

[0003] However, further improvements to group III nitride-based devices are desirable. High 2DEG density (resulting in low Rdson and high saturation current) leads to high parasitic capacitances (e.g., gate-drain capacitance C). GD This can have undesirable effects, especially for RF applications. The challenge is to minimize parasitic capacitance just below the operating voltage without reducing the 2DEG density. Summary of the Invention

[0004] According to the present invention, a group III nitride-based transistor device includes a source electrode, a drain electrode, and a gate electrode located on a first main surface of a group III nitride-based base layer, wherein the gate electrode is laterally disposed between the source electrode and the drain electrode. The group III nitride-based transistor device further includes a field plate laterally disposed between and spaced apart from the gate electrode and the drain electrode.

[0005] In some embodiments, the bottom of the gate electrode has a width of 50 nm to 500 nm, or 30 nm to 350 nm, for example, about 250 nm, and the distance between the gate electrode and the field plate at the closest point is 30 nm to 500 nm, or 30 nm to 350 nm, for example, about 250 nm. In some embodiments, both the bottom of the gate electrode and the bottom of the field plate have a width of 200 nm to 350 nm, for example, about 250 nm, and the distance between the gate electrode and the field plate at the closest point is 200 nm to 350 nm, for example, about 250 nm.

[0006] In some embodiments, group III nitride-based transistor devices have a gate-drain capacitance (C0). GD), drain-source capacitance (C) DS ) and drain-source on-resistance (RDSon). In some embodiments, drain-source voltage (V DS The gate-drain capacitance (C) when it is 0V GD That is, C GD (0V) and V DS Gate-drain capacitance C when the value is >0V GD That is, C GD The ratio of V is at least 2:1, or at least 6:1, where V DS Less than 20V. In some embodiments, the gate-drain capacitance (C) GD The ratio of V to V is at least 3:1, where V DS Less than 15V.

[0007] In some embodiments, V DS C at 0V GD The value of V DS Voltage at 0 <V DS C within the range of <15V GD The ratio of values ​​greater than 2.5, and / or V DS C at 0V GD The value of V DS Voltage at 0 <V DS C within the range of <15V GD The ratio of values ​​is greater than 4, and / or V DS C at 0V GD The value of V DS Voltage at 0 <V DS C within the range of <15V GD The ratio of values ​​greater than 5, and / or V DS C at 0V GD The value of V DS Voltage at 0 <V DS C when the voltage is less than 12V GD The ratio of values ​​is greater than 3, and / or V DS C at 0V GD The value of V DS Voltage at 0 <V DS C in the range of <20V GD The ratio of values ​​greater than 6, and / or V DS C at =0V GD The value of V DS Voltage at 0 <V DS C when the voltage is less than 12V GD The ratio of values ​​is greater than 10, and / or V DS C at 0V GD The value of V DSVoltage at 0 <V DS C in the range of <10V GD The ratio of the values ​​is greater than 15.

[0008] In some embodiments, a group III nitride-based transistor device includes: a source electrode, a drain electrode, and a gate electrode located on a first main surface of a group III nitride-based base layer, wherein the gate electrode is laterally disposed between the source electrode and the drain electrode; a passivation layer disposed on the first main surface; and a field plate electrically connected to the source electrode, the field plate having a lower surface disposed on the passivation layer, the field plate being laterally disposed between the gate electrode and the drain electrode and spaced laterally from the gate electrode and the drain electrode. The group III nitride-based transistor device has a gate-drain capacitance (C0). GD ), drain-source capacitance (C) DS ) and drain-source on-resistance (RDSon). Drain-source voltage (V DS The gate-drain capacitance (C) when it is 0V GD That is, C GD (0V) and V DS Gate-drain capacitance C when the value is >0V GD That is, C GD The ratio of V is at least 3:1, where V DS Less than 15V.

[0009] In some embodiments, in V DS dC within a subrange of values GD / dV DS Less than -10 fF / mm / V, with a subrange of values ​​greater than 100 mV, and within which 5 V <V DS <20V, preferably 5V <V DS In some embodiments, within the range of VDS <15V. DS dC within a subrange of values GD / dV DS Less than -15 fF / mm / V, with a subrange of values ​​greater than 100 mV. In some embodiments, at V DS dC within a subrange of values GD / dV DS Less than -30 fF / mm / V, with a sub-value range greater than 100 mV. In these embodiments, there are gate-drain capacitances C at voltages significantly lower than the device's operating voltage. DG A sharp decrease in the value.

[0010] A high saturation current Idssat is achieved. In some embodiments, Idssat is at least 300 mA / mm, or at least -400 mA / mm up to 1 A / mm.

[0011] Gate-drain capacitance C GD It may be low, and in the range of 20 fF / mm to 30 fF / mm, for example, at ns = 8.6e 12 cm -2 In some cases, the value is 30 fF / mm. In some embodiments, C is at low voltages of 20V, 15V, or even 10V. GD Less than 100 fF / mm. In some embodiments, C is at a low voltage of 20V, 15V, or even 10V. GD Less than 50 fF / mm.

[0012] In some embodiments, Rdson is less than 10 ohm*mm, or less than 5 ohm*mm, or less than 3.2 ohm*mm.

[0013] In some embodiments, a group III nitride-based transistor device includes a gate-source capacitor C. GS And C under the value of VDS GS / C DS Greater than 2 or greater than 3 or greater than 5, where V DS Less than 20V.

[0014] In some embodiments, the passivation layer has a thickness d FP This ensures that the field plate and the conductive channel are spaced at a certain distance, thereby increasing the drain-source voltage (V). DS The gate-drain capacitance (C) when it is 0V GD That is, C GD (0V) and V DS Gate-drain capacitance C when the value is >0V GD That is, C GD The ratio of V is greater than 3:1, or at least 5:1, where V DS Less than 15V.

[0015] In some embodiments, the passivation layer has a thickness d FP This ensures that the field plate and the conductive channel are spaced at a certain distance, so that V DS C at 0V GD The value of V DS Voltage at 0 <V DS C within the range of <15V GD The ratio of the values ​​is greater than 3, and / or makes V DS C at 0V GD The value of V DS Voltage at 0 <V DS C within the range of <15V GD The ratio of the values ​​is greater than 4, making V DSC at 0V GD The value of V DS Voltage at 0 <V DS C within the range of <15V GD The ratio of the values ​​is greater than 5, and / or makes V DS C at 0V GD The value of V DS Voltage at 0 <V DS C when the voltage is less than 12V GD The ratio of the values ​​is greater than 3, and / or makes V DS C at 0V GD The value of V DS Voltage at 0 <V DS C in the range of <10V GD The ratio of the values ​​is greater than 5, and / or makes V DS C at 0V GD The value of V DS Voltage at 0 <V DS C in the range of <20V GD The ratio of the values ​​is greater than 6.

[0016] Since high-resistivity semiconductors can act as dielectrics, in some embodiments, the distance between the metal field plate and the two-dimensional charge gas is chosen based on the dielectric constant of the material between the metal field plate and the two-dimensional charge gas (i.e., the material of the passivation layer and the semiconductor material in between), such that the drain-source voltage (V0) is such that... DS The gate-drain capacitance (C) when it is 0V GD That is, C GD (0V) and V DS Gate-drain capacitance C when the value is >0V GD That is, C GD The ratio of V is greater than 3:1, or at least 4:1, or at least 5:1, where V DS Less than 15V, and / or make V DS C at 0V GD The value of V DS Voltage at 0 <V DS C when the voltage is less than 12V GD The ratio of the values ​​is greater than 3, and / or makes V DS C at 0V GD The value of V DS Voltage at 0 <V DS C in the range of <10V GD The ratio of the values ​​is greater than 5, and / or makes V DS C at 0V GD The value of V DS Voltage at 0 <V DSC in the range of <20V GD The ratio of the values ​​is greater than 6.

[0017] In some embodiments, the dielectric constant of the material between the field plate and the first main surface, divided by the distance between the lower surface of the field plate and the first main surface, is 5e. -8 F / cm 2 and 1e -6 F / cm 2 between.

[0018] In some embodiments, the thickness d of the passivation layer between the lower surface of the field plate and the first main surface... FP For wavelengths below 110 nm or 10 nm ≤ d FP ≤ 110 nm, or less than 60 nm, or 10 nm ≤ d FP ≤ 60 nm.

[0019] In some embodiments, the passivation layer is made of SiN x form.

[0020] In some embodiments, the passivation layer is formed of an amorphous insulating material.

[0021] In some embodiments, the passivation layer is formed of a material with a higher dielectric constant than silicon dioxide (also known as a "high-k" dielectric), such as hafnium-based or zirconium-based dielectric materials, such as hafnium silicate, hafnium dioxide, zirconium silicate, and zirconium dioxide. This allows for increasing the thickness d of the passivation layer between the lower surface of the field plate and the first main surface. FP This helps to prevent leakage and improve the reliability of these thin passivation layers.

[0022] In some embodiments, the bottom of the gate electrode has a width of 30 nm to 500 nm, or 30 nm to 350 nm, or 30 nm to 250 nm, and in some embodiments has a width of approximately 250 nm or less, and the distance d between the gate electrode and the field plate at the closest point is... GF For 30 nm to 500 nm or 30 nm to 350 nm or 30 nm to 250 nm or 80 nm to 350 nm, or 80 nm to 250 nm or 100 nm and 350 nm or 100 nm to 250 nm.

[0023] In some embodiments, the bottom of the gate electrode has a width of 30 nm to 500 nm, or 30 nm to 350 nm, or 30 nm to 250 nm, and the lower surface of the field plate has a width of 30 nm to 1000 nm, and the distance d between the gate electrode and the field plate at the closest point is... GFFor 30 nm to 350 nm or 30 nm to 350 nm or 30 nm to 250 nm or 80 nm to 350 nm, or 80 nm to 250 nm or 100 nm and 350 nm or 100 nm to 250 nm.

[0024] In some embodiments, the bottom of the gate electrode and the lower surface of the field plate both have a width of 30 nm to 500 nm, or 30 nm to 350 nm, or 30 nm to 250 nm, and in some embodiments have a width of approximately 250 nm or less, and the distance d between the gate electrode and the field plate at the closest point is... GF The range is from 30 nm to 500 nm, for example, about 250 nm or smaller.

[0025] Because for lower values, the gate-source capacitance C GS The lower limit of dGF can be increased to 80 nm or 100 nm, thus increasing the distance d between the gate electrode and the field plate at the closest point. GF It can be in the range of 80 nm to 500 nm, or 100 nm to 500 nm.

[0026] Since the current gain h21 decreases with a greater distance between the gate electrode and the field plate, the distance d between the gate electrode and the field plate at the closest point is therefore reduced. GF The upper limit can be reduced to 350 nm or 250 nm, thus d GF It is within the range of 30 nm to 350 nm or 30 nm to 250 nm. In some embodiments, d GF It is within the range of 80 nm to 350 nm, or 80 nm to 250 nm, or 100 nm and 350 nm, or 100 nm to 250 nm.

[0027] In some embodiments, a group III nitride-based transistor device includes a maximum stable gain (MSG) at frequency f and a current gain h21 measured under predetermined conditions, or a maximum available gain (MAG) at frequency f and a current gain h21 measured under predetermined conditions, wherein the ratio MSG / h21 2 >6dB, or >7dB, or >8dB, or the ratio MAG / h21 2 >6dB, or >7dB, or >8dB. MSG / h21 in dB. 2 The ratio is limited to 10·log 10 (MSG / h21 2 ).

[0028] In some embodiments, the group III nitride-based transistor device includes a maximum stable gain (MSG) greater than 26 dB measured at a frequency of 4 GHz and a ratio MSG / h21 2 >6dB, or >7dB, or >8dB.

[0029] In some embodiments, the group III nitride-based transistor device includes a maximum usable gain (MAG) greater than 26 dB measured at a frequency of 4 GHz and a ratio MAG / h21 2 >6dB, or >7dB, or >8dB.

[0030] In some embodiments, the group III nitride-based transistor device includes a maximum stable gain (MSG) greater than 12 dB measured at a frequency of 28 GHz and a ratio MSG / h21 2 >7dB, or >10dB, or >13dB.

[0031] In some embodiments, the group III nitride-based transistor device includes a maximum usable gain (MAG) greater than 12 dB measured at a frequency of 28 GHz and a ratio MAG / h21 2 >7dB, or >10dB, or >13dB.

[0032] In some embodiments, the field plate includes one or more conductive vias that extend substantially perpendicular to the first main surface and are electrically connected to the source electrode via a lateral field plate redistribution structure that extends over and is spaced apart from the gate electrode.

[0033] In some embodiments, the source electrode, gate electrode, drain electrode, and field plate all have elongated shapes and extend substantially parallel to each other in the longitudinal direction on the first main surface.

[0034] In some embodiments, the lateral field plate redistribution structure includes a longitudinal segment located above the field plate and extending substantially parallel to the longitudinal direction, and a plurality of transverse segments spaced apart in the longitudinal direction, each transverse segment extending above and spaced apart from the gate electrode and electrically connected to the field plate through conductive vias.

[0035] In some embodiments, the group III nitride-based transistor device further includes a lateral gate redistribution structure, the lateral gate redistribution structure including a plurality of gate traversal segments, each gate traversal segment being spaced apart from the gate electrode and electrically connected to the gate electrode through a conductive via, the gate traversal segments of the lateral gate redistribution structure being interleaved with the traversal segments of the lateral field plate redistribution structure.

[0036] One or more gate traversing segments of the lateral gate distribution structure extend substantially perpendicular to the length of the elongated strip-shaped gate electrode, and in embodiments comprising two or more segments, are spaced apart along the length of the gate electrode. In some embodiments, one or more gate traversing segments of the lateral gate distribution structure are arranged in the same plane as the traversing segments of the lateral field plate redistribution structure, and are spaced apart from and extend substantially parallel to the traversing segments of the lateral field plate redistribution structure.

[0037] The gate traversal section of the lateral gate distribution structure and the traversal section of the lateral field plate distribution structure are arranged above the active region of the III-nitride-based transistor device within the length of the strip-shaped source and drain electrodes.

[0038] In some embodiments, the source electrode is electrically connected to a lateral field plate redistribution structure.

[0039] In some embodiments, the group III nitride-based transistor device further includes a source redistribution structure extending in the longitudinal direction, and the source redistribution structure is disposed above and spaced apart from the source electrode, wherein the source electrode is electrically connected to the source redistribution structure through one or more conductive vias, and the source redistribution structure is integral with the transverse section of the field plate redistribution structure.

[0040] In some embodiments, the longitudinal section of the transverse field plate redistribution structure is wider in the transverse direction than the conductive via and the field plate.

[0041] In some embodiments, the field plate is divided into two field plate segments that extend substantially parallel to each other and are laterally spaced apart from each other. These two field plate segments are laterally arranged between and spaced apart from the gate electrode and the drain electrode.

[0042] In some embodiments, a group III nitride-based transistor device is provided, comprising: a first passivation layer disposed on a first main surface of a group III nitride-based base layer; a second passivation layer disposed on the first passivation layer; a source ohmic contact, a drain ohmic contact, and a gate located on the first main surface of the group III nitride-based base layer, wherein the gate is laterally disposed between the source ohmic contact and the drain ohmic contact, and includes a gate via extending to the upper surface of the second passivation layer. The group III nitride-based transistor device further comprises a field plate laterally disposed between and spaced from the gate and drain ohmic contacts, and extending to the upper surface of the second passivation layer. The transistor device based on group III nitrides further includes: a first via extending from the source ohmic contact to the upper surface of the second passivation layer; a second via extending from the drain ohmic contact to the upper surface of the second passivation layer, wherein the second passivation layer covers the outer peripheral regions of the source ohmic contact and the drain ohmic contact; and a substantially flat first insulating layer disposed on the upper surface of the second passivation layer and disposed on the outer peripheral regions of the gate electrode, the field plate, the first via, and the second via.

[0043] In some embodiments, the bottom of the gate electrode has a width of 30 nm to 500 nm, and the distance d between the gate electrode and the field plate at the closest point is... GF The range is from 30 nm to 500 nm.

[0044] In some embodiments, the bottom of the gate electrode has a width of 30 nm to 500 nm, and the lower surface of the field plate has a width of 30 nm to 1000 nm, and the distance d between the gate electrode and the field plate at the closest point is... GF The range is from 30 nm to 350 nm.

[0045] In some embodiments, the bottom of the gate electrode and the bottom of the field plate both have a width of 50 nm to 400 nm, or 200 nm to 350 nm, such as about 250 nm, and the distance between the gate electrode and the field plate at the closest point is 100 nm to 400 nm, or 200 nm to 350 nm, such as about 250 nm.

[0046] In some embodiments, the source ohmic contact includes a bottom portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and having different compositions.

[0047] In some embodiments, the first through-hole is located on the central portion of the conductive surface.

[0048] In some embodiments, the drain ohmic contact includes a bottom portion having a conductive surface, the conductive surface including an outer peripheral portion and a central portion, the outer peripheral portion and the central portion being substantially coplanar and having different compositions.

[0049] In some embodiments, the second via is located on the central portion of the conductive surface.

[0050] In some embodiments, the central portion comprises TiN, and the outer peripheral portion comprises aluminum, aluminum-copper, or titanium-aluminum alloy.

[0051] In some embodiments, the bottom of the field plate is in direct contact with the first passivation layer, the bottom of the gate via is in direct contact with the first main surface, the source ohmic contact extends at least partially through the first passivation layer, and the drain ohmic contact extends at least partially through the first passivation layer.

[0052] In some embodiments, the field plate extends substantially perpendicular to the first main surface and is electrically connected to the source electrode via a lateral field plate redistribution structure that extends above and is spaced apart from the gate electrode.

[0053] In some embodiments, the source electrode, gate electrode, drain electrode, and field plate all have elongated shapes and extend substantially parallel to each other in the longitudinal direction on the first main surface.

[0054] In some embodiments, the lateral field plate redistribution structure includes a longitudinal segment located above the field plate and extending substantially parallel to the longitudinal direction, and a plurality of transverse segments spaced apart in the longitudinal direction, each transverse segment extending above and spaced apart from the gate electrode and electrically coupled to the field plate through a field plate conductive via.

[0055] In some embodiments, the group III nitride-based transistor device further includes a lateral gate redistribution structure, the lateral gate redistribution structure including a plurality of gate traversing segments extending substantially perpendicular to the longitudinal direction, each gate traversing segment being spaced apart from the gate electrode and electrically connected to the gate electrode through a gate conductive via, the gate traversing segments of the lateral gate redistribution structure being interleaved with the traversing segments of the lateral field plate distribution structure.

[0056] In some embodiments, the source electrode is electrically connected to a lateral field plate redistribution structure.

[0057] In some embodiments, one or more gate traversal segments of the lateral gate distribution structure are arranged in the same plane as the traversal segments of the lateral field plate redistribution structure, and are spaced apart from and extend substantially parallel to the traversal segments of the lateral field plate redistribution structure. The gate traversal segments of the lateral gate distribution structure and the traversal segments of the lateral field plate distribution structure are arranged over the active region of the group III nitride-based transistor device within the length of the strip-shaped source and drain electrodes.

[0058] In some embodiments, the group III nitride-based transistor device further includes a source redistribution structure extending in the longitudinal direction, and the source redistribution structure is disposed above and spaced apart from the source electrode, wherein the source electrode is electrically connected to the source redistribution structure through one or more source conductive vias, and the source redistribution structure is integral with the transverse section of the field plate redistribution structure.

[0059] The source redistribution structure can be arranged in the same plane as the gate redistribution structure and the field redistribution structure.

[0060] In some embodiments, the longitudinal section of the transverse field plate redistribution structure is wider than the field plate in the transverse direction.

[0061] In some embodiments, the field plate is divided into two field plate segments that extend substantially parallel to each other and are laterally spaced apart from each other. These two field plate segments are laterally arranged between and spaced apart from the gate electrode and the drain electrode.

[0062] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and viewing the accompanying drawings. Attached Figure Description

[0063] The elements in the accompanying drawings are not necessarily proportional to each other. The same reference numerals indicate corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Exemplary embodiments are depicted in the accompanying drawings, and exemplary embodiments are described in detail below.

[0064] Figure 1a The figure shows a cross-sectional view of a group III nitride-based transistor device according to an embodiment. Figure 1b The diagram shows its plan view.

[0065] Figure 2 Figure a illustrates the DC output characteristics of a (0.2 × 2 × 240) μm transistor with and without a deeply scaled field-plate (DSFP) at VDS = 15V. Figure 2Figure b illustrates its DC input characteristics.

[0066] Figure 3 Figure a illustrates the breakdown characteristics of a (0.2×2×240)μm transistor with and without depth scaling in a field plate (DSFP). Figure 3 Figure b shows the drain hysteresis double-pulse measurement.

[0067] Figure 4 The diagram (a) illustrates the open-state capacitance CGD with and without a field plate (DSFP) with depth scaling. Figure 4 (b) shows the disconnected state capacitor CDS with and without a depth-scaled field plate (DSFP). The pinch-off voltage of the field plate with the source connected is 10V.

[0068] Figure 5 The illustration shows the small-signal behavior of (0.2×2×240)μm transistors with and without depth scaling field plates (DSFP), demonstrating a significant gain improvement for field plate devices.

[0069] Figure 6 The figure shows the gate-drain capacitance C in pF / mm for different passivation layer thicknesses. GD A line graph of the ratio.

[0070] Figure 7a illustrates the situation with Figure 7c The figure shows a line graph of the MAG, MSC, and h21 measurements of the transistor structure. Figure 7b The diagram is for those with Figure 7c MSG / h21 of the transistor structure with dimensions shown in the figure 2 and MAG / h21 2 Line graph. Detailed Implementation

[0071] In the following detailed description, reference is made to the accompanying drawings, which form a part herein, and which illustrate specific embodiments in which the invention may be practiced. In this regard, directional terms such as “top,” “bottom,” “front,” “rear,” “forward,” “end,” etc., are used to indicate orientation with reference to the described figures(s). Because components of the embodiments may be positioned in many different orientations, these directional terms are used for illustrative purposes and are by no means limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. The following detailed description of the invention is not intended to be limiting, and the scope of the invention is defined by the appended claims.

[0072] Many exemplary embodiments will be explained below. In this context, the same structural features in the figures are identified by the same or similar reference numerals. In the context of this description, “lateral” or “lateral direction” should be understood to mean a direction or extension generally parallel to the lateral extension of the semiconductor material or semiconductor carrier. Thus, the lateral direction generally extends parallel to these surfaces or sides. In contrast, the term “vertical” or “vertical direction” is understood to mean a direction generally perpendicular to these surfaces or sides and therefore perpendicular to the lateral direction. Thus, the vertical direction travels in the thickness direction of the semiconductor material or semiconductor carrier.

[0073] As used in this specification, when an element such as a layer, region, or substrate is referred to as being "on" or extending "on" another element, it may be directly on or directly extending onto the other element, or there may be intermediate elements present. In contrast, when an element is referred to as being "directly on" or "directly extending" onto another element, no intermediate elements are present.

[0074] As used in this specification, when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements exist.

[0075] As used herein, the term "Group III nitride" refers to a compound semiconductor comprising nitrogen (N) and at least one Group III element, including aluminum (Al), gallium (Ga), indium (In), and boron (B), and including, but not limited to, any of their alloys, such as, for example, aluminum gallium nitride (Al). x Ga (1-x) N), Indium gallium nitride (In) y Ga (1-y) N), aluminum indium gallium nitride (Al) x In y Ga (1-x-y) N), gallium arsenide phosphide (GaAs) a P b N (1-a-b) ) and aluminum indium gallium arsenide phosphide (Al x In y Ga (1-x-y) As a P b N (1-a-b) AlGaN and AlGaN refer to the components represented by the expression Al. x Ga (1-x) N describes the alloy, where 0 < x < 1.

[0076] Some embodiments described herein provide a group III nitride-based transistor device having a short gate length Lg (e.g., Lg ≤ 250 nm) and an optimized feedback capacitance Cgd. Such a short gate length is useful for RF applications requiring high transition frequencies fT in the 50 GHz to 150 GHz range. This short gate length can be achieved using high-accuracy patterning (using DUV lithography).

[0077] Figure 1a The illustration shows a schematic cross-sectional view of a group III nitride-based device 10 according to an embodiment, and Figure 1b The figure shows a plan view of the device 10.

[0078] The group III nitride-based device 10 includes a group III nitride-based layer 11. A first ohmic contact 12, a second ohmic contact 13, and a gate 14 are disposed on a first main surface 15 of the group III nitride-based layer 11. The group III nitride-based device 10 may be a transistor device 16, such as a high electron mobility transistor (HEMT). In an embodiment where the group III nitride device 10 is a transistor device 16, the first ohmic contact 12 may provide a source contact, and the second ohmic contact 13 may provide a drain contact. The gate 14 is laterally disposed between the source contact 12 and the drain contact 13. The group III nitride-based device 10 also includes a field plate 17 located on the first main surface 15 and laterally positioned between and spaced apart from the gate 14 and the drain contact 13.

[0079] A group III nitride-based layer 11 is formed on a substrate 19, which may be a heterogeneous substrate. The substrate 19 has a growth surface 20 capable of supporting the epitaxial growth of at least one group III nitride layer. The supporting substrate 20 may be a single-crystal silicon substrate, for example... <111> or <110> Silicon wafers or single-crystal sapphire substrates.

[0080] Layer 11 based on group III nitrides can have multiple layers. The multilayer group III nitride structure 11 may include a group III nitride buffer structure 21 disposed on the growth surface 20, a group III nitride channel layer 22 disposed on the group III nitride buffer structure 21, and a group III nitride barrier layer 23 disposed on the group III nitride channel layer 22. The group III nitride barrier layer 23 has a different composition and bandgap than the group III nitride channel layer 22, allowing a heterojunction 24 to be formed between them. For example, the group III nitride channel layer 22 may include gallium nitride, and the group III nitride barrier layer 23 may include aluminum gallium nitride. The heterojunction 24 is capable of supporting a two-dimensional charge gas schematically indicated by dashed line 26 in FIG. 1. A first ohmic contact 12 and a second ohmic contact 13 form ohmic contacts with the two-dimensional charge gas 26.

[0081] The group III nitride layer 11 may also include a further group III nitride layer 27 disposed on the group III nitride barrier layer 23. The further group III nitride layer 27 may, for example, be a gallium nitride overlay.

[0082] A typical buffer structure 21 for a silicon substrate includes an AlN initiation layer on the silicon substrate, which may have a thickness of several hundred nanometers, followed by Al x Ga (1-x) The N-layer sequence, with each layer again having a thickness of several hundred nanometers, reduces the Al content from approximately 50-75% to 10-25% before growing the GaN layer that forms the AlGaN back barrier. Alternatively, a superlattice buffer can be used. Again, an AlN initiation layer is used on a silicon substrate. Depending on the superlattice chosen, AlN and Al... x Ga (1-x) N pairs of sequences, where AlN layer and Al x Ga (1-x) The thickness of N ranges from 2 to 25 nm. Depending on the desired breakdown voltage, the superlattice can comprise between 20 and 100 pairs. Alternatively, Al can be used in combination with the superlattice mentioned above, as described above. x Ga (1-x) N-layer sequence.

[0083] In such Figure 1aIn some embodiments, such as the one illustrated in the figure, the buffer structure 21 includes a carbon-doped group III nitride-based buffer layer 28 disposed on a substrate 20 and a group III nitride back-side barrier layer 29 disposed on the carbon-doped group III nitride-based buffer layer 28. A channel layer 22 is disposed on the group III nitride back-side barrier layer 29. The group III nitride back-side barrier layer 29 comprises a group III nitride having a larger band gap than the channel layer 22, and may be formed of aluminum gallium nitride, for example, when the channel layer 22 is formed of gallium nitride.

[0084] The III-nitride-based device 10 includes a first passivation layer 18 disposed on a first main surface 15 of a III-nitride-based layer 11. The passivation layer 18 may be formed of silicon nitride.

[0085] Source contact 12, gate contact 14, and drain contact 15 extend through a first passivation layer 18, while a field plate 17 is disposed on the first passivation layer 18 and spaced apart from the underlying group III nitride-based layer 11 by the first passivation layer 18. In some embodiments, source contact 12, gate contact 14, and drain contact 15 are in direct contact with the group III nitride-based layer 11. Figure 1a In the embodiment illustrated in the figure, the source contact 12, gate 14, and drain contact 15 are in direct contact with the group III nitride-based overlay 27.

[0086] In some embodiments, each of the first ohmic contact 12 and the second ohmic contact 13 includes a bottom portion 30 having an upper conductive surface 31 located within a second passivation layer 32 disposed on the first passivation layer 18. Each of the ohmic contacts 12 and 13 may have the same structure. The ohmic contacts 12 and 13 may be fabricated substantially simultaneously, prior to the fabrication of the gate 14 and the field plate 17. Both the gate 14 and the field plate 17 are formed of a conductive material. The gate 14 may be a Schottky contact. In other embodiments, the transistor device 16 includes an insulated gate contact. In some embodiments, the gate 14 includes a p-doped group III nitride region disposed on the group III nitride layer 11 and a metal gate disposed on the p-doped group III nitride region.

[0087] The second passivation layer 32 is located on the source ohmic contact 12, drain ohmic contact 13, gate 14, field plate 17, and the first passivation layer 18. As indicated by the dashed line 31 in FIG1, the second passivation layer 32 may include two sublayers 33 and 34. The lower sublayer 33 is located on the group III nitride-based layer 11, and during the fabrication of the group III nitride-based device 10, a flat surface is formed with the conductive surfaces 31 of the bottom portions 30 of the first ohmic contact 12 and the second ohmic contact 13, after which the upper sublayer 34 is deposited on the flat surface. The lower sublayer 33 and the upper sublayer 34 may have the same composition, such as silicon oxide, and may be formed using TEOS (tetraethyl orthosilicate). The first passivation layer 18 is located on the upper surface of the group III nitride-based layer 11 between the second passivation layer 31, and may have a different composition than the second passivation layer 31.

[0088] The formation of the planarized surface, indicated by dashed line 35, allows subsequent layers built upon it to be planar. This enables the formation of the gate 14 and field plate 17 using lithography after the fabrication of ohmic contacts 22, 23, thereby allowing photoresist masking and deposition processes for at least the bottom portion of the gate 14 and field plate 17 to be performed on the planarized surface 35. This approach allows for more precise structuring of the photoresist layer for the gate 14 and field plate 17, as it is formed on the planar surface 35 and can be formed after the formation of ohmic contacts 22, 23 for the multilayer group III structure 11 (which typically involves higher processing temperatures). As a result of this more precise structuring of the photoresist layer, the dimensions and positions of the gate 14 and field plate 17 can be more precisely controlled. This also allows for more precise control over the distance D between the ohmic source contact 12 and the gate 14, as measured at the bottom of the ohmic contact 12 and the gate 14. SG It can be reduced in size, and reliably generated with that reduced length. The distance d from the gate to the source. SG It can be smaller than 0.5 µm, for example, 250 nm or smaller, in order to reduce R DSON Furthermore, it improves device performance. The more precise the structure of the photoresist layer, the better the position d of the field plate 17 relative to the gate. GFP The more reliably it can be controlled, the smaller it can be, such as 30 nm to 500 nm, 30 nm to 350 nm, or 250 nm or smaller, such as 30 nm to 250 nm.

[0089] Additionally, critical dimension control for gate processing was improved to enhance manufacturability and device performance. Gate length L G and / or the length L of the field plate FPIt can also be less than 0.5 µm, for example, 250 nm or smaller. Because the photoresist treatment of the gate and field plate is unaffected by the topographic steps created by the ohmic metal contacts 12, 13, due to the formation of the planarized surface 35 after the formation of the bottom portion 16, this enables such high-precision patterning of the gate electrode. Such topographic steps would impair the local uniformity of the antireflective coating and resist coating processes involved, and would degrade the depth of focus of the lithographic exposure process. In fact, the control of small-size lithographic structures would be severely limited.

[0090] In some embodiments, the upper conductive surface 21 of the ohmic contacts 22, 23 comprises a single composition. The ohmic contacts 22, 23 may comprise a single composition, or may comprise a stack of two or more layers with different compositions.

[0091] In some embodiments, the upper conductive surface 21 of the ohmic contacts 22, 23 includes two coplanar regions of different compositions. A central portion and an outer peripheral portion may be provided as the upper surface of a bottom portion, the bottom portion including a well comprising a first composition of metal or alloy extending into the lower portion, the lower portion comprising a different second composition of metal or alloy. The upper surface of the well provides the central portion of the conductive surface, and the upper surface of the lower portion provides the outer peripheral portion of the conductive surface, such that the upper surface of the well and the upper surface of the lower portion are substantially coplanar.

[0092] In some embodiments, the central portion of the well and conductive surface comprises a conductive barrier material, and the lower and outer peripheral portions comprise an ohmic contact material. The ohmic contact material is a material that forms an ohmic contact with the Group III nitride material of the uppermost Group III nitride layer of the multilayer Group III nitride structure 11. In some embodiments, the conductive barrier material of the central portion of the well and conductive surface comprises titanium nitride, and the lower and outer peripheral portions of the conductive surface comprise aluminum, an aluminum-copper alloy, or a titanium-aluminum alloy.

[0093] The bottom portion 20 of the ohmic contacts 12 and 13 and the lower portion of the gate via 14 can be referred to as electrodes, namely the source electrode, the gate electrode, and the drain electrode.

[0094] Reference Figure 1b In the top view, the ohmic contacts 12, 13, the gate 14, and the field plate 17 have elongated strip-like structures that extend to... Figure 1a The longest dimension or length extending in the plane of the accompanying drawings and in the longitudinal or Y direction of the transistor device 10, as shown using Cartesian coordinates. Ohmic contacts 12, 13, gate 14, and field plate 17 extend substantially parallel to each other. Field plate 17 is laterally located between and spaced apart from gate 14 and drain ohmic contact 13 in the X direction.

[0095] The field plate 17 is electrically connected to the source potential and the source ohmic contact 12 via one or more traverse conductive portions 40 of a metallized structure, the traverse conductive portions 40 extending in the X direction and substantially perpendicular to the length of the field plate 17. In embodiments including two or more traverse portions 40, each traverse portion 40 is spaced apart from adjacent traverse portions 40 in the Y direction. The traverse portions are disposed above the first main surface 15 and spaced apart from the first main surface 15 by one or more passivation layers or insulating layers (e.g., first passivation layer 18 and second passivation layer 32). The traverse portions 40 are correspondingly electrically connected to the field plate 17 and the ohmic source contact 12 via conductive vias 43, 44.

[0096] Gate 14 may be electrically connected to gate channel 41, which is positioned laterally adjacent to and spaced apart from the side of elongated source ohmic contact 12 opposite to the side facing gate 14. Gate 14 may be electrically connected to gate channel 41 by one or more transverse portions 42 of a metallized structure extending laterally between gate channel 41 and gate 14 and extending above source ohmic contact 12. Transverse portions 42 connected to gate 14 and transverse portions 41 connected to field plate 17 may be arranged alternately in the Y direction. Transverse portions 42 are disposed above field plate 17 and source ohmic contact 12 and are spaced apart from field plate 17 and source ohmic contact 12 by one or more passivation layers or insulating layers. Transverse portions 42 are correspondingly electrically connected to gate 14 and gate channel 41 through conductive vias 45, 46.

[0097] The transverse portion 40 electrically connected to the field plate and the transverse portion 42 connected to the gate 14 can be arranged in the same plane and located above the active region of the group III nitride transistor device 10.

[0098] In any transistor device, there exists a trade-off between a low Rdson, which translates into a high saturation current, and the parasitic coupling capacitance, namely the feedback capacitance Cgd. The lower the Rdson, the higher the Cgd and Cds. A high Cgd has various drawbacks in the design of RF and millimeter-wave power amplifiers, such as reduced gain, degraded stability, and adversely affecting the matching required for some applications.

[0099] The gate / drain channel can be pinched off using a field plate that is sufficiently close to the source connection, i.e., at a specific voltage that should typically be lower than the applied DC drain voltage. However, this becomes more challenging with higher sheet charge and lower applied DC drain voltage. In the case of RF III-nitride based transistors, the sheet charge is high, meaning such channels can only be depleted at 30V or higher.

[0100] According to the embodiments described herein, group III nitride-based transistor devices are provided with electrical characteristics, namely very low Cgd and still high Isat, which simultaneously increases gain and stability without significantly releasing saturation current. This can be used to provide high-frequency circuits with much higher performance. Another advantage is a significant reduction in input feedback, which significantly improves input matching.

[0101] Transistor devices based on group III nitrides, such as HEMTs, are disclosed. These transistor devices have short gate lengths Lg, for example, Lg ≤ 250 nm, and optimized feedback capacitance Cgd. Such short gate lengths are useful for RF applications requiring high transition frequencies fT in the range of 50 GHz to 150 GHz.

[0102] In some embodiments, group III nitride-based transistor devices have a gate-drain capacitance (C0). GD ), drain-source capacitance (C) DS ) and drain-source on-resistance (RDSon). Drain-source voltage (V DS The gate-drain capacitance (C) when it is 0V GD That is, C GD (0V) and V DS Gate-drain capacitance C when the value is >0V GD That is, C GD The ratio of V is at least 3:1, where V DS Less than 15V.

[0103] In some embodiments, group III nitride-based transistor devices have V DS dC values ​​less than -10 fF / mm / V GD / dV DS The value range is greater than 100 mV.

[0104] In some embodiments, group III nitride-based transistor devices include Rdson values ​​of less than 10 ohm*mm.

[0105] In some embodiments, group III nitride-based transistor devices include C values ​​greater than 2, greater than 3, or greater than 5 at VDS. GS / C DS Ratio, where V DS Less than 20V.

[0106] In some embodiments, the passivation layer 18 has a thickness d FP This creates a certain distance between the field plate and the conductive channel, resulting in a certain drain-source voltage (V). DS The gate-drain capacitance (C) when it is 0V GD That is, C GD (0V) and V DS Gate-drain capacitance C when the value is >0V GD That is, C GD The ratio of V is greater than 3:1, where V DS Less than 15V.

[0107] In some embodiments, V DS C at 0V GD The value of V DS Voltage at 0 <V DS C within the range of <15V GD The ratio of values ​​greater than 3, 4, or 5, and / or V DS C at 0V GD The value of V DS Voltage at 0 <V DS C when the voltage is less than 12V GD The ratio of values ​​is greater than 3, and / or V DS C at 0V GD The value of V DS Voltage at 0 <V DS C in the range of <10V GD The ratio of values ​​greater than 5, and / or V DS C at 0V GD The value of V DS Voltage at 0 <V DS C in the range of <20V GD The ratio of the values ​​is greater than 6.

[0108] In some embodiments, the thickness d of the passivation layer 18 between the lower surface of the field plate and the first main surface is... FP For wavelengths below 110 nm or 10 nm ≤ d FP ≤ 110 nm. The passivation layer 18 can be formed of a high-k dielectric, such as a hafnium-based or zirconium-based dielectric material, such as hafnium silicate, hafnium dioxide, zirconium silicate and zirconium dioxide.

[0109] In some embodiments, the dielectric constant of the material between the field plate 17 and the first main surface 15 divided by the distance between the lower surface of the field plate 17 and the first main surface 15 is 5e-8 F / cm. 2 and 1e-6 F / cm 2 between.

[0110] In some embodiments, the bottom of the gate 14 and the lower surface of the field plate 17 both have a width of 30 nm to 500 nm, or 50 nm to 400 nm, for example, 250 nm, and the distance dGF between the gate 14 and the field plate 17 at the closest point is 30 nm to 350 nm, for example, 250 nm. In some embodiments, the lower surface of the field plate 17 has a larger width, for example, in the range of 50 nm to 1000 nm or 500 nm to 1000 nm.

[0111] In some embodiments, a group III nitride-based transistor device includes a maximum stable gain (MSG) at frequency f and a current gain h21 measured under predetermined conditions, or a maximum available gain (MAG) at frequency f and a current gain h21 measured under predetermined conditions, wherein the ratio MSG / h21 2 >6dB, or >7dB, or >8dB, or the ratio MAG / h21 2 >6dB, or >7dB, or >8dB. MSG / h21 in dB. 2 The ratio is limited to 10·log 10 (MSG / h21 2 ).

[0112] In some embodiments, the group III nitride-based transistor device includes a maximum stable gain (MSG) greater than 26 dB measured at a frequency of 4 GHz, and a ratio of MSG / h21 2 >6dB, or >7dB, or >8dB.

[0113] In some embodiments, the group III nitride-based transistor device includes a maximum usable gain (MAG) greater than 26 dB measured at a frequency of 4 GHz, and a ratio MAG / h21 2 >6dB, or >7dB, or >8dB.

[0114] In some embodiments, the group III nitride-based transistor device includes a maximum stable gain (MSG) greater than 12 dB measured at a frequency of 28 GHz, and a ratio of MSG / h21 2 >7dB, or >8dB, or >9dB, or >10dB, or >13dB.

[0115] In some embodiments, the group III nitride-based transistor device includes a maximum usable gain (MAG) greater than 12 dB measured at a frequency of 28 GHz, and a ratio MAG / h21 2 >7dB, or >8dB, or >9dB, or >10dB, or >13dB.

[0116] A method for fabricating group III nitride-based devices, such as transistors, is employed that enables the fabrication of devices with short gate lengths Lg (e.g., Lg ≤ 250 nm) and optimized feedback capacitance Cgd. Such short gate lengths are useful for RF applications requiring high transition frequencies fT in the 50 GHz to 150 GHz range. These short gate lengths can be achieved using high-accuracy patterning, which requires lithography processes with thin photoresist flows, such as DUV lithography.

[0117] Such photoresist treatment is highly sensitive to morphological steps on the wafer—such as those created by the ohmic metals of the source and drain contacts fabricated prior to the gate structure. This disclosure utilizes an ohmic metallization concept that does not leave morphological steps such as vertical steps caused by RIE (reactive ion etching) patterning of the ohmic metal stacks used for the source and drain contacts. This allows for the application of lithography to form shorter gate lengths and to position the gate closer to the source contacts to reduce RIE. DSON The method can be performed using the processing power of a 200 mm CMOS production line, and is therefore cost-effective on wafers with a diameter of at least 200 mm.

[0118] Ohm-contact-first methods can be used to fabricate group III nitride-based devices, particularly transistor devices such as HEMTs (high electron mobility transistors). In embodiments, the method is performed on a wafer that may have a diameter of 6 inches or greater and includes planarizing the ohmic metal prior to fabricating the gate structure. The ohmic metal can be formed by: opening a window in group III nitride passivation, depositing an ohmic metal stack, structuring the ohmic metal stack, and applying an ohmic metal annealing step to alloy the ohmic metal. The ohmic metal can be planarized by: depositing a CMP (chemical mechanical polishing) stop layer on the front side of the wafer, applying chemical mechanical polishing to the structured ohmic metal to produce a planarized surface, and subsequently stripping away the remainder of the stop layer.

[0119] The planarized surface is used for further device processing, such as forming the gate using DUV lithography without the presence of a squared topography that affects the accuracy of the lithography process. Advantages of this method include enabling lower gate-to-source distances to improve device performance and improving critical dimension control for gate processing to enhance manufacturability and device performance.

[0120] Below are the electrical characteristics of an example AlGaN / GaN HEMT grown on a Si substrate with a field plate featuring depth-scaled source connections. An epitaxial layer is grown on a 200 mm high-resistivity Si substrate, and the device is processed in a high-capacity 200 mm silicon fabrication fab. The field plate rests directly on a 35 nm thick SiN passivation layer, adjacent to a 0.2 μm long gate. The gate and field plate are alternately connected to the gate channel and source metal to ensure low gate and field plate resistance.

[0121] Using this field plate design, for a drain voltage of 15V at 5.0 GHz, the small-signal gain is improved by 7.3dB compared to devices without a field plate, reaching a value greater than 26dB. The breakdown voltage is improved by 30V, reaching 170V.

[0122] Gallium nitride (GaN) high electron mobility transistors are highly attractive candidates for power amplifiers (PAs) in next-generation communication systems. In terms of efficiency and power density, group III nitride materials offer advantages over silicon-based devices, such as high breakdown field strength, saturation velocity, and low field mobility. However, commercially available GaN devices are typically grown on silicon carbide substrates, resulting in significantly higher costs. The ability to grow wide-bandgap nitrides on silicon substrates opens up the possibility of leveraging the advantages of group III nitride materials for high-capacity and cost-sensitive applications. Additionally, it allows for full utilization of the processing power of CMOS-based GaN devices.

[0123] Electrical characteristics of a field plate concept for depth scaling in GaN HEMTs are presented, which leverages advanced metal handling capabilities in a 200 mm fabrication environment to improve breakdown voltage and small-signal gain.

[0124] The device studied is an AlGaN / GaN heterostructure grown on a 200 mm diameter silicon (111) substrate with high resistivity (4000 cm⁻¹) via metal-organic chemical vapor deposition. The epitaxial stack consists of a 3 nm GaN overlay and an 18 nm thick Al₂O₃ overlay. 0.24 Ga 0.76 N-barrier layer, 300 nm thick GaN channel and Al 0.04 Ga 0.96 The N-backside barrier is followed by a carbon-doped stress-relief buffer and an AlN nucleation layer. Hall measurements revealed an 8.44 × 10⁻⁶ potential.12 cm -2 The average sheet carrier density is 2125 cm⁻¹. 2 V -1 s -1 Electron mobility. Transistors were fabricated in a CMOS-compatible fabrication environment using all-optical DUV processing. Au-free ohmic contacts were formed, resulting in an average contact resistance RC = 0.5 mm for the source contact and RC = 0.8 mm for the drain contact, as measured by a transmission line model. For the field plate device, the source-connected field plate metal rests on a 35 nm thick silicon nitride passivation layer adjacent to a 200 nm long gate electrode without any grooves. The spacing between the gate electrode and the source field plate is 300 nm. The gate-source spacing and gate-drain distance are 0.5 μm and 1.8 μm, respectively. All electrodes are defined without any stripping process. The transistor is fully encapsulated by a dielectric based on a back-channel (BEOL) process. In the BEOL, the gate and source-connected field plates are alternately connected to the gate channel and the ohmic source contact to obtain low gate and field plate resistances. A schematic structure of the fabricated field plate device is shown in Figure 1.

[0125] DC and pulse characteristics

[0126] Figure 2 a and Figure 2 Figure b shows the DC output and DC input characteristics of a (0.2 × 2 × 240) μm SiN passivated transistor with and without a field plate having source connections with depth scaling. The transistor with the field plate exhibits 0:72 A / mm². -1 The maximum drain current measured at VGS = 0V, and the structure without a field plate exhibits 0:70A / mm². -1 The maximum drain current.

[0127] Figure 2 Figure a illustrates the DC output characteristics of a (0.2×2×240)μm transistor with and without depth scaling in a field-plate flat panel (DSFP) at VDS = 15V, and... Figure 2 Figure b illustrates the DC input characteristics of a (0.2 × 2 × 240) μm transistor with and without depth scaling in a field plate (DSFP) at VDS = 15V. The maximum transconductance for the field plate device is determined to be gm = 0.30 Smm. -1 Furthermore, the maximum transconductance for non-field plate devices was determined to be gm = 0.28 Smm. -1The threshold voltages are correspondingly Vth = -2.76V and Vth = -3.0V. Under these conditions, the two devices do not show a significant difference in DC characteristics. Conversely, using a depth-scaled field plate, the breakdown voltage increases by 30V from 140V to 170V, as shown in... Figure 3 As shown in a. Transverse breakdown is determined by the sudden drop in drain current during the drain voltage ramp-up.

[0128] Figure 3 Figure a illustrates the breakdown characteristics of a (0.2×2×240)μm transistor with and without depth scaling in a field plate (DSFP). Figure 3 Figure b illustrates the drain hysteresis double-pulse measurement of a (0.2×2×240)μm transistor with and without depth scaling field plates (DSFP).

[0129] To evaluate the trapping behavior, double-pulse drain hysteresis measurements were performed under various drain voltage stress conditions. During the stress pulse, the gate voltage was held in an off state at VGS = -8:0V, and the drain voltage was held at VDS = Vstress. The relative decrease in saturation current Idsat and dynamic on-resistance Rdson, normalized to stress-free values, was measured. Figure 3 As shown in b, significantly less trapping was observed for field-plate devices at stress voltages greater than 12V. Both the decrease in Idsat and the increase in Rdson can be significant. For field-plate devices, Rdson increased by 142% after applying a stress voltage of 60V.

[0130] RF characteristics

[0131] The S-parameters were measured using an Agilent N5230A vector network analyzer (VNA) and an off-chip SOLT standard up to 20 GHz to evaluate the device's RF characteristics. To illustrate the effect of the deep-source-connected field plate on RF behavior, the off-state capacitances Cgd and Cds were determined for various drain voltages. After on-chip open-circuiting and short-de-embedding, the capacitance was approximated by the imaginary part of the y-parameter at 0:5 GHz, according to G. Dambrine, A. Cappy, F. Heliodore, and E. Playez, “A new method for determining the FET small-signal equivalent circuit” (IEEE Transactions on Microwave Theory and Techniques, vol. 36, no. 7, pp. 1151–1159, July 1988). A comparison of bias-dependent capacitances with and without depth-scaled field plates is shown in [the table / document / reference]. Figure 5 middle.

[0132] Figure 4 The diagram illustrates the disconnected state capacitors (a) CGD and (b) CDS with and without a field plate (DSFP). The pinch-off voltage of the field plate with the source connected is 10V.

[0133] The pinch-off characteristics of the depth-scaled field plate at Vp = 10V can be observed by reducing the step on CGD and CDS. The depth-scaled field plate effectively reduces gate-drain coupling by shielding the gate and drain electrodes and by extending the depletion region below the gate toward the drain after pinch-off. Both of these effects lead to a significant reduction in gate-drain capacitance. Similarly, the source-connected field plate results in strong coupling between the source and drain, causing an increase in CDS.

[0134] At a drain voltage of Vd = 15V and Id = 100 mAmm -1 Small-signal MSG and MAG, as well as current gain h21, were measured for two devices at a current of [value missing]. Results were obtained in [data missing]. Figure 5 As shown in the image.

[0135] Figure 5The small-signal behavior of (0.2 × 2 × 240) μm transistors with and without depth scaling field plates (DSFP) is illustrated, showing a significant gain improvement for the field plate device. The cutoff frequency was determined by extrapolation, giving a maximum fT = 46 GHz for both devices. Small-signal characteristics were modeled using the standard small-signal equivalent circuit according to G. Dambrine, A. Cappy, F. Heliodore, and E. Playez (IEEE Transactions on Microwave Theory and Techniques, vol. 36, no. 7, pp. 1151–1159, July 1988). The measured S-parameters (Si) were optimized across the entire frequency range. meas ) and modeling S-parameters (S model The relative deviation (S) meas - S model ) / S meas Table I summarizes the extrinsic and intrinsic parameters.

[0136]

[0137] Table 1: Parameters of the small-signal model of the 2×240μm device.

[0138] As discussed earlier, when a field plate with depth-scaled source connections is introduced, the capacitance CGD increases from 95 fF / mm². -1 Reduced to 17 fFmm -1 The value of causes a gain increase of 7:3 dB. An explanation for the observed gain enhancement could be the thin passivation layer under the field plate and the small gate-field plate distance, while keeping the gate and field plate resistances low.

[0139] In the case of these examples with deeply scaled source-connected field plates, high small-signal gain is achieved for conventional normally-on GaN-based RF transistors.

[0140] Figure 6 The figure shows a line graph of the gate-drain capacitance (CGD) ratio in pF / mm, measured at voltages between 0 and 40V for transistor structures with different passivation layer thicknesses. Simulation results for passivation layer thicknesses of 20nm, 35nm, 40nm, 54nm, 60nm, and 100nm are shown using lines, while measurement results for 35nm and 53nm passivation layers are shown using symbols. The passivation layer is made of SiN. xFormation. Each curve includes a sharp decrease in gate-drain capacitance at voltage values ​​below the device's operating voltage. For a 20nm passivation layer thickness, a sharp decrease is seen below 10V, and for 20nm and 35nm passivation layer thicknesses, a sharp decrease is seen around or slightly above 10V. At voltages above approximately 8V, the CGD values ​​are in the range of 20fF / mm to 30fF / mm and are very low.

[0141] Figure 7a illustrates the situation with Figure 7c The substrate structure and dimensions shown in the figure are in V DS Line plots of MAG, MSC, and h21 at different frequencies for a group III nitride transistor structure measured at 40V and Id = 50 mA / mm. Figure 7b The diagram is for those with Figure 7c The substrate structure and dimensions shown in the figure are in V DS MSG / h21 of a Group III nitride transistor structure measured at different frequencies at 40V and Id = 50 mA / mm 2 and MAG / h21 2 Line graph.

[0142] In this structure, the passivation layer 18 is made of SiN x Formed and having a thickness of 50 nm FP The bottom of gate electrode 14 has a width of 190 nm and the distance d between gate electrode 14 and field plate 17 is... GF The width is 190 nm. The field plate 17 has a width of 690 nm. The distance between the drain side edge of the gate electrode 14 and the drain electrode 13 is 1700 nm, and the distance between the source side edge of the gate electrode 14 and the source electrode 12 is 500 nm.

[0143] At 4 GHz, h21 is 18.7 dB, MSG and MAG are 27.3 dB, and MSG / h21 is... 2 and MAG / h21 2 It is 8.6dB. At 28GHz, h21 is 3.1dB, MSG and MAG are 17.1dB, and MSG / h21 is... 2 and MAG / h21 2 It is 14dB.

[0144] A depth-scaled field-plate concept for a 0:2 μm GaN HEMT on a 200 mm silicon substrate is presented. The field-plate device produces the high small-signal gain reported for GaN RF transistors operating below 28 V and reaching the X-band. The field plate, with the source connection close to the gate electrode and resting on a thin passivation layer, shields the electric field from the gate and reduces gate-drain capacitance. Alternating gate and field-plate connections in the BEOL are used to ensure low gate and field-plate resistances. This innovative device concept exhibits enhanced breakdown characteristics, lower current collapse, and significantly higher gain while maintaining good DC performance.

[0145] For ease of description, spatial relative terms such as "below," "lower," "down," "above," and "upper" are used to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device other than those depicted in the figures. Furthermore, terms such as "first," "second," etc., are also used to describe various elements, areas, sections, etc., without any intention of limitation. Throughout the description, the same terms refer to the same elements.

[0146] As used herein, the terms “having,” “comprising,” “including,” and “including” are open-ended terms that indicate the presence of the stated element or feature but do not exclude additional elements or features. The quantifiers “a,” “an,” and the pronoun “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise. It is to be understood that, unless otherwise specifically indicated, features of the various embodiments described herein can be combined with each other.

[0147] While specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various alternatives and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only to the claims and their equivalents.

Claims

1. A transistor device based on group III nitrides, comprising: Source electrode, drain electrode and gate electrode located on the first main surface of the group III nitride-based base layer, wherein the gate electrode is arranged laterally between the source electrode and the drain electrode. A passivation layer disposed on the first main surface; A field plate electrically connected to the source electrode, the field plate having a lower surface disposed on a passivation layer, the field plate being disposed laterally between the gate electrode and the drain electrode and spaced laterally from the gate electrode and the drain electrode. Among them, transistor devices based on group III nitrides have gate-drain capacitance C. GD Drain-source capacitance C DS and drain-source on-resistance R DSon , Where the drain-source voltage V DS Gate-drain capacitance C at 0V GD That is, C GD (0V) and V DS Gate-drain capacitance C when the value is > 0V GD That is, C GD The ratio of V is at least 3:1, where V DS Less than 15V.

2. The transistor device based on group III nitrides according to claim 1, wherein... V DS C at 0V GD The value of V DS Voltage in 0 < V DS C when the voltage is less than 15V GD The ratio of values ​​greater than 4, and / or V DS C at 0V GD The value of V DS Voltage in 0 < V DS C when the voltage is less than 12V GD The ratio of the values ​​is greater than 3.

3. The transistor device based on group III nitrides according to claim 1, wherein... V DS C at 0V GD The value of V DS Voltage in 0 < V DS C when the voltage is less than 15V GD The ratio of values ​​is greater than 5, and / or V DS C at 0V GD The value of V DS Voltage in 0 < V DS C when the voltage is less than 12V GD The ratio of the values ​​is greater than 3.

4. The transistor device based on group III nitrides according to claim 1, wherein in V DS dC within a subrange of values GD / dV DS Less than -10 fF / mm / V, with a subrange of values ​​greater than 100 mV, and where 5 V < V DS < 20 V.

5. The transistor device based on group III nitrides according to any one of claims 1 to 4, wherein R DSon Less than 10 ohm*mm.

6. The group III nitride-based transistor device according to any one of claims 1 to 4, wherein the group III nitride-based transistor device includes a gate-source capacitor C. GS And in V DS C under the value GS / C DS Greater than 2, where V DS Less than 20V.

7. The group III nitride-based transistor device according to any one of claims 1 to 4, wherein the group III nitride-based transistor device includes a gate-source capacitor C. GS And in V DS C under the value GS / C DS Greater than 3, where V DS Less than 20V.

8. The group III nitride-based transistor device according to any one of claims 1 to 4, wherein the group III nitride-based transistor device includes a gate-source capacitor C. GS And in V DS C under the value GS / C DS Greater than 5, where V DS Less than 20V.

9. The group III nitride-based transistor device according to any one of claims 1 to 4, wherein the passivation layer has a thickness d FP This creates a certain distance between the field plate and the conductive channel, resulting in a certain drain-source voltage V. DS Gate-drain capacitance C at 0V GD That is, C GD (0V) and V DS Gate-drain capacitance C when the value is > 0V GD That is, C GD The ratio of V is greater than 3:1, where V DS Less than 15V.

10. The group III nitride-based transistor device according to any one of claims 1 to 4, wherein the passivation layer has a thickness d FP This creates a certain distance between the field plate and the conductive channel, allowing V to... DS C at 0V GD The value of V DS Voltage in 0 < V DS C when the voltage is less than 15V GD The ratio of values ​​is greater than 3, and / or Make V DS C at 0V GD The value of V DS Voltage in 0 < V DS C when the voltage is less than 12V GD The ratio of the values ​​is greater than 3.

11. The group III nitride-based transistor device according to any one of claims 1 to 4, wherein the passivation layer has a thickness d FP This creates a certain distance between the field plate and the conductive channel, allowing V to... DS C at 0V GD The value of V DS Voltage in 0 < V DS C when the voltage is less than 15V GD The ratio of values ​​is greater than 5, and / or Make V DS C at 0V GD The value of V DS Voltage in 0 < V DS C when the voltage is less than 12V GD The ratio of the values ​​is greater than 3.

12. The group III nitride-based transistor device of claim 9, wherein the dielectric constant of the material between the field plate and the first main surface, divided by the distance between the lower surface of the field plate and the first main surface, is 5e -8 F / cm 2 and 1e -6 F / cm 2 between.

13. The transistor device based on group III nitrides according to claim 9, wherein the passivation layer is made of SiN X It is formed or is formed from materials with a higher dielectric constant than silicon dioxide.

14. The group III nitride-based transistor device according to any one of claims 1 to 4, wherein the bottom of the gate electrode has a width of 30 nm to 500 nm, and the distance d between the gate electrode and the field plate at the closest point is... GF The range is from 30 nm to 500 nm.

15. The group III nitride-based transistor device of claim 14, wherein the bottom of the gate electrode has a width of 30 nm to 500 nm, and the lower surface of the field plate has a width of 30 nm to 1000 nm, and the distance d between the gate electrode and the field plate at the closest point is... GF The range is from 30 nm to 350 nm.

16. The group III nitride-based transistor device according to any one of claims 1 to 4, wherein the group III nitride-based transistor device comprises a maximum stable gain MSG at frequency f and a current gain h21 measured under predetermined conditions, or a maximum available gain MAG at frequency f and a current gain h21 measured under predetermined conditions, wherein the ratio MSG / h21 2 >6dB, or ratio MAG / h21 2 >6dB.

17. A group III nitride-based transistor device according to any one of claims 1 to 4, wherein the group III nitride-based transistor device comprises a maximum stable gain MSG at frequency f and a current gain h21 measured under predetermined conditions, or a maximum available gain MAG at frequency f and a current gain h21 measured under predetermined conditions, wherein the ratio MSG / h21 2 >7dB, or ratio MAG / h21 2 >7dB.

18. A group III nitride-based transistor device according to any one of claims 1 to 4, wherein the group III nitride-based transistor device comprises a maximum stable gain MSG at frequency f and a current gain h21 measured under predetermined conditions, or a maximum available gain MAG at frequency f and a current gain h21 measured under predetermined conditions, wherein the ratio MSG / h21 2 >8dB, or ratio MAG / h21 2 >8dB.

19. The transistor device based on group III nitrides according to claim 16, wherein... The group III nitride-based transistor device includes a maximum stable gain MSG greater than 26 dB measured at a frequency of 4 GHz and a ratio MSG / h21 2 >6dB, or The group III nitride-based transistor device includes a maximum usable gain (MAG) greater than 26 dB measured at a frequency of 4 GHz and a ratio of MAG / h21. 2 >6dB, The group III nitride-based transistor device includes a maximum stable gain MSG greater than 12 dB measured at a frequency of 28 GHz and a ratio MSG / h21 2 >7dB, or The group III nitride-based transistor device includes a maximum usable gain (MAG) greater than 12 dB measured at a frequency of 28 GHz and a ratio of MAG / h21. 2 >7dB.

20. The transistor device based on group III nitrides according to claim 16, wherein... The group III nitride-based transistor device includes a maximum stable gain MSG greater than 26 dB measured at a frequency of 4 GHz and a ratio MSG / h21 2 >7dB, or The group III nitride-based transistor device includes a maximum usable gain (MAG) greater than 26 dB measured at a frequency of 4 GHz and a ratio of MAG / h21. 2 >7dB, The group III nitride-based transistor device includes a maximum stable gain MSG greater than 12 dB measured at a frequency of 28 GHz and a ratio MSG / h21 2 >10dB, or The group III nitride-based transistor device includes a maximum usable gain (MAG) greater than 12 dB measured at a frequency of 28 GHz and a ratio of MAG / h21. 2 >10dB.

21. The transistor device based on group III nitrides according to claim 16, wherein... The group III nitride-based transistor device includes a maximum stable gain MSG greater than 26 dB measured at a frequency of 4 GHz and a ratio MSG / h21 2 >8dB, or The group III nitride-based transistor device includes a maximum usable gain (MAG) greater than 26 dB measured at a frequency of 4 GHz and a ratio of MAG / h21. 2 >8dB, The group III nitride-based transistor device includes a maximum stable gain MSG greater than 12 dB measured at a frequency of 28 GHz and a ratio MSG / h21 2 >13dB, or The group III nitride-based transistor device includes a maximum usable gain (MAG) greater than 12 dB measured at a frequency of 28 GHz and a ratio of MAG / h21. 2 >13dB.

22. The group III nitride-based transistor device according to any one of claims 1 to 4, wherein the field plate includes one or more conductive vias extending substantially perpendicular to the first main surface and electrically connected to the source electrode via a lateral field plate redistribution structure extending over and spaced apart from the gate electrode.

23. The group III nitride-based transistor device of claim 22, wherein the source electrode, gate electrode, drain electrode, and field plate all have elongated shapes and extend substantially parallel to each other in the longitudinal direction on the first main surface. The lateral field plate redistribution structure includes a longitudinal segment located above the field plate and extending substantially parallel to the longitudinal direction, and a plurality of transverse segments spaced apart in the longitudinal direction. Each transverse segment extends above the gate electrode and is spaced apart from the gate electrode, and is electrically connected to the field plate through conductive vias.

24. The transistor device based on group III nitrides according to any one of claims 1 to 4, further comprising a lateral gate redistribution structure, the lateral gate redistribution structure comprising a plurality of gate traversing segments, each gate traversing segment being spaced apart from a gate electrode and electrically connected to the gate electrode through a conductive via, the gate traversing segments of the lateral gate redistribution structure being interleaved with the traversing segments of the lateral field plate redistribution structure.

25. The group III nitride-based transistor device of claim 19, wherein the source electrode is electrically connected to a lateral field plate redistribution structure.

26. The transistor device based on group III nitrides according to claim 19, wherein the longitudinal section of the lateral field plate redistribution structure is wider laterally than the conductive via and the field plate.

27. The group III nitride-based transistor device of claim 19, wherein the field plate is divided into two field plate segments that extend substantially parallel to each other and are laterally spaced apart from each other, the two field plate segments being laterally arranged between and spaced apart from the gate electrode and the drain electrode.

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