Data bus inversion circuit and memory

Abstract

The disclosed embodiments provide a data bus flipping circuit and a memory, wherein the data bus flipping circuit comprises: a processing circuit for performing at least partial sorting processing on a data signal in a comparison result between current data and previous data to obtain an output result; a first determination circuit for determining the number of bits that need to be flipped in the current data based on a portion of the output signals in the output result, wherein the data bits of the portion of the output signals are determined by the rules of the sorting processing; and a second determination circuit for determining a data flipping signal corresponding to the current data based on the number of bits that need to be flipped in the current data and a data flipping signal corresponding to the previous data.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor storage design, and is related to but not limited to a data bus flip circuit and a memory. Background Art

[0002] Starting with the fourth-generation double data rate synchronous dynamic random access memory (DDR4 SDRAM), the data bus inversion (DBI) operation was added to the dynamic random access memory (DRAM) to reduce frequent data flipping and thus reduce dynamic power consumption.

[0003] In the original Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), it is only necessary to determine whether the number of 0 or 1 bits in the current byte is greater than a certain value. For example, in DDR4, if the number of 0s in the byte is greater than 4, the data flip signal dbi_n is pulled low and all the data is flipped. In the third generation of high bandwidth memory (High Band width Memory Third Generation, HBM3), the data flip signal needs to be combined with the previous data to calculate the number of bits that need to be flipped in the current data, and it needs to be combined with the data flip signal of the previous data to determine whether the current data needs to be flipped. However, the current data bus flip circuit is relatively complex and consumes a lot of power. Summary of the invention

[0004] Embodiments of the present disclosure provide a data bus flipping circuit and a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides a data bus flipping circuit, which includes: a processing circuit, which is used to perform at least partial sorting processing on a data signal in a comparison result between current data and previous data to obtain an output result; a first determination circuit, which is used to determine the number of bits that need to be flipped in the current data based on a part of the output signal in the output result, wherein the data bits of the part of the output signal are determined by the rules of the sorting processing; and a second determination circuit, which is used to determine a data flipping signal corresponding to the current data based on the number of bits that need to be flipped in the current data and the data flipping signal corresponding to the previous data.

[0006] In some embodiments, the processing circuit is used to perform at least a partial merge sort process on the data signal in the comparison result to obtain a merge sort result; wherein the middle two bits of data signal of the merge sort result are used as the partial output signal.

[0007] In some embodiments, the number of bits of the data signal in the comparison result includes 8*2 n bits; the value of n is an integer greater than or equal to 0; the processing circuit includes (2 i )2 (j+3) The sorting module of each bit is 2 (j+3) The bit sorting module is used to sort the input 2 (j+3) Sort the bit data and get 2 (j+3) The result of the bit sorting; wherein: the value of j is an integer starting from n and greater than or equal to 0, i+j=n, the value of i is an integer starting from 0 and less than or equal to n; when the value of j is greater than or equal to 1, 2 2 (j+2) The sorting result of the bit sorting module is 2 (j+3) The input data of the bit sorting module.

[0008] In some embodiments, each 8-bit sorting module includes 2 p 2 q The ordering unit of each bit; q The bit sorting unit is used to convert the input 2 q The bit data signal is sorted to obtain 2 q The result of the bit sorting; wherein: the value of q is an integer starting from 3 and greater than or equal to 1, the value of p is an integer starting from 0 and less than 2, p+q=3; when the value of q is greater than or equal to 1, 2 2 q The sorting result of the sorting unit of the bit is taken as 2 (q+1) The input data of the bit sorting unit.

[0009] In some embodiments, when j is equal to 0, each 8-bit sorting module is used to sort the data signals of each non-repeating adjacent 8 bits in the comparison result into a group to obtain an 8-bit sorting result; when n is equal to 0, the processing circuit includes one 8-bit sorting module, and the 8-bit sorting result is used as the merge sorting result; when j is equal to 1, each 16-bit sorting module is used to sort the data signals at the corresponding positions of each non-repeating adjacent two 8-bit first sorting results to obtain a 16-bit sorting result; when n is equal to 1, In the case where j is equal to 2, the processing circuit includes two of the 8-bit sorting modules and one 16-bit sorting module, and the 16-bit sorting result is used as the merge sorting result; in the case where j is equal to 2, each 32-bit sorting module is used to sort the data signals at the corresponding positions of two non-repeating adjacent 16-bit second sorting results to obtain a 32-bit sorting result; in the case where n=2, the processing circuit includes four of the 8-bit sorting modules, two of the 16-bit sorting modules and one 32-bit sorting module, and the 32-bit sorting result is used as the merge sorting result.

[0010] In some embodiments, when j=0, the 8-bit sorting module includes 4 2-bit sorting units, 2 4-bit sorting units and 1 8-bit sorting unit, wherein: each of the 2-bit sorting units is used to sort each non-repeating adjacent two data signals in the 8-bit data signal to obtain a 2-bit sorting result; each of the 4-bit sorting units is used to sort the 4-bit sorting results output by each non-repeating adjacent two 2-bit sorting units to obtain a 4-bit sorting result; and one 8-bit sorting unit is used to sort the 8-bit sorting results output by each non-repeating adjacent two 4-bit sorting units to obtain the 8-bit sorting result.

[0011] In some embodiments, each of the 4-bit sorting units includes: a first sorting sub-unit, used to sort the two data signals at the same position for each non-repeating 2-bit sorting result output by two adjacent 2-bit sorting units to obtain a first sub-sorting result; a 4-bit sorting sub-unit, used to sort the two middle data signals of the first sub-sorting result to obtain the 4-bit sorting result.

[0012] In some embodiments, each of the 8-bit sorting units includes: a second sorting sub-unit, used to sort the two-bit data signals at the same position for each non-repeating 8-bit sorting result output by two adjacent 4-bit sorting units, to obtain a second sub-sorting result; an 8-bit sorting sub-unit, used to divide each non-repeating adjacent two-bit data signal into a first group for the middle 4-bit data signal of the second sub-sorting result, and sort the two-bit data signals at the same position in the two first groups respectively, to obtain the 8-bit sorting result.

[0013] In some embodiments, each 16-bit sorting module includes: 1 16-bit sorting unit; the 16-bit sorting unit includes a third sorting subunit, a fourth sorting subunit and a 16-bit sorting subunit, wherein: the third sorting subunit is used to sort the two-bit data signals at the same position for each non-repeating 16-bit sorting result output by two adjacent 8-bit sorting units to obtain a third sub-sorting result; the fourth sorting subunit is used to divide each non-repeating adjacent 4-bit data signal into a second group for the middle 8-bit data signal of the third sub-sorting result, and compare the two 4-bit data signals at the same position in the second groups to obtain a fourth sub-sorting result; the 16-bit sorting subunit is used to divide each non-repeating adjacent two-bit data signal into a third group for the middle 4-bit data signal of the fourth sub-sorting result, and sort the two-bit data signals at the same position in the third groups to obtain the 16-bit sorting result.

[0014] In some embodiments, each of the third sorting subunits includes 8 first logic units; each of the second sorting subunits and the fourth sorting subunit includes 4 of the first logic units; each of the 2-bit sorting subunits and each of the 4-bit sorting subunits includes 1 first logic unit; each of the first sorting subunits, the 16-bit sorting subunits and each of the 8-bit sorting subunits include 2 first logic units, and each of the first logic units includes at least one first AND gate and a first OR gate; wherein the first input terminal and the second input terminal of the first AND gate are respectively connected to the first input terminal and the second input terminal of the first OR gate for inputting data signals; the output terminal of the first AND gate is used to output a first type of data signal; the output terminal of the first OR gate is used to output a second type of data signal; the potential of the first type of data signal is less than or equal to the potential of the second type of data signal.

[0015] In some embodiments, the first determination circuit is used to: determine that the number of bits that need to be flipped in the current data is greater than or equal to a preset value plus one when some of the output signals in the output results are all at the first potential; determine that the number of bits that need to be flipped in the current data is less than the preset value when some of the output signals in the output results are all at the second potential; determine that the number of bits that need to be flipped in the current data is the preset value when some of the output signals in the output results are different; wherein the preset value is half of the number of data signal bits of the current data.

[0016] In some embodiments, the processing circuit is used to perform at least logical operation processing on the data signal in the comparison result to obtain a logical operation result; wherein the first and last two data signals of the logical operation result are used as the partial output signal; wherein the logical operation processing includes reversing the same two-bit data signal and outputting a high potential and a low potential of a fixed data bit for different two-bit data signals.

[0017] In some embodiments, the number of bits of the data signal in the comparison result includes 8 bits; the processing circuit includes the following 5 types of processing units: a first processing unit, used to perform the logic operation processing on each non-repeating adjacent two-bit data signal in the 8-bit data signal to obtain a first operation result; a second processing unit, used to divide each non-repeating adjacent 4-bit data signal into a fourth group for the first operation result; divide each non-repeating adjacent two-bit data signal in each of the fourth groups into a fifth group; for each of the fourth groups in the first operation result, perform the logic operation processing on the two-bit data signals in the same position in the two fifth groups to obtain a second operation result; a third processing unit, used to divide each non-repeating adjacent two-bit data signal in each of the fourth groups into a fifth group for the second operation result; The adjacent 4-bit data signals are divided into a sixth group; the first and last two data signals in each of the sixth groups are processed by the logic operation to obtain a third operation result; the fourth processing unit is used to divide each non-repeating adjacent 4-bit data signal into a seventh group for the third operation result; the two data signals at the same position in the two seventh groups are processed by the logic operation to obtain a fourth operation result; the first bit result and the sixth bit result in the fourth operation result are reversed to obtain a fifth operation result; the fifth processing unit is used to divide each non-repeating adjacent two-bit data signal into an eighth group for the fifth operation result; the first and last two data signals in the eighth groups are processed by the logic operation to obtain the logic operation result.

[0018] In some embodiments, the first processing unit and the second processing unit each include 4 second logic units; the third processing unit and the fifth processing unit include 2 second logic units; the fourth processing unit includes 2 second logic units, 1 third logic unit and 1 fourth logic unit; wherein: each of the second logic units includes a NAND gate and a first NOR gate; the third logic unit includes the second logic unit and a first inverter connected to the output end of the first NOR gate in the second logic unit; the fourth logic unit includes the second logic unit and a second inverter connected to the output end of the NAND gate in the second logic unit; wherein the first input end and the second input end of the NAND gate are respectively connected to the first input end and the second input end of the first NOR gate for inputting data signals.

[0019] In some embodiments, the first determination circuit is used to: determine that the number of bits that need to be flipped in the current data is less than a preset value when some of the output signals in the output results are all at the first level; determine that the number of bits that need to be flipped in the current data is greater than or equal to the preset value plus one when some of the output signals in the output results are all at the second level; determine that the number of bits that need to be flipped in the current data is the preset value when some of the output signals in the output results are different; wherein the preset value is half of the number of data signal bits of the current data.

[0020] In a second aspect, an embodiment of the present disclosure provides a memory, comprising at least the data bus flipping circuit described in any one of the above embodiments.

[0021] In the disclosed embodiment, first, the processing circuit in the data bus flip circuit performs at least partial sorting processing on the data signal in the comparison result of the current data and the previous data to obtain the output result. In this way, the first determination circuit does not need to determine the number of bits that need to be flipped in the current data based on all the output signals in the output result, but determines the number of bits that need to be flipped in the current data based on part of the output signals in the output result, wherein the data bits of the part of the output signal are determined by the rules of sorting processing. In this way, the disclosed embodiment can provide a relatively simple data bus flip circuit, thereby reducing the power consumption of the circuit. Secondly, the second determination circuit is used to determine the data flip signal corresponding to the current data based on the number of bits that need to be flipped in the current data and the data flip signal corresponding to the previous data. In this way, by dynamically comparing with the previous data and its data flip signal, not only can the dynamic data flip signal be realized, but also it can be more accurately judged whether the current data needs to be flipped. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0023] Figure 1 A schematic diagram of the structure of a data bus flip circuit provided by an embodiment of the present disclosure;

[0024] Figure 2 A schematic diagram of the structure of an 8-bit sorting module provided in an embodiment of the present disclosure;

[0025] Figure 3 A logical diagram of a merge sorting process provided by an embodiment of the present disclosure;

[0026] Figure 4 A schematic diagram of the composition structure of a 16-bit sorting unit provided in an embodiment of the present disclosure;

[0027] Figure 5 A logical diagram of another merge sorting process provided by an embodiment of the present disclosure;

[0028] Figures 6 to 10 Schematic diagrams of the composition structures of a 2-bit sorting unit, a first sorting subunit, a 4-bit sorting subunit, a second sorting subunit and an 8-bit sorting subunit provided in the embodiments of the present disclosure;

[0029] Fig.11 A schematic diagram of the structure of a second determination circuit provided in an embodiment of the present disclosure;

[0030] Fig.12 A schematic diagram of the structure of a processing circuit provided in an embodiment of the present disclosure;

[0031] Figures 13 to 17 Schematic diagrams of the composition structures of a first processing unit, a second processing unit, a third processing unit, a fourth processing unit and a fifth processing unit provided in embodiments of the present disclosure;

[0032] Fig.18 A logic diagram of a logic operation process provided by an embodiment of the present disclosure;

[0033] Fig.19 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0035] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0036] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0037] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] The present disclosure provides a data bus flip circuit, referring to Figure 1 , the data bus flip circuit 100 comprises:

[0040] The processing circuit 10 is used to perform at least a partial sorting process on the data signal in the comparison result between the current data and the previous data to obtain an output result;

[0041] A first determination circuit 20, for determining the number of bits to be flipped in the current data based on a portion of the output signals in the output result, wherein the data bits of the portion of the output signals are determined by a sorting processing rule;

[0042] The second determination circuit 30 is used to determine the data flip signal corresponding to the current data based on the number of bits that need to be flipped in the current data and the data flip signal corresponding to the previous data.

[0043] Here, the current data is the data currently stored in the storage unit or the data currently read from the storage unit. The previous data refers to the data previously transmitted from the data line, and can also be called the previous data. The number of data signal bits included in the current data and the previous data can be a multiple of 8, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc., which is not limited in the embodiments of the present disclosure. In addition, for convenience, the embodiments of the present disclosure are explained by taking the comparison result including an 8-bit data signal as an example.

[0044] The comparison result refers to the result obtained by comparing the current data with the previous data. The comparison result of the current data with the previous data can reflect the difference between the current data and the previous data. In some embodiments, the comparison result of the current data with the previous data can be the result of the XOR processing of the two. For example, if the data signals on the same bit in the current data and the previous data are the same, the comparison result is 0; if the data signals on the same bit in the current data and the previous data are different, the comparison result is 1. The number of bits of the data signal included in the comparison result is the same as the number of bits of the data signal included in the current data or the previous data.

[0045] The processing circuit 10 performs at least partial sorting processing on the data signals in the comparison result between the current data and the previous data, which can be understood as: completely sorting the data signals in the comparison result, that is, the data signals in the obtained output result are arranged according to a certain pattern, such as a regular arrangement from large to small, or a regular arrangement from small to large; it can also be understood as partially sorting the data signals in the comparison result, that is, some data signals in the output result are still out of order, but the overall distribution of the data in the comparison result can be obtained based on the situation of the partially sorted data signals in the output result.

[0046] The first determination circuit 20 is used to determine the number of bits that need to be flipped in the current data based on the partial output signal in the output result. Part of the output signal can be determined according to the rules of sorting processing. For example, when the processing circuit performs partial merge sorting on the data signal in the comparison result, the two data bits in the middle of the merge sorting result, such as the 3rd and 4th bits (the comparison result includes an 8-bit data signal) can be used as partial output signals. For another example, when the processing circuit performs partial other types of sorting on the data signal in the comparison result, two data bits in the sorting result, such as the 0th and 7th bits, can be used as partial output signals. Output signals of different data bits are used to represent different information. According to the data signals of different data bits, the proportion of the number of bits that need to be flipped in the current data signal to the current data signal can be obtained.

[0047] The data flip signal can be a high level or "1", or a low level or "0". In some embodiments, when the data flip signal is "1", the current data can be flipped, which can reduce the number of flips of the data bus, thereby reducing power consumption. Flipping the current data can be understood as changing "0" to "1", or changing "1" to "0".

[0048] In some embodiments, the processing circuit is used to perform at least a partial merge sort process on the data signal in the comparison result to obtain a merge sort result; wherein the middle two bits of the data signal of the merge sort result are used as a partial output signal.

[0049] Here, merge sort refers to a sorting process of first ordering each subsequence in the data signal in the comparison result, and then merging the ordered subsequences to obtain a completely ordered merge sort result.

[0050] Partial merge sort processing means that the merge sort result obtained is not completely ordered, for example, the order of the data signals at the 3rd and 4th bits is incorrect. Since the number of bits that need to be flipped in the current data is determined based on the data signals at the 3rd and 4th bits in the subsequent process, the incorrect order of the data signals at the 3rd and 4th bits does not affect the number of bits that need to be flipped in the current data that is ultimately determined.

[0051] The processing circuit may include any circuit element capable of performing at least partial merge and sort processing on the data signal in the comparison result to obtain a merge and sort result, which is not limited in the embodiments of the present disclosure.

[0052] In implementation, for an 8-bit merge sort result, the middle two data signals are the 3rd and 4th bits respectively; for a 16-bit merge sort result, the middle two data signals are the 7th and 8th bits respectively.

[0053] In the disclosed embodiment, the processing circuit in the data bus flipping circuit performs at least a partial merge sorting process on the data signal in the comparison result to obtain a merge sorting result, wherein the middle two data signals of the merge sorting result are used as partial output signals. In this way, compared with other methods for determining the number of bits that need to be flipped in the current data, the merge sorting result is obtained by merge sorting, and the number of bits that need to be flipped in the current data is determined based on partial output signals in the merge sorting result, which can further simplify the circuit complexity.

[0054] In some embodiments, the number of bits of the data signal in the comparison result includes 8*2 n bits; the value of n is an integer greater than or equal to 0;

[0055] The processing circuit includes (2 i )2 (j+3) The sorting module of each bit is (j+3) The bit sorting module is used to sort the input 2 (j+3) Sort the bit data and get 2 (j+3) Bit sort result; where:

[0056] The value of j is an integer starting from n and greater than or equal to 0, i+j=n, and the value of i is an integer starting from 0 and less than or equal to n;

[0057] When the value of j is greater than or equal to 1, 2 (j+2) The sorting result of the bit sorting module is 2 (j+3) The input data of the bit sorting module.

[0058] In some embodiments, when j is equal to 0, each 8-bit sorting module is used to sort the data signal that divides each non-repeating adjacent 8 bits in the comparison result into a group to obtain an 8-bit sorting result; when n=0, the processing circuit includes 1 8-bit sorting module, and the 8-bit sorting result is used as a merge sorting result.

[0059] Each 8-bit sorting module divides each non-repeating adjacent 8 bits in the comparison result into a group of data signals, so that the data signals in two adjacent groups are not repeated. For example, if the comparison result includes 16-bit data signals, the data signals of bits 0 to 7 are divided into one group, and the data signals of bits 8 to 15 are divided into one group.

[0060] In some embodiments, the 8-bit sorting module may include 2 p 2 q The ordering unit of bits; every 2 q The bit sorting unit is used to convert the input 2 q The bit data signal is sorted to obtain 2 q Bit sort result;

[0061] Among them: the value of q is an integer starting from 3 and greater than or equal to 1, the value of p is an integer starting from 0 and less than 2, p+q=3; when the value of q is greater than or equal to 1, 2 2 q The sorting result of the sorting unit of the bit is taken as 2 (q+1) The input data of the bit sorting unit.

[0062] When implementing, refer to Figure 2 and Figure 3 , the 8-bit sorting module 11 includes 4 2-bit sorting units 111, 2 4-bit sorting units 112 and 1 8-bit sorting unit 113, wherein: each 2-bit sorting unit 111 is used to sort each non-repeating adjacent two-bit data signal in the 8-bit data signal to obtain a 2-bit sorting result; each 4-bit sorting unit 112 is used to sort the 4-bit sorting results output by each non-repeating adjacent two 2-bit sorting units to obtain a 4-bit sorting result; and the 8-bit sorting unit 113 is used to sort the 8-bit sorting results output by each non-repeating adjacent two 4-bit sorting units to obtain an 8-bit sorting result. It can be seen from the above that the sorting results of two 2-bit sorting units 111 will be used as input data of a 4-bit sorting unit 112, and the sorting results of two 4-bit sorting units 112 will be used as input data of an 8-bit sorting unit 113.

[0063] In some embodiments, continue to refer to Figure 2 , each 4-bit sorting unit 112 includes:

[0064] The first sorting subunit 1121 is used for sorting the two-bit data signals at the same position for each non-repeating two adjacent 2-bit sorting results output by the sorting units 111 to obtain a first sub-sorting result;

[0065] The 4-bit sorting subunit 1122 is used to sort the middle two bits of the data signal of the first sub-sorting result to obtain a 4-bit sorting result.

[0066] It should be noted that the 4-bit sorting subunit 1122 sorts the two middle data signals of the first sub-sorting result, and does not sort the first and last two data signals of the first sub-sorting result. Therefore, the first and last two data signals in the obtained 4-bit sorting result are the same as the first and last two data signals in the first sorting sub-result.

[0067] In some embodiments, continue to refer to Figure 2 , each 8-bit sorting unit 113 includes:

[0068] The second sorting subunit 1131 is used to sort the two-bit data signals at the same position for each non-repeating 8-bit sorting result output by two adjacent 4-bit sorting units to obtain a second sub-sorting result;

[0069] The 8-bit sorting subunit 1132 is used to divide each non-repeating adjacent two-bit data signal into a first group for the middle 4-bit data signal of the second sub-sorting result, and sort the two-bit data signals with the same position in two first groups respectively to obtain an 8-bit sorting result.

[0070] It should be noted that the 8-bit sorting subunit 1132 sorts the middle 4-bit data signal of the second sub-sorting result, and does not sort the other bit data signals of the second sub-sorting result (for example, the 0th, 1st, 6th and 7th bit data signals). Therefore, the 0th, 1st, 6th and 7th bit data signals in the obtained 8-bit sorting result are respectively the same as the 0th, 1st, 6th and 7th bit data signals in the second sorting result.

[0071] When j is equal to 1, each 16-bit sorting module is used to sort the data signals at the corresponding positions of each two non-repeating adjacent 8-bit first sorting results to obtain a 16-bit sorting result; when n is equal to 1, refer to Figure 5 The processing circuit includes two 8-bit sorting modules 11 and one 16-bit sorting module 12, and the 16-bit sorting result is used as the merge sorting result.

[0072] When j is equal to 2, each 32-bit sorting module is used to sort the data signals at the corresponding positions of two non-repeating adjacent 16-bit second sorting results to obtain a 32-bit sorting result; when n=2, the processing circuit includes 4 8-bit sorting modules, 2 16-bit sorting modules and 1 32-bit sorting module, and the 32-bit sorting result is used as the merge sorting result.

[0073] In the disclosed embodiment, not only 8-bit data signals can be sorted, but also other bits, such as 16, 32 or 64-bit data signals, can be sorted, which can expand the scope of application of the data bus flip circuit.

[0074] In some embodiments, reference Figure 4 and Figure 5 Each 16-bit sorting module 12 includes: a 16-bit sorting unit 121; the 16-bit sorting unit 121 includes a third sorting subunit 1211, a fourth sorting subunit 1212 and a 16-bit sorting subunit 1213, wherein:

[0075] The third sorting subunit 1211 is used to sort the two-bit data signals at the same position for each non-repeating 16-bit sorting result output by two adjacent 8-bit sorting units to obtain a third sub-sorting result;

[0076] The fourth sorting subunit 1212 is used to divide each non-repeating adjacent 4-bit data signal into a second group for the middle 8-bit data signal of the third sub-sorting result, and compare the 4-bit data signals with the same position in two second groups to obtain a fourth sub-sorting result;

[0077] The 16-bit sorting subunit 1213 is used to divide each non-repeating adjacent two-bit data signal into a third group for the middle 4-bit data signal of the fourth sub-sorting result, and sort the two-bit data signals with the same position in two third groups respectively to obtain a 16-bit sorting result.

[0078] In some embodiments, each 16-bit sorting module also includes a fifth sorting subunit, which is used to sort the two middle data signals of the 8-bit sorting result to obtain a fifth sorting sub-result; the third sorting subunit is also used to sort the two data signals in the same position of each non-repeating 16-bit sorting result output by two adjacent fifth sorting subunits to obtain a third sub-sorting result, and the fourth sorting subunit and the 16-bit sorting subunit are further sorted.

[0079] When D<0:7>=D<8:15>, a structure without the fifth sorting subunit may be used. When D<0:7> is not equal to D<8:15>, for example, when D<0:15>=0001011100011111, a structure without the fifth sorting subunit needs to be used. Therefore, a selection module may be provided. The selection module is used to receive D<0:15>, and to determine whether D<0:7> is equal to D<8:15>, and to determine whether to start the fifth sorting subunit according to the determination result. That is, when D<0:7>=D<8:15>, the fifth sorting subunit is shielded, and the 16-bit sorting results of the two 8-bit sorting modules 11 are directly sent to the third sorting subunit 1211. When D<0:7>≠D<8:15>, the fifth sorting subunit is enabled, and the 16-bit sorting results of the two 8-bit sorting modules 11 are first sent to the fifth sorting subunit, and then the output of the fifth sorting subunit is sent to the third sorting subunit. It can be understood that the 16-bit sorting result of the fifth sorting subunit is partially identical to the 16-bit sorting results of the two 8-bit sorting modules 11, and only the re-sorted fourth and fifth digits and the twelfth and thirteenth digits may be different.

[0080] In addition, it can be understood that the meaning of "sorting" of the fifth sorting subunit is the same as the meaning of "sorting" in the 8-bit sorting module 11 and the "sorting" in the third sorting subunit. In addition, the selection module can also directly receive a flag signal indicating whether D<0:7> is equal to D<8:15>, and determine whether to shield the fifth sorting subunit based on the flag signal, that is, the fifth sorting subunit can be closed or opened by default; the fifth sorting subunit can also be in a normally open state, that is, it is always connected between the 8-bit sorting module 11 and the third sorting subunit and enabled.

[0081] In some embodiments, reference Figure 6 , each 2-bit sorting unit 111 includes one first logic unit 40 .

[0082] refer to Figure 7 , each first sorting subunit 1121 includes two first logic units 40 .

[0083] refer to Figure 8 , each 4-bit sorting subunit 1122 includes one first logic unit 40.

[0084] refer to Fig. 9 , each second sorting subunit 1131 includes four first logic units 40 .

[0085] refer to Fig.10 , each 8-bit sorting subunit 1132 includes two first logic units 40 .

[0086] Please continue to see Figure 6 Each first logic unit 40 includes at least one first AND gate 401 and a first OR gate 402; the first input terminal and the second input terminal of the first AND gate 401 are respectively connected to the first input terminal and the second input terminal of the first OR gate 402, and are respectively connected to nodes A and B for inputting data signals. The output terminal G of the first AND gate 401 is used to output the first type of data signal; the output terminal P of the first OR gate 402 is used to output the second type of data signal; the potential of the first type of data signal is less than or equal to the potential of the second type of data signal. In the sorting result, the first type of data signal will eventually be on the left of the second type of data signal.

[0087] In some embodiments, each third sorting subunit includes 8 first logic units; each fourth sorting subunit includes 4 first logic units; and each 16-bit sorting subunit includes 2 first logic units.

[0088] In the disclosed embodiment, a first logic unit consisting of a first AND gate and a first OR gate is used to merge and sort the comparison results of the current data and the previous data to obtain a merged sort result. That is, only AND gates and OR gates are used during sorting, which can simplify the data bus flip circuit.

[0089] The following will be combined Figure 3 , Figures 6 to 10 , taking the comparison result D<7:0> of 11110010 as an example, the role of each unit in the 8-bit sorting module is explained in detail.

[0090] First, refer to Figure 6 and Figure 3Perform 1 sort: the first 2-bit sort unit 111 pairs D <0> =0 and D <1> = 1 to sort, the output of the first AND gate 401 is G <0> = 0, the output terminal P of the first OR gate 402 outputs the result P <0> =1, so the 2-bit sorting result is 10. The second 2-bit sorting unit 111 is D <2> =0 and D <3> = 0, the output of the first AND gate 401 is G <1> = 0, the output terminal P of the first OR gate 402 outputs the result P <1> =0, so the 2-bit sorting result is 00. The third 2-bit sorting unit 111 is for D <4> =1 and D <5> = 1 to sort, the output of the first AND gate 401 is G <2> =1, the output terminal P of the first OR gate 402 outputs the result P <2> =1, so the 2-bit sorting result is 11. The fourth 2-bit sorting unit 111 is D <6> =1 and D <7> = 1 to sort, the output of the first AND gate 401 is G <3> =1, the output terminal P of the first OR gate 402 outputs the result P <3> =1, so the 2-bit sorting result is 11. From the above, it can be obtained that the sorting result after the four 2-bit sorting units 111 sort D<7:0> is 11110010.

[0091] Secondly, refer to Figure 7 and Figure 3 Perform two sorting operations: the two first logic units 40 in the first sorting subunit 1121 respectively sort the two-bit data signals at the same position of the 2-bit sorting result 10 and the 2-bit sorting result 00, and obtain the first sub-sorting result of 1000, that is, U <1> =0,P <4> =0, F <4> =0,U <2> =1. The two first logic units 40 in the second first sorting subunit 1121 respectively sort the 2-bit sorting result 11 and the two-bit data signal at the same position of the 2-bit sorting result 11, and obtain the first sub-sorting result of 1111, that is, L <1> =1,P <5> =1, F <5> =1,L <2> = 1. From the above, it can be obtained that the sorting result after the two first sorting subunits 1121 sort 11110010 is 11111000.

[0092] Again, reference Figure 8 and Figure 3The first logic unit 40 in the first 4-bit sorting sub-unit 1122 performs three sorting operations on the middle two-bit data signals (i.e., P <4> =0 and F <4> =0) to sort, the output terminal G of the first AND gate 401 outputs the result H <4> =0, the output terminal P of the first OR gate 402 outputs the result G <4> =0, and the 4-bit sorting result is 1000. The first logic unit 40 in the second 4-bit sorting subunit 1122 processes the middle two data signals (i.e., P <5> =1 and F <5> =1) to sort, the output terminal G of the first AND gate 401 outputs the result H <5> =1, the output terminal P of the first OR gate 402 outputs the result G <5> =1, and the 4-bit sorting result is 1111. From the above, it can be obtained that the sorting result after the two 4-bit sorting sub-units 1122 sort 11111000 is 11111000.

[0093] Again, reference Fig. 9 and Figure 3 The four first logic units 40 in the second sorting subunit 1131 respectively sort the 0th data signal (i.e., U <1> =0) and the 4th data signal (i.e. L <1> =1), the first data signal (ie H <4> =0) and the 5th data signal (i.e. H <5> =1), the second data signal (i.e. G <4> =0) and the 6th data signal (i.e. G <5> =1) and the third data signal (i.e., U <2> =1) and the 7th data signal (i.e. L <2> =1) to sort, the outputs G of the four first AND gates 401 are respectively output as O <0> =0,O <1> =0,O <2> =0 and O <3> =1, the output results of the four first OR gates 402 output terminals P are respectively 0 <4> =1, O <5> =1, O <6> =1 and O <7> =1, and the second sub-sort result is 11111000.

[0094] Finally, reference Fig.10 and Figure 3The 8-bit sorting subunit 1132 is used to sort the 4-bit data signal in the middle of the second sub-sorting result by dividing the 2nd data signal and the 3rd data signal into the first group, and the 4th data signal and the 5th data signal into the first group, respectively, through the two first logic units 40 in the 8-bit sorting subunit 1132, the 2nd data signal (that is, 0 <2> =0) and the 4th data signal (ie, O <4> =1), the third data signal (ie, 0 <3> =1) and the 5th data signal (ie, O <5> =1) to sort, the output ends G of the two first AND gates 401 respectively output the results O1 <2> =0 and O1 <3> =1, the output terminals P of the two first OR gates 402 respectively output the results O1 <4> =1 and O1 <5> =1, and the 8-bit sorting result is 11111000. In implementation, the 8-bit sorting result can be recorded as O1<7:0>, so O1<7:0> is 11111000, O1 <3> and O1 <4> They are 1 and 1 respectively. Combined with the following analysis, we can know that the number of bits that need to be flipped in the current data is greater than 5.

[0095] The following will be combined Figure 3 and Figures 6 to 10 , taking the comparison result D<7:0> of 00010101 as an example, the role of each unit in the 8-bit sorting module is explained in detail.

[0096] First, refer to Figure 6 and Figure 3 Perform 1 sort: the first 2-bit sort unit 111 pairs D <0> =1 and D <1> = 0, the output of the first AND gate 401 is G <0> = 0, the output terminal P of the first OR gate 402 outputs the result P <0> =1, so the 2-bit sorting result is 10. The second 2-bit sorting unit 111 is D <2> =1 and D <3> = 0, the output of the first AND gate 401 is G <1> = 0, the output terminal P of the first OR gate 402 outputs the result P <1> =1, so the 2-bit sorting result is 10. The third 2-bit sorting unit 111 is D <4> =1 and D <5> = 0, the output of the first AND gate 401 is G <2> = 0, the output terminal P of the first OR gate 402 outputs the result P <2> =1, so the 2-bit sorting result is 10. The fourth 2-bit sorting unit 111 is for D <6> =0 and D <7> = 0, the output of the first AND gate 401 is G <3> = 0, the output terminal P of the first OR gate 402 outputs the result P <3> =0, so the 2-bit sorting result is 00. From the above, it can be obtained that the sorting result after the four 2-bit sorting units 111 sort D<7:0> is 00101010.

[0097] Secondly, refer to Figure 7 and Figure 3 Perform 2 sorting: The two first logic units 40 in the first first sorting subunit 1121 respectively sort the 2-bit sorting result 10 and the two-bit data signal at the same position of the 2-bit sorting result 10, and obtain the first sub-sorting result of 1010, that is, U <1> =0,P <4> =1, F <4> =0,U <2> =1. The two first logic units 40 in the second first sorting subunit 1121 respectively sort the two-bit data signals at the same position of the 2-bit sorting result 10 and the 2-bit sorting result 00, and obtain the first sub-sorting result of 1000, that is, L <1> =0,P <5> =0, F <5> =0,L <2> = 1. From the above, it can be obtained that the sorting result after the two first sorting subunits 1121 sort 001010 is 10001010.

[0098] Again, reference Figure 8 and Figure 3 The first logic unit 40 in the first 4-bit sorting sub-unit 1122 performs three sorting operations on the middle two-bit data signals (i.e., P <4> =1 and F <4> =0) to sort, the output terminal G of the first AND gate 401 outputs the result H <4> =0, the output terminal P of the first OR gate 402 outputs the result G <4> =1, and the 4-bit sorting result is 1100. The first logic unit 40 in the second 4-bit sorting subunit 1122 processes the middle two data signals (i.e., P <5> =0 and F <5> =0) to sort, the output terminal G of the first AND gate 401 outputs the result H <5> =0, the output terminal P of the first OR gate 402 outputs the result G <5> =0, and the 4-bit sorting result is 1000. From the above, it can be obtained that the sorting result after the two 4-bit sorting sub-units 1122 sort 10001010 is 10001100.

[0099] Again, reference Fig. 9 and Figure 3The four first logic units 40 in the second sorting subunit 1131 respectively sort the 0th data signal (i.e., U <1> =0) and the 4th data signal (i.e. L <1> =0), the first data signal (i.e. H <4> =0) and the 5th data signal (i.e. H <5> =0), the second data signal (i.e. G <4> =1) and the 6th data signal (i.e. G <5> =0) and the third data signal (i.e., U <2> =1) and the 7th data signal (i.e. L <2> =1) to sort, the outputs G of the four first AND gates 401 are respectively output as O <0> =0,O <1> =0,O <2> =0 and O <3> =1, the output results of the four first OR gate output terminals P are respectively O <4> =0,O <5> =0,O <6> =1 and O <7> =1, and the second sub-sort result is 11001000.

[0100] Finally, reference Fig.10 and Figure 3 The 8-bit sorting subunit 1132 is used to sort the 4-bit data signal in the middle of the second sub-sorting result by dividing the 2nd data signal and the 3rd data signal into the first group, and the 4th data signal and the 5th data signal into the first group, respectively, through the two first logic units 40 in the 8-bit sorting subunit 1132, the 2nd data signal (that is, 0 <2> =0) and the 4th data signal (ie, O <4> =0), the third data signal (ie, 0 <3> =1) and the 5th data signal (ie, O <5> =0) for sorting, the output terminals G of the two first AND gates 401 respectively output the results O1 <2> =0 and O1 <3> =0, the output terminals P of the two first OR gates 402 respectively output the results O1 <4> =0 and O1 <5> =1, and the 8-bit sorting result is 11100000. In implementation, the 8-bit sorting result can be recorded as O1<7:0>, so O1<7:0> is 11100000, O1 <3> and O1 <4> They are 0 and 0 respectively. Combined with the following analysis, we can know that the number of bits that need to be flipped in the current data is less than 4.

[0101] The following will be combined Figures 5 to 10 , taking the comparison result D<15:0> of 1011111110111111 as an example, the final merge sort result is described in detail.

[0102] First, refer to Figure 5 and Figure 6 Perform one sorting: eight 2-bit sorting units 111 sort each non-repeating adjacent two-bit data signal of D<15:0>. The sorting result after the eight 2-bit sorting units 111 sort D<15:0> is 10111111101111111.

[0103] Secondly, refer to Figure 5 and Figure 7 Perform two sortings: after the four first sorting subunits 1121 sort 1011111110111111, the sorting result is 11101111111101111.

[0104] Again, reference Figure 6 and Figure 8 After three sorting operations are performed, the sorting result after four 4-bit sorting subunits 1122 sort 1110111111101111 is 11101111111101111.

[0105] Again, reference Figure 7 and Fig. 9 After four sorting operations are performed, the sorting result after the two second sorting subunits 1131 sort 1110111111101111 is 11111111011111110.

[0106] Again, reference Figure 8 and Fig.10 After five sorting operations are performed, the sorting result after the two 8-bit sorting subunits 1132 sort 1111111011111110 is 111111110111111110.

[0107] Again, reference Figure 5 After six sorting operations, the sorting result after the third sorting subunit 1211 sorts 1111111011111110 is 111111110111111110.

[0108] Again, reference Figure 5 After seven sorting operations, the fourth sorting subunit 1212 sorts 1111111011111110, and the sorting result is 11111111111101110.

[0109] Again, reference Figure 5 After 8 sortings, the 16-bit sorting subunit 1213 sorts 1111111111101110, and the sorting result is 11111111111101110. The middle two data signals of the merge sort result are 11, so the partial output signal is 11. Combined with the following analysis, it can be known that the number of bits that need to be flipped in the current data is greater than 8.

[0110] In some embodiments, the first determination circuit is used to: when some output signals in the output results are all of the first potential, determine that the number of bits that need to be flipped in the current data is greater than or equal to a preset value plus one; when some output signals in the output results are all of the second potential, determine that the number of bits that need to be flipped in the current data is less than a preset value; when some output signals in the output results are different, determine that the number of bits that need to be flipped in the current data is the preset value.

[0111] Here, the first potential can be a high potential (i.e., 1), and the second potential can be a low potential (i.e., 0). The preset value is related to the number of data signal bits of the current data or the comparison result. For example, if the number of data signal bits of the current data is 8, the preset value is half of the number of data signal bits of the current data, i.e., 4; for another example, if the number of data signal bits of the current data is 16, the preset value is 8.

[0112] For example, when the data signals of the 3rd and 4th bits in the output result are both 1, at least 5 bits in the current data need to be flipped; when the data signals of the 3rd and 4th bits in the output result are both 0, the number of bits that need to be flipped in the current data is less than 4, and the current data does not need to be flipped; when there is a 1 in the data signals of the 3rd and 4th bits in the output result, four bits in the current data need to be flipped.

[0113] In some embodiments, reference Fig.11 , when the number of bits to be flipped in the current data is a preset value, the second determination circuit 30 includes:

[0114] The first operation module 31 is used to perform a partial operation on a part of the output signal (for example, O1 <3> and O1 <4> ) performs a first operation to obtain a first output signal Y1;

[0115] The second operation module 32 is used to perform a second operation on a part of the output signals in the output result, the first output signal Y1 and the data flip signal DBI_before corresponding to the previous data to determine the data flip signal DBI_next corresponding to the current data.

[0116] During implementation, continue to refer to Fig.11 The first operation module 31 may include a first XOR gate 311 ; the second operation module 32 may include a second AND gate 321 , a second NOR gate 322 , and a second OR gate 323 .

[0117] The second NOR gate 322 is used to output a part of the output signal (for example, O1 <3> and O1 <4> ) is used to perform an OR operation to obtain the second output signal Y2. The second AND gate 321 is used to perform an AND operation on the data flip signal DBI_before corresponding to the previous data and the first output signal Y1 to obtain the third output signal Y3; the second OR gate 323 is used to perform an OR operation on the second output signal Y2 and the third output signal Y3 to obtain the data flip signal DBI_next corresponding to the current data.

[0118] In the embodiment of the present disclosure, when the number of bits that need to be flipped in the current data is a preset value, the data flip signal corresponding to the current data can be obtained by only using the first XOR gate in the first operation module, the second AND gate, the second NOR gate and the second OR gate in the second operation module. This can reduce the number of circuit levels and thus reduce the calculation time of the data flip signal corresponding to the current data.

[0119] The present disclosure provides a data bus flip circuit. Figure 1 , the data bus flip circuit 100 comprises:

[0120] The processing circuit 10 is used to perform at least logic operation processing on the data signal in the comparison result to obtain a logic operation result; wherein the first and last two data signals of the logic operation result are used as part of the output signal.

[0121] The logic operation processing includes inverting the same two-bit data signal and outputting a high potential and a low potential of a fixed data bit for different two-bit data signals.

[0122] The first determination circuit 20 is used to determine the number of bits that need to be flipped in the current data based on a part of the output signals in the output result, where the data bits of the part of the output signals are determined by a sorting processing rule.

[0123] The second determination circuit 30 is used to determine the data flip signal corresponding to the current data based on the number of bits that need to be flipped in the current data and the data flip signal corresponding to the previous data.

[0124] Here, outputting high potential and low potential of fixed data bits for different two-bit data signals means that when the two-bit data signals are 0 and 1 or 1 and 0 respectively, the output after logic operation is a high potential (i.e., 1) and a low potential (i.e., 0). In implementation, the logic operation can be implemented by using a NAND gate and a NOR gate.

[0125] In some embodiments, reference Fig.12 , the number of bits of the data signal in the comparison result includes 8 bits; the processing circuit 10 includes the following 5 types of processing units:

[0126] The first processing unit 101 is used to perform a logic operation on each non-repeating adjacent two-bit data signal in the 8-bit data signal to obtain a first operation result;

[0127] The second processing unit 102 is used for dividing each non-repeating adjacent 4-bit data signal into a fourth group for the first operation result; dividing each non-repeating adjacent 2-bit data signal of each fourth group into a fifth group; for each fourth group in the first operation result, performing a logic operation on the 2-bit data signals at the same position in two fifth groups to obtain a second operation result;

[0128] The third processing unit 103 is used to divide each non-repeating adjacent 4-bit data signal into a sixth group for the second operation result; perform a logic operation on the first and last two bits of the data signal in each sixth group to obtain a third operation result;

[0129] The fourth processing unit 104 is used to divide each non-repeating adjacent 4-bit data signal into a seventh group for the third operation result; perform logic operation processing on the two-bit data signals at the same position in two seventh groups to obtain a fourth operation result; and invert the first bit result and the sixth bit result in the fourth operation result to obtain a fifth operation result;

[0130] The fifth processing unit 105 is used for dividing each non-repeating adjacent two-bit data signal into an eighth group for the fifth operation result; performing logic operation processing on the two-bit data signals in the first and last eight groups to obtain a logic operation result.

[0131] When implementing, refer to Figures 13 to 17 , the first processing unit 101 and the second processing unit 102 may each include four second logic units 50; the third processing unit 103 and the fifth processing unit 105 include two second logic units 50; the fourth processing unit 104 includes two second logic units 50, one third logic unit 60 and one fourth logic unit 70;

[0132] Each second logic unit 50 includes a NAND gate 501 and a first NOR gate 502; the third logic unit 60 includes a second logic unit 50 and a first inverter 61 connected to the output terminal P of the first NOR gate 502 in the second logic unit 50; the fourth logic unit 70 includes a second logic unit 50 and a second inverter 71 connected to the output terminal G of the NAND gate 501 in the second logic unit 50; wherein the first input terminal and the second input terminal of the NAND gate 501 are respectively connected to the first input terminal and the second input terminal of the first NOR gate 502, and are respectively connected to nodes A and B for inputting data signals.

[0133] In the disclosed embodiment, a second logic unit consisting of a NAND gate and a first NOR gate is used to perform a logic operation on the comparison result between the current data and the previous data to obtain a logic operation result. That is, only NAND gates and NOR gates are used in the logic operation processing. Compared with using an AND gate (obtained by combining a NAND gate + a NOT gate) and an OR gate (obtained by combining a NOR gate + a NOT gate) to process the comparison result, using NAND gates and NOR gates can simplify the circuit to reduce the number of levels.

[0134] The following example takes the comparison result D<7:0> as 11110010 as an example, and combines Figures 13 to 18 The processing process of the comparison result D<7:0> between the current data and the previous data by the processing circuit 10 is described in detail.

[0135] refer to Fig.13 The four second logic units 50 in the first processing unit 101 are respectively for D <0> =0 and D <1> =1, D <2> =0 and D <3> =0, D <4> =1 and D <5> =1, D <5> =1 and D <6> =1 to perform logic operation, the two output terminals G and P of the first second logic unit 50 respectively output G <0> =1,P <0> =0; the two output terminals G and P of the second second logic unit 50 respectively output G <1> =1,P <1> =1; the two output terminals G and P of the third second logic unit 50 respectively output G <2> =0,P <2> =0; the two output terminals G and P of the fourth second logic unit 50 respectively output G <3> =0,P <3> = 0. From the above, we can get the first operation result is 00001101.

[0136] For the first operation result 00001101, each non-repeating adjacent 4-bit data signal is divided into the fourth group. The first fourth group is 1101, and 1101 is divided into the fifth group, that is, 11 and 01; the second fourth group is 0000, and 0000 is divided into the fifth group, that is, 00 and 00. Fig.14 , through the four second logic units 50 in the second processing unit 102, respectively <0> =1 and G <1> =1, P <0> =0 and P <1> =1, G <2> =0 and G <3> =0, P <2> =0 and P <3> =0 to perform logic operation, the two output terminals G and P of the first second logic unit 50 respectively output U <1> =0 and F <4> =0; the two output terminals G and P of the second second logic unit 50 respectively output P <4> =1 and U <2> =0; the two output terminals G and P of the third second logic unit 50 respectively output L <1> =1 and F <5> =1; the two output terminals G and P of the fourth second logic unit 50 respectively output P <5> =1 and L <2> = 1. From the above, we can get the second operation result is 11110010.

[0137] For the second operation result 11110010, each non-repeating adjacent 4-bit data signal is divided into the sixth group; the first sixth group is 0010, and the second sixth group is 1111. The first and last two bits of the data signal in each sixth group are subjected to logic operation processing. Fig.15 , through the two second logic units 50 in the third processing unit 103 respectively <1> =0 and U <2> =0, L <1> =1 and L <2> =1 respectively perform logic operation processing, and the two output terminals G and P of the first second logic unit 50 respectively output H <4> =1 and G <4> =1, the two output terminals G and P of the second second logic unit 50 respectively output H <5> =0 and G <5> = 0. From the above, we can get the third operation result is 01101011.

[0138] For the third operation result 01101011, each non-repeating adjacent 4-bit data signal is divided into the seventh group; the first seventh group is 1011, and the second seventh group is 0110. The two-bit data signals at the same position in the two seventh groups are subjected to logic operation processing. Fig.16 , the four second logic units 50 in the fourth processing unit 104 respectively process H <4> =1 and H <5> =0, P <4> =1 and P <5> =1, F <4> =0 and F <5> =1, G <4> =1 and G <5> =0 respectively perform logic operation processing, and the two output terminals G and P of the first second logic unit 50 respectively output 0 <2> =1 and O <6> =0; the two output terminals G and P of the second second logic unit 50 respectively output 0 <4> ' = 0 and O <0> =0; the two output terminals G and P of the third second logic unit 50 respectively output 0 <7> =1 and O <3> '=0; the two output terminals G and P of the fourth second logic unit 50 respectively output 0 <1> =1 and O <5> =0. From the above, the fourth operation result can be obtained as 00001101. The first bit result and the sixth bit result in the fourth operation result 00001101 are inverted by the second inverter 81 and the first inverter 71, Fig.18 The shaded circle 90 represents O <3> ' = 0 and O <4> '=0 and reverse, we get O <3> =1 and O <4> =1, and the final result of the fifth operation is 01001111.

[0139] For the fifth operation result 01001111, each non-repeating adjacent two-bit data signal is divided into the eighth group; the two-bit data signals in the first and last eight groups, 01 and 11, are subjected to logic operation processing. Fig.17, through the two second logic units 50 in the fifth processing unit 105, respectively <2> =1 and O <4> =1, O <3> =1 and O <5> =0 to perform logic operation, the two output terminals G and P of the first second logic unit 50 respectively output O1 <4> =0 and O1 <2> =0; the two output terminals G and P of the second second logic unit 50 respectively output O1 <5> =1 and O1 <3> =0, the final logical operation result is 01010100. The first and last two data signals are O1 <3> =0 and O1 <4> =0 as partial output signal.

[0140] In some embodiments, the first determination circuit is used to: determine that the number of bits to be flipped in the current data is less than a preset value when some output signals in the output result are all at the first level;

[0141] When some output signals in the output result are at the second level, determining that the number of bits to be flipped in the current data is greater than or equal to a preset value plus one;

[0142] When some output signals in the output result are different, it is determined that the number of bits that need to be flipped in the current data is a preset value; wherein the preset value is half of the number of data signal bits of the current data.

[0143] The first and last two data signals are, for example, O1 <3> and O1 <4> When both are 1, it is determined that the number of bits that need to be flipped in the current data is less than 4; when the first and last two data signals are, for example, O1 <3> and O1 <4> When both are 0, it is determined that the number of bits to be flipped in the current data is greater than or equal to 5; when the first and last two data signals are, for example, O1 <3> and O1 <4> Under different circumstances, it is determined that the number of bits that need to be flipped in the current data is 4.

[0144] When the number of bits that need to be flipped in the current data is 4, a second determination circuit is required to determine the data flip signal corresponding to the current data based on the number of bits that need to be flipped in the current data and the data flip signal corresponding to the previous data. This part has been explained in detail above and will not be repeated here.

[0145] The present disclosure provides a memory, referring to Fig.19 The memory 300 at least includes the data bus flip circuit 100 in any one of the above embodiments.

[0146] In some embodiments, the memory 300 further includes a storage unit 301, a latch 302, a third AND gate 303, and a second XOR gate 304. When reading data from the storage unit 301, the current data (taking an 8-bit data signal as an example) is XOR-compared with the previous data in the latch to obtain a comparison result; then the data bus flip circuit 100 performs at least a partial sorting process on the comparison result to obtain an output result, and determines the number of bits to be flipped in the current data based on a portion of the output signals in the output result, and determines the data flip signal DBI_next corresponding to the current data based on the number of bits to be flipped in the current data and the data flip signal corresponding to the previous data. Then the third AND gate 303 performs an AND operation on the enable signal in the mode register and the data flip signal DBI_next corresponding to the current data. When DBI_next is at a high level and the enable signal is enable, the third AND gate 303 outputs the data flip signal DBI_next corresponding to the current data and latches DBI_next into the latch 302 for use in determining whether the next data needs to be flipped. At the same time, the second XOR gate 304 performs an XOR operation on the data flip signal DBI_next corresponding to the current data and the current data, outputs the current data that has not been flipped or the flipped data DQ, and latches the data signal of the above data DQ into the latch 302 for use in determining whether the next data needs to be flipped.

[0147] It should be noted that Fig.19 The data signal latched into the latch 302 has 9 bits, including 8 bits of data signals in the current data and 1 bit of data flip signal DBI_next corresponding to the current data.

[0148] When writing data to the storage unit 301 in the memory 300, the third AND gate 303 will perform an AND operation on the enable signal in the mode register and the data flip signal DBI_next corresponding to the current data, and then the second XOR gate 304 will perform an XOR operation on the AND operation result and the current data. When DBI_next is a high level and the enable signal is enable, the current data is flipped, thereby writing real data into the storage unit 301.

[0149] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-targeted manner. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0150] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0151] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0152] The above are only some implementations of the embodiments of the present disclosure, but the protection scope of the embodiments of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the embodiments of the present disclosure, which should be included in the protection scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be based on the protection scope of the claims.

Claims

1. A data bus flip circuit, characterized in that: The circuit comprises: A processing circuit, used for performing at least a partial sorting process on the data signal in the comparison result between the current data and the previous data to obtain an output result; A first determination circuit is used to determine the number of bits that need to be flipped in the current data based on a portion of output signals in the output result, wherein the data bits of the portion of output signals are determined by the rule of the sorting process; The second determination circuit is used to determine the data flip signal corresponding to the current data based on the number of bits that need to be flipped in the current data and the data flip signal corresponding to the previous data.

2. The circuit according to claim 1, characterized in that The processing circuit is used to perform at least a partial merge sort process on the data signal in the comparison result to obtain a merge sort result; The middle two bits of data signals of the merge sort result are used as the partial output signal.

3. The circuit according to claim 2, characterized in that The number of bits of the data signal in the comparison result includes 8*2 n The value of n is an integer greater than or equal to 0; The processing circuit includes (2 i )2 (j+3) The sorting module of each bit is 2 (j+3) The bit sorting module is used to sort the input 2 (j+3) Sort the bit data and get 2 (j+3) Bit sort result; where: The value of j is an integer greater than or equal to 0, i+j=n, and the value of i is an integer starting from 0 and less than or equal to n; When the value of j is greater than or equal to 1, 2 (j+2) The sorting result of the bit sorting module is 2 (j+3) The input data of the bit sorting module.

4. The circuit according to claim 3, characterized in that Each 8-bit sorting module consists of 2 p 2 q The ordering unit of bits; Each of the 2 q The bit sorting unit is used to convert the input 2 q The bit data signal is sorted to obtain 2 q Bit sort result; Wherein: the value of q is an integer greater than or equal to 1, the value of p is an integer starting from 0 and less than 2, and p+q=3; When the value of q is greater than or equal to 1, 2 q The sorting result of the sorting unit of the bit is taken as 2 (q+1) The input data of the bit sorting unit.

5. The circuit according to claim 3, characterized in that When j is equal to 0, each 8-bit sorting module is used to sort each non-repeating adjacent 8 bits in the comparison result into a group of data signals to obtain an 8-bit sorting result; when n is equal to 0, the processing circuit includes one 8-bit sorting module, and the 8-bit sorting result is used as the merge sorting result; In the case where j is equal to 1, each 16-bit sorting module is used to sort the data signals at the corresponding positions of each two non-repeating adjacent 8-bit first sorting results to obtain a 16-bit sorting result; in the case where n=1, the processing circuit includes two of the 8-bit sorting modules and one 16-bit sorting module, and the 16-bit sorting result is used as the merge sorting result; When j is equal to 2, each 32-bit sorting module is used to sort the data signals at the corresponding positions of two non-repeating adjacent 16-bit second sorting results to obtain a 32-bit sorting result; when n=2, the processing circuit includes 4 of the 8-bit sorting modules, 2 of the 16-bit sorting modules and 1 32-bit sorting module, and the 32-bit sorting result is used as the merged sorting result.

6. The circuit according to claim 4, characterized in that In the case where j=0, the 8-bit sorting module includes 4 2-bit sorting units, 2 4-bit sorting units and 1 8-bit sorting unit, wherein: Each of the 2-bit sorting units is used to sort each non-repeating adjacent two-bit data signal in the 8-bit data signal to obtain a 2-bit sorting result; Each of the 4-bit sorting units is used to sort the 4-bit sorting results output by each non-repeating adjacent two 2-bit sorting units to obtain a 4-bit sorting result; An 8-bit sorting unit is used to sort the 8-bit sorting results output by each non-repeating adjacent two 4-bit sorting units to obtain the 8-bit sorting result.

7. The circuit according to claim 6, characterized in that Each of the 4-bit sorting units comprises: A first sorting subunit is used to sort the two-bit data signals at the same position for each non-repeating 2-bit sorting result output by two adjacent 2-bit sorting units to obtain a first sub-sorting result; The 4-bit sorting subunit is used to sort the middle two data signals of the first sub-sorting result to obtain the 4-bit sorting result.

8. The circuit according to claim 7, characterized in that Each of the 8-bit sorting units comprises: A second sorting subunit is used to sort the two-bit data signals at the same position for each non-repeating 8-bit sorting result output by two adjacent 4-bit sorting units to obtain a second sub-sorting result; The 8-bit sorting subunit is used to divide each non-repeating adjacent two-bit data signal into a first group for the middle 4-bit data signal of the second sub-sorting result, and sort the two-bit data signals with the same position in two of the first groups respectively to obtain the 8-bit sorting result.

9. The circuit according to claim 8, characterized in that Each 16-bit sorting module includes: a 16-bit sorting unit; the 16-bit sorting unit includes a third sorting subunit, a fourth sorting subunit and a 16-bit sorting subunit, wherein: A third sorting subunit is used to sort the two-bit data signals at the same position for each non-repeating 16-bit sorting result output by two adjacent 8-bit sorting units to obtain a third sub-sorting result; a fourth sorting subunit, configured to divide each non-repeating adjacent 4-bit data signal into a second group for the middle 8-bit data signal of the third sub-sorting result, and compare two 4-bit data signals with the same position in the second group to obtain a fourth sub-sorting result; The 16-bit sorting subunit is used to divide each non-repeating adjacent two-bit data signal into a third group for the middle 4-bit data signal of the fourth sub-sorting result, and sort the two-bit data signals with the same position in two of the third groups respectively to obtain the 16-bit sorting result.

10. The circuit according to claim 9, characterized in that Each of the third sorting sub-units includes 8 first logic units; Each of the second sorting subunit and the fourth sorting subunit includes four of the first logic units; Each of the 2-bit sorting units and each of the 4-bit sorting sub-units includes one of the first logic units; Each of the first sorting subunits, the 16-bit sorting subunits and each of the 8-bit sorting subunits comprises two first logic units, Each of the first logic units includes at least one first AND gate and a first OR gate; Among them, the first input terminal and the second input terminal of the first AND gate are respectively connected to the first input terminal and the second input terminal of the first OR gate for inputting data signals; the output terminal of the first AND gate is used to output a first type of data signal; the output terminal of the first OR gate is used to output a second type of data signal; the potential of the first type of data signal is less than or equal to the potential of the second type of data signal.

11. The circuit according to claim 2, characterized in that The first determining circuit is used for: When part of the output signals in the output result are all at the first potential, determining that the number of bits to be flipped in the current data is greater than or equal to a preset value plus one; When part of the output signals in the output result are all at the second potential, determining that the number of bits to be flipped in the current data is less than the preset value; When some output signals in the output result are different, the number of bits that need to be flipped in the current data is determined to be the preset value; wherein the preset value is half of the number of data signal bits of the current data.

12. The circuit according to claim 1, characterized in that The processing circuit is used to perform at least logic operation processing on the data signal in the comparison result to obtain a logic operation result; wherein the first and last two data signals of the logic operation result are used as the partial output signal; The logic operation processing includes inverting the same two-bit data signal and outputting a high potential and a low potential of a fixed data bit for different two-bit data signals.

13. The circuit according to claim 12, characterized in that The number of bits of the data signal in the comparison result includes 8 bits; the processing circuit includes the following 5 types of processing units: A first processing unit, configured to perform the logic operation on each non-repeating adjacent two-bit data signal in the 8-bit data signal to obtain a first operation result; a second processing unit, configured to, for the first operation result, divide each non-repeating adjacent 4-bit data signal into a fourth group; divide each non-repeating adjacent 2-bit data signal of each of the fourth groups into a fifth group; and for each of the fourth groups in the first operation result, perform the logic operation processing on the 2-bit data signals at the same position in two of the fifth groups to obtain a second operation result; a third processing unit, configured to divide each non-repeating adjacent 4-bit data signal into a sixth group based on the second operation result; Perform the logic operation on the first and last two data signals in each of the sixth groups to obtain a third operation result; a fourth processing unit, configured to divide each non-repeating adjacent 4-bit data signal into a seventh group for the third operation result; perform the logic operation on the two-bit data signals at the same position in two of the seventh groups to obtain a fourth operation result; and invert the first bit result and the sixth bit result in the fourth operation result to obtain a fifth operation result; The fifth processing unit is used to divide each non-repeating adjacent two-bit data signal into an eighth group for the fifth operation result; and perform the logic operation processing on the first and last two-bit data signals in the eighth group to obtain the logic operation result.

14. The circuit according to claim 13, characterized in that The first processing unit and the second processing unit each include four second logic units; the third processing unit and the fifth processing unit include two second logic units; the fourth processing unit includes two second logic units, one third logic unit and one fourth logic unit; Wherein: each of the second logic units includes a NAND gate and a first NOR gate; the third logic unit includes the second logic unit and a first inverter connected to the output end of the first NOR gate in the second logic unit; the fourth logic unit includes the second logic unit and a second inverter connected to the output end of the NAND gate in the second logic unit; wherein the first input end and the second input end of the NAND gate are respectively connected to the first input end and the second input end of the first NOR gate for inputting data signals.

15. The circuit according to claim 12, characterized in that The first determining circuit is used for: When some output signals in the output result are at the first level, determining that the number of bits to be flipped in the current data is less than a preset value; When some of the output signals in the output result are at the second level, determining that the number of bits to be flipped in the current data is greater than or equal to the preset value plus one; When some output signals in the output result are different, the number of bits that need to be flipped in the current data is determined to be the preset value; wherein the preset value is half of the number of data signal bits of the current data.

16. A memory, characterized in that: At least comprises the data bus flipping circuit as claimed in any one of claims 1 to 15.

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