Isolated gate driver

Abstract

An isolated gate driver includes: a transformer including a primary winding and a secondary winding; a synchronous rectifier connected between the secondary winding and an output terminal of the isolated gate driver; a first switch including a first terminal connected to a power supply voltage; a second switch including a first terminal connected to a power supply voltage; a first damping resistor connected between the first terminal of the secondary winding and a second terminal of the first switch; a second damping resistor connected between the second terminal of the secondary winding and a second terminal of the second switch; a first inverter including an input terminal connected to the first terminal of the secondary winding and an output terminal connected to the gate terminal of the first switch; and a second inverter including an input terminal connected to the second terminal of the secondary winding and an output terminal connected to the gate terminal of the second switch.

Description

Technical Field

[0001] This invention relates to isolated gate drivers. More specifically, this invention relates to circuitry for managing impedance and leakage inductance in transformer-based isolated gate drivers. Background Technology

[0002] Floating gate drivers, as isolated gate drivers, include components of isolated DC-DC converters and isolators that transmit data separately from the primary side of a transformer to the secondary side of the transformer in the DC-DC converter. However, because power and data are transmitted separately, known floating gate drivers require many components to transmit both power and data. Furthermore, when using a single component, it is difficult to transmit isolated signals and isolated power at high frequencies.

[0003] exist Figure 1 In the conventional floating gate driver shown, a transformer with primary and secondary windings divides the driver into a primary side with circuitry connected to the primary winding Lprim and a secondary side with circuitry connected to the secondary winding Lsec. A positive signal input at terminal TXPP and a negative signal input at terminal TXPN on the primary side of the transformer are rectified by a synchronous rectifier including switches S1, S2, MC1, and MC2, providing output power indicated by the output voltage VSEC across capacitor CSEC. When a positive signal is input at terminal TXPP, the first buffer BUF1 is triggered when it detects a voltage above a threshold level to provide a data signal indicating that a positive signal has been received on the primary side of the transformer. When a negative signal is input at terminal TXPN, the second buffer BUF2 is triggered when it detects a voltage above a threshold level to provide a data signal indicating that a negative signal has been received on the primary side of the transformer. That is, the first buffer BUF1 and the second buffer BUF2 can provide output data signals that are analog or similar to drive signals.

[0004] Switches MC1 and MC2 are used to connect lines TXSP and TXSN to the power supply voltage VSUP-, which can be a reference voltage or ground. When a positive signal is input at terminal TXPP, switch MC1 connects line TXSN to the power supply voltage VSUP-. When a negative signal is input at terminal TXPN, switch MC2 connects line TXSP to the power supply voltage VSUP-. Switching the lines TXSP and TXSN connected to the power supply voltage VSUP- allows power to be transferred to capacitor CSEC. The output power can be used to drive, for example, a gang chip (not shown).

[0005] Figure 1The conventional floating gate driver shown also includes common-mode setting resistors RCM1 and RCM2. The common-mode setting resistors RCM1 and RCM2 preferably have relatively high resistance values ​​(e.g., about 100 kΩ) to reduce power consumption. For example, the common-mode setting resistors RCM1 and RCM2 may have the same or substantially the same resistance values.

[0006] However, as Figure 2 As shown, conventional floating gate drivers are susceptible to ringing, which can cause undesirable changes in the state of the gate driver. For example, when the input signal goes high (e.g., a positive signal input on the primary side of the transformer), a pulse is provided at terminal TXPP. The primary winding Lprim on the primary side of the transformer induces a voltage on the secondary winding Lsec on the secondary side of the transformer at line TXSP, which turns on switch MC1 and charges capacitor CSEC.

[0007] When the input signal goes low and no pulse is provided at the TXPP terminal, the voltage across the primary winding Lprim on the primary side of the transformer becomes zero. However, since energy is stored as the transformer's leakage inductance Llk, ringing due to resonance may occur. More specifically, the current from the transformer's leakage inductance Llk continues to flow until the diode of switch S1 is blocked, causing the voltage across line TXSN to drop rapidly while the voltage across line TXSN rises. The transformer's leakage inductance Llk then passes through zero volts and reverses polarity, repeating the above resonance process.

[0008] During the aforementioned resonance process, the line TXSN may reach a sufficiently high voltage to trigger the second buffer BUF2, causing the floating gate driver to incorrectly provide a data signal indicating that a negative signal has been received, which in turn leads to an undesirable state change of the gate driver.

[0009] In order to reduce the above about Figure 2 The resonant process described can be achieved by adding a resistor Rdamp between the line TXSP and the line TXSN, such as... Figure 3 As shown, resistor Rdamp dissipates the energy accumulated in the leakage inductance Llk of the transformer, thereby reducing ringing on the secondary side of the transformer. Preferably, the resistance of resistor Rdamp is relatively small (e.g., about 200Ω or less) to effectively dissipate the energy of the higher leakage inductance. However, since resistor Rdamp also dissipates the energy induced by the input signal on the primary side of the transformer on the secondary side, it reduces the overall efficiency of transferring energy to capacitor CSEC. Summary of the Invention

[0010] To overcome the aforementioned problems, a preferred embodiment of the present invention provides floating gate drivers, each of which effectively transmits isolated power and isolated signals while significantly reducing or preventing ringing. Furthermore, a preferred embodiment of the present invention enables power supply and gate drive functionality to be provided in a single module, thereby reducing the cost and overall size of the circuitry included in the floating gate drivers and related components.

[0011] According to a preferred embodiment of the present invention, an isolated gate driver includes: a transformer including a primary winding and a secondary winding; a synchronous rectifier electrically connected between the secondary winding and an output terminal of the isolated gate driver; a first switch including a first terminal electrically connected to a power supply voltage; a second switch including a first terminal electrically connected to a power supply voltage; a first damping resistor electrically connected between the first terminal of the secondary winding and a second terminal of the first switch; a second damping resistor electrically connected between the second terminal of the secondary winding and a second terminal of the second switch; a first inverter including an input terminal electrically connected to the first terminal of the secondary winding and an output terminal electrically connected to the gate terminal of the first switch; and a second inverter including an input terminal electrically connected to the second terminal of the secondary winding and an output terminal electrically connected to the gate terminal of the second switch.

[0012] The first buffer can be electrically connected to the first terminal of the secondary winding, and the second buffer can be electrically connected to the second terminal of the secondary winding.

[0013] An isolated gate driver may include: a first filter circuit electrically connecting a first terminal of the secondary winding to a first buffer; and a second filter circuit electrically connecting a second terminal of the secondary winding to a second buffer. The first filter circuit may include: a first filter resistor connected in series between the first terminal of the secondary winding and the input terminal of the first buffer; and a first filter capacitor connected between the input terminal of the first buffer and a power supply voltage. The second filter circuit may include: a second filter resistor connected in series between the second terminal of the secondary winding and the input terminal of the second buffer; and a second filter capacitor connected between the input terminal of the second buffer and the power supply voltage. The first filter circuit may include a first delay unit, a first AND gate, and a first buffer; the first delay unit may be connected in series between the first terminal of the secondary winding and the first input terminal of the first AND gate; the second input terminal of the first AND gate may be electrically connected to the first terminal of the secondary winding; and the output terminal of the first AND gate may be electrically connected to the first buffer. The second filter circuit may include a second delay unit, a second AND gate, and a second buffer; the second delay unit may be electrically connected in series between the second terminal of the secondary winding and the first input terminal of the second AND gate; and the second input terminal of the second AND gate may be electrically connected to the second terminal of the secondary winding. The output terminal of the second AND gate may be electrically connected to the second buffer.

[0014] According to a preferred embodiment of the present invention, an isolated gate driver includes: a transformer including a primary winding and a secondary winding; a synchronous rectifier supplying power at a power output terminal of the isolated gate driver by rectifying a high voltage and a low voltage provided by a first terminal of the secondary winding and a high voltage and a low voltage provided by a second terminal of the secondary winding; a buffer circuit providing a data signal at a signal output terminal of the isolated gate driver based on the high voltage and low voltage provided by the first terminal of the secondary winding and based on the high voltage and low voltage provided by the second terminal of the secondary winding; and an adjustable damping circuit increasing the damping provided at the first terminal of the secondary winding when a low voltage is provided at the first terminal of the secondary winding, and increasing the damping provided at the second terminal of the secondary winding when a low voltage is provided at the second terminal of the secondary winding.

[0015] The adjustable damping circuit can increase the damping provided at the first terminal of the secondary winding by connecting the first terminal of the secondary winding to the power supply voltage via a first damping resistor, and the adjustable damping circuit can increase the damping provided at the second terminal of the secondary winding by connecting the second terminal of the secondary winding to the power supply voltage via a second damping resistor.

[0016] The adjustable damping circuit may include: a first switch, including a first terminal electrically connected to a power supply voltage; a second switch, including a first terminal electrically connected to a power supply voltage; a first damping resistor electrically connected between a first terminal of a secondary winding and a second terminal of the first switch; a second damping resistor electrically connected between a second terminal of a secondary winding and a second terminal of the second switch; a first inverter, including an input terminal electrically connected to the first terminal of the secondary winding and an output terminal electrically connected to the gate terminal of the first switch; and a second inverter, including an input terminal electrically connected to the second terminal of the secondary winding and an output terminal electrically connected to the gate terminal of the second switch.

[0017] The buffer circuit may include: a first buffer electrically connected to a first terminal of the secondary winding; and a second buffer electrically connected to a second terminal of the secondary winding. The isolated gate driver may further include: a filter circuit connected between the secondary winding and the buffer circuit. The filter circuit may include: a first filter circuit electrically connecting the first terminal of the secondary winding to the first buffer; and a second filter circuit electrically connecting the second terminal of the secondary winding to the second buffer.

[0018] The first filter circuit may include: a first filter resistor connected in series between the first terminal of the secondary winding and the input terminal of the first buffer; and a first filter capacitor connected in series between the input terminal of the first buffer and the power supply voltage. The second filter circuit may include: a second filter resistor connected in series between the second terminal of the secondary winding and the input terminal of the second buffer; and a second filter capacitor connected in series between the input terminal of the second buffer and the power supply voltage.

[0019] The first filter circuit may include a first delay unit, a first AND gate, and a first buffer; the first delay unit may be electrically connected in series between a first terminal of the secondary winding and a first input terminal of the first AND gate; the second input terminal of the first AND gate may be electrically connected to the first terminal of the secondary winding; and the output terminal of the first AND gate may be electrically connected to the first buffer. The second filter circuit may include a second delay unit, a second AND gate, and a second buffer; the second delay unit may be electrically connected in series between a second terminal of the secondary winding and a first input terminal of the second AND gate; the second input terminal of the second AND gate may be electrically connected to the second terminal of the secondary winding; and the output terminal of the second AND gate may be electrically connected to the second buffer.

[0020] The above and other features, elements, steps, configurations, characteristics, and advantages of the invention will become more apparent from the following detailed description of preferred embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0021] Figure 1 This is a circuit diagram of a conventional floating gate driver.

[0022] Figure 2 It shows Figure 1 The voltage waveform of a conventional floating gate driver is shown.

[0023] Figure 3 Yes Figure 1 The circuit diagram shown is a modified version of a conventional floating gate driver.

[0024] Figure 4 This is a circuit diagram of a floating gate driver according to a first preferred embodiment of the present invention.

[0025] Figure 5 This is a circuit diagram of a floating gate driver according to a second preferred embodiment of the present invention. Detailed Implementation

[0026] Now refer to Figure 4 and Figure 5 Preferred embodiments of the present invention are described in detail below. Note that the following description is illustrative in all respects and not restrictive, and should not be construed as limiting the application or use of the preferred embodiments of the invention in any way. Figure 1 and Figure 3 China and Figure 4 and Figure 5 Components with the same reference numerals in the figures have the same or similar functions.

[0027] Figure 4 This is a circuit diagram of a floating gate driver according to a first preferred embodiment of the present invention. Figure 4 As shown, damping resistors RD1 and RD2, switches MD1 and MD2, and inverters INV3 and INV4 are included in the floating gate driver.

[0028] The floating gate driver includes a transformer with a primary winding Lprim and a secondary winding Lsec, which divides the floating gate driver into a primary side with circuitry connected to the primary winding Lprim and a secondary side with circuitry connected to the secondary winding Lsec.

[0029] On the primary side, terminals TXPP and TXPN are connected to the primary winding. High and low voltages (e.g., positive and negative voltages) can be applied to terminals TXPP and TXPN. As explained below, the high and low voltages can be included in a voltage pulse that indicates the detection of an edge of a control signal, i.e., a transition from low to high voltage or from high to low voltage.

[0030] On the secondary side, terminals TXSP and TXSN are connected to the secondary winding. The leakage inductance Llk is shown connected between the secondary winding Lsec and terminal TXSP, and the resistor Rdamp is connected between terminals TXSP and TXSN.

[0031] A synchronous rectifier comprising switches S1, S2, MC1, and MC2 is connected to terminals TXSP and TXSN, and to capacitor CSEC at the output voltage VSEC. A floating gate driver provides output power at the output voltage VSEC. Each of switches S1, S2, MC1, and MC2 may include three terminals, one of which is a control terminal, while the other two provide a path for current to flow. The control terminal of switch MC1 is connected to terminal TXSP, and the other two terminals of switch MC1 are connected between terminal TXSN and the power supply voltage VSUP-. The control terminal of switch MC2 is connected to terminal TXSN, and the other two terminals of switch MC2 are connected between terminal TXSP and the power supply voltage VSUP-. The control terminal of switch S1 is connected to a controller (not shown), and the other two terminals of switch S1 are connected between terminal TXSP and the output voltage VSEC. The control terminal of switch S2 is connected to a controller (not shown), and the other two terminals of switch S2 are connected between terminal TXSN and the output voltage VSEC.

[0032] The common-mode setting circuit may include: a common-mode setting resistor RCM1 connected between the terminal TXSN and the power supply voltage VSUP-; and a common-mode setting resistor RCM2 connected between the terminal TXSP and the power supply voltage VSUP-.

[0033] A buffer circuit can be connected to terminals TXSP and TXSN. The buffer circuit may include a first buffer BUF1 and a second buffer BUF2. The first buffer BUF1 can be connected to terminal TXSP, and the second buffer BUF2 can be connected to terminal TXSN. The floating gate driver can provide a signal at the output of the buffer circuit based on the signals at terminals TXSP and TXSN, which are based on the signals applied to terminals TXPP and TXPN.

[0034] A filtering circuit can be connected between terminals TXSP, TXSN and the buffer circuit. The filtering circuit may include a first filter connected to the first buffer BUF1, and a second filtering circuit may include a second filter connected to the second buffer BUF2. The first filter may include a filter resistor RFILT1 connected between terminal TXSP and the input of the first buffer BUF1, and may include a filter capacitor CFILT1 connected between the input of the first buffer BUF1 and the power supply voltage VSUP-; and the second filter may include a filter resistor RFILT2 connected between terminal TXSN and the input of the second buffer BUF2, and may include a filter capacitor CFILT2 connected between the input of the second buffer BUF2 and the power supply voltage VSUP-. Other suitable filtering circuits may also be used, including, for example, those having the following combination... Figure 5 The second embodiment shown includes the filtering circuits for the first and second time blanking circuits.

[0035] An adjustable damping circuit can be connected to terminals TXSP and TXSN. When terminals TXSP and TXSN are low, the adjustable damping circuit can increase the damping provided at terminals TXSP and TXSN, thereby reducing ringing on the secondary side. The adjustable damping circuit can increase damping by increasing the resistance connected to terminals TXSP and TXSN. The adjustable damping circuit may include a first damping circuit connected to terminal TXSP and a second damping circuit connected to terminal TXSN. The adjustable damping circuit may include switches MD1 and MD2, each of which may include three terminals, one of which is a control terminal, while the other two terminals provide a path for current to flow. The first damping circuit may include a damping resistor RD1, switch MD1, and inverter INV4. The control terminal of switch MD1 can be connected to terminal TXSN via inverter INV4, while the other two terminals of switch MD1 can be connected across terminal TXSN and the power supply voltage VSUP-. The second damping circuit may include a damping resistor RD2, switch MD2, and inverter INV3. The control terminal of switch MD2 can be connected to terminal TXSP via inverter INV3, while the other two terminals of switch MD2 can be connected across terminal TXSP and the power supply voltage VSUP-. Other possible configurations of the adjustable damping circuit are also possible, which increase the damping provided on terminals TXSP and TXSN when terminals TXSP and TXSN are low to reduce ringing on the secondary side.

[0036] When line TXSP is low, switch MD2 is turned on via inverter INV3, thereby connecting damping resistor RD2 between the TXPP terminal and the power supply voltage VSUP-. Therefore, the voltage at terminal TXPP is pulled down to the power supply voltage VSUP-. When line TXSP is low and line TXSN is high, line TXSP is connected to the power supply voltage VSUP- via switch MC2, damping resistor RD2, and switch MD2. When line TXSP is high, switch MD2 is turned off, and no additional power is dissipated through damping resistor RD2. Therefore, damping resistor RD2 can have a relatively small resistance value.

[0037] When line TXSN is low, switch MD1 is turned on via inverter INV4, thereby connecting damping resistor RD1 between line TXSN and the power supply voltage VSUP-. Therefore, the voltage at terminal TXPN is pulled down to the power supply voltage VSUP-. When line TXSN is low and line TXSP is high, line TXSN is connected to the power supply voltage VSUP- via switch MC1, damping resistor RD1, and switch MD1. When line TXSN is high, switch MD1 is open, and no additional power is dissipated through damping resistor RD1. Therefore, damping resistor RD1 can have a relatively small resistance value.

[0038] Therefore, by switching switches MD1 and MD2, the total damping resistance of the circuit can be dynamically changed by selectively enabling the ringing current to flow through damping resistors RD1 and RD2. Since damping resistors RD1 and RD2 have relatively small resistance values, the resonance effect caused by leakage inductance Llk is greatly reduced, and common-mode noise immunity is improved by providing a constant or substantially constant connection to the common ground via a relatively low impedance.

[0039] Figure 4 The floating gate driver shown may also include filtering circuitry, illustrated as filter resistors RFILT1 and RFILT2 and filter capacitors CFILT1 and CFILT2. The filtering circuitry provides additional reduction or prevention of any residual resonant effects. The filtering circuitry includes: a first filtering circuit comprising filter resistor RFILT1 and filter capacitor CFILT1; and a second filtering circuit comprising filter resistor RFILT2 and filter capacitor CFILT2. Each of the first and second filtering circuits provides a relatively short RC time constant to provide relatively fast switching, thereby reducing the load on the energy and signal output from lines TXSP and TXSN.

[0040] Figure 4 The circuit shown can use edge detection to detect the signal used for gate drive. Therefore, the pulses used to control the gate drive can be relatively narrow, thereby enabling the transformer to have a relatively small size, for example, by including a relatively small core. Furthermore, Figure 4 The circuit shown can use a single transformer to transmit both power and data, and has a wide frequency range. For example, Figure 4 The circuit shown can be used in the range of 0Hz (i.e., DC power supply) to approximately 3MHz.

[0041] Figure 5 This is a circuit diagram of a floating gate driver according to a second preferred embodiment of the present invention.

[0042] like Figure 5 As shown, a combination of a delay unit T and AND gates AND1 and AND2 can be used to replace... Figure 4 The filter circuit shown includes filter resistors RFILT1 and RFILT2, and filter capacitors CFILT1 and CFILT2. That is, Figure 4 The filter circuit shown consists of Figure 5 The delay unit T shown is replaced. Figure 5The filtering circuit can be connected between terminals TXSP, TXSN and the buffer circuit. The filtering circuit may include a first time-blank circuit connected to the first buffer BUF1 and a second time-blank circuit connected to the second buffer BUF2. The first time-blank circuit may include an AND gate AND2 and a first delay unit T, and the second time-blank circuit may include an AND gate AND1 and a second delay unit T. In the first time-blank circuit, one input of the AND gate AND2 can be connected to terminal TXSP, and the other input of the AND gate AND2 can be connected to terminal TXSP through the first delay unit T; and in the second time-blank circuit, one input of the AND gate AND1 can be connected to terminal TXSN, and the other input of the AND gate AND1 can be connected to terminal TXSN through the second delay unit T.

[0043] The combination of a first delay unit T and an AND gate AND1 provides a first time blanking circuit that filters any signal higher than the detection level of the AND gate AND1 for a time less than a first predetermined delay time τ of the first delay unit T. Similarly, the combination of a second delay unit T and an AND gate AND2 provides a second time blanking circuit that filters any signal higher than the detection level of the AND gate AND2 for a time less than a second predetermined delay time τ of the second delay unit T. Each of the first and second time blanking circuits provides noise blanking for noise from lines TXSP and TXSN. For example, each of the first and second predetermined delay times τ can be equal to approximately half the period of the ringing signal on line TXSP or line TXSN, such as... Figure 2 As shown.

[0044] Similar to Figure 3 The circuit shown, in Figure 4 The first preferred embodiment shown and Figure 5 In the second preferred embodiment shown, a resistor Rdamp can be added between the online TXSP and TXSN. When damping resistors RD1 and RD2 are selectively connected, resistor Rdamp provides constant damping resistance to dissipate the energy accumulated in the leakage inductance Llk of the transformer. Therefore, ringing on the secondary side of the transformer is further reduced. The resistance of resistor Rdamp can be between approximately 100Ω and approximately 10kΩ.

[0045] For example, each of switches MD1, MD2, MC1, MC1, S1, and S2 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). However, other types of transistors, switches, repeaters, etc., can be used. If switches MD1, MD2, MC1, MC1, S1, and S2 are MOSFETs, the control terminal can be the gate terminal, while the other two terminals can be the source and drain terminals.

[0046] While preferred embodiments of the invention have been described above, it should be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Therefore, the scope of the invention is defined only by the appended claims.

Claims

1. An isolated gate driver, comprising: A transformer consists of a primary winding and a secondary winding; A synchronous rectifier is electrically connected between the secondary winding and the output terminal of the isolated gate driver; The first switch includes a first terminal electrically connected to the power supply voltage; The second switch includes a first terminal electrically connected to the power supply voltage; The first damping resistor is electrically connected between the first terminal of the secondary winding and the second terminal of the first switch; The second damping resistor is electrically connected between the second terminal of the secondary winding and the second terminal of the second switch; The first inverter includes an input terminal electrically connected to a first terminal of the secondary winding and an output terminal electrically connected to the gate terminal of the first switch; as well as The second inverter includes an input terminal electrically connected to the second terminal of the secondary winding and an output terminal electrically connected to the gate terminal of the second switch.

2. The isolated gate driver according to claim 1, further comprising: The first buffer is electrically connected to the first terminal of the secondary winding; as well as The second buffer is electrically connected to the second terminal of the secondary winding.

3. The isolated gate driver according to claim 1, further comprising: The first filter circuit electrically connects the first terminal of the secondary winding to the first buffer. as well as The second filter circuit electrically connects the second terminal of the secondary winding to the second buffer.

4. The isolated gate driver according to claim 3, wherein: The first filter circuit includes: A first filter resistor is connected in series between the first terminal of the secondary winding and the input terminal of the first buffer; and The first filter capacitor is electrically connected between the input terminal of the first buffer and the power supply voltage. The second filter circuit includes: The second filter resistor is connected in series between the second terminal of the secondary winding and the input terminal of the second buffer; and The second filter capacitor is electrically connected between the input terminal of the second buffer and the power supply voltage.

5. The isolated gate driver according to claim 3, wherein: The first filtering circuit includes a first delay unit, a first AND gate, and a first buffer; The first delay unit is connected in series between the first terminal of the secondary winding and the first input terminal of the first AND gate; The second input terminal of the first AND gate is electrically connected to the first terminal of the secondary winding; The output of the first AND gate is electrically connected to the first buffer; The second filter circuit includes a second delay unit, a second AND gate, and a second buffer; The second delay unit is connected in series between the second terminal of the secondary winding and the first input terminal of the second AND gate; The second input terminal of the second AND gate is electrically connected to the second terminal of the secondary winding; and The output of the second AND gate is electrically connected to the second buffer.

6. An isolated gate driver, comprising: A transformer consists of a primary winding and a secondary winding; The synchronous rectifier supplies power to the power output terminal of the isolated gate driver by rectifying the high and low voltages provided by the first terminal of the secondary winding and the high and low voltages provided by the second terminal of the secondary winding. A buffer circuit provides a data signal at the signal output terminal of the isolated gate driver based on a high voltage and a low voltage provided by a first terminal of the secondary winding and a high voltage and a low voltage provided by a second terminal of the secondary winding. as well as An adjustable damping circuit that increases the damping provided at the first terminal of the secondary winding when the low voltage is provided, and increases the damping provided at the second terminal of the secondary winding when the low voltage is provided.

7. The isolated gate driver according to claim 6, wherein: The adjustable damping circuit increases the damping provided at the first terminal of the secondary winding by connecting the first terminal of the secondary winding to the power supply voltage via a first damping resistor; as well as The adjustable damping circuit increases the damping provided at the second terminal of the secondary winding by connecting the second terminal of the secondary winding to the power supply voltage via a second damping resistor.

8. The isolated gate driver according to claim 6, wherein, The adjustable damping circuit includes: The first switch includes a first terminal electrically connected to the power supply voltage; The second switch includes a first terminal electrically connected to the power supply voltage; The first damping resistor is electrically connected between the first terminal of the secondary winding and the second terminal of the first switch; The second damping resistor is electrically connected between the second terminal of the secondary winding and the second terminal of the second switch; The first inverter includes an input terminal electrically connected to a first terminal of the secondary winding and an output terminal electrically connected to the gate terminal of the first switch; and The second inverter includes an input terminal electrically connected to the second terminal of the secondary winding and an output terminal electrically connected to the gate terminal of the second switch.

9. The isolated gate driver according to any one of claims 6 to 8, wherein, The buffer circuit includes: A first buffer is electrically connected to a first terminal of the secondary winding; and The second buffer is electrically connected to the second terminal of the secondary winding.

10. The isolated gate driver according to claim 6, further comprising: A filter circuit is connected between the secondary winding and the buffer circuit.

11. The isolated gate driver according to claim 10, wherein, The filtering circuit includes: A first filter circuit electrically connects the first terminal of the secondary winding to a first buffer; and The second filter circuit electrically connects the second terminal of the secondary winding to the second buffer.

12. The isolated gate driver according to claim 11, wherein: The first filter circuit includes: A first filter resistor is connected in series between the first terminal of the secondary winding and the input terminal of the first buffer; and The first filter capacitor is electrically connected between the input terminal of the first buffer and the power supply voltage. The second filter circuit includes: The second filter resistor is connected in series between the second terminal of the secondary winding and the input terminal of the second buffer; and The second filter capacitor is electrically connected between the input terminal of the second buffer and the power supply voltage.

13. The isolated gate driver according to claim 11, wherein: The first filtering circuit includes a first delay unit, a first AND gate, and a first buffer; The first delay unit is connected in series between the first terminal of the secondary winding and the first input terminal of the first AND gate; The second input terminal of the first AND gate is electrically connected to the first terminal of the secondary winding; The output of the first AND gate is electrically connected to the first buffer; The second filter circuit includes a second delay unit, a second AND gate, and a second buffer; The second delay unit is connected in series between the second terminal of the secondary winding and the first input terminal of the second AND gate; The second input terminal of the second AND gate is electrically connected to the second terminal of the secondary winding; and The output of the second AND gate is electrically connected to the second buffer.

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