A method for fabricating a silicon carbide power MOSFET device

Abstract

This invention discloses a method for fabricating silicon carbide power MOSFET devices. Based on a two-stage self-alignment process, the channel self-alignment, contact hole self-alignment, and contact passivation self-alignment of the SiC MOSFET are completed respectively. Compared with the traditional SiC MOSFET process, it can reduce three photomasks and three photolithography processes, avoid channel asymmetry and contact hole misalignment caused by photolithography alignment, reduce the cell design size, reduce the specific on-resistance of the SiC MOSFET, and improve product performance and yield.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and more specifically, this invention relates to a method for fabricating a silicon carbide power MOSFET device. Background Technology

[0002] SiC materials have advantages such as wide bandgap, high saturation drift velocity, high thermal conductivity and high critical breakdown electric field, making them particularly suitable for fabricating high-power, high-voltage, and high-temperature MOSFET devices.

[0003] Unlike traditional Si materials, SiC does not diffuse much even at high temperatures of 1700°C due to the lack of diffusion of doped impurity ions. Therefore, it cannot form self-aligned channels using a double diffusion method as in Si materials. In the fabrication of SiC MOSFETs, channels are typically formed through two implantation processes: well implantation and source implantation. However, this method is highly dependent on the alignment accuracy of photolithography. For MOSFET devices with channel lengths less than 0.6 μm, deviations introduced by this manufacturing method can easily lead to significant differences in channel length on both sides, resulting in degraded device performance and reduced reliability. Summary of the Invention

[0004] This invention provides a method for fabricating a silicon carbide power MOSFET device, aiming to improve the above-mentioned problems.

[0005] This invention is achieved by providing a method for fabricating a silicon carbide power MOSFET device, the method comprising the following steps:

[0006] S1. Ion implantation is performed on the SiC epitaxial layer based on mask I to form the P-WELL region;

[0007] S2. Self-align N-PLUS implantation mask is formed on both sides of mask I and ion implantation is performed to form N-PLUS contact source region in P-WELL region. The implantation distance between N-PLUS contact source region and P-WELL region forms a channel.

[0008] S3. Remove all masks on the SiC epitaxial layer, perform ion implantation on the SiC epitaxial layer based on mask II, and form the P-PLUS contact source region.

[0009] S4. Remove mask II, deposit a carbon film on the SiC epitaxial layer, and activate the implanted ions by high-temperature annealing;

[0010] S5. After removing the carbon film, the wafer surface is subjected to sacrificial oxidation to form a sacrificial oxide layer. After removing the sacrificial oxide layer, a field oxide layer is deposited, and a field oxide pattern is formed on the field oxide layer to expose the SiC layer in the active region. The SiC is subjected to high-temperature oxidation to form a gate oxide layer in the active region. Then, a polysilicon gate layer and an ILD dielectric layer are deposited in sequence.

[0011] S6. Form a gate mask layer on the ILD dielectric layer, and sequentially etch the ILD dielectric layer and polysilicon gate layer outside the gate to remove the gate mask layer.

[0012] S7. Form a sidewall insulating layer by self-alignment on both sides of the polysilicon gate layer, and etch the gate oxide layer on the side of the sidewall insulating layer.

[0013] S8. Ni metal is deposited on the side of the sidewall insulating layer and silicide contact is formed by RTA annealing. Metal thickening deposition is performed on the upper surface of the source ohmic contact alloy and the upper surface of the ILD dielectric layer. After photolithography etching of the metal layer, the gate and source are formed.

[0014] S9. A drain electrode is formed on the back side of the substrate.

[0015] Furthermore, the specific method for forming the drain is as follows:

[0016] After thinning the back substrate, Ni metal is deposited and ohmic contacts are formed by laser annealing. The back metal is then thickened to form the drain of the device.

[0017] Furthermore, after forming the gate and source, the following steps are also included:

[0018] S11. Passivation dielectric deposition and polyimide coating are performed sequentially on the metal layer. The gate contact electrode and source contact electrode are exposed by photolithography and then cured.

[0019] S12. Using the cured polyimide as a mask, the passivation medium layer is etched to form the final passivation structure.

[0020] Furthermore, the etching methods for the ILD dielectric layer and polysilicon gate layer in step S7 are as follows:

[0021] Using the gate mask layer as a mask, the ILD dielectric layer is etched down to the polysilicon gate layer. The remaining gate mask layer on the surface is removed. Using the etched ILD dielectric layer as a mask, the polysilicon gate layer is etched down to the gate oxide layer.

[0022] Furthermore, the specific method for forming the N-PLUS injection mask is as follows:

[0023] Film deposition and etching are performed on mask layer I, and N-PLUS injection masks are formed by self-alignment on both sides of mask layer I.

[0024] Furthermore, the specific method for forming the N-PLUS injection mask is as follows:

[0025] When mask layer I is polysilicon, the wafer with mask layer I is subjected to high-temperature oxidation at a temperature of 800-1200℃, so that the surface and sidewalls of the polysilicon mask are oxidized to form SiO layer, which is the self-aligned N-PLUS implantation mask.

[0026] Furthermore, prior to step S1, the following is also included:

[0027] The silicon carbide epitaxial wafer was cleaned using the RCA method to remove the natural oxides on the silicon carbide surface, resulting in a clean silicon carbide epitaxial wafer.

[0028] Furthermore, the specific parameters for the implanted ion activation process in step S4 are as follows:

[0029] The carbon film has a thickness of 10nm-600nm and is annealed in a high-temperature inert gas atmosphere at a temperature of 1600℃-1900℃ for 5min-60min.

[0030] Furthermore, in step S5, the sacrificial oxidation temperature of the wafer is 1000℃-1300℃.

[0031] Compared with traditional methods, the method for fabricating silicon carbide power MOSFET devices provided by this invention can reduce the fabrication of three photolithography layers, improve device reliability, reduce channel length asymmetry and gate-source contact insulation layer thickness asymmetry introduced by photolithography overlay, and reduce device fabrication cost. Attached Figure Description

[0032] Figure 1 A flowchart illustrating the fabrication method of a silicon carbide power MOSFET device provided in an embodiment of the present invention;

[0033] Figure 2 This is a schematic diagram of the structure of a clean silicon carbide epitaxial wafer provided in an embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of the formation of the P-WELL region provided in an embodiment of the present invention;

[0035] Figure 4 This is a schematic diagram of the formation of the N-PLUS contact source region provided in an embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of the formation of the P-PLUS contact source region provided in an embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of a wafer after carbon film formation provided in an embodiment of the present invention;

[0038] Figure 7 This is a schematic diagram of a wafer after the formation of a sacrificial oxide layer, provided in an embodiment of the present invention.

[0039] Figure 8 This is a schematic diagram of a wafer after sequentially depositing a polysilicon gate layer and an ILD dielectric layer, as provided in an embodiment of the present invention.

[0040] Figure 9 This is a schematic diagram of a wafer after etching the ILD dielectric layer, provided in an embodiment of the present invention.

[0041] Figure 10 This is a schematic diagram of a wafer after the polysilicon gate layer has been etched, as provided in an embodiment of the present invention.

[0042] Figure 11 This is a schematic diagram of a wafer after forming a self-aligned sidewall insulating layer, provided in an embodiment of the present invention.

[0043] Figure 12 This is a schematic diagram of a wafer after forming Ni metal silicide according to an embodiment of the present invention;

[0044] Figure 13 This is a schematic diagram of a wafer after metal deposition and thickening, provided in an embodiment of the present invention.

[0045] Figure 14 This is a schematic diagram of a wafer coated with polyimide according to an embodiment of the present invention;

[0046] Figure 15 A schematic diagram of a wafer after etching the passivation dielectric layer, provided in an embodiment of the present invention.

[0047] Figure 16 This is a schematic diagram of a wafer after substrate thinning provided in an embodiment of the present invention;

[0048] Figure 17 This is a schematic diagram of a wafer after Ni metal deposition, provided in an embodiment of the present invention.

[0049] Figure 18 This is a schematic diagram of a wafer with thickened back metal provided in an embodiment of the present invention;

[0050] Figure 19 The topographic images of P-WELL mask etching and implantation provided in the embodiments of the present invention;

[0051] Figure 20 This is a topographic image of the mask layer I after direct deposition, provided in an embodiment of the present invention.

[0052] Figure 21 The topography of the N-PLUS implantation mask formed by first depositing and then etching the mask layer I provided in the embodiment of the present invention is shown in the figure.

[0053] Figure 22 This is a topographic image of the gate-source insulating dielectric formed by ILD deposition and etching to create sidewalls, provided in an embodiment of the present invention. Detailed Implementation

[0054] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, so as to help those skilled in the art to have a more complete, accurate and in-depth understanding of the inventive concept and technical solution of the present invention.

[0055] Figure 1 The flowchart illustrates a method for fabricating a silicon carbide power MOSFET device according to an embodiment of the present invention. The method specifically includes the following steps:

[0056] S1. Clean the silicon carbide epitaxial wafer and remove the native oxides on its surface;

[0057] A silicon carbide epitaxial wafer consists of an n-type 4H-SiC substrate and an epitaxial SiC layer. The silicon carbide epitaxial wafer is cleaned using the RCA method, and the native oxide on the silicon carbide surface is removed using BOE (buffered oxide etch) or DHF (diluted HF) to obtain a clean silicon carbide epitaxial wafer. Figure 2 As shown.

[0058] S2. A mask layer I deposited on the SiC epitaxial layer is subjected to Al ion implantation to form a P-WELL region;

[0059] A mask layer I is deposited on the SiC epitaxial layer. Mask layer I can be polysilicon, silicon dioxide, or silicon dioxide, USG, etc., deposited by LPCVD or PECVD. The P-WELL mask pattern is transferred onto mask layer I through photolithography and dry etching. Al ion implantation is then performed on the SiC epitaxial layer to form the P-WELL region. A schematic diagram of the wafer structure is shown below. Figure 3 As shown, the topographic diagram is as follows: Figure 19 As shown.

[0060] S3. Self-align N-PLUS implantation mask is formed on both sides of mask I and ion implantation is performed to form N-PLUS contact source region in P-WELL region. The implantation distance between N-PLUS contact source region and P-WELL region forms a channel.

[0061] CVD film deposition was performed on mask layer I (see the morphology image after deposition). Figure 20 ) and etching (see the morphology diagram after etching) Figure 21 An N-PLUS implantation mask is formed on both sides of mask layer I through self-alignment. The deposited medium can be the same as or different from that of mask layer I. The CVD deposition method is not limited to PECVD, LPCVD, or APCVD. Nitrogen or phosphorus elements are implanted into the formed self-aligned mask to form the N-PLUS contact source region. Figure 4 As shown;

[0062] When mask layer I is polysilicon, the wafer with mask layer I is placed in an oxidation furnace and subjected to high-temperature oxidation at 800-1200℃ to oxidize the surface and sidewalls of the polysilicon mask to form a SiO layer, forming a self-aligned N-PLUS implantation mask. Nitrogen or phosphorus elements are implanted using the self-aligned N-PLUS implantation mask to form an N-PLUS contact source region.

[0063] S4. Remove all masks on the SiC epitaxial layer, then deposit mask layer II. Transfer the P-PLUS mask pattern onto mask layer II using photolithography and dry etching, and perform Al ion implantation to form the P-PLUS contact source region. Figure 5 As shown;

[0064] S5. Remove mask layer II, deposit a carbon film on the SiC epitaxial layer, and activate the implanted ions by high-temperature annealing;

[0065] After removing mask layer II, the wafer is cleaned and a carbon film with a thickness of 10nm-600nm is deposited to protect the surface. Annealing is then performed in a high-temperature inert gas atmosphere at 1600℃-1900℃ for 5-60 minutes. During the high-temperature annealing process, the implanted ions are activated, such as... Figure 6 As shown.

[0066] S6. After removing the carbon film, sacrificial oxidation is performed on the wafer surface to form a sacrificial oxide layer. After removing the sacrificial oxide layer, a field oxygen layer is deposited.

[0067] The wafer oxidation temperature is 1000℃-1300℃. The sacrificial oxide layer on the surface is removed by BOE cleaning, followed by RCA cleaning. Then, a field oxide layer is deposited on the wafer surface. Figure 7 As shown, field oxygen patterns are formed by photolithography and BOE wet etching. The deposition method can be PECVD, LPCVD or APCVD.

[0068] S7. Form a field oxide pattern on the field oxide layer to expose the SiC layer in the active region. Perform high-temperature oxidation on the SiC to form a gate oxide layer in the active region. Then, deposit a polysilicon gate layer and an ILD dielectric layer in sequence.

[0069] The wafer is placed in a high-temperature oxidation furnace at 1200℃-1500℃ to form a gate oxide layer. The gate oxide layer is then annealed in a NO atmosphere. Immediately afterwards, in-situ doped polysilicon with a thickness of 300-800 nm is deposited on the gate oxide layer surface using LPCVD. Then, an ILD dielectric layer with a thickness of 1 μm-1.5 μm is deposited on the polysilicon surface. The ILD dielectric layer is composed of one or more of USG, PSG, or BPSG. Figure 8 As shown.

[0070] S8. Form a gate mask layer on the ILD dielectric layer, sequentially etch the ILD dielectric layer and polysilicon gate layer outside the gate, and remove the gate mask layer.

[0071] Using photoresist as a mask, excess ILD dielectric layer outside the gate is etched away, with the etching endpoint stopping at the polysilicon gate layer, such as... Figure 9 As shown, the residual photoresist on the surface is then removed. Using the etched ILD dielectric layer as a mask, the polysilicon gate layer is etched. Utilizing the high selectivity of polysilicon etching over silicon oxide, the polysilicon gate etching is completed. The etching ends at the gate oxide layer. Following this, dilute hydrochloric acid cleaning and SC-1 cleaning are performed to remove the surface polymer, such as... Figure 10 As shown;

[0072] S9. Form a sidewall insulating layer by self-alignment on both sides of the polysilicon gate layer, and etch the gate oxide layer on the side of the sidewall insulating layer.

[0073] An ILD dielectric (silicon dioxide dielectric layer) layer is deposited on the wafer surface and then reflow annealed. The deposited ILD layer is either BPSG or PSG. Following this, the ILD is etched. Through deposition and etching, a sidewall insulating layer is formed on the gate sidewall of the polysilicon. See the morphology diagram below. Figure 22 Because the sidewall insulation layer is self-aligned, it improves the alignment accuracy of the gate source, such as... Figure 11 As shown;

[0074] S10. Ni metal is deposited on the sidewall insulating layer and silicide contacts are formed by RTA annealing, such as... Figure 12 As shown, metal thickening deposition is performed on the upper surface of the source ohmic contact alloy and the upper surface of the ILD dielectric layer, such as... Figure 13 As shown, the gate and source are formed after photolithography etching of the metal layer;

[0075] The metal layer between the gate window and the source window is etched away, forming the gate inside the gate window and the source inside the source window.

[0076] S11. Passivation dielectric deposition and polyimide coating are performed on the metal layer, such as... Figure 14 As shown, the gate contact electrode and source contact electrode are exposed by photolithography and then cured.

[0077] S12. Next, using the cured polyimide as a mask, the passivation dielectric layer is etched to form the final passivation structure, such as... Figure 15 As shown;

[0078] S13. Thin the back substrate to reduce the specific on-resistance of the device, such as... Figure 16 As shown, Ni metal is deposited on the back side and an ohmic contact is formed by laser annealing, as... Figure 17As shown, the back metal is thickened to form the drain of the device, such as... Figure 18 As shown.

[0079] Based on two self-alignment processes, the channel self-alignment, contact hole self-alignment, and contact passivation self-alignment of SiC MOSFET are completed separately. Compared with the traditional method, the fabrication of three photomasks can be reduced, the reliability of the device can be improved, and the channel length asymmetry and gate-source contact insulation layer thickness asymmetry introduced by photolithography overlay can be reduced, thus reducing the cost of device fabrication.

[0080] The present invention has been described by way of example. Obviously, the specific implementation of the present invention is not limited to the above-described manner. Any non-substantial improvements made using the inventive concept and technical solution of the present invention, or the direct application of the inventive concept and technical solution of the present invention to other occasions without modification, are all within the protection scope of the present invention.

Claims

1. A method of fabricating a silicon carbide power MOSFET device, comprising: The method comprises the following steps: S1, ion implantation is performed on the SiC epitaxial layer based on mask I to form a P-WELL region; S2, an N-PLUS implantation mask is formed on both sides of the mask I in a self-aligned manner, ion implantation is performed, and an N-PLUS contact source region is formed in the P-WELL region; the implantation spacing between the N-PLUS contact source region and the P-WELL region forms a channel; S3, all masks on the SiC epitaxial layer are removed, ion implantation is performed on the SiC epitaxial layer based on mask II to form a P-PLUS contact source region; S4, the mask II is removed, a carbon film is deposited on the SiC epitaxial layer, and the implanted ions are activated through high-temperature annealing; S5, after the carbon film is removed, the wafer surface is subjected to sacrificial oxidation to form a sacrificial oxide layer, the sacrificial oxide layer is removed, a field oxide layer is deposited, and a field oxide pattern is formed on the field oxide layer to expose the SiC layer of the active region, the SiC is subjected to high-temperature oxidation to form a gate oxide layer in the active region, and then a polysilicon gate layer and an ILD dielectric layer are sequentially deposited; S6, a gate mask layer is formed on the ILD dielectric layer, the ILD dielectric layer outside the gate and the polysilicon gate layer are etched in sequence, and the gate mask layer is removed; S7, a side wall insulating layer is formed on both sides of the polysilicon gate layer in a self-aligned manner, and the gate oxide layer on the side of the side wall insulating layer is etched; S8, Ni metal is deposited on the side of the side wall insulating layer, and a silicide contact is formed through RTA annealing; metal thickening deposition is performed on the surface of the source ohmic contact alloy and the surface of the ILD dielectric layer, and the gate and the source are formed after the metal layer is subjected to photolithography and etching; S9, a drain is formed on the back of the substrate; The forming method of the N-PLUS implantation mask is as follows: When the mask layer I is polysilicon, the wafer with the mask layer I is subjected to high-temperature oxidation at a temperature of 800-1200°C, so that the surface and the sidewall of the polysilicon mask are oxidized to form a SiO layer, which is a self-aligned N-PLUS implantation mask.

2. The method of producing a silicon carbide power MOSFET device as claimed in claim 1, wherein, The forming method of the drain is as follows: After the back substrate is subjected to thinning treatment, Ni metal is deposited and an ohmic contact is formed through laser annealing, and the back metal is subjected to thickening treatment to form the drain of the device.

3. The method of producing a silicon carbide power MOSFET device as claimed in claim 1, wherein, After the gate and the source are formed, the following steps are further included: S11, passivation dielectric deposition and polyimide coating are sequentially performed on the metal layer, the gate contact electrode and the source contact electrode are exposed through photolithography, and solidification is performed; S12, the passivation dielectric layer is etched with the solidified polyimide as a mask to form a final passivation structure.

4. The method of producing a silicon carbide power MOSFET device as claimed in claim 1, wherein The etching method of the ILD dielectric layer and the polysilicon gate layer in step S7 is as follows: The ILD dielectric layer is etched with the gate mask layer as a mask, the polysilicon gate layer is etched until the gate oxide layer, and the surface residual gate mask layer is removed; the polysilicon gate layer is etched with the etched ILD dielectric layer as a mask until the gate oxide layer.

5. The method of producing a silicon carbide power MOSFET device as claimed in claim 1, wherein The forming method of the N-PLUS implantation mask is as follows: Deposition and etching of the film layer are performed on the mask layer I to form an N-PLUS implantation mask on both sides of the mask layer I in a self-aligned manner.

6. The method of producing a silicon carbide power MOSFET device as claimed in claim 1, wherein, Before step S1, the following is further included: The silicon carbide epitaxial wafer is cleaned by using the RCA method, and the natural oxide on the surface of the silicon carbide is removed to obtain a clean silicon carbide epitaxial wafer.

7. The method of producing a silicon carbide power MOSFET device as claimed in claim 1, wherein The injection ion activation process parameters in step S4 are as follows: The thickness of the carbon film is 10nm-600nm, and the carbon film is annealed in a high-temperature inert gas atmosphere, the annealing temperature is 1600℃-1900℃, and the annealing time is 5min-60min.

8. The method of producing a silicon carbide power MOSFET device of claim 1, wherein, The gate oxide layer of the wafer in step S5 is annealed at a temperature of 1000℃-1300℃.

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