Thin film transistor and electronic device thereof

Abstract

The application provides a thin film transistor and an electronic device thereof. The thin film transistor comprises an insulating substrate and an active layer arranged on the insulating substrate, and the active layer comprises a first active layer, a channel layer and a second active layer arranged in a stack. The first active layer comprises a first doped part and a second doped part, the first doped part is connected with the channel layer and the second doped part, and the ion doping concentration in the first doped part is less than that in the second doped part. By arranging the first active layer to comprise the first doped part and the second doped part with different ion doping concentrations, the channel length of the "channel region" is increased, the leakage current is reduced, and the mobility of the "channel region" of the thin film transistor is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display technology, and in particular to a thin film transistor and an electronic device thereof. BACKGROUND

[0002] With the continuous development of display technology, the resolution parameter of display panels is increasingly required, and therefore the array substrate needs to have an ultra-high resolution and a sub-micron level device size. In order to meet these requirements, the size and the area occupied by the thin film transistor device on the array substrate need to be reduced as much as possible. However, the channel length of the active layer of the conventional thin film transistor is usually greater than 1 micrometer due to the limitation of exposure accuracy and etching accuracy, which makes it difficult to further reduce the size and the area occupied by the thin film transistor device.

[0003] At present, there is a thin film transistor device with a vertical structure, which can overcome the problem of large size and area occupied by the device by stacking the doped part and the channel part of the active layer. In order to improve the mobility of the poly-silicon (Poly-Si) active layer, it is also necessary to reduce the channel length as much as possible. However, the channel length of the thin film transistor with a vertical structure is too small, which can easily lead to an increase in leakage current and is not conducive to the stability of the thin film transistor device. SUMMARY

[0004] The present application provides a thin film transistor and an electronic device thereof to solve the technical problem that the leakage current of the current thin film transistor device with a vertical structure increases due to the too small channel length, which further causes the stability of the device to decrease.

[0005] To solve the above technical problems, the technical solutions provided by the present application are as follows:

[0006] The present application provides a thin film transistor, comprising:

[0007] an insulating substrate; and

[0008] an active layer disposed on the insulating substrate, the active layer comprising a first active layer, a channel layer and a second active layer stacked together;

[0009] wherein the first active layer comprises a first doped part and a second doped part, the first doped part is connected with the channel layer and the second doped part, and the doping ion concentration in the first doped part is less than the doping ion concentration in the second doped part.

[0010] In the thin film transistor of the present application, the ratio of the doping ion concentration in the first doped part to the doping ion concentration in the second doped part is 1 / 10 to 1 / 5.

[0011] In the thin film transistor of the present application, the first doped portion and the second doped portion are arranged on the insulating substrate in the same layer, and the thickness of the second doped portion is less than or equal to the thickness of the first doped portion in the direction perpendicular to the insulating substrate.

[0012] In the thin film transistor of the present application, the ratio of the thickness of the second doped portion to the thickness of the first doped portion is 1 / 4 to 1 in the direction perpendicular to the insulating substrate.

[0013] In the thin film transistor of the present application, the channel layer corresponds to the first doped portion in the direction perpendicular to the insulating substrate;

[0014] The orthogonal projection of the channel layer on the first active layer partially overlaps the first doped portion and the second doped portion.

[0015] In the thin film transistor of the present application, the channel layer corresponds to the first doped portion in the direction perpendicular to the insulating substrate;

[0016] The orthogonal projection of the channel layer on the first active layer is located in the first doped portion, and the orthogonal projection of the channel layer on the first active layer does not overlap the second doped portion.

[0017] In the thin film transistor of the present application, the thin film transistor further comprises a gate layer, and the gate layer is annularly and insulatively arranged on the side of the channel layer;

[0018] The orthogonal projection of the channel layer on the gate layer at least partially overlaps the gate layer.

[0019] In the thin film transistor of the present application, the gate layer comprises a first gate portion and a second gate portion connected as a whole, the first gate portion is arranged above the insulating substrate, and the second gate portion is insulatively arranged above the second doped portion;

[0020] The orthogonal projection of the channel layer on the first gate portion is located in the first gate portion, and the orthogonal projection of the channel layer on the second gate portion at least partially overlaps the second gate portion.

[0021] In the thin film transistor of the present application, the orthogonal projection of the second gate portion on the insulating substrate partially overlaps the orthogonal projection of the channel layer on the insulating substrate.

[0022] In the thin film transistor of the present application, the channel layer comprises doped ions, and the concentration of the doped ions on the side of the channel layer away from the insulating substrate is greater than the concentration of the doped ions on the side of the channel layer close to the insulating substrate.

[0023] In the thin film transistor of the present application, the thin film transistor further comprises a first insulating layer arranged between the active layer and the gate layer;

[0024] The first insulating layer covers the surface of the second doped part, the surface of the second doped part and part of the surface of the insulating substrate.

[0025] In the thin film transistor of the present application, the thin film transistor further comprises a second insulating layer and a source-drain layer, the second insulating layer covers the first insulating layer and the gate layer, and the source-drain layer is arranged on the second insulating layer;

[0026] The first insulating layer and the second insulating layer are provided with a first via hole and a second via hole, the source-drain layer is connected with the second doped part through the first via hole, and the source-drain layer is connected with the second doped part through the second via hole.

[0027] In the thin film transistor of the present application, the thin film transistor further comprises a light shielding layer arranged in the insulating substrate, and the active layer is arranged on the light shielding layer.

[0028] The gate layer and the light shielding layer are connected through a third via hole.

[0029] The present application further provides an electronic device comprising the thin film transistor.

[0030] Advantages

[0031] The present application sets the first active layer to comprise a first doped part and a second doped part with different ion concentrations, so that the second doped part and the second active layer respectively serve as two "doped regions" of the thin film transistor, and the channel layer and the first doped part form a "channel region" of the thin film transistor, which is equivalent to increasing the channel length, thereby reducing the leakage current. Moreover, the first doped part has a higher mobility than the channel layer due to the doping of ions, which is equivalent to improving the mobility of the "channel region" of the thin film transistor. Therefore, the thin film transistor provided by the present application can better solve the problems of excessive leakage current and low mobility. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0033] Figure 1This is a schematic diagram of the first stacked structure of the thin-film transistor described in this application;

[0034] Figure 2 This is a schematic diagram of the planar structure of the thin-film transistor described in this application;

[0035] Figure 3 This is a schematic diagram of a second stacked structure of the thin-film transistor described in this application;

[0036] Figure 4 This is a schematic diagram of the third stacked structure of the thin-film transistor described in this application;

[0037] Figure 5 This is a schematic diagram of the fourth stacked structure of the thin-film transistor described in this application;

[0038] Figure 6 This is a schematic diagram of the fifth stacked structure of the thin-film transistor described in this application;

[0039] Figure 7 This is a flowchart of the method for fabricating the thin-film transistor described in this application;

[0040] Figures 8 to 13 This is a schematic diagram of the fabrication process of the thin-film transistor described in this application.

[0041] Explanation of reference numerals in the attached figures:

[0042] 100, Insulating substrate; 101, First via; 102, Second via; 103, Third via; 110, Substrate; 120, Buffer layer;

[0043] 200, Active layer; 210, First active layer; 211, First doped portion; 212, Second doped portion; 220, Channel layer; 230, Second active layer;

[0044] 300. First insulating layer;

[0045] 400, Gate layer; 410, First gate portion; 420, Second gate portion;

[0046] 500, Second insulation layer;

[0047] 600, Source / Drain layer; 610, Source; 620, Drain;

[0048] 700. Light-blocking layer. Detailed Implementation

[0049] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0050] Currently, vertically oriented thin-film transistor (TFT) devices overcome the problems of large size and footprint by stacking the doped portion of the active layer with the channel portion. Furthermore, to improve the mobility of the polysilicon (Poly-Si) active layer, the channel length needs to be minimized. However, excessively short channel lengths in vertically oriented TFTs can lead to increased leakage current, which is detrimental to device stability. This application proposes the following solution to address these technical problems.

[0051] Please see Figures 1 to 6 This application provides a thin-film transistor, including an insulating substrate 100 and an active layer 200 disposed on the insulating substrate 100. The active layer 200 includes a first active layer 210, a channel layer 220 and a second active layer 230 stacked together. The first active layer 210 includes a first doped portion 211 and a second doped portion 212. The first doped portion 211 is connected to the channel layer 220 and the second doped portion 212. The doped ion concentration in the first doped portion 211 is less than the ion doping concentration in the second doped portion 212.

[0052] This application configures the first active layer 210 to include a first doped portion 211 and a second doped portion 212 with different doping ion concentrations, so that the second doped portion 212 and the second active layer 230 respectively serve as two "doped regions" of the thin-film transistor, and the channel layer 220 and the first doped portion 211 constitute the "channel region" of the thin-film transistor. This is equivalent to increasing the channel length, thereby reducing the leakage current. Moreover, because the first doped portion 211 is doped with ions, its mobility is higher than that of the channel layer 220, which is equivalent to improving the mobility of the "channel region" of the thin-film transistor. Therefore, the thin-film transistor provided by this application can better solve the problems of excessive leakage current and low mobility of vertical thin-film transistors.

[0053] The technical solutions of this application will now be described with reference to specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0054] Please see Figure 1 In the thin-film transistor of this application, the insulating substrate 100 may include a substrate 110 and a buffer layer 120 disposed on the substrate 110. The substrate 110 may be a glass substrate or a polyimide substrate, and the buffer layer 120 may be an inorganic film layer such as SiOx, SiNx, or SiON or a stack thereof.

[0055] In this embodiment, the active layer 200 may be made of polycrystalline silicon.

[0056] In this embodiment, the first active layer 210 and the second active layer 230 can be phosphorus ion-doped polycrystalline silicon films.

[0057] In this embodiment, the doping concentration of phosphorus ions in the second doped portion 212 of the first active layer 210 can be the same as the doping concentration of phosphorus ions in the second active layer 230, or the doping concentration of phosphorus ions in the second doped portion 212 can be greater than the doping concentration of phosphorus ions in the second active layer 230.

[0058] In this embodiment, the phosphorus ion doping concentration in the first doped portion 211 of the first active layer 210 may be different from the phosphorus ion doping concentration in the second doped portion 212 and the second active layer 230. Specifically, the phosphorus ion doping concentration in the first doped portion 211 may be less than the phosphorus ion doping concentration in the second doped portion 212 and the phosphorus ion doping concentration in the second active layer 230.

[0059] In this embodiment, the first doped portion 211, the second doped portion 212, and the second active layer 230 in the first active layer 210 can achieve differences in phosphorus ion doping concentration through different doping times. For example, the first doped portion 211 of the first active layer 210 can be formed by one doping, while the second doped portion 212 and / or the second active layer 230 can be formed by two or more doping times. It should be noted that the number of doping times in the first doped portion 211, the second doped portion 212, and the second active layer 230 in this embodiment is not limited to one, two, three, etc. The specific number of doping times can be adjusted according to the phosphorus ion doping concentration difference requirements of the three, and this application does not impose specific limitations in this regard.

[0060] In this embodiment, the ratio of the doped ion concentration in the first doped portion 211 to the doped ion concentration in the second doped portion 212 can be any value between 1 / 10 and 1 / 5. For example, in one embodiment, the ratio of the doped ion concentration in the first doped portion 211 to the doped ion concentration in the second doped portion 212 can be 1:10. In another embodiment, the ratio of the doped ion concentration in the first doped portion 211 to the doped ion concentration in the second doped portion 212 can be 3:20. In another embodiment, the ratio of the doped ion concentration in the first doped portion 211 to the doped ion concentration in the second doped portion 212 can be 1:5. It should be noted that the ratio of the doped ion concentration in the first doped portion 211 to the doped ion concentration in the second doped portion 212 can also be other values ​​between 1 / 10 and 1 / 5. This embodiment is only illustrative and not exhaustive.

[0061] In this embodiment, by setting the ratio of the doped ion concentration in the first doped portion 211 to the doped ion concentration in the second doped portion 212 to 1 / 10 to 1 / 5, a suitable doped ion concentration difference can be achieved between the first doped portion 211 and the second doped portion 212, thereby achieving the effect of reducing leakage current and improving channel mobility.

[0062] In this embodiment, the channel layer 220 may also include doped ions, specifically, the doped ions may be phosphorus ions.

[0063] In this embodiment, the dopant ion concentration on the side of the channel layer 220 away from the insulating substrate 100 can be greater than the dopant ion concentration on the side of the channel layer 220 closer to the insulating substrate 100. The dopant ions in the channel layer 220 can be derived from phosphorus ions penetrating downwards during the doping process of the second active layer 230. Therefore, the dopant ion concentration penetrating into the channel layer 220 gradually decreases along the direction away from the second active layer 230 until there are no dopant ions.

[0064] Please see Figure 1 and Figure 2 In the thin-film transistor of this application, the first doped portion 211 and the second doped portion 212 can be disposed on the insulating substrate 100 in the same layer. Specifically, the first doped portion 211 and the second doped portion 212 can be integrally formed on the insulating substrate 100 by the polycrystalline silicon material forming the first active layer 210, and then the polycrystalline silicon material is subjected to different doping processes to form the first doped portion 211 and the second doped portion 212 disposed in the same layer but with different ion doping concentrations.

[0065] In this embodiment, in the direction perpendicular to the insulating substrate 100, the thickness of the second doped portion 212 may be less than or equal to the thickness of the first doped portion 211.

[0066] Specifically, please refer to Figure 1 and Figure 2 When the thickness of the second doped portion 212 is equal to the thickness of the first doped portion 211, the first doped portion 211 and the second doped portion 212 are integrally formed on the insulating substrate 100 by the polycrystalline silicon material forming the first active layer 210. In this case, the difference between the first doped portion 211 and the second doped portion 212 lies only in the concentration of doped ions. The first doped portion 211 and the second doped portion 212 can be fabricated using only different doping processes, resulting in a simple overall process and low cost.

[0067] Please see Figure 2 and Figure 3 When the thickness of the second doped portion 212 is less than or equal to the thickness of the first doped portion 211, the first doped portion 211 and the second doped portion 212 are formed as follows: after the polycrystalline silicon material of the first active layer 210 is formed on the insulating substrate 100, photolithography is performed at the position corresponding to the second doped portion 212, so that the thickness of the polycrystalline silicon material corresponding to the second doped portion 212 is less than the thickness of the polycrystalline silicon material corresponding to the first doped portion 211. At this time, taking the surface of the insulating substrate 100 near the first active layer 210 as the reference plane, the surface height of the second doped portion 212 on the side away from the insulating substrate 100 is lower than the surface height of the first doped portion 211 on the side away from the insulating substrate 100. This results in a gap between the channel layer 220 on the first doped portion 211 and the second doped portion 212, avoiding or reducing the possibility of direct contact between the channel layer 220 and the second doped portion 212. This reduces the risk of charge carriers being directly transferred from the channel layer 220 to the second doped portion 212 or from the second doped portion 212 to the channel layer 220, which is beneficial to further improve the stability of reducing the leakage current of the thin film transistor.

[0068] In this embodiment, in the direction perpendicular to the insulating substrate 100, the ratio of the thickness of the second doped portion 212 to the thickness of the first doped portion 211 can be any value between 1 / 4 and 1. Specifically, for example, in one embodiment, the ratio of the thickness of the second doped portion 212 to the thickness of the first doped portion 211 can be 1 / 4. In another embodiment, the ratio of the thickness of the second doped portion 212 to the thickness of the first doped portion 211 can be 1 / 2. In yet another embodiment, the ratio of the thickness of the second doped portion 212 to the thickness of the first doped portion 211 can be 1. It should be noted that the ratio of the thickness of the second doped portion 212 to the thickness of the first doped portion 211 can also be other values ​​between 1 / 4 and 1; this embodiment is merely illustrative and not exhaustive.

[0069] In this embodiment, the ratio of the thickness of the second doped portion 212 to the thickness of the first doped portion 211 is set to 1 / 4 to 1, so that the thickness of the second doped portion 212 can meet the stability requirements for reducing the leakage current of the thin film transistor, while also taking into account the carrier mobility requirements in the active layer 200 of the thin film transistor, thus achieving a performance balance.

[0070] Please see Figure 4 In the thin-film transistor of this application, in the direction perpendicular to the insulating substrate 100, the channel layer 220 may correspond to the first doped portion 211, or in other words, the channel layer 220 may be disposed on the first doped portion 211, so that when the charge carriers are transported between the channel layer 220 and the second doped portion 212, they must pass through the first doped portion 211, thereby achieving the effect of extending the channel length of the "channel region" and reducing leakage current.

[0071] In this embodiment, the orthogonal projection of the channel layer 220 onto the first active layer 210 can partially overlap with the first doped portion 211 and the second doped portion 212. That is, the channel layer 220 is simultaneously disposed on the first doped portion 211 and the second doped portion 212, or in other words, the channel layer 220 spans across the first doped portion 211 and the second doped portion 212. In this case, the width of the channel layer 220 is extended in the direction from the first doped portion 211 to the second doped portion 212, which is equivalent to increasing the width of the "channel region", that is, increasing the "channel width-to-length ratio" of the channel region. The probability of carriers not being captured by the interface gap state during migration is greater, that is, carriers are easier to drift, which is beneficial to reducing the threshold voltage of the thin-film transistor.

[0072] In this embodiment, if the thickness of the second doped portion 212 is the same as the thickness of the first doped portion 211, then there are two transport paths for the charge carriers between the channel layer 220 and the second doped portion 212: path one is that the channel layer 220 and the second doped portion 212 are directly connected, and path two is that the channel layer 220 is connected to the second doped portion 212 through the first doped portion 211. When the thin-film transistor is working, most of the charge carriers are transported through path one, and a small portion of the charge carriers are transported through path two. At this time, the carrier mobility of the thin-film transistor is higher, but the leakage current is larger.

[0073] In this embodiment, if the thickness of the second doped portion 212 is different from the thickness of the first doped portion 211, then there is only one transport path for the carriers between the channel layer 220 and the second doped portion 212: the channel layer 220 is connected to the second doped portion 212 through the first doped portion 211, i.e., path two. In this case, compared to the aforementioned method of transporting carriers through path one and path two, the mobility of the thin-film transistor is reduced, but the leakage current is significantly improved.

[0074] Please see Figure 1 and Figure 5 In the thin-film transistor of this application, in the direction perpendicular to the insulating substrate 100, the orthogonal projection of the channel layer 220 onto the first active layer 210 lies within the first doped portion 211, and the orthogonal projection of the channel layer 220 onto the first active layer 210 does not overlap with the second doped portion 212. In other words, the edge of the channel layer 220 does not extend beyond the boundary line between the first doped portion 211 and the second doped portion 212, thereby creating a gap between the edge of the channel layer 220 and the second doped portion 212 in the direction from the first doped portion 211 to the second doped portion 212. This also avoids or reduces the possibility of direct contact between the channel layer 220 and the second doped portion 212, thereby reducing the risk of charge carriers being directly transferred from the channel layer 220 to the second doped portion 212 or from the second doped portion 212 to the channel layer 220, which is beneficial for further improving the stability of reducing the leakage current of the thin-film transistor.

[0075] Please see Figure 1 In the thin-film transistor of this application, the thin-film transistor may further include a first insulating layer 300 disposed on the active layer 200, a gate layer 400 disposed on the first insulating layer 300, a second insulating layer 500 disposed on the first insulating layer 300, and a source-drain layer 600 disposed on the second insulating layer 500.

[0076] In this embodiment, the first insulating layer 300 is continuously disposed and covers the surface of the active layer 200 and the surface of the insulating substrate 100 except for the area where the active layer 200 is located. At this time, the first insulating layer 300 covers the surfaces of the second active layer 230 and the second doped portion 212 located on the surface of the stacked structure of the active layer 200, so that the second active layer 230 can be isolated from other film layers.

[0077] In this embodiment, the first insulating layer 300 may be an inorganic film layer such as SiOx, SiNx, or SiON, or a stack thereof, and the thickness of the first insulating layer 300 may be from 30 nanometers to 200 nanometers.

[0078] In this embodiment, the gate layer 400 may be a metal such as Mo, Ti, W or a stack thereof, and the thickness of the gate layer 400 is 0.1 micrometer to 1 micrometer.

[0079] In this embodiment, the second insulating layer 500 may be a stack of SiOx and SiNx.

[0080] In this embodiment, the source / drain layer 600 can be a metal such as Mo, Ti, W, Al, Cu, or a stack thereof.

[0081] In this embodiment, the gate layer 400 may be arranged in a ring shape on the side of the first insulating layer 300 away from the active layer 200. Specifically, the gate layer 400 may be disposed in close contact with the sidewall of the first insulating layer 300 on the stacked first doped portion 211, the channel layer 220, and the second active layer 230. The ring-shaped gate layer 400 surrounds the periphery of the stacked structure formed by the first doped portion 211, the channel layer 220, and the second active layer 230.

[0082] In this embodiment, the orthographic projection of the channel layer 220 onto the gate layer 400 at least partially overlaps with the gate layer 400, so that the gate layer 400 is at least partially aligned with the channel layer 220, thereby achieving a control effect and realizing the switching control function of the thin-film transistor. The annular gate layer 400 has a stronger control capability over the channel layer 220, which can further reduce the leakage current of the vertical structure thin-film transistor.

[0083] In this embodiment, the second insulating layer 500 covers the surfaces of the first insulating layer 300 and the gate layer 400, and the surface of the second insulating layer 500 away from the insulating substrate 100 is flat, so that the source-drain layer 600 can be stably disposed on the surface of the second insulating layer 500.

[0084] In this embodiment, the source / drain layer 600 may include a source 610 and a drain 620. A first via 101 and a second via 102, corresponding to the source 610 and drain 620 respectively, are provided on the first insulating layer 300 and the second insulating layer 500. The first via 101 and the second via 102 extend along the stacking direction of the first insulating layer 300 and the second insulating layer 500. The orthographic projection of the first via 101 onto the insulating substrate 100 lies within the orthographic projection of the second active layer 230 onto the insulating substrate 100, and the orthographic projection of the second via 102 onto the insulating substrate 100 lies within the orthographic projection of the second doped portion 212 onto the insulating substrate 100. The source 610 is connected to the second active layer 230 through the first via 101, and the drain 620 is connected to the second doped portion 212 through the second via 102.

[0085] In this embodiment, by providing a first via 101 and a second via 102 on the first insulating layer 300 and the second insulating layer 500 corresponding to the second active layer 230 and the second doped portion 212, and connecting the source / drain layer 600 to the second active layer 230 and the second doped portion 212 through the first via 101 and the second via 102, the carrier migration path of the thin-film transistor must pass through the first doped portion 211, thereby extending the "channel region" length, reducing leakage current while maintaining a high mobility. Moreover, the connection structure between the source / drain layer 600 and the active layer 200 in this application is simple, easy to manufacture, and can effectively reduce manufacturing costs.

[0086] Please see Figure 1 and Figure 3 In the thin-film transistor of this application, the gate layer 400 may include a first gate portion 410 and a second gate portion 420 connected as one piece. The first gate portion 410 is disposed above the insulating substrate 100, and the second gate portion 420 is disposed above the second doped portion 212 in an insulating manner.

[0087] In this embodiment, the first gate portion 410 and the second gate portion 420 are integrally formed. However, due to the stacking height of the second doped portion 212, the gate portion on the second doped portion 212 protrudes beyond the gate portions at other locations, thus forming the first gate portion 410 and the second gate portion 420. It is understood that, due to the "lifting" effect of the second doped portion 212, the distance from the surface of the second gate portion 420 away from the insulating substrate 100 to the insulating substrate 100 is greater than the distance from the surface of the first gate portion 410 away from the insulating substrate 100 to the insulating substrate 100.

[0088] In this embodiment, the orthogonal projection of the channel layer 220 onto the first gate portion 410 is located within the first gate portion 410, and the orthogonal projection of the channel layer 220 onto the second gate portion 420 at least partially overlaps with the second gate portion 420.

[0089] Understandably, please refer to Figure 1 When the thickness of the second doped portion 212 is the same as the thickness of the first doped portion 211, due to the "lifting" effect of the second doped portion 212, the "facing" area between the second gate portion 420 and the channel layer 220 decreases, causing the orthogonal projection of the channel layer 220 onto the second gate portion 420 to partially overlap with the second gate portion 420; see also Figure 3 When the thickness of the second doped portion 212 is less than the thickness of the first doped portion 211, the "padded" effect on the second gate portion 420 is reduced, and its "opposite" area with the channel layer 220 can be increased accordingly. In some cases, the channel layer 220 and the second gate portion 420 are completely opposite, that is, the orthogonal projection of the channel layer 220 on the second gate portion 420 completely overlaps with the second gate portion 420.

[0090] In this embodiment, since the first gate portion 410 is not "lifted" by the second doped portion 212, it can be completely aligned with the channel layer 220, thereby achieving a good control effect on the channel layer 220.

[0091] Please see Figure 1 and Figure 6 In the thin-film transistor of this application, the thin-film transistor may further include a light-shielding layer 700 disposed within the insulating substrate 100. The light-shielding layer 700 is a conductive metal layer, such as Mo, Ti, W, or a stack thereof. The orthogonal projection of the active layer 200 onto the light-shielding layer 700 is located within the light-shielding layer 700.

[0092] Please see Figure 3 In this embodiment, the light-shielding layer 700 can be disposed between the substrate 110 and the buffer layer 120. The buffer layer 120 is provided with a third via 103 corresponding to the first gate portion 410. The first gate portion 410 can be connected to the light-shielding layer 700 through the third via 103, so that the accumulated charge on the gate layer 400 can be introduced to the light-shielding layer 700, thereby reducing the charge accumulation on the gate layer 400 and improving the device stability of the thin-film transistor.

[0093] In this embodiment, the first active layer 210 is configured to include a first doped portion 211 and a second doped portion 212 with different doping ion concentrations. The second doped portion 212 and the second active layer 230 respectively serve as two "doped regions" of the thin-film transistor, while the channel layer 220 and the first doped portion 211 constitute the "channel region" of the thin-film transistor. This effectively increases the channel length. Furthermore, an annular gate layer 400 is provided around the channel layer 220 to enhance the control capability of the channel layer 220, thereby reducing leakage current. Moreover, because the first doped portion 211 is doped with ions, its mobility is higher than that of the channel layer 220, which is equivalent to improving the mobility of the "channel region" of the thin-film transistor. Therefore, the thin-film transistor provided in this application can effectively solve the problems of excessive leakage current and low mobility.

[0094] Please see Figures 7 to 13 This application also provides a method for fabricating a thin-film transistor, used to fabricate the thin-film transistor described in the above embodiments.

[0095] In this embodiment, the method for fabricating the thin-film transistor may include:

[0096] S100, providing an insulating substrate 100, such as Figure 8 As shown;

[0097] S200, a first active layer 210, a channel layer 220, and a second active layer 230 are sequentially formed on the insulating substrate 100 to constitute the active layer 200 of the thin-film transistor, as shown below. Figure 9 and Figure 10 As shown;

[0098] S300, a gate layer 400 is formed on the periphery of the active layer 200, such as Figure 11 As shown;

[0099] S400, an insulating source / drain layer 600 is formed on the gate layer 400, and the source / drain layer 600 is connected to the first active layer 210 and the second active layer 230, such as... Figure 12 and Figure 13 As shown.

[0100] This embodiment fabricates the thin-film transistor through the above steps, enabling the thin-film transistor to reduce its occupied area and size by utilizing a vertical structure. It can also extend the length of the "channel region" through the first doped portion 211, thereby improving mobility and achieving lower leakage current. Furthermore, the annular gate layer 400 disposed around the active layer 200 enhances the control of the channel layer 220, thereby further reducing the leakage current of the vertical structure thin-film transistor and improving the device performance and stability of the thin-film transistor.

[0101] In this embodiment, step S200 may include:

[0102] S210, A first polycrystalline silicon material layer is formed on the insulating substrate 100, such as... Figure 8 As shown.

[0103] In this embodiment, the thickness of the first polycrystalline silicon material layer can be 10 to 100 nanometers, and the first polycrystalline silicon material layer can be transformed from an a-Si material layer through processes such as laser annealing.

[0104] S220. The first polycrystalline silicon material layer is lightly doped to form a lightly doped material layer, such as... Figure 9 As shown.

[0105] In this embodiment, the dopant ions used to lightly dope the first polycrystalline silicon material layer can be phosphorus ions.

[0106] S230, A channel layer 220 is formed on a portion of the lightly doped material layer, such as Figure 10 As shown.

[0107] In this embodiment, the channel layer 220 can be formed by transforming an a-Si material layer with a thickness of 10 nanometers to 200 nanometers into polycrystalline silicon material through processes such as laser annealing.

[0108] S240, A second polycrystalline silicon material layer is formed on the channel layer 220, such as Figure 10 As shown.

[0109] In this embodiment, the second polycrystalline silicon material layer can be formed by transforming an a-Si material layer with a thickness of 50 nanometers to 300 nanometers into polycrystalline silicon material through processes such as laser annealing.

[0110] S250. The second polysilicon material layer and the lightly doped material layer, except for the region corresponding to the channel layer 220, are subjected to secondary doping. Simultaneously, a second active layer 230 is formed on the side of the channel layer 220 away from the insulating substrate 100, and a second doped portion 212 is formed below one side of the channel layer 220. The portion of the lightly doped material layer not subjected to secondary doping is the first doped portion 211. Figure 10 As shown.

[0111] In this embodiment, the first doped portion 211, the second doped portion 212, and the second active layer 230 of the first active layer 210 are formed through the above steps, so that the second active layer 230 can be formed simultaneously with the first doped portion 211 and the second doped portion 212, which can effectively improve the fabrication efficiency of the active layer 200 and save photomask costs.

[0112] This application also provides an electronic device, which may include the thin-film transistor described in the above embodiments.

[0113] The foregoing has provided a detailed description of a thin-film transistor and its electronic device according to the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A thin-film transistor, characterized in that, include: Insulating substrate; as well as An active layer is disposed on the insulating substrate. The active layer includes a first active layer, a channel layer, and a second active layer stacked together. The first active layer includes a first doped portion and a second doped portion. The first doped portion is connected to the channel layer and the second doped portion. The doped ion concentration in the first doped portion is less than the doped ion concentration in the second doped portion. The first doped portion and the second doped portion are disposed in the same layer on the insulating substrate. A gate layer is provided in an annular insulating manner on the periphery of the channel layer. The gate layer includes a first gate portion and a second gate portion connected as a single unit. The first gate portion is disposed above the insulating substrate, and the second gate portion is disposed in an insulating manner above the second doped portion. Wherein, in the direction perpendicular to the insulating substrate, the thickness of the second doped portion is less than the thickness of the first doped portion, and the orthogonal projection of the channel layer on the first gate portion is located within the first gate portion, and the orthogonal projection of the channel layer on the second gate portion is located within the second gate portion.

2. The thin-film transistor according to claim 1, characterized in that, The ratio of the doped ion concentration in the first doped region to the doped ion concentration in the second doped region is 1 / 10 to 1 / 5.

3. The thin-film transistor according to claim 1, characterized in that, In the direction perpendicular to the insulating substrate, the ratio of the thickness of the second doped portion to the thickness of the first doped portion is 1 / 4 to 1.

4. The thin-film transistor according to claim 1, characterized in that, The channel layer includes doped ions, and the concentration of doped ions on the side of the channel layer away from the insulating substrate is greater than the concentration of doped ions on the side of the channel layer closer to the insulating substrate.

5. The thin-film transistor according to claim 1, characterized in that, The thin-film transistor further includes a first insulating layer disposed between the active layer and the gate layer; The first insulating layer covers the surface of the second active layer, the surface of the second doped portion, and part of the surface of the insulating substrate.

6. The thin-film transistor according to claim 5, characterized in that, The thin-film transistor further includes a second insulating layer and a source-drain layer, wherein the second insulating layer covers the first insulating layer and the gate layer, and the source-drain layer is disposed on the second insulating layer; The first insulating layer and the second insulating layer are provided with a first via and a second via. The source and drain layers are connected to the second active layer through the first via, and the source and drain layers are connected to the second doped portion through the second via.

7. The thin-film transistor according to claim 1, characterized in that, The thin-film transistor further includes a light-shielding layer disposed within the insulating substrate, wherein the orthographic projection of the active layer onto the light-shielding layer is located within the light-shielding layer; The gate layer and the light-shielding layer are connected through a third via.

8. An electronic device, characterized in that, Including the thin-film transistor as described in any one of claims 1 to 7.

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