A DLL phase compensation circuit

Abstract

The present invention discloses a DLL phase compensation circuit, which belongs to the field of integrated circuits. The DLL phase compensation circuit adds a clock input port level detection delay simulation unit and a Q port data output drive delay simulation unit, which are respectively used to analogize the phase time delay generated by the input port level detection circuit and the Q port data sampling and drive output circuit, and compensate for the phase difference generated by the two. At the same time, the power supply parameters of the clock input port level detection delay simulation unit remain consistent with the power supply of the input port level detection, and the power supply parameters of the Q port data output drive delay simulation unit remain consistent with the power supply of the Q port data sampling and drive output circuit. In addition, an adjustable delay unit circuit is used to compensate for the time delay caused by large parasitic resistance and parasitic capacitance generated by long metal traces in the layout.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a DLL phase compensation circuit. Background Art

[0002] As memory operating frequencies increase, both DDR (Double Data Rate) and QDR (Quad Data Rate) static random-access memories (SRAMs) incorporate DLL (Delay-Locked Loop) circuits. The DLL circuit's role in the system is to offset the built-in delay of the external system clock. This is particularly important when controlling the timing of reading data from internal memory cells to external data ports. The data must be established at a specific delay of N (N can be 1, 1.5, 2, etc.) system clock cycles. The DLL circuit's phase compensation plays a crucial role. The compensated phase must match the input port delay and the output port driver delay.

[0003] Traditional phase compensation implementation methods have complex logic control and poor adaptability. For example, the compensation method implemented in patent CN109842413A is implemented by connecting gate-level circuits in series. The phase compensation size will cause phase compensation imbalance as the process, voltage and temperature change, and the solution has poor adaptability. Summary of the Invention

[0004] The object of the present invention is to provide a DLL phase compensation circuit to solve the problem of poor adaptability of traditional phase compensation methods.

[0005] To solve the above technical problems, the present invention provides a DLL phase compensation circuit, comprising:

[0006] Clock input port level detection delay simulation unit, used to achieve input clock delay;

[0007] The Q port data output drives the delay simulation unit to achieve the delay of the output data;

[0008] Adjustable delay unit circuit to achieve system clock phase delay;

[0009] The timing matching of input clock and output data is achieved by detecting the delay simulation unit at the clock input port level and driving the delay simulation unit at the Q port data output, in conjunction with the delay of the adjustable delay unit circuit.

[0010] In one embodiment, the clock input port level detection delay simulation unit includes PMOS tubes M31-M32, NMOS tubes M33-M35 and X36 unit;

[0011] The PMOS transistors M31 to M32 and the NMOS transistors M33 to M35 constitute a level comparator unit; the drain terminal of the PMOS transistor M31 is connected to the drain terminal of the NMOS transistor M33, the drain terminal of the PMOS transistor M32 is connected to the drain terminal of the NMOS transistor M34, and the gate terminal of the PMOS transistor M32 is connected to both the gate terminal and the drain terminal of the PMOS transistor M31; the source terminal of the PMOS transistor M31 and the source terminal of the PMOS transistor M32 are both connected to the power supply VCC;

[0012] The gate terminal of the NMOS transistor M33 is connected to the detected signal IN, the gate terminal of the NMOS transistor M34 is connected to the reference voltage VREF, and the source terminals of the NMOS transistors M33 and M34 are commonly connected to the drain terminal of the NMOS transistor M35; the gate terminal of the NMOS transistor M35 is connected to the power supply VCC, and the source terminal is grounded; the X36 unit is an output drive circuit, whose input terminal is connected to the drain terminal of the PMOS transistor M32 and the drain terminal of the NMOS transistor M34 at the same time, and the output terminal outputs the OUT signal.

[0013] In one embodiment, the circuit of the Q port data output driving delay simulation unit includes a PMOS transistor and an NMOS transistor, which form a push-pull structure. The PMOS transistor and the NMOS transistor are respectively connected to a pull-up buffer structure and a pull-down buffer structure, wherein the input end of the pull-up buffer structure is connected to a high-voltage converter, and the input end of the high-voltage converter is connected to an inverter, and the inverter and the pull-down buffer structure are commonly connected to the data input end.

[0014] In one embodiment, the circuit of the Q-port data output driving delay simulation unit includes PMOS transistors M41-M42, PMOS transistors M45-M46, NMOS transistors M43-M44, NMOS transistor M47, and inverters INV1-INV5; the source terminals of the PMOS transistors M41-M42 and the PMOS transistors M45-M46 are all connected to the power supply voltage VCCQ; the drain terminal of the PMOS transistor M41 is connected to the gate terminal of the PMOS transistor M42, the drain terminal of the PMOS transistor M42 is connected to the gate terminal of the PMOS transistor M41, the gate terminal of the PMOS transistor M45 is connected to the drain terminal of the PMOS transistor M41, and the drain terminal of the PMOS transistor M45 is connected to the drain terminal of the NMOS transistor M44; the gate terminal of the NMOS transistor M43 is simultaneously connected to the gate terminal of the NMOS transistor M44 and the drain terminal of the PMOS transistor M41, and the source terminal of the NMOS transistor M43 and the source terminal of the NMOS transistor M44 are both grounded;

[0015] The detected signal IN is simultaneously connected to the input terminal of the inverter INV1 and the input terminal of the inverter INV2; the output terminal of the inverter INV1 is connected to the gate terminal of the NMOS transistor M43; the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3, the output terminal of the inverter INV3 is connected to the gate terminal of the NMOS transistor M47, and the source terminal of the NMOS transistor M47 is grounded; the input terminal of the inverter INV4 is simultaneously connected to the drain terminal of the PMOS transistor M45 and the drain terminal of the NMOS transistor M44, the output terminal is connected to the input terminal of the inverter INV5, the output terminal of the inverter INV5 is connected to the gate terminal of the PMOS transistor M46, the drain terminal of the PMOS transistor M46 is connected to the drain terminal of the NMOS transistor M47, and the inverter outputs the OUT signal.

[0016] In one embodiment, the clock input port level detection delay simulation unit realizes a first delay time; the Q port data output drive delay simulation unit realizes a second delay time; the adjustable delay unit circuit realizes a third delay time; through the first delay time, the second delay time and the third delay time, the input clock and the output data sampling clock are the same in phase, and the sampling data can be output normally.

[0017] In one embodiment, the first delay time is less than one system clock cycle; the second delay time is less than one system clock cycle; the third delay time is less than one system clock cycle; and the sum of the three delay times is no more than one system clock cycle.

[0018] In the DLL phase compensation circuit provided by the present invention, a clock input port level detection delay simulation unit and a Q port data output drive delay simulation unit are added, which are used to analogize the phase time delay generated by the input port level detection circuit and the Q port data sampling and drive output circuit, respectively, to compensate for the phase difference generated by the two. At the same time, the power supply parameters of the clock input port level detection delay simulation unit remain consistent with the power supply of the input port level detection, and the power supply parameters of the Q port data output drive delay simulation unit remain consistent with the power supply of the Q port data sampling and drive output circuit. In addition, an adjustable delay unit circuit is used to compensate for the time delay caused by large parasitic resistance and parasitic capacitance generated by long metal traces in the layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a block diagram of the memory data read system.

[0020] Figure 2 This is a schematic diagram of the structure of a DLL phase compensation circuit provided by the present invention.

[0021] Figure 3 This is a circuit structure diagram of a clock input port level detection delay simulation unit.

[0022] Figure 4 This is a schematic diagram of the circuit structure of the Q port data output driving delay simulation unit.

[0023] Figure 5 This is the main timing diagram related to DLL phase compensation. DETAILED DESCRIPTION

[0024] The following is a detailed description of a DLL phase compensation circuit proposed by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clarify the purpose of illustrating the embodiments of the present invention.

[0025] like Figure 1 The following is a block diagram of the data readout system of the memory device according to the present invention. CLK_IN is the external input clock signal, and VREF is the reference level of the input port level detection circuit. CLK is the internal system clock signal after the external input clock signal CLK_IN passes through the input port level detection circuit. CLK_DLL is the synchronous clock signal output by the DLL circuit. A phase difference detection circuit detects the phase difference between the feedback signal CLK_FB and the internal system clock signal CLK, generating a control signal VPCT. The timing control logic circuit outputs a control signal VDLY_CT, which is used to adjust the delay time of the cascaded delay chain circuit. DATA is the internal data signal to be output. The data signal DATA is output to the external bus QOUT via the Q port data sampling and drive output circuit. Figure 1 The dotted box in the figure is the DLL circuit module, which consists of a phase difference detection circuit, a series delay chain circuit, a timing control logic circuit, a driver output stage and a feedback delay time adjustment circuit.

[0026] Figure 2 This is a schematic diagram of the structure of a DLL phase compensation circuit proposed by the present invention. CLKFB_IN is the sampling signal of the synchronous clock signal CLK_DLL output by the DLL circuit. The first level shift module converts the core level VDD logic into VCCQ level logic. The Q port data output drive delay analog unit is analogous to Figure 1 The Q port data sampling and drive output circuit in the circuit has a delay time To_q_an equal to To_q. The second level shift module converts the VCCQ level logic into the VCC level logic. The clock input port level detection delay simulation unit is analogous to Figure 1In the input port level detection circuit, the delay time Tin_an is equal to Tin. The third level shift module converts the VCC level logic to the VDD level logic. The delay time of the adjustable delay unit circuit is Tdet, which is used to compensate for the time delay caused by large parasitic resistance and capacitance generated by long metal traces in the layout.

[0027] like Figure 3 The figure shows the circuit structure of the clock input port level detection delay simulation unit, which includes PMOS tubes M31-M32, NMOS tubes M33-M35 and X36 unit; the PMOS tubes M31-M32 and NMOS tubes M33-M35 constitute a level comparator unit. The drain of the PMOS transistor M31 is connected to the drain of the NMOS transistor M33, the drain of the PMOS transistor M32 is connected to the drain of the NMOS transistor M34, and the gate of the PMOS transistor M32 is connected to both the gate and drain of the PMOS transistor M31; the source of the PMOS transistor M31 and the source of the PMOS transistor M32 are both connected to the power supply VCC; the gate of the NMOS transistor M33 is connected to the detected signal IN, the gate of the NMOS transistor M34 is connected to the reference voltage VREF, the source of the NMOS transistor M33 and the source of the NMOS transistor M34 are commonly connected to the drain of the NMOS transistor M35; the gate of the NMOS transistor M35 is connected to the power supply VCC, and the source is grounded; the X36 unit is an output drive circuit, whose input is connected to both the drain of the PMOS transistor M32 and the drain of the NMOS transistor M34, and whose output outputs the OUT signal.

[0028] Figure 4 The circuit structure of the Q-port data output driving delay simulation unit includes PMOS transistors M41-M42, PMOS transistors M45-M46, NMOS transistors M43-M44, NMOS transistor M47, and inverters INV1-INV5. The source terminals of the PMOS transistors M41-M42 and PMOS transistors M45-M46 are all connected to the power supply voltage VCCQ. The drain terminal of the PMOS transistor M41 is connected to the gate terminal of the PMOS transistor M42, the drain terminal of the PMOS transistor M42 is connected to the gate terminal of the PMOS transistor M41, the gate terminal of the PMOS transistor M45 is connected to the drain terminal of the PMOS transistor M41, and the drain terminal of the PMOS transistor M45 is connected to the drain terminal of the NMOS transistor M44. The gate terminal of the NMOS transistor M43 is connected to the gate terminal of the NMOS transistor M44 and the drain terminal of the PMOS transistor M41 at the same time. The source terminal of the NMOS transistor M43 and the source terminal of the NMOS transistor M44 are both grounded.

[0029] The detected signal IN is simultaneously connected to the input terminal of the inverter INV1 and the input terminal of the inverter INV2; the output terminal of the inverter INV1 is connected to the gate terminal of the NMOS transistor M43; the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3, the output terminal of the inverter INV3 is connected to the gate terminal of the NMOS transistor M47, and the source terminal of the NMOS transistor M47 is grounded; the input terminal of the inverter INV4 is simultaneously connected to the drain terminal of the PMOS transistor M45 and the drain terminal of the NMOS transistor M44, the output terminal is connected to the input terminal of the inverter INV5, the output terminal of the inverter INV5 is connected to the gate terminal of the PMOS transistor M46, the drain terminal of the PMOS transistor M46 is connected to the drain terminal of the NMOS transistor M47, and the inverter outputs the OUT signal.

[0030] exist Figure 4 In the figure, the circuit within the dashed box is powered by VCCQ, while inverters INV1 through INV3 are powered by the core power supply VDD. PMOS transistors M41 through M42, NMOS transistors M43 through M44, and PMOS transistor M45 together form a level shift circuit, converting the VDD logic level to the VCCQ logic level. Inverters INV4 and INV5 act as driver buffers and form the high-side drive branch, driving the gate of PMOS transistor M46. Inverters INV2 and INV3 form the low-side drive branch, driving the gate of NMOS transistor M47. PMOS transistors M46 and NMOS transistors M47 form a push-pull output structure. The time delay generated by the series connection of low-side inverters INV2 and INV3 balances the high-side drive time delay.

[0031] like Figure 5 The following diagram shows the key timing diagrams related to DLL phase compensation. CLK_IN is the external input clock, READ is the read command signal, ADDRESS is the address signal, QOUT is the output bus, CLK is the internal system clock signal, CLK_DLL is the synchronous clock signal output by the DLL circuit, and CLKF_FB is the sampling feedback signal of the DLL circuit output clock CLK_DLL. The system specifically delays the data output to the QOUT bus after sampling the READ command. To_q is the delay time of the Q port data output driver delay analog unit (i.e., the second delay time), Tin is the delay time of the clock input port level detection delay analog unit (i.e., the first delay time), and the DLL circuit's phase compensation time, Tfb, compensates for the Tin and To_q time delays.

[0032] The above are preferred embodiments of the present invention. Various modifications can be made to the present invention within the scope of the present invention, such as modifying the comparator type of the clock input port level detection delay simulation unit.

[0033] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A DLL phase compensation circuit, characterized in that: include: Clock input port level detection delay simulation unit, used to achieve input clock delay; The Q port data output drives the delay simulation unit to achieve the delay of the output data; Adjustable delay unit circuit to achieve system clock phase delay; The timing matching of input clock and output data is achieved by detecting the delay of the clock input port level delay simulation unit and the delay of the Q port data output driving delay simulation unit in conjunction with the delay of the adjustable delay unit circuit; The clock input port level detection delay simulation unit includes PMOS tubes M31-M32, NMOS tubes M33-M35 and X36 unit; The PMOS tubes M31~M32 and the NMOS tubes M33~M35 constitute a level comparator unit; The drain of the PMOS transistor M31 is connected to the drain of the NMOS transistor M33, the drain of the PMOS transistor M32 is connected to the drain of the NMOS transistor M34, and the gate of the PMOS transistor M32 is connected to both the gate and drain of the PMOS transistor M31; the source of the PMOS transistor M31 and the source of the PMOS transistor M32 are both connected to the power supply VCC; The gate terminal of the NMOS transistor M33 is connected to the detected signal IN, the gate terminal of the NMOS transistor M34 is connected to the reference voltage VREF, and the source terminals of the NMOS transistors M33 and M34 are connected to the drain terminal of the NMOS transistor M35. The gate terminal of the NMOS transistor M35 is connected to the power supply VCC, and the source terminal is grounded. The X36 unit is an output drive circuit, whose input terminal is connected to the drain terminal of the PMOS transistor M32 and the drain terminal of the NMOS transistor M34 at the same time, and the output terminal outputs the OUT signal. The circuit of the Q port data output driving delay simulation unit includes a PMOS transistor and an NMOS transistor, which form a push-pull structure. The PMOS transistor and the NMOS transistor are respectively connected to a pull-up buffer structure and a pull-down buffer structure, wherein the input end of the pull-up buffer structure is connected to a high-voltage converter, and the input end of the high-voltage converter is connected to an inverter. The inverter and the pull-down buffer structure are commonly connected to the data input end; The circuit of the Q-port data output driving delay simulation unit includes PMOS transistors M41-M42, PMOS transistors M45-M46, NMOS transistors M43-M44, NMOS transistor M47 and inverters INV1-INV5; the source terminals of the PMOS transistors M41-M42 and PMOS transistors M45-M46 are all connected to the power supply voltage VCCQ; the drain terminal of the PMOS transistor M41 is connected to the gate terminal of the PMOS transistor M42, the drain terminal of the PMOS transistor M42 is connected to the gate terminal of the PMOS transistor M41, the gate terminal of the PMOS transistor M45 is connected to the drain terminal of the PMOS transistor M41, and the drain terminal of the PMOS transistor M45 is connected to the drain terminal of the NMOS transistor M44; the gate terminal of the NMOS transistor M43 is connected to the gate terminal of the NMOS transistor M44 and the drain terminal of the PMOS transistor M41 at the same time, and the source terminal of the NMOS transistor M43 and the source terminal of the NMOS transistor M44 are both grounded; The detected signal IN is simultaneously connected to the input terminal of the inverter INV1 and the input terminal of the inverter INV2; the output terminal of the inverter INV1 is connected to the gate terminal of the NMOS transistor M43; the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3, the output terminal of the inverter INV3 is connected to the gate terminal of the NMOS transistor M47, and the source terminal of the NMOS transistor M47 is grounded; the input terminal of the inverter INV4 is simultaneously connected to the drain terminal of the PMOS transistor M45 and the drain terminal of the NMOS transistor M44, the output terminal is connected to the input terminal of the inverter INV5, the output terminal of the inverter INV5 is connected to the gate terminal of the PMOS transistor M46, the drain terminal of the PMOS transistor M46 is connected to the drain terminal of the NMOS transistor M47, and the inverter outputs the OUT signal.

2. The DLL phase compensation circuit according to claim 1, wherein: The clock input port level detection delay simulation unit realizes a first delay time; the Q port data output drive delay simulation unit realizes a second delay time; the adjustable delay unit circuit realizes a third delay time; through the first delay time, the second delay time and the third delay time, the input clock and the output data sampling clock are made identical in phase, and the sampled data can be output normally.

3. The DLL phase compensation circuit according to claim 2, wherein: The first delay time is less than one system clock cycle; the second delay time is less than one system clock cycle; the third delay time is less than one system clock cycle; and the sum of the three delay times is no more than one system clock cycle.

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