An electronic device

Abstract

The embodiments of the present application relate to the technical field of electronic products, and particularly to an electronic device, including: a circuit board; the circuit board is provided with a first layer having a first ground copper foil, a second layer having a preset circuit, a third layer having a second ground copper foil, and a fourth layer provided with a sensitive area; the distance between the first layer and the second layer is less than the distance between the second layer and the third layer; the preset circuit is a signal circuit and / or a power supply circuit; the orthographic projection of the preset circuit on the first layer is located on the first ground copper foil; the sensitive area is an area of a sensitive circuit provided on the fourth layer, or a projection area on the fourth layer of a sensitive device provided on the fourth layer; the orthographic projection of the sensitive circuit on the third layer is located on the second ground copper foil. The electronic device provided by the embodiments of the present application avoids the common ground interference of the sensitive circuit and / or the sensitive device corresponding to the sensitive area by the interference source signal circuit and / or the power supply circuit.

Description

[0001] Cross - Reference to Related Applications

[0002] This application is based on and claims priority to a Chinese patent application "An Electronic Device" with an application number of "202210730434.1" and a filing date of June 24, 2022. The entire content of this Chinese patent application is incorporated herein by reference. Technical Field

[0003] Embodiments of this application relate to the technical field of electronic products, and in particular, to an electronic device. Background Art

[0004] In electronic devices, circuit boards are often used as carriers for electrical connection of electronic components. In order to enable the development of electronic information technology towards high speed, multi-function, large capacity, small size, thinness, and light weight, multi-layer circuit boards have emerged. Among them, four-layer circuit boards are the most widely used in multi-layer circuit boards.

[0005] In existing four-layer circuit boards, a sensitive area is often set on the first layer. At the same time, interference source signal lines and / or power lines are arranged near the same layer of the sensitive area, which easily causes the sensitive lines and / or sensitive devices corresponding to the sensitive area to be subjected to common ground interference from the interference source signal lines and / or power lines, resulting in deterioration of the performance indicators of the sensitive lines and / or sensitive devices corresponding to the sensitive area.

[0006] Therefore, there is an urgent need to provide an electronic device to avoid the common ground interference of the sensitive lines and / or sensitive devices corresponding to the sensitive area from the interference source signal lines and / or power lines. Summary of the Invention

[0007] The purpose of the embodiments of this application is to provide an electronic device to avoid the common ground interference of the sensitive lines and / or sensitive devices corresponding to the sensitive area from the interference source signal lines and / or power lines.

[0008] To solve the above problems, an embodiment of the present application provides an electronic device, including a circuit board; the circuit board is provided with a first layer having a first ground copper foil, a second layer having a preset circuit, a third layer having a second ground copper foil, and a fourth layer provided with a sensitive area, which are stacked in sequence; the distance between the first layer and the second layer is less than the distance between the second layer and the third layer; the preset circuit is a signal circuit and / or a power supply circuit; the orthographic projection of the preset circuit on the first layer is located on the first ground copper foil; the sensitive area includes the area where the sensitive circuit provided on the fourth layer is located, and / or the projection area of the sensitive device provided on the fourth layer on the fourth layer; the orthographic projection of the sensitive area on the third layer is located on the second ground copper foil; wherein, the orthographic projection of the preset circuit on the fourth layer at least partially overlaps with the sensitive area; or the minimum interval between the orthographic projection of the preset circuit on the fourth layer and the sensitive area does not exceed 0.8 mm.

[0009] For the electronic device provided by the embodiment of the present application, when the orthographic projection of the preset circuit on the fourth layer at least partially overlaps with the sensitive area, or the minimum interval between the orthographic projection of the preset circuit on the fourth layer and the sensitive area does not exceed 0.8 mm, in order to avoid the preset circuit from interfering with the sensitive circuit and / or the sensitive device corresponding to the sensitive area, by making the distance between the first layer and the second layer less than the distance between the second layer and the third layer, the preset circuit uses the first ground copper foil as the main reference ground instead of using the second ground copper foil as the main reference ground, so that the sensitive circuit and / or the sensitive device corresponding to the sensitive area will not be interfered by the preset circuit when using the second ground copper foil as the reference ground, and further avoid the common ground interference caused by the interference source signal circuit and / or the power supply circuit on the second layer to the sensitive circuit and / or the sensitive device corresponding to the sensitive area on the fourth layer.

[0010] In addition, since the first layer of the present application has a first grounding copper foil and the orthographic projection of the preset circuit on the first layer is located on the first grounding copper foil, when electronic components are arranged on the side of the first layer away from the second layer, the preset circuit will not interfere with the electronic components arranged on the side of the first layer away from the second layer. At the same time, the present application can also arrange electronic components on the side of the fourth layer away from the third layer. In this way, since the present application can arrange electronic components on the side of the first layer away from the second layer and also on the side of the fourth layer away from the third layer, even when the sum of the orthographic projection areas of all the electronic components on the fourth layer is relatively large, there is no need to increase the area of the circuit board or the number of layers of the circuit board. Since the area of the circuit board is roughly proportional to its price and the number of layers of the circuit board is also roughly proportional to its price, when there is no need to increase the area of the circuit board or the number of layers of the circuit board, the manufacturing cost of the circuit board can be reduced. In addition, in actual products, since the size of the circuit board is also restricted by various factors such as structure, appearance, and stacking, resulting in the inability to change the size of the circuit board, and the product pricing of the electronic device also restricts the number of layers of the circuit board. Therefore, when using the electronic device provided by the present application, the limitations of the prior art can be broken through to achieve the maximum performance at the lowest cost (i.e., without increasing the area of the circuit board or the number of layers of the circuit board). Description of the Drawings

[0011] Figure 1 A cross-sectional view of a circuit board in an electronic device provided by some embodiments of the present application;

[0012] Figure 2 A partial cross-sectional view of the fourth layer of a circuit board in an electronic device provided by some embodiments of the present application;

[0013] Figure 3 A schematic structural diagram of a partial circuit structure of a circuit board in an electronic device provided by some embodiments of the present application;

[0014] Figure 4 A schematic diagram of the voltage waveform at the output end of an audio amplifier;

[0015] Figure 5 A schematic diagram of the voltage waveform of a 25 MHz clock circuit provided by some embodiments of the present application;

[0016] Figure 6 Another cross-sectional view of an electronic device provided by some embodiments of the present application;

[0017] Figure 7 A top view of the first layer provided by some embodiments of the present application;

[0018] Figure 8 A schematic diagram of the return current of each layer of the circuit board in an electronic device provided by some embodiments of the present application;

[0019] Figure 9 A partial cross-sectional view of a circuit board in an electronic device provided for some embodiments of the present application;

[0020] Figure 10 Another partial cross-sectional view of a circuit board in an electronic device provided for some embodiments of the present application;

[0021] Figure 11 An electric field schematic diagram of each layer of circuits on a circuit board in an electronic device provided for some embodiments of the present application;

[0022] Figure 12 A top view of a circuit board in an electronic device provided for some embodiments of the present application. Detailed implementation manners

[0023] As can be known from the background art, in an existing four-layer circuit board, a sensitive area is mostly provided on the first layer. At the same time, interference source signal lines and / or power supply lines are mostly provided near the sensitive area, which easily causes the sensitive lines and / or sensitive devices corresponding to the sensitive area to be subjected to common ground interference from the interference source signal lines and / or power supply lines, resulting in deterioration of the indicators of the sensitive lines and / or sensitive devices corresponding to the sensitive area.

[0024] To solve the above problems, the inventors of the present application designed an electronic device including a circuit board; the circuit board is provided with a first layer having a first ground copper foil, a second layer having a preset circuit, a third layer having a second ground copper foil, and a fourth layer provided with a sensitive area, which are stacked in sequence; the distance between the first layer and the second layer is less than the distance between the second layer and the third layer; the preset circuit is a signal line and / or a power supply line; the orthographic projection of the preset circuit on the first layer is located on the first ground copper foil; the sensitive area includes the area where the sensitive line provided on the fourth layer is located, and / or the projection area of the sensitive device provided on the fourth layer on the fourth layer; the orthographic projection of the sensitive area on the third layer is located on the second ground copper foil; wherein, the orthographic projection of the preset circuit on the fourth layer at least partially overlaps with the sensitive area; or the minimum distance between the orthographic projection of the preset circuit on the fourth layer and the sensitive area does not exceed 0.8 mm.

[0025] When using the circuit board designed by the inventor of the present application, when the orthographic projection of the preset line on the fourth layer at least partially overlaps with the sensitive area, or the minimum distance between the orthographic projection of the preset line on the fourth layer and the sensitive area does not exceed 0.8 mm, in order to avoid the preset line from interfering with the sensitive line and / or sensitive device corresponding to the sensitive area, the distance between the first layer and the second layer is made smaller than the distance between the second layer and the third layer, so that the preset line uses the first grounding copper foil as the main reference ground instead of the second grounding copper foil as the main reference ground. As a result, when the sensitive line and / or sensitive device corresponding to the sensitive area uses the second grounding copper foil as the reference ground, it will not be interfered by the preset line, thereby avoiding the common ground interference caused by the interference source signal line and / or power supply line on the second layer to the sensitive line and / or sensitive device corresponding to the sensitive area on the fourth layer.

[0026] In addition, since the first layer of the present application has a first grounding copper foil and the orthographic projection of the preset line on the first layer is located on the first grounding copper foil, when setting electronic components on the side of the first layer away from the second layer, the preset line will not interfere with the electronic components set on the side of the first layer away from the second layer; at the same time, the present application can also set electronic components on the side of the fourth layer away from the third layer. In this way, since the present application can set electronic components on the side of the first layer away from the second layer and can also set electronic components on the side of the fourth layer away from the third layer, even when the sum of the orthographic projection areas of all electronic components on the fourth layer is relatively large, there is no need to increase the area of the circuit board or increase the number of layers of the circuit board; since the area of the circuit board is roughly proportional to its price and the number of layers of the circuit board is also roughly proportional to its price, when there is no need to increase the area of the circuit board or increase the number of layers of the circuit board, the manufacturing cost of the circuit board can be reduced. In addition, in actual products, since the size of the circuit board is also restricted by various factors such as structure, appearance, and stacking, resulting in the inability to change the size of the circuit board, and the product pricing of the electronic device also restricts the number of layers of the circuit board, when using the electronic device provided by the present application, the limitations of the prior art can be broken through to achieve the maximum performance at the lowest cost (that is, without increasing the area of the circuit board or increasing the number of layers of the circuit board).

[0027] Among them, the above-mentioned electronic device can be applied to various medical devices, industrial devices, and mining devices, and is particularly suitable for communication devices such as electric bicycle drivers, electric motorcycle drivers, vehicle-mounted devices, mobile phones, and dash cams. The embodiment of the present application takes the network device applied in an electric bicycle driver as an example for illustration.

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the following will elaborate on the various embodiments of this application in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in the various embodiments of this application, many technical details are presented to help readers better understand this application. Nevertheless, based on the various changes and modifications of the following embodiments, the technical solutions claimed in this application can also be achieved.

[0029] Referring to Figures 1 to 3 , some embodiments of this application provide an electronic device, including a circuit board 100; the circuit board 100 is provided with a first layer 110 having a first ground copper foil 111, a second layer 120 having a preset circuit 121, a third layer 130 having a second ground copper foil 131, and a fourth layer 140 having a sensitive area 707, which are stacked in sequence; the distance between the first layer 110 and the second layer 120 is less than the distance between the second layer 120 and the third layer 130; the preset circuit 121 is a signal circuit 129 and / or a power supply circuit 124; the orthographic projection of the preset circuit 121 on the first layer 110 is located on the first ground copper foil 111; the sensitive area 707 includes the area where the sensitive circuit 141 is disposed on the fourth layer 140, and / or the projection area on the fourth layer 140 of the sensitive device 706 (such as: Figure 2 and Figure 3 the radio frequency matching components 321, 322, and 323 in are all sensitive devices 706) on the fourth layer 140; the orthographic projection of the sensitive area 707 on the third layer 130 is located on the second ground copper foil 131; wherein, the orthographic projection of the preset circuit 121 on the fourth layer 140 at least partially overlaps with the sensitive area 707; or the minimum distance between the orthographic projection of the preset circuit 121 on the fourth layer 140 and the sensitive area 707 does not exceed 0.8 mm.

[0030] The preset circuit 121 (disposed on the second layer 120) is a circuit that can generate strong interference, while the sensitive circuit 141 is a circuit that is easily interfered with. Continuing to refer to Figures 1 to 3 , and simultaneously referring to Figure 4, since the peak-to-peak value of the signal on the audio amplifier output line 122 is relatively high (for example, the peak-to-peak value at the output of a certain type of class D power amplifier is as high as 8V, and there is a very large spike overshoot on the rising edge of the square wave, and there is also a relatively large back groove on the falling edge of the square wave), the audio amplifier output line 122 is a line that can generate strong interference; since the clock line 123 will generate strong overshoots on the rising and falling edges, the clock line 123 is a line that can generate strong interference; the power supply line 124 is a low-frequency and large-dynamic interference source; in summary, the clock line 123, the audio amplifier output line 122, and the power supply line 124 all belong to the preset line 121. When the sensitive line 141 that is easily interfered with overlaps with the projection of the preset line 121 on the fourth layer 140 or the minimum spacing does not exceed 0.8mm and they share the same ground, the preset line 121 will interfere with the sensitive line 141.

[0031] In some embodiments, the sensitive line 141 includes at least one of a radio frequency line, an audio microphone line, an audio line, a phase-locked loop line, an analog sampling line, an analog operational amplifier line, an image sensor line, a pyroelectric infrared sensing line, a thermosensitive line, a photosensitive line, a gas-sensitive line, a force-sensitive line, a magnetic-sensitive line, a humidity-sensitive line, a taste-sensitive line, a radiation-sensitive line, a color-sensitive line, a sound-sensitive line, and an optoelectronic converter line.

[0032] Specifically, in one example, the radio frequency line 158, the pads of the radio frequency matching components 322 for transmitting radio frequency signals ( Figure 2 and Figure 3 not labeled), the radio frequency line 188, the pads of the radio frequency matching components 323 for transmitting radio frequency signals ( Figure 2 and Figure 3 not labeled), the radio frequency line 199, the pads of the radio frequency matching components 321 for transmitting radio frequency signals ( Figure 2 and Figure 3 not labeled), and the radio frequency line 142 provided on the fourth layer 140 all belong to the sensitive line 141.

[0033] In some embodiments, the sensitive device 706 includes at least one of a phase-locked loop element, an analog sampling element, a radio frequency element, an analog operational amplifier element, an audio microphone, a radio frequency device, an audio element, an image sensor, a pyroelectric infrared sensing element, a thermosensitive element, a photosensitive element, a gas-sensitive element, a force-sensitive element, a magnetic-sensitive element, a humidity-sensitive element, a sound-sensitive element, a radiation-sensitive element, an optoelectronic converter element, a color-sensitive element, and a taste-sensitive element provided on the fourth layer 140.

[0034] Specifically, in one example, the radio frequency matching components 321, 322, and 323 provided on the fourth layer 140 all belong to the sensitive device 706.

[0035] In some embodiments, the lines led out by the sensor device 706 (such as radio frequency lines, audio microphone lines, audio lines, phase-locked loop lines, analog sampling lines, analog operational amplifier lines, image sensor lines, pyroelectric infrared sensing lines, thermosensitive lines, photosensitive lines, gas-sensitive lines, force-sensitive lines, magnetosensitive lines, humidity-sensitive lines, taste-sensitive lines, radiation-sensitive lines, color-sensitive lines, sound-sensitive lines, optoelectronic converter lines) belong to the sensitive lines 141. When the projections of these sensitive lines 141 and the preset lines 121 (which belong to strong interference lines) on the fourth layer 140 overlap or the minimum interval does not exceed 0.8 mm and they share the same ground, the sensitive lines 141 are likely to be interfered by the preset lines 121, resulting in abnormal functions.

[0036] If the preset lines 121 are arranged on the second layer 120, the sensor device 706 can also be arranged on the first layer 110, and the sensitive lines 141 can be arranged on the fourth layer 140. That is, the sensor device 706 can be arranged on either the first layer 110 or the fourth layer 140, but the sensitive lines 141 are arranged on the fourth layer 140. The radio frequency line is both a sensitive line 141, but it is also an interference source line relative to the audio microphone line (one of the sensitive lines 141), because the radio frequency line is likely to interfere with the audio microphone line, resulting in an increase in the microphone signal background noise and abnormal operation. If the radio frequency line is arranged on the second layer 120 and the audio microphone line is arranged on the fourth layer 140, then the audio microphone line belongs to the sensitive lines 141, and the radio frequency line is the preset line 121 (interference source line).

[0037] Regarding the clock line 123, further refer to Figure 5, the period of the 25MHz clock line 123 is 40ns, the peak-to-peak value of the 25MHz clock line 123 reaches 3.4V, the maximum amplitude reaches 2.56V, and the minimum amplitude reaches -640mV. Therefore, the 25MHz clock line 123 belongs to the preset line 121. Among them, the maximum amplitude of the overshoot 500 of the clock signal in the preset line 121 reaches 2.56V, the minimum amplitude of the undershoot 502 of the clock signal in the preset line 121 reaches -640mV, and 501 is the ringing of the clock signal in the preset line 121. The clock signal in the preset line 121 belongs to a high-speed signal. The higher the transmission rate (i.e., the operating frequency) of the clock signal in the preset line 121, the faster the signal mutation speed, the stronger the EMI radiation generated outside the circuit board 100, and the stronger the interference to the sensitive line 141 inside the circuit board 100, which easily causes the sensitive line 141 to work abnormally. The steeper the rising edge of the clock signal in the preset line 121, the higher the overshoot 500 generated in the preset line 121, the faster the signal mutation speed, the stronger the EMI radiation generated outside the circuit board 100, and the stronger the interference to the sensitive line 141 inside the circuit board 100, which easily causes the sensitive line 141 to work abnormally. The ringing 501 in the clock signal of the preset line 121 is equivalent to multiple harmonics of the frequency doubling of the clock signal. The amplitude of the ringing 501 will also strongly interfere with the sensitive line 141 inside the circuit board 100, which easily causes the sensitive line 141 to work abnormally.

[0038] Since the first layer 110 has the first ground copper foil 111, the orthographic projection of the preset line 121 on the first layer 110 is located on the first ground copper foil 111, and the distance between the first layer 110 and the second layer 120 is less than the distance between the second layer 120 and the third layer 130. Therefore, even though the third layer 130 has the second ground copper foil 131, the preset line 121 still uses the first ground copper foil 111 of the first layer 110 as the main reference ground.

[0039] Since the orthographic projection of the structure corresponding to the sensitive area 707 (i.e., the sensitive line 141 or the sensitive device 706, where the sensitive device 706 such as the radio frequency matching components 321, 322, 323, etc., are all connected to the sensitive line 141) on the third layer 130 is located on the second ground copper foil 131, the structure corresponding to the sensitive area 707 uses the second ground copper foil 131 of the third layer 130 as the reference ground.

[0040] Precisely because the preset line 121 still uses the first grounding copper foil 111 of the first layer 110 as the main reference ground, while the structure corresponding to the sensitive area 707 uses the second grounding copper foil 131 of the third layer 130 as the reference ground, interference from the preset line 121 to the structure corresponding to the sensitive area 707 can be avoided. That is, when the structure corresponding to the sensitive area 707 transmits sensitive signals (e.g., the sensitive line 141 transmits radio frequency signals), there is no problem of cross-segmentation or interference caused by adjacent / crossed lines between the second layer 120 and the fourth layer 140.

[0041] It should be noted that in some embodiments, the first layer 110 may also be provided with other circuit structures in addition to the first grounding copper foil 111, the second layer 120 may also be provided with other circuit structures in addition to the preset line 121, the third layer 130 may also be provided with other circuit structures in addition to the second grounding copper foil 131, and the fourth layer 140 may also be provided with other circuit structures in addition to the sensitive line 141. The present application does not limit this.

[0042] In some embodiments, the minimum distance between the positive projection of the preset line 121 on the fourth layer 140 and the sensitive area 707 does not exceed 0.4 mm. In this case, interference from the preset line 121 to the structure corresponding to the sensitive area 707 can also be avoided.

[0043] Continue to refer to Figures 1 to 3 and at the same time refer to Figure 6 In some embodiments, the distance between the first layer 110 and the second layer 120 is the first distance H1; the distance between the second layer 120 and the third layer 130 is the second distance H2; the second distance H2 is more than 1.5 times the first distance H1. In this way, it can be further ensured that the preset line 121 uses the first grounding copper foil 111 of the first layer 110 as the main reference ground, thereby avoiding interference from the preset line 121 to the structure corresponding to the sensitive area 707.

[0044] In some embodiments, the electronic device further includes: a GPS antenna 200 and a GPS module 300; the circuit board 100 is provided with a through hole 101, one end of the through hole 101 is located in the first layer 110 and the other end is located in the fourth layer 140. The first layer 110 is provided with a first via pad 102 surrounding the end of the through hole 101, and the fourth layer 140 is provided with a second via pad 103 surrounding the end of the through hole 101; the sensitive area 707 includes the area where the sensitive circuit 141 is disposed on the fourth layer 140; the GPS antenna 200 includes a GPS antenna body 210 and a GPS antenna pin 220 connected to the GPS antenna body 210. The GPS antenna body 210 is disposed on the side of the first layer 110 away from the second layer 120. One end of the GPS antenna pin 220 connected to the GPS antenna body 210 is fixed to the first via pad 102. The portion between the two ends of the GPS antenna pin 220 is located in the through hole 101, and the other end of the GPS antenna pin 220 is fixed to the second via pad 103; the GPS module 300 includes a GPS chip 310 and peripheral devices. The GPS chip 310 is connected to the second via pad 103 through the peripheral devices and the sensitive circuit 141, and the GPS chip 310 and the peripheral devices ( Figures 1 to 6 are not labeled) are both located on the side of the fourth layer 140 away from the third layer 130. Among them, the peripheral devices may be crystal oscillators, RF matching components, RF filters, etc.

[0045] Since the second ground copper foil 131 is disposed on the third layer 130, the preset circuit 121 can be separated from the sensitive circuit 141 through the second ground copper foil 131, that is, the signal circuit 129 and / or the power supply circuit 124 disposed on the second layer 120 is separated from the RF circuit 142 and the RF pads disposed on the fourth layer 140 through the second ground copper foil 131. Among them, the number of RF pads is multiple, and the multiple RF pads are respectively used to fix the various electronic components of the GPS module 300 (such as: GPS chip 310, crystal oscillator, RF matching component, RF filter, etc.).

[0046] Specifically, since the distance between the first layer 110 and the second layer 120 is less than the distance between the second layer 120 and the third layer 130, the preset circuit 121 takes the first ground copper foil 111 of the first layer 110 as the main return ground and the second ground copper foil 131 of the third layer 130 as the secondary return ground. Thus, the electric field and the return magnetic field generated by taking the second ground copper foil 131 of the third layer 130 as the reference ground for the preset circuit 121 have less influence on the sensitive circuit 141, thereby avoiding the interference of the preset circuit 121 on the sensitive circuit 141 and the various electronic components of the GPS module 300 (such as: GPS chip 310, crystal oscillator, RF matching component, RF filter, etc.) connected to the sensitive circuit 141.

[0047] In some embodiments, the signal line 129 is a line of the GPS module 300, and the power line 124 is the power line 124 of the GPS module 300. It should be noted that the signal line 129 can also be a line of other electronic components, and the power line 124 can also be the power line 124 of other electronic components. The present application does not limit this.

[0048] Continue to refer to Figures 1 to 6 and refer to Figure 7 simultaneously. In some embodiments, the area where the orthographic projection of the GPS antenna body 210 on the first layer 110 is located is the first area 703; the first ground copper foil 111 includes a first ground copper foil 112 disposed within the first area 703 and surrounding the first via pad 102, and there is a spacing between the first ground copper foil 112 and the first via pad 102. In this way, the GPS antenna body 210 can form a positive oscillator of the GPS antenna, and the first ground copper foil 112 can form an electric field with the GPS antenna 200, so that the first ground copper foil 112 forms a negative oscillator of the GPS antenna.

[0049] In some embodiments, a complete ground copper foil is provided on the orthographic projection area of the GPS antenna body 210 on the first layer 110 (i.e., the first area 703) (that is, the ground copper foil on the first layer 110 completely covers the GPS antenna body 210). The peripheral devices of the GPS antenna 200 include a first radio frequency matching component 321, a second radio frequency matching component 322, and a third radio frequency matching component 323; an audio amplifier output line 122, an audio amplifier output line 166, a clock line 123, and a power line 124 are provided on the orthographic projection of the first area 703 on the second layer 120; a radio frequency line 142, a radio frequency line 199, a radio frequency line 188, a radio frequency line 158 (at this time, the radio frequency lines 142, 199, 188, and 158 are all GPS radio frequency lines), and a radio frequency matching component 321 are provided on the orthographic projection of the first area 703 on the fourth layer 140. One end of the radio frequency matching component 323 is connected to the ground copper foil 143 of the fourth layer 140, and the other end is connected to both the radio frequency matching component 321 and the radio frequency matching component 322. One end of the radio frequency line 142 is connected to the second via pad 103, and the other end is connected to the radio frequency matching component 321. One end of the radio frequency line 158 is connected to the radio frequency matching component 322, and the other end of the radio frequency line 158 is connected to the GPS chip 310. One end of the radio frequency line 199 is connected to the radio frequency matching component 323, and the other end of the radio frequency line 199 is connected to the radio frequency matching component 321. One end of the radio frequency line 188 is connected to the radio frequency matching component 323, and the other end of the radio frequency line 188 is connected to the radio frequency matching component 323.

[0050] The GPS antenna pin 220 is inserted into the through-hole 101 in the circuit board 100 and soldered to the second through-hole pad 103 on the fourth layer 140 of the circuit board 100, so as to fix the GPS antenna 200 on the circuit board 100. When the GPS antenna body 210 receives a signal, it can be transmitted to the GPS chip 310 through the GPS antenna pin 220, the second through-hole pad 103, the RF line 142, the first RF matching component 321, the RF line 199, the second RF matching component 322, the RF line 188, the third RF matching component 323, and the RF line 158 and processed by the GPS chip 310.

[0051] At this time, when the orthographic projections of the audio amplifier output line 122, the audio amplifier output line 166, the clock line 123, and the power supply line 124 on the fourth layer 140 overlap at least partially with the RF line 142, or the minimum distance between the orthographic projections of the audio amplifier output line 122, the audio amplifier output line 166, the clock line 123, and the power supply line 124 on the fourth layer 140 and the RF line 142 does not exceed 0.8 mm, since the distance between the first layer 110 and the second layer 120 is less than the distance between the second layer 120 and the third layer 130, the audio amplifier output line 122, the audio amplifier output line 166, the clock line 123, and the power supply line 124 can refer to the first ground copper foil 111 as the main reference ground, thus avoiding interference to the RF line 142 caused by the audio amplifier output line 122, the audio amplifier output line 166, the clock line 123, and the power supply line 124.

[0052] In some embodiments, taking the board thickness H5 of the circuit board 100 as 1.2 mm (1.2 mm is approximately equal to 47.244 mil) as an example for illustration, the distance H1 between the first layer 110 and the second layer 120 is 4 mil (i.e., the thickness of the insulating layer between the first layer 110 and the second layer 120 is 4 mil), the distance H3 between the third layer 130 and the fourth layer 140 is 4 mil (i.e., the thickness of the insulating layer between the third layer 130 and the fourth layer 140 is 4 mil), the thicknesses of the first layer 110, the second layer 120, the third layer 130, and the fourth layer 140 are all 1.2 mil, and the thicknesses of the ink on the first layer 110 and the fourth layer 140 are both 0.4 mil. At this time, the distance between the second layer 120 and the third layer 130 is H2.

[0053] H2 = 47.244 mil - 4 mil - 4 mil - 1.2 mil - 1.2 mil - 1.2 mil - 1.2 mil - 0.4 mil - 0.4 mil = 33.644 mil ≈ 0.85456 mm.

[0054] That is to say, when the board thickness H5 of the circuit board 100 is 1.2 mm, there is a gap of 0.85456 mm (i.e., the distance between the second layer 120 and the third layer 130) between the audio amplifier output line 122, the audio amplifier output line 166, the clock line 123, and the power supply line 124 of the second layer 120 and the RF line 142 of the fourth layer 140. The distance between the third layer 130 and the fourth layer 140 is only 4 mils (about 0.1 mm). Thus, the influence of the return of the audio amplifier output line 122, the audio amplifier output line 166, the clock line 123, and the power supply line 124 of the second layer 120 on the return of the RF line 142 of the fourth layer 140 can be negligible.

[0055] Specifically, since the distance between the first layer 110 and the second layer 120 is 4 mils (about 0.1 mm), and the distance between the second layer 120 and the third layer 130 is 0.85456 mm, that is, the distance H2 between the second layer 120 and the third layer 130 is 8.5456 times the distance H1 between the first layer 110 and the second layer 120. Therefore, the audio amplifier output line 122, the audio amplifier output line 166, the clock line 123, and the power supply line 124 refer to the first ground copper foil 111 as the main return reference plane, and the audio amplifier output line 122, the audio amplifier output line 166, the clock line 123, and the power supply line 124 refer to the second ground copper foil 131 as the secondary return reference plane. Thus, the audio amplifier output line 122, the audio amplifier output line 166, the clock line 123, and the power supply line 124 will not interfere with the RF line.

[0056] The following takes the example that the clock line 123 and the power supply line 124 will not interfere with the RF line 142 for analysis and explanation:

[0057] Continue to refer to Figures 1 to 7 and simultaneously refer to Figure 8, on the one hand, the clock line 123 generates a return current i1 on the first ground copper foil 111 (i.e., the clock line 123 generates a return current i1 with the opposite direction on the first layer 110), the clock line 123 generates a return current i3 on the second ground copper foil 131 (i.e., the clock line 123 generates a closed-loop return current i3 on the third layer 130), the clock line 123 generates a return magnetic field B1 on the first ground copper foil 111 (i.e., the clock line 123 generates a return magnetic field B1 with the opposite direction on the first layer 110), and the clock line 123 generates a return magnetic field B3 on the second ground copper foil 131 (i.e., the clock line 123 generates a closed-loop return magnetic field B3 on the third layer 130); while the RF line 142 generates a return current i5 on the second ground copper foil 131 (i.e., the RF line 142 generates a return current i5 with the opposite direction on the third layer 130), and the RF line 142 generates a return magnetic field B5 on the second ground copper foil 131 (i.e., the RF line 142 generates a closed-loop return magnetic field B5 between the second layer 120 and the third layer 130).

[0058] More specifically, taking the clock line 123 walking in a straight line in the horizontal direction on the second layer 120 as an example for illustration, the length of the clock line 123 from point A0 to point B0 in the horizontal direction on the second layer 120 is the first length W1 (such as Figure 9As shown in the figure, the distance from the clock line 123 in the second layer 120 to the first ground copper foil 111 in the first layer 110 is H1, and the return current area of the clock line 123 in the second layer 120 to the first ground copper foil 111 in the first layer 110 is S1 = H1 × W1. The distance from the clock line 123 in the second layer 120 to the second ground copper foil 131 in the third layer 130 is H2, and the return current area of the clock line 123 in the second layer 120 to the second ground copper foil 131 in the third layer 130 is S3 = H2 × W1. According to the magnetic field strength calculation formula: B = Φ / S, the magnetic field B1 generated by the clock line 123 in the second layer 120 to the first ground copper foil 111 in the first layer 110 is B1 = Φ / S1 = Φ / H1 × W1, and the magnetic field B3 generated by the clock line 123 in the second layer 120 to the second ground copper foil 131 in the third layer 130 is B3 = Φ / S3 = Φ / H2 × W1. Since the magnetic flux Φ is a fixed value, then B1 / B3 = (Φ / H1 × W1) / (Φ / H2 × W1) = H2 / H1 = 0.85456mm / 0.1mm = 8.5456. That is, the magnetic field B1 generated by the clock line 123 in the second layer 120 to the first ground copper foil 111 in the first layer 110 is 8.5456 times the magnetic field B3 generated by the clock line 123 in the second layer 120 to the second ground copper foil 131 in the third layer 130. Therefore, the return current generated by the clock line 123 in the second layer 120 is mainly distributed in the first ground copper foil 111, and the return current of the clock line 123 in the second layer 120 distributed on the second ground copper foil 131 is very weak. Therefore, the interference caused by the return current of the clock line 123 in the second layer 120 distributed on the second ground copper foil 131 to the return current of the RF line 142 in the fourth layer 140 distributed on the second ground copper foil 131 can be ignored.

[0059] The power line 124 will generate a return current i2 on the first ground copper foil 111 (that is, the power line 124 will generate a return current i2 with the opposite direction on the first layer 110), and the power line 124 will generate a return current i4 on the second ground copper foil 131 (that is, the power line 124 will generate a return current i4 with the opposite direction on the third layer 130). The power line 124 will generate a return magnetic field B2 on the first ground copper foil 111 (that is, the power line 124 will generate a return magnetic field B2 with the opposite direction on the first layer 110), and the power line 124 will generate a return magnetic field B4 on the second ground copper foil 131 (that is, the power line 124 will generate a return magnetic field B4 with the opposite direction on the third layer 130).

[0060] More specifically, taking the power line 124 walking in a straight line in the horizontal direction of the second layer 120 as an example, the length of the power line 124 in the horizontal direction from point A to point B in the second layer 120 is the first length W2 (such as Figure 10As shown, the distance between the power line 124 in the second layer 120 and the first ground copper foil 111 in the first layer 110 is H1, and the return area of the power line 124 in the second layer 120 to the first ground copper foil 111 in the first layer 110 is S2 = H1 × W2. The distance between the power line 124 in the second layer 120 and the second ground copper foil 131 in the third layer 130 is H2, and the return area of the power line 124 in the second layer 120 to the second ground copper foil 131 in the third layer 130 is S4 = H2 × W2. According to the magnetic field strength calculation formula: B = Φ / S, the magnetic field B2 generated by the power line 124 in the second layer 120 to the first ground copper foil 111 in the first layer 110 is B2 = Φ / S2 = Φ / H1 × W2, and the magnetic field B4 generated by the power line 124 in the second layer 120 to the second ground copper foil 131 in the third layer 130 is B4 = Φ / S4 = Φ / H2 × W2. Since the magnetic flux Φ is a fixed value, we can get B2 / B4 = (Φ / H1 × W2) / (Φ / H2 × W2) = H2 / H1 = 0.85456mm / 0.1mm = 8.5456. That is, the magnetic field B2 generated by the power line 124 in the second layer 120 to the first ground copper foil 111 in the first layer 110 is 8.5456 times the magnetic field B4 generated by the power line 124 in the second layer 120 to the second ground copper foil 131 in the third layer 130. Therefore, the return current generated by the power line 124 in the second layer 120 is mainly distributed in the first ground copper foil 111, and the return current of the power line 124 in the second layer 120 distributed on the second ground copper foil 131 is very weak. Therefore, the interference generated by the return current of the power line 124 in the second layer 120 distributed on the second ground copper foil 131 to the return current of the RF line 142 in the fourth layer 140 distributed on the second ground copper foil 131 can be ignored.

[0061] Continue to refer to Figures 1 to 8 , and at the same time refer to Figure 11 , on the other hand, the clock line 123 will generate an electric field E1 on the first ground copper foil 111 (that is, the clock line 123 will generate an electric field E1 on the first layer 110), and the clock line 123 will generate an electric field E3 on the second ground copper foil 131 (that is, the clock line 123 will generate an electric field E3 on the third layer 130).

[0062] More specifically, according to the electric field strength calculation formula: E = U / d, where d is the distance between two layers (H1, H2). The electric field E1 generated by the clock line 123 on the first grounding copper foil 111 is E1 = U / d = U / H1; the electric field E3 generated by the clock line 123 on the second grounding copper foil 131 is E3 = U / d = U / H2. At this time, E1 / E3 = (U / H1) / (U / H2) = H2 / H1 = 0.85456mm / 0.1mm = 8.5456 times, that is, the electric field E1 generated by the clock line 123 on the first grounding copper foil 111 is 8.5456 times that of the electric field E3 generated by the clock line 123 on the second grounding copper foil 131. Therefore, the electric field generated by the clock line 123 on the first grounding copper foil 111 is mainly distributed in the first grounding copper foil 111, and the electric field of the clock line 123 in the second layer 120 distributed on the second grounding copper foil 131 is very weak. Therefore, the interference caused by the electric field of the clock line 123 in the second layer 120 distributed on the second grounding copper foil 131 to the RF line 142 in the fourth layer 140 can be ignored.

[0063] The power line 124 will generate an electric field E2 on the first grounding copper foil 111 (that is, the power line 124 will generate an electric field E2 on the first layer 110), and the power line 124 will generate an electric field E4 on the second grounding copper foil 131 (that is, the power line 124 will generate an electric field E4 on the third layer 130).

[0064] More specifically, according to the electric field strength calculation formula: E = U / d, where d is the distance between two layers (H1, H2). The electric field E2 generated by the power line 124 on the first grounding copper foil 111 is E2 = U / d = U / H1; the electric field E4 generated by the power line 124 on the second grounding copper foil 131 is E4 = U / d = U / H2. At this time, E2 / E4 = (U / H1) / (U / H2) = H2 / H1 = 0.85456mm / 0.1mm = 8.5456 times, that is, the electric field E2 generated by the power line 124 on the first grounding copper foil 111 is 8.5456 times that of the electric field E4 generated by the power line 124 on the second grounding copper foil 131. Therefore, the electric field generated by the power line 124 on the first grounding copper foil 111 is mainly distributed in the first grounding copper foil 111, and the electric field of the power line 124 in the second layer 120 distributed on the second grounding copper foil 131 is very weak. Therefore, the interference caused by the electric field of the power line 124 in the second layer 120 distributed on the second grounding copper foil 131 to the RF line 142 in the fourth layer 140 can be ignored.

[0065] Continue to refer to Figures 1 to 11, in another embodiment, taking the board thickness H5 of the circuit board 100 as 1.6 mm (1.6 mm is approximately equal to 62.992 mil) as an example for illustration, the spacing between the first layer 110 and the second layer 120 is 4 mil (that is, the thickness of the insulating layer between the first layer 110 and the second layer 120 is 4 mil), the spacing between the third layer 130 and the fourth layer 140 is 4 mil (that is, the thickness of the insulating layer between the third layer 130 and the fourth layer 140 is 4 mil), the thicknesses of the first layer 110, the second layer 120, the third layer 130, and the fourth layer 140 are all 1.2 mil, and the thicknesses of the ink on the first layer 110 and the fourth layer 140 are both 0.4 mil. At this time, the spacing between the second layer 120 and the third layer 130 is H2.

[0066] H2 = 47.244 mil - 4 mil - 4 mil - 1.2 mil - 1.2 mil - 1.2 mil - 1.2 mil - 0.4 mil - 0.4 mil = 49.392 mil ≈ 1.25456 mm.

[0067] That is to say, when the board thickness H5 of the circuit board 100 is 1.6 mm, there is a 1.25456 mm gap (that is, the spacing between the second layer 120 and the third layer 130) between the audio amplifier output line 122, the audio amplifier output line 166, the clock line 123, and the power line 124 on the second layer 120 and the RF line 142 on the fourth layer 140, while the spacing between the third layer 130 and the fourth layer 140 is only 4 mil (about 0.1 mm). Thus, the influence of the audio amplifier output line 122, the audio amplifier output line 166, the clock line 123, and the power line 124 on the second layer 120 on the RF line 142 on the fourth layer 140 can be ignored.

[0068] Specifically, since the spacing between the first layer 110 and the second layer 120 is 4 mil (about 0.1 mm), and the spacing between the second layer 120 and the third layer 130 is 1.25456 mm, that is, the spacing H2 between the second layer 120 and the third layer 130 is 12.5456 times the spacing H1 between the first layer 110 and the second layer 120. Therefore, the audio amplifier output line 122, the audio amplifier output line 166, the clock line 123, and the power line 124 refer to the first ground copper foil 111 as the main reference plane for return, and the audio amplifier output line 122, the audio amplifier output line 166, the clock line 123, and the power line 124 refer to the second ground copper foil 131 as the secondary reference plane for return. Thus, the audio amplifier output line 122, the audio amplifier output line 166, the clock line 123, and the power line 124 will not cause interference to the RF line 142.

[0069] The following takes the example that the clock line 123 and the power line 124 will not cause interference to the RF line 142 for analysis and explanation:

[0070] Continue to refer to Figure 8 , on the one hand, the clock line 123 will generate a return current i1 on the first ground copper foil 111 (that is, the clock line 123 will generate a return current i1 with the opposite direction on the first layer 110), the clock line 123 will generate a return current i3 on the second ground copper foil 131 (that is, the clock line 123 will generate a closed-loop return current i3 on the third layer 130), the clock line 123 will generate a return magnetic field B1 on the first ground copper foil 111 (that is, the clock line 123 will generate a return magnetic field B1 with the opposite direction on the first layer 110), and the clock line 123 will generate a return magnetic field B3 on the second ground copper foil 131 (that is, the clock line 123 will generate a closed-loop return magnetic field B3 on the third layer 130); while the RF line 142 will generate a return current i5 on the second ground copper foil 131 (that is, the RF line 142 will generate a return current i5 with the opposite direction on the third layer 130), and the RF line 142 will generate a return magnetic field B5 on the second ground copper foil 131 (that is, the RF line 142 will generate a closed-loop return magnetic field B5 on the third layer 130).

[0071] More specifically, taking the example that the clock line 123 moves in a straight line in the horizontal direction on the second layer 120, the length of the clock line 123 from point A0 to point B0 in the horizontal direction on the second layer 120 is the first length W1 (such as Figure 9As shown in the figure, the distance between the clock line 123 in the second layer 120 and the first ground copper foil 111 in the first layer 110 is H1, and the return area of the clock line 123 in the second layer 120 to the first ground copper foil 111 in the first layer 110 is S1 = H1 × W1. The distance between the clock line 123 in the second layer 120 and the second ground copper foil 131 in the third layer 130 is H2, and the return area of the clock line 123 in the second layer 120 to the second ground copper foil 131 in the third layer 130 is S3 = H2 × W1. According to the magnetic field strength calculation formula: B = Φ / S, the magnetic field B1 generated by the clock line 123 in the second layer 120 to the first ground copper foil 111 in the first layer 110 is B1 = Φ / S1 = Φ / H1 × W1, and the magnetic field B3 generated by the clock line 123 in the second layer 120 to the second ground copper foil 131 in the third layer 130 is B3 = Φ / S3 = Φ / H2 × W1. Since the magnetic flux Φ is a fixed value, we can get B1 / B3 = (Φ / H1 × W1) / (Φ / H2 × W1) = H2 / H1 = 1.25456mm / 0.1mm = 12.5456. That is, the magnetic field B1 generated by the clock line 123 in the second layer 120 to the first ground copper foil 111 in the first layer 110 is 12.5456 times the magnetic field B3 generated by the clock line 123 in the second layer 120 to the second ground copper foil 131 in the third layer 130. Therefore, the return current generated by the clock line 123 in the second layer 120 is mainly distributed in the first ground copper foil 111, and the return current of the clock line 123 in the second layer 120 distributed on the second ground copper foil 131 is very weak. Therefore, the interference caused by the return current of the clock line 123 in the second layer 120 distributed on the second ground copper foil 131 to the return current of the RF line 142 in the fourth layer 140 distributed on the second ground copper foil 131 can be ignored.

[0072] The power supply line 124 will generate a return current i2 on the first ground copper foil 111 (that is, the power supply line 124 will generate a return current i2 with the opposite direction on the first layer 110), and the power supply line 124 will generate a return current i4 on the second ground copper foil 131 (that is, the power supply line 124 will generate a return current i4 with the opposite direction on the third layer 130). The power supply line 124 will generate a return magnetic field B2 on the first ground copper foil 111 (that is, the power supply line 124 will generate a return magnetic field B2 with the opposite direction on the first layer 110), and the power supply line 124 will generate a return magnetic field B4 on the second ground copper foil 131 (that is, the power supply line 124 will generate a return magnetic field B4 with the opposite direction on the third layer 130).

[0073] More specifically, taking the power supply line 124 walking in a straight line in the horizontal direction of the second layer 120 as an example, the length of the power supply line 124 from point A to point B in the horizontal direction in the second layer 120 is the first length W2 (such asFigure 10 As shown, the distance between the power line 124 in the second layer 120 and the first ground copper foil 111 in the first layer 110 is H1, and the return current area of the power line 124 in the second layer 120 to the first ground copper foil 111 in the first layer 110 is S2 = H1×W2. The distance between the power line 124 in the second layer 120 and the second ground copper foil 131 in the third layer 130 is H2, and the return current area of the power line 124 in the second layer 120 to the second ground copper foil 131 in the third layer 130 is S4 = H2×W2. According to the magnetic field strength calculation formula: B = Φ / S, the magnetic field B2 generated by the power line 124 in the second layer 120 to the first ground copper foil 111 in the first layer 110 is B2 = Φ / S2 = Φ / H1×W2, and the magnetic field B4 generated by the power line 124 in the second layer 120 to the second ground copper foil 131 in the third layer 130 is B4 = Φ / S4 = Φ / H2×W2. Since the magnetic flux Φ is a fixed value, we can get B2 / B4 = (Φ / H1×W2) / (Φ / H2×W2) = H2 / H1 = 1.25456mm / 0.1mm = 12.5456. That is, the magnetic field B2 generated by the power line 124 in the second layer 120 to the first ground copper foil 111 in the first layer 110 is 12.5456 times the magnetic field B4 generated by the power line 124 in the second layer 120 to the second ground copper foil 131 in the third layer 130. Therefore, the return current generated by the power line 124 in the second layer 120 is mainly distributed in the first ground copper foil 111, and the return current of the power line 124 in the second layer 120 distributed on the second ground copper foil 131 is very weak. Therefore, the interference caused by the return current of the power line 124 in the second layer 120 distributed on the second ground copper foil 131 to the return current of the RF line 142 in the fourth layer 140 distributed on the second ground copper foil 131 can be ignored.

[0074] Continue to refer to Figure 11 On the other hand, the clock line 123 will generate an electric field E1 on the first ground copper foil 111 (i.e., the clock line 123 will generate an electric field E1 on the first layer 110), and the clock line 123 will generate an electric field E3 on the second ground copper foil 131 (i.e., the clock line 123 will generate an electric field E3 on the third layer 130). The RF line 142 will generate an electric field E5 on the second ground copper foil 131 (i.e., the RF line 142 will generate an electric field E5 on the third layer 130).

[0075] More specifically, according to the electric field strength calculation formula: E = U / d, where d is the distance between the two layers (H1, H2). The electric field E1 generated by the clock line 123 on the first ground copper foil 111 is E1 = U / d = U / H1; the electric field E3 generated by the clock line 123 on the second ground copper foil 131 is E3 = U / d = U / H2. At this time, E1 / E3 = (U / H1) / (U / H2) = H2 / H1 = 1.25456 mm / 0.1 mm = 12.5456 times, that is, the electric field E1 generated by the clock line 123 on the first ground copper foil 111 is 12.5456 times that of the electric field E3 generated by the clock line 123 on the second ground copper foil 131. Therefore, the electric field generated by the clock line 123 on the first ground copper foil 111 is mainly distributed in the first ground copper foil 111, and the electric field of the clock line 123 in the second layer 120 distributed on the second ground copper foil 131 is very weak. Therefore, the interference caused by the electric field of the clock line 123 in the second layer 120 distributed on the second ground copper foil 131 to the RF line 142 in the fourth layer 140 can be ignored.

[0076] The power line 124 will generate an electric field E2 on the first ground copper foil 111 (that is, the power line 124 will generate an electric field E2 on the first layer 110), and the power line 124 will generate an electric field E4 on the second ground copper foil 131 (that is, the power line 124 will generate an electric field E4 on the third layer 130).

[0077] More specifically, according to the electric field strength calculation formula: E = U / d, where d is the distance between the two layers (H1, H2). The electric field E2 generated by the power line 124 on the first ground copper foil 111 is E2 = U / d = U / H1; the electric field E4 generated by the power line 124 on the second ground copper foil 131 is E4 = U / d = U / H2. At this time, E2 / E4 = (U / H1) / (U / H2) = H2 / H1 = 1.25456 mm / 0.1 mm = 12.5456 times, that is, the electric field E2 generated by the power line 124 on the first ground copper foil 111 is 12.5456 times that of the electric field E4 generated by the power line 124 on the second ground copper foil 131. Therefore, the electric field generated by the power line 124 on the first ground copper foil 111 is mainly distributed in the first ground copper foil 111, and the electric field of the power line 124 in the second layer 120 distributed on the second ground copper foil 131 is very weak. Therefore, the interference caused by the electric field of the power line 124 in the second layer 120 distributed on the second ground copper foil 131 to the RF line 142 in the fourth layer 140 can be ignored.

[0078] It can be seen that the greater the magnification relationship between the distance H2 between the second layer 120 and the third layer 130 and the distance H1 between the first layer 110 and the second layer 120, the less interference the preset circuit 121 of the second layer 120 causes to the sensitive circuit 141 of the fourth layer 140.

[0079] In some embodiments, the distance H2 between the second layer 120 and the third layer 130 is more than eight times the distance H1 between the first layer 110 and the second layer 120. The thickness of the four-layer circuit board is mostly 1.2 mm or 1.6 mm. From the above, it can be seen that for a 1.2-mm or 1.6-mm four-layer circuit board, the distance H2 between the second layer 120 and the third layer 130 can be more than eight times the distance H1 between the first layer 110 and the second layer 120, which can further avoid the preset circuit 121 of the second layer 120 from interfering with the sensitive circuit 141 of the fourth layer 140.

[0080] Continue to refer to Figures 1 to 6 and at the same time refer to Figure 12 In some embodiments, a ground hole 150 is provided in the projection area of the GPS antenna body 210 on the circuit board 100; the ground hole 150 is connected to the first ground copper foil 111 of the first layer 110, the second ground copper foil 131 of the third layer 130, the ground copper foil 125 of the second layer 120, and the ground copper foil 302 of the fourth layer 140. The ground copper foil 302 of the fourth layer 140 is connected to the ground pin of the GPS chip 310. In some embodiments, the number of ground holes 150 is greater than or equal to 1, and preferably the number of ground holes 150 is greater than or equal to 10.

[0081] Specifically, the ground pin 307 of the GPS chip 310 is connected to the first ground copper foil 111 of the first layer 110 and the second ground copper foil 131 of the third layer 130 through the ground pad 306 of the GPS chip 310 and the ground hole 301. It should be noted that the number of ground holes 301 is greater than or equal to 1, and preferably the number of ground holes 301 is greater than or equal to 10.

[0082] More specifically, the GPS RF signal pin 304 of the GPS chip 310 is soldered to the GPS RF signal pad 305. The GPS RF signal is led out from the GPS RF signal pad 305 and sent to the RF matching component 322 through the RF line 158, then sent to the RF matching component 323 through the RF line 188, then sent to the RF matching component 321 through the RF line 199, then sent to the second via pad 103 through the RF line 142, and finally sent to the GPS antenna body 210 through the GPS antenna pin 220. At this time, a pulsed electric field E8 is formed between the GPS antenna body 210 and the first ground copper foil 112, creating conditions for receiving GPS signals transmitted from sky satellites.

[0083] Thus, a radio frequency current i21 is generated in the fourth layer 140. The radio frequency current i21 flows from the GPS chip 310 through the radio frequency line 158 to the radio frequency matching component 322, then through the radio frequency line 188 to the radio frequency matching component 323, and then through the radio frequency line 199 to the radio frequency matching component 321, and then through the radio frequency line 142 to the second via pad 103. The radio frequency current i21 is then transmitted from the second via pad 103 in the fourth layer 140 to the GPS antenna pin 220 and flows to the GPS antenna body 210; a reverse return current i20 is generated in the first ground copper foil 112 and flows from the via hole 150 to the second ground copper foil 131 in the third layer 130, returns to the ground pad 306 of the GPS chip 310 and the ground pin of the GPS chip 310 through the via hole 301, and finally reaches the inside of the GPS chip 310, forming a closed-loop circuit for the entire GPS radio frequency link.

[0084] In some embodiments, the first region 703 is divided into a second region 701 and a third region 702 surrounding the second region 701. The first via pad 102 is located in the second region 701, and the minimum distance L1 between the boundary of the second region 701 and the first via pad 102 is not less than 0.5 mm. Among them, the distance between the boundary of the second region 701 and the first via pad 102 forms a clearance region 104; the first ground copper foil 112 is disposed in the third region 702.

[0085] The purpose of setting the clearance region 104 around the first via pad 102 on the circuit board 100 is to reduce the parasitic capacitance between the first via pad 102 and the surrounding first ground copper foil 112 (i.e., a part of the first ground copper foil 111). In practical applications, if the above parasitic capacitance exceeds a certain value, it will affect the impedance of the first via pad 102 in the circuit board 100. As a result, when the GPS antenna 200 transmits radio frequency signals, due to the impedance of the first via pad 102 not meeting the specified requirements, the performance of the GPS antenna 200 is affected. Specifically, when the above parasitic capacitance exceeds a certain capacitance value, the impedance of the first via pad 102 during the transmission of radio frequency signals will jump, which will cause the relevant indicators such as the gain, VSWR, noise figure, axial ratio, and receiving sensitivity of the GPS antenna 200 to deteriorate, affecting the performance of the GPS antenna 200.

[0086] When the minimum distance L1 between the boundary of the second region 701 and the first via pad 102 is set to be not less than 0.5 mm, the parasitic capacitance between the first via pad 102 and the first ground copper foil 112 around it can be made less than 0.5 pF. When the parasitic capacitance between the first via pad 102 and the first ground copper foil 112 around it is less than 0.5 pF, it will not affect the relevant indicators such as the gain, VSWR, noise figure, axial ratio, and receiving sensitivity of the GPS antenna 200. At this time, the diameter D1 of the GPS antenna pin 220 can be 1 mm, and the diameter D2 of the first via pad 102 can be 1.2 mm.

[0087] Preferably, the minimum distance L1 between the boundary of the second region 701 and the first via pad 102 is not less than 1 mm. In this way, it can be further ensured that the parasitic capacitance between the first via pad 102 and the first ground copper foil 112 around it is less than 0.5 pF, so as to avoid affecting the relevant indicators such as the gain, VSWR, noise figure, axial ratio, and receiving sensitivity of the GPS antenna 200.

[0088] In some embodiments, the first ground copper foil 112 is located in the third region 702 and covers the third region 702. At this time, there are no other circuits, signal vias, power vias, power lines 124, etc. in the third region 702. In this way, a complete ground copper foil can be provided in the orthographic projection area (i.e., the first region 703) of the GPS antenna body 210 on the first layer 110.

[0089] Since the GPS antenna body 210 is generally a cube or a cuboid, in this application, the GPS antenna body 210 is taken as an example of a cuboid for illustration. Looking down at the electronic device (as Figure 12 shown), the size of the GPS antenna body 210 in its width direction (i.e., the Figure 12 shown X direction) is L2, and the size of the GPS antenna body 210 in its length direction (i.e., the Figure 12 shown Y direction) is L3. At this time, the area of the first region 703 is L2 multiplied by L3. The area of the third region 702 covered with the first ground copper foil 112 is L2 multiplied by L3 minus the area of the clearance area and minus the area of the first via pad 102 and minus the area of the via 101.

[0090] The GPS antenna pin 220 is cylindrical, the diameter of the GPS antenna pin 220 is D1, the diameter of the first through-hole pad 102 is D2, the second region 701 is circular, the diameter of the second region 701 is D3, and D3 > D2 > D1. Wherein, the distance between the boundary of the second region 701 and the first through-hole pad 102 is L1, and the relationship between L1, D1, and D2 satisfies: (D1 - D2) / 2 = L1.

[0091] In some embodiments, signal lines 129 or power lines 124 with a line width less than or equal to 0.5 mm, and / or transmission vias with a hole diameter less than or equal to 0.6 mm are provided in the first region 703. Among them, the number of lines falling within the projection area of the GPS antenna body 210 does not exceed 10; the number of transmission vias does not exceed 30, and the transmission vias are signal vias or power vias.

[0092] In this way, the wiring density of the circuit board 100 can be increased through the transmission vias in the first region 703 and / or the lines falling within the projection area of the GPS antenna body 210. At the same time, since the line width of the signal lines 129 or power lines 124 is less than or equal to 0.5 mm, the hole diameter of the transmission vias is less than or equal to 0.6 mm, the number of lines falling within the projection area of the GPS antenna body 210 does not exceed 10, and the number of transmission vias does not exceed 30, it is ensured that the transmission vias and / or the lines falling within the projection area of the GPS antenna body 210 will not cause interference to the GPS antenna 200.

[0093] Preferably, the number of lines falling within the projection area of the GPS antenna body 210 does not exceed 3, and the number of transmission vias does not exceed 10. In this way, the area of the first ground copper foil in the first region 703 that the first ground copper foil 112 can occupy can be increased, so that the performance of the GPS antenna 200 is better. Further, the number of lines falling within the projection area of the GPS antenna body 210 does not exceed 2, the number of transmission vias does not exceed 5, and the hole diameter of the transmission vias is not greater than 0.2 mm. In this way, the area of the first ground copper foil in the first region 703 that the first ground copper foil 112 can occupy can be further increased, so that the performance of the GPS antenna 200 is even better.

[0094] Continue to refer to Figure 6, the GPS antenna body 210 is installed on the first layer 110. Since the density of the circuit board 100 is very high, it is impossible to route all the signal lines 129 or power lines 124 outside the projection area of the GPS antenna body 210 on the first layer 110. Signal lines 129 or power lines 124 are provided in the first layer 110 within the projection area of the GPS antenna body 210, but the signal lines 129 or power lines 124 will damage the integrity of the first ground copper foil 111 in the projection area of the GPS antenna body 210 on the first layer 110. Therefore, the length of the signal lines 129 or power lines 124 in the projection area of the GPS antenna body 210 on the first layer 110 should be reduced to minimize the impact on the performance of the GPS antenna 200. The signal lines 129 or power lines 124 are not high-speed lines (such as clock lines), RF lines or other strongly interfering lines to reduce interference to the GPS antenna 200. Signal vias or power vias 551 are provided in the projection area of the GPS antenna body 210 on the first layer 110 to increase the routing rate of the PCB, but the signal vias or power vias 551 will damage the integrity of the first ground copper foil 111 in the projection area of the GPS antenna body 210 on the first layer 110. Therefore, the number of signal vias or power vias 551 should be minimized as much as possible to minimize the impact on the performance of the GPS antenna 200. The signal vias or power vias 551 cannot be high-speed digital signal vias (such as clock vias), GPU power vias, CPU core power vias, NPU power vias, etc., because the interference of high-speed digital signal vias, GPU power vias, CPU core power vias, and NPU power vias is very strong, which will cause a decline in GPS performance (such as poor reception sensitivity, etc.).

[0095] In some embodiments, the first ground copper foil 111 further includes a second ground copper foil 113 that surrounds the first ground copper foil 112 and is connected to the first ground copper foil 112. The minimum distance L5 between the edge of the second ground copper foil 113 away from the first region 703 and the first region 703 is not less than 0.3 mm.

[0096] By providing the second ground copper foil 113 and ensuring that the minimum distance L5 between the edge of the second ground copper foil 113 away from the first region 703 and the first region 703 is not less than 0.3 mm, the performance of the GPS antenna 200 can be improved. Here, the connection of the second ground copper foil 113 to the first ground copper foil 112 means that the first ground copper foil 112 and the second ground copper foil 113 are connected to each other at various locations to form an integral whole. The distance between the edge of the second ground copper foil 113 away from the first region 703 and the first region 703 is L5, and the minimum distance between the edge of the second ground copper foil 113 away from the first region 703 and the first region 703 not less than 0.3 mm means that L5 is not less than 0.3 mm.

[0097] Preferably, L5 is not less than 0.5 mm. In this way, the performance of the GPS antenna 200 can be further improved. It should be noted that the specific value of L5 can be determined according to the specific installation positions of the electronic components on the circuit board 100, the wiring method of the circuit board 100, and the size of the circuit board 100.

[0098] In some embodiments, at least part of a preset line 121 is provided in the orthographic projection of the GPS antenna body 210 on the second layer 120. Since a first ground copper foil 111 is provided in the orthographic projection area of the preset line 121 on the first layer 110, there is no need to worry about the preset line 121 interfering with the GPS antenna body 210.

[0099] Specifically, since the GPS antenna body 210 can form a positive oscillator of the GPS antenna, and the first ground copper foil 112 can form an electric field with the GPS antenna 200, so that the first ground copper foil 112 forms a negative oscillator of the GPS antenna. Such a setting already meets the conditions of the pulse electric field of the GPS antenna 200. Therefore, setting at least part of the preset line 121 in the orthographic projection of the GPS antenna body 210 on the second layer 120 will not destroy the conditions of the pulse electric field of the GPS antenna 200. That is, since the first ground copper foil 112 is provided in the first area 703 and surrounds the first via pad 102, the GPS antenna body 210 (i.e., the positive oscillator of the GPS antenna) can form a GPS antenna pulse electric field with reference to the first ground copper foil 112, so that the GPS antenna body 210 can use the first ground copper foil 112 as the signal return. Therefore, setting at least part of the preset line 121 in the orthographic projection of the GPS antenna body 210 on the second layer 120 will not interfere with the GPS antenna.

[0100] By setting at least part of the preset line 121 in the orthographic projection of the GPS antenna body 210 on the second layer 120, the wiring penetration rate of the circuit board 100 can be improved, and then the density of the circuit board 100 can be increased, so as to avoid increasing the cross-sectional area or the number of layers of the circuit board 100 to increase the number of circuits on the circuit board 100.

[0101] Those of ordinary skill in the art can understand that the above embodiments are specific examples for implementing the present application. In actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. An electronic device, characterized in that, including a circuit board; The circuit board is provided with a first layer having a first ground copper foil, a second layer having a preset circuit, a third layer having a second ground copper foil, and a fourth layer provided with a sensitive area, which are stacked in sequence; The distance between the first layer and the second layer is less than the distance between the second layer and the third layer; The preset circuit is a signal circuit and / or a power supply circuit; the orthographic projection of the preset circuit on the first layer is located on the first ground copper foil; the sensitive area includes the area where the sensitive circuit is arranged on the fourth layer, and / or the projection area of the sensitive device arranged on the fourth layer on the fourth layer; The orthographic projection of the sensitive area on the third layer is located on the second ground copper foil; Wherein, the orthographic projection of the preset circuit on the fourth layer at least partially overlaps with the sensitive area; or the minimum distance between the orthographic projection of the preset circuit on the fourth layer and the sensitive area does not exceed 0.8 mm; The distance between the first layer and the second layer is a first distance; the distance between the second layer and the third layer is a second distance; the second distance is more than 1.5 times the first distance.

2. The electronic device according to claim 1, wherein It further includes: A GPS antenna and a GPS module; the circuit board is provided with a through hole, one end of the through hole is located on the first layer and the other end is located on the fourth layer, the first layer is provided with a first via pad surrounding the end of the through hole, and the fourth layer is provided with a second via pad surrounding the end of the through hole; the sensitive area includes the area where the sensitive circuit is arranged on the fourth layer; the GPS antenna includes a GPS antenna body and a GPS antenna pin connected to the GPS antenna body, the GPS antenna body is arranged on the side of the first layer away from the second layer, one end of the GPS antenna pin connected to the GPS antenna body is fixed to the first via pad, the part between the two ends of the GPS antenna pin is located in the through hole, and the other end of the GPS antenna pin is fixed to the second via pad; the GPS module includes a GPS chip and peripheral devices, the GPS chip is connected to the second via pad through the peripheral devices and the sensitive circuit, and both the GPS chip and the peripheral devices are located on the side of the fourth layer away from the third layer.

3. The electronic device according to claim 2, wherein The area where the orthographic projection of the GPS antenna body on the first layer is located is a first area; The first ground copper foil includes a first ground copper foil arranged in the first area and surrounding the first via pad, and there is a distance between the first ground copper foil and the first via pad.

4. The electronic device according to claim 3, wherein The first area includes a second area and a third area surrounding the second area, the first via pad is located in the second area, the minimum distance between the boundary of the second area and the first via pad is not less than 0.5 mm, and the first ground copper foil is located in the third area and covers the third area.

5. The electronic device according to claim 3, wherein the first ground copper foil further includes a second ground copper foil surrounding and connected to the first ground copper foil, and the minimum distance between the edge of the second ground copper foil away from the first region and the first region is not less than 0.3 mm.

6. The electronic device according to claim 3, wherein signal lines and / or power supply lines with a line width less than 0.5 mm are provided in the first region, and / or via holes with a hole diameter less than or equal to 0.6 mm are provided in the first region, wherein the number of the lines does not exceed 10, the number of the via holes does not exceed 30, and the via holes are signal via holes and / or power supply via holes.

7. The electronic device according to claim 2, wherein at least part of the preset lines are provided in the orthographic projection of the GPS antenna body on the second layer.

8. The electronic device according to claim 2, wherein A ground hole is provided in the projection area of the GPS antenna body on the circuit board; the ground hole is connected to the first ground copper foil of the first layer and the second ground copper foil of the third layer; the ground copper foil of the second layer and the ground copper foil of the fourth layer are both connected to the ground hole; the ground copper foil of the fourth layer is connected to the ground pin of the GPS chip.

9. The electronic device according to claim 1, wherein the signal lines include audio amplifier output line, clock line, high-speed line and / or radio frequency line.

10. The electronic device according to claim 1, wherein the sensitive area includes the area where the sensitive lines provided on the fourth layer are located, and the sensitive lines include at least one of radio frequency line, audio line, phase-locked loop line, analog sampling line, analog operational amplifier line, pyroelectric infrared sensing line, thermal sensitive line, photosensitive line, gas sensitive line, force sensitive line, magnetic sensitive line, humidity sensitive line, taste sensitive line, radiation sensitive line, color sensitive line, sound sensitive line, photoelectric converter line.

11. The electronic device according to claim 1, wherein the sensitive area includes the projection area of the sensitive devices provided on the fourth layer on the fourth layer, and the sensitive devices include at least one of phase-locked loop element, analog sampling element, radio frequency element, analog operational amplifier element, audio element, pyroelectric infrared sensing element, thermal sensitive element, photosensitive element, gas sensitive element, force sensitive element, magnetic sensitive element, humidity sensitive element, sound sensitive element, radiation sensitive element, photoelectric converter element, color sensitive element, taste sensitive element provided on the fourth layer.

Images