A PCB Design Method for High-Frequency Digital Circuits

Abstract

The present invention discloses a PCB design method for a high-frequency digital circuit. The method includes: determining a wiring model of the high-frequency digital circuit and selecting a processing chip for the high-frequency digital circuit; determining an external impedance circuit of the high-frequency digital circuit; dividing the circuit that needs to be segmented in the external impedance circuit into N segments, setting the impedance of each segment as a target value, and then based on the stack-up design and the setting of the reference layer, the line width and line spacing of this segment can be determined; setting global impedance rules, the global impedance rules include multiple sub-rules, and each sub-rule corresponds to a segment; applying the global impedance rules to the unprocessed segments; aligning signals in the high-frequency digital circuit. This method adopts a strategy of rule rotation, which not only avoids the situation that the same rule cannot meet the requirements of segmented impedance matching, but also avoids the situation where multiple rules coexist and the priority cannot be controlled.

Description

Technical Field

[0001] The present invention relates to the field of high-frequency digital circuits, and particularly to a PCB design method for high-frequency digital circuits. Background Art

[0002] With the rapid development of microelectronics technology and related processes, the design of multi-layer printed circuit boards (PCBs) has become increasingly complex, and the working frequency has been continuously increased. The design of PCBs has entered the stage above GHz. However, with the increase in frequency, a series of electromagnetic interference problems have arisen. The rise time of the working clock / signal bus has reached the picosecond level, and the high-frequency harmonic components of the signal have also increased accordingly, generating electromagnetic radiation with a wider frequency spectrum, which poses a great challenge to the electromagnetic compatibility design of the system.

[0003] In the high-frequency case, common components will exhibit a series of parasitic characteristics. For example, even a very short transmission line may become a radiation antenna, forming electromagnetic interference (EMI). Therefore, in modern PCB design, electromagnetic compatibility has received more and more attention. Among them, processing methods for high-speed PCBs such as stack-up design, impedance matching, equal-length routing, and ground shielding are crucial. Some extremely sensitive devices, such as DDR4 and EMMC, have relatively strict requirements for electromagnetic compatibility. While ensuring equal-length routing and ground shielding, it is also necessary to meet their stripline and microstrip line models and ensure segmented impedance matching.

[0004] Impedance matching means that during energy transmission, it is required that the load impedance be equal to the characteristic impedance of the transmission line. At this time, there will be no reflection in the transmission, which means that all energy is absorbed by the load. Otherwise, there will be energy loss during transmission. SSTL drivers such as DDR and DDR2 have quite high requirements for impedance. With the wide application of these integrated circuits, the implementation of impedance matching is quite important. During the impedance matching process, it is usually constrained by rule design. However, segmented impedance obviously cannot be constrained by one rule. In the prior art, the circuit is usually set by updating the rules at any time. However, the problem brought by this method is that it is impossible to ensure segmented impedance matching. If multiple rules coexist, it is difficult to determine the priority of the rules, which is likely to cause disorder in the routing rules during the PCB drawing process. Therefore, the present invention adopts a rule rotation strategy to quickly and effectively achieve segmented impedance matching. Summary of the Invention

[0005] In view of this, the present invention provides a PCB design method for high-frequency digital circuits, which can solve the technical problem of how to quickly and effectively achieve segmented impedance matching.

[0006] To solve the above technical problems, the present invention is implemented as follows.

[0007] A PCB design method for a high-frequency digital circuit, comprising:

[0008] Step S1: Obtain the design requirements of the high-frequency digital circuit, select a processing chip for the high-frequency digital circuit, and determine the wiring model of the high-frequency digital circuit;

[0009] Step S2: Based on the model of the chip and the types of signals in the high-frequency digital circuit, determine the impedance driving ability of the high-frequency digital circuit, and then determine the external impedance circuit of the high-frequency digital circuit; Based on the circuit structure of the external impedance circuit, determine the impedance of each part of the external impedance circuit, divide the devices that need segmented impedance in the external impedance circuit into N segments, each segment includes one or more parts, and the absolute value of the difference between the impedances corresponding to each part included in each segment is less than a preset threshold; Set each segment to an unprocessed state, and set global impedance rules, where the global impedance rules include multiple sub-rules, and each sub-rule corresponds to one segment; Among them, the part that needs segmented impedance is one or more;

[0010] Step S3: If all segments have been processed, go to Step S5; otherwise, select an unprocessed segment and enter Step S4;

[0011] Step S4: Apply the global impedance rules to the unprocessed segment; Set the unprocessed segment to a processed state, set each sub-rule in the global impedance rules to be valid, and enter Step S3;

[0012] Step S5: Align the signals of the devices in the high-frequency digital circuit that have alignment requirements.

[0013] Preferably, Step S4 includes:

[0014] The external impedance circuit includes devices that do not require impedance, devices that require impedance and do not require segmentation, and devices that require impedance and require segmentation; Devices that do not require impedance do not set impedance rules, devices that require impedance and do not require segmentation set fixed impedance rules, and global rules are set for devices that require impedance and require segmentation;

[0015] Call the global impedance rules, set the remaining sub-rules in the global impedance rules except the sub-rule corresponding to the unprocessed segment to be invalid, apply the global impedance rules to the unprocessed segment, and route the unprocessed segment; Set the unprocessed segment to a processed state, set each sub-rule in the global impedance rules to be valid, and enter Step S3.

[0016] Preferably, the step S2 further includes determining the PCB core board material based on the signal of the high-frequency digital circuit and the propagation speed of the signal, performing a stack-up design on the high-frequency digital circuit, determining a reference layer, and each layer in the stack-up is a reference layer; determining each core board parameter of the core board, inputting the core board parameters into SI9000, and adjusting the stack-up model, line width, and line spacing to achieve the external impedance.

[0017] Preferably, each layer in the stack-up is a reference layer. For signals with specific impedance requirements in the reference layer, perform interlayer referencing, hollow out the adjacent negative layer, and lay copper on the selected positive layer as an independent reference layer.

[0018] Preferably, the stack-up design includes determining the sorting method of the power layer, ground layer, and signal layer of the high-frequency digital circuit according to the wiring model.

[0019] Preferably, the step S5 includes: determining the signals that need to be transmitted simultaneously according to the transmission speed of each signal in the high-frequency digital circuit, performing serpentine routing on the connected signals, and completing signal alignment.

[0020] Beneficial effects:

[0021] (1) The present invention adopts a strategy of regular rotation, which not only avoids the situation where the same rule cannot meet the requirements of segmented impedance matching, but also avoids the situation where multiple rules coexist and the priority cannot be controlled.

[0022] (2) It has strong guidance for the design of high-speed PCBs, especially for the PCB design of devices such as DDR4 and EMMC, making the high-speed PCB design simpler and clearer.

[0023] (3) The PCB layout designed by the present invention is complete and has a high correct rate.

[0024] (4) The present invention has strong practical value for the design of high-speed digital circuits and PCB design. Description of the Drawings

[0025] Figure 1 It is a schematic flow chart of the PCB design method for the high-frequency digital circuit provided by the present invention;

[0026] Figure 2 It is a schematic diagram of the matching circuit provided by the present invention;

[0027] Figure 3 It is a schematic diagram of the load matching circuit with a source impedance of 75 ohms provided by the present invention;

[0028] Figure 4 It is a schematic diagram of the double-layer design provided by the present invention;

[0029] Figure 5Schematic diagram of the microstrip line model provided by the present invention;

[0030] Figure 6 Schematic diagram of impedance segmentation for DDR4. Specific implementation manner

[0031] The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0032] As Figure 1 shown, the present invention proposes a PCB design method for high-frequency digital circuits, including the following steps:

[0033] Step S1: Obtain the design requirements of the high-frequency digital circuit, select a type of processing chip for the high-frequency digital circuit, and determine the wiring model of the high-frequency digital circuit;

[0034] Step S2: Based on the model of the chip and the type of signals in the high-frequency digital circuit, determine the driving ability of the high-frequency digital circuit for impedance, and then determine the external impedance circuit of the high-frequency digital circuit; based on the circuit structure of the external impedance circuit, determine the impedance of each part of the external impedance circuit, divide the devices that need segmented impedance in the external impedance circuit into N segments, each segment includes one or more parts, and the absolute value of the difference between the impedances corresponding to each part included in each segment is less than a preset threshold; set each segment to an unprocessed state, and set global impedance rules, where the global impedance rules include multiple sub-rules, and each sub-rule corresponds to one segment; wherein, the part that needs segmented impedance is one or more;

[0035] Step S3: If all segments are processed, enter Step S5; otherwise, select an unprocessed segment and enter Step S4;

[0036] Step S4: Apply the global impedance rules to the unprocessed segment; set the unprocessed segment to a processed state, set each sub-rule in the global impedance rules to be valid, and enter Step S3;

[0037] Step S5: Align the signals of the devices in the high-frequency digital circuit that have alignment requirements.

[0038] The present invention is applied in the process of designing the high-frequency digital circuit. By determining the impedance that each segment of the external impedance circuit of the high-frequency digital circuit should have, and then adopting global impedance rules, all sub-rules in the global impedance rules except the sub-rule corresponding to the selected unprocessed segment are set to be invalid, so as to ensure that the routing of the PCB design is reasonable and correct. The present invention adopts a strategy of rule-based segmented rotation to achieve complex impedance matching situations.

[0039] In this embodiment, in the external impedance circuit, some devices require segmented impedance, and some devices do not require impedance or do not need segmentation, and the rules corresponding to the parts that do not require segmented impedance and / or the parts that do not require segmentation are set to be fixed. The part of the external impedance circuit that requires segmented impedance is divided into N segments, and each segmented impedance device is set based on the global impedance rule.

[0040] The purpose of step S1, selecting the processing chip of the high-frequency digital circuit and performing stacking design on the high-frequency digital circuit, is to ensure the wiring model of the high-frequency digital circuit, such as microstrip line, strip line, etc., to ensure the data transmission speed while minimizing the impact of electromagnetic interference.

[0041] Furthermore, the step S2 also includes determining the PCB core board material based on the signal of the high-frequency digital circuit and the propagation speed of the signal, performing a stacking design for the high-frequency digital circuit, determining a reference layer, and each layer in the stacking is a reference layer; determining each core board parameter of the core board, inputting the core board parameters into SI9000, and adjusting the stacking model, line width, and line spacing to achieve the external impedance.

[0042] In the present invention, the wiring model of the high-frequency digital circuit is ensured through stacking design. For example, DDR data and address lines require microstrip lines. Therefore, the microstrip line model is ensured as much as possible in the stacking design, and the impedance design is performed using SI9000.

[0043] The same reference layer may not be able to achieve multiple impedances, or may cause the line width and line spacing values ​​to be quite outrageous. In the present invention, an interlayer reference is performed for the signal with specific impedance requirements in the reference layer, and its adjacent negative layer is hollowed out, and copper is laid on the selected positive layer as an independent reference layer.

[0044] In this embodiment, for a relatively simple high-frequency digital circuit, it is only necessary to control the impedance value during the PCB wiring process according to the determined impedance. However, devices such as DDR4 require that segmented impedance matching be ensured during the wiring process. For example, the impedance matching circuit is Figure 6 The figure shows the FLY-BY structure of DDR4. The impedance requirements for each section of L0-L4 are different, and the impedance of each section is determined according to the circuit characteristics.

[0045] In the present invention, the driving capability of the high-frequency digital circuit is determined by the design requirements. Since the source impedance is not exactly the same as the load impedance, several impedance matching circuits are required. The matching circuit is composed of inductors and capacitors. At this time, capacitors and inductors are needed to debug the impedance matching circuit to achieve optimal RF performance.

[0046] Further, the stacked design includes determining the sorting method of the power layer, ground layer, and signal layer of the high-frequency digital circuit according to the wiring model.

[0047] Further, step S4 includes: the external impedance circuit includes devices that do not require impedance, devices that require impedance and do not require segmentation, and devices that require impedance and require segmentation; impedance rules are not set for the devices that do not require impedance, fixed impedance rules are set for the devices that require impedance and do not require segmentation, and global rules are set for the devices that require impedance and require segmentation;

[0048] Call the global impedance rule, invalidate all the sub-rules in the global impedance rule except the sub-rule corresponding to the unprocessed segment, apply the global impedance rule to the unprocessed segment, and route the unprocessed segment; set the unprocessed segment to the processed state, set all the sub-rules in the global impedance rule to be valid, and enter step S3.

[0049] In step S4, call the global impedance rule, invalidate all the sub-rules in the global impedance rule except the sub-rule corresponding to the unprocessed segment, and apply the global impedance rule to the unprocessed segment, that is, on the premise of ensuring other simple rules of the external impedance circuit, set the impedance rules for different segments respectively, so that each rule corresponds to a different impedance value. When drawing the corresponding segment, enable the global impedance rule, and make other rules except the impedance rule corresponding to the unprocessed segment invalid, and then rotate in turn until the signal traces of the entire external impedance circuit are drawn. The reason for the present invention to adopt this method is that for a certain device, when it inputs the same signal, different segments require different impedances. The present invention innovatively uses the rule rotation system, that is, first set a rule to complete a certain segment of the trace, then cancel the current rule, set the second rule to complete the second segment of the trace, and so on, until the impedance matching of different segments of the same signal is completed. The implementation method of the present invention is different from the prior art. The present invention is an impedance continuity matching strategy, which can design the subsequent impedance according to the requirements of the high-frequency digital circuit and complete impedance matching during the wiring process.

[0050] The present invention performs an interlayer reference design and segment rule setting on the PCB according to the different impedance requirements of different segments to complete the PCB design.

[0051] Further, in step S5, after completing the impedance matching of the signal, determine the signals that need to be transmitted simultaneously according to the transmission speeds of the signals in the high-frequency digital circuit, perform serpentine routing on the connected signals to complete signal alignment. And perform ground wrapping on the signals that are more sensitive and vulnerable to interference to reduce the interference of external signals on them. For example, align the clock signals and data signals in the same group.

[0052] For example, there are five devices A, B, C, D, and E in a high-frequency digital circuit. Among them, A, B, and C require signal alignment, while D and E have no requirements for signal alignment. In addition, A, B, C, and D only require one type of impedance, and E requires five-segment stepped impedance. During the design process, the impedances of these five devices must be set first. Since A, B, C, and D only need to meet one type of impedance, rules rulezkA, rulezkB, rulezkC, and rulezkD are set in the rules first to limit the impedances of A, B, C, and D. After that, the impedance rules rulezkA, rulezkB, rulezkC, and rulezkD of A, B, C, and D are no longer allowed to change. Then, the stepped impedance of E, rulezkE1, rulezkE2, rulezkE3, rulezkE4, and rulezkE5, is formulated. Then, the following combinations will occur during the PCB routing process:

[0053] 1. rulezkA, rulezkB, rulezkC, rulezkD, rulezkE1.

[0054] 2. rulezkA, rulezkB, rulezkC, rulezkD, rulezkE2

[0055] 3. rulezkA, rulezkB, rulezkC, rulezkD, rulezkE3

[0056] 4. rulezkA, rulezkB, rulezkC, rulezkD, rulezkE4

[0057] 5. rulezkA, rulezkB, rulezkC, rulezkD, rulezkE5

[0058] When each segment of the rule takes effect, routing is performed on the corresponding segment; at this time, the impedance adjustment has been completed, and then signal alignment is performed. This sequence can reduce the workload. According to the requirements, only devices A, B, and C need signal alignment. The signals required for alignment of devices A, B, and C are grouped into different NETCLASSES; the transmission speed is determined according to the PCB material, and the maximum allowable time interval between each signal is determined. The line width and line spacing of the PCB traces can be calculated based on the parameters of the selected PCB material and the stack-up design.

[0059] The above specific embodiments only describe the design principle of the present invention. The shapes and names of the components in this description can be different and are not restricted. Therefore, those skilled in the art of the present invention can modify or make equivalent substitutions to the technical solutions recorded in the foregoing embodiments; and these modifications and substitutions do not depart from the purpose and technical solutions of the present invention, and shall all fall within the protection scope of the present invention.

Claims

1. A PCB design method for high-frequency digital circuits, characterized in that, The method includes the following steps: Step S1: Obtain the design requirements of the high-frequency digital circuit, select a processing chip for the high-frequency digital circuit, and determine the wiring model of the high-frequency digital circuit; Step S2: Based on the model of the chip and the types of signals in the high-frequency digital circuit, determine the impedance driving ability of the high-frequency digital circuit, and then determine the external impedance circuit of the high-frequency digital circuit; Based on the circuit structure of the external impedance circuit, determine the impedance of each part of the external impedance circuit, divide the devices that require segmented impedance in the external impedance circuit into N segments, each segment includes one or more parts, and each part included in each segment corresponds to a different impedance value; Set each segment to an unprocessed state, and set global impedance rules, where the global impedance rules include multiple sub-rules, and each sub-rule corresponds to one segment; Among them, the part that requires segmented impedance is one or more; Step S3: If all segments have been processed, enter Step S5; Otherwise, select an unprocessed segment and enter Step S4; Step S4: Apply the global impedance rules to the unprocessed segment; Set the unprocessed segment to a processed state, set all the sub-rules in the global impedance rules to be valid, and enter Step S3; Step S5: Align the signals of the devices in the high-frequency digital circuit that have alignment requirements; Step S2 includes: The external impedance circuit includes devices that do not require impedance, devices that require impedance and do not require segmentation, and devices that require impedance and require segmentation; Devices that do not require impedance are not set with impedance rules, devices that require impedance and do not require segmentation are set with fixed impedance rules, and global rules are set for devices that require impedance and require segmentation; Call the global impedance rules, set all the sub-rules in the global impedance rules except the sub-rule corresponding to the unprocessed segment to be invalid, apply the global impedance rules to the unprocessed segment, and perform wiring on the unprocessed segment; Set the unprocessed segment to a processed state, set all the sub-rules in the global impedance rules to be valid, and enter Step S3.

2. The method according to claim 1, wherein Step S2 further includes determining the PCB core board material based on the signals of the high-frequency digital circuit and the propagation speed of the signals, performing a stack-up design on the high-frequency digital circuit, determining the reference layer, and each layer in the stack-up is a reference layer; Determine each core board parameter of the core board, input the core board parameters into SI9000, and adjust the stack-up model, line width, and line pitch to achieve the external impedance.

3. The method according to claim 2, wherein Perform an isolation reference on the signals with specific impedance requirements in the reference layer, hollow out its adjacent negative layer, and lay copper on its selected positive layer as an independent reference layer.

4. The method according to claim 2, wherein The stack-up design includes determining the sorting method of the power layer, ground layer, and signal layer of the high-frequency digital circuit according to the wiring model.

5. The method according to claim 1, wherein Step S5 includes: According to the transmission speed of each signal in the high-frequency digital circuit, determine the signals that need to be transmitted simultaneously, perform serpentine routing on the connected signals, and complete signal alignment.

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