A valley locking method and circuit for converter

Abstract

The present invention relates to the field of converter design, and provides a valley locking method and circuit for a converter. The valley locking method slows down the modulation speed of the PFM pulse frequency modulation unit by setting a hysteresis compensation link after the error signal; by comparing the opening valley position of the current cycle and the previous cycle, the threshold and hysteresis required for the valley switching of the next cycle are dynamically changed; specifically, if it is judged that the number of valleys in the current cycle has increased compared with the number of valleys in the previous cycle, the time threshold for the valley switching of the next cycle is delayed by a hysteresis time; if it is judged that the number of valleys in the current cycle has decreased compared with the number of valleys in the previous cycle, the time threshold for the valley switching of the next cycle is advanced by a hysteresis time. Different valleys correspond to different switching thresholds and hysteresis, so that a good locking effect can be achieved under different system parameters.

Description

Technical Field

[0001] The invention relates to the field of converter design, in particular to a method and circuit for locking a trough in a power converter, and in particular to a method and circuit for dynamically locking a trough. Background Art

[0002] The quasi-resonant (QR) control mode detects the resonant waveform of the converter switch node voltage, determines the trough of the sine wave, and turns on the power tube at the trough to reduce the switching loss of the power tube. The reduction of switching loss improves the efficiency of the converter, facilitating its development towards high frequency and miniaturization.

[0003] like Figure 1 As shown, the switching node voltage (ie, the drain voltage of the power tube) VDS waveform of a typical flyback converter and the gate drive voltage G_M of the power tube P After the transformer is demagnetized, the switch node voltage VDS is resonated by the excitation inductance and the switch node parasitic capacitance to form a resonant waveform, G_M P At the trough of the resonant waveform, it becomes a high level, driving the N-type power tube to turn on, minimizing the switching loss of the power tube.

[0004] However, there is an inherent technical difficulty in trough opening control. Figure 1 In the first cycle, the power tube is turned on at the first valley bottom of the resonant waveform, and in the second cycle, the power tube is turned on at the second valley bottom due to slight jitter of the input voltage or load; at this time, the frequency suddenly decreases, and the excitation time of the transformer needs to be longer to meet the energy conservation; and the increase in excitation time will cause the controller to reselect the first valley bottom to turn on, as shown in the third cycle. If the above valley bottom turn-on moment is repeatedly switched, and the switching frequency is within the audio range, it will cause the converter to make abnormal noises and low-frequency ripples in the output voltage. Therefore, a valley locking technology is needed so that small changes in the input voltage or load will not cause repeated switching of the valley turn-on point.

[0005] Common valley locking technologies on the market can be divided into three categories: (1) Within a certain range of the feedback error voltage, the Nth valley is fixed to open, and the valley is switched only when the error voltage jumps out of the set range, such as ON Semiconductor's chip NCP1342; (2) Detect the operating frequency of the converter, convert it into voltage through integration, filtering and other steps, and after comparing it with the reference voltage, decide whether to keep the current valley open or choose the previous or next valley to open, such as the Chinese patent application publication number "CN 108347173A"; (3) Increase the switching threshold by setting the time hysteresis of valley switching, such as the Chinese patent application publication number "CN111049388 A". These locking technologies are all based on fixed comparison thresholds, and need to set thresholds specifically for different converter power parameters, which is not flexible enough. Summary of the invention

[0006] In view of the shortcomings of the existing valley locking technology, such as fixed comparison thresholds and insufficient flexibility in system application, the purpose of the present invention is to provide a dynamic valley locking method and circuit. This locking method and circuit dynamically changes the threshold and hysteresis required for valley switching based on each different opening valley, so that no additional design is required when the system is applied.

[0007] The present invention provides a valley locking method for a converter, comprising:

[0008] Detecting the resonant waveform of the switch node voltage of the power tube of the converter in the current cycle to obtain the number of valleys of the resonant waveform;

[0009] Compare the detected number of troughs of the current cycle with the number of troughs of the previous cycle;

[0010] If the number of troughs in the current cycle increases compared to the number of troughs in the previous cycle, the time threshold for trough switching will be delayed by a hysteresis time in the next cycle;

[0011] If the number of troughs in the current cycle is smaller than that in the previous cycle, the time threshold for trough switching is advanced by a hysteresis time in the next cycle.

[0012] In one embodiment, the time threshold of the valley switching is the moment when the rising edge or the falling edge of the valley selection signal used to control the turning on of the power tube is generated.

[0013] In one embodiment, within a cycle, the hysteresis time corresponding to a smaller number of troughs is greater than the hysteresis time corresponding to a larger number of troughs.

[0014] In one embodiment, the valley locking method further comprises the step of slowing down the modulation speed of the pulse frequency modulation unit by performing hysteresis compensation on the error signal fed back by the control loop.

[0015] The present invention also provides a valley locking circuit for a converter, which comprises: a pulse frequency modulation unit, a valley detection unit, a dynamic threshold generation unit and a valley selection unit;

[0016] The pulse frequency modulation unit is used to generate a valley selection signal for controlling the opening of the power tube of the converter, and transmit the valley selection signal to the dynamic threshold generation unit and the valley selection unit;

[0017] The valley detection unit is used to detect the voltage waveform of the switch node of the power tube of the converter and generate a valley mark signal indicating the position of the resonance valley;

[0018] The dynamic threshold generating unit is used to receive the trough mark signal and the trough selection signal, and count the number of troughs in the current cycle according to the trough mark signal; if the number of troughs in the current cycle increases compared with the number of troughs in the previous cycle, the trough selection signal is controlled to be delayed by a hysteresis time in the next cycle; if the number of troughs in the current cycle decreases compared with the number of troughs in the previous cycle, the trough selection signal is controlled to be advanced by a hysteresis time in the next cycle;

[0019] The valley selection unit is used to receive the valley mark signal and the valley selection signal, and output the power tube opening signal according to the valley mark signal and the valley selection signal.

[0020] In one embodiment, the valley locking circuit further includes a hysteresis compensation unit, the input end of the hysteresis compensation unit is used to input the error signal fed back by the control loop, and generate a compensation signal whose phase lags relative to the error signal according to the error signal;

[0021] The pulse frequency modulation unit receives the compensation signal, and modulates the charging current of the capacitor disposed inside the pulse frequency modulation unit according to the difference between the compensation signal and the reference voltage, so that the charging cycle of the capacitor changes to generate a valley selection signal.

[0022] In one embodiment, the lag compensation unit includes: a narrow pulse generator, a first switch, a resistor R1, a capacitor C1, a resistor R2, a buffer and a resistor R3; one end of the first switch is connected to the error signal and one end of the resistor R2, the other end of the first switch is connected to one end of the resistor R1, and the control end of the first switch is connected to the output end of the narrow pulse generator; the other end of the resistor R1 is connected to the positive input end of the buffer and the first plate of the capacitor C1; the second plate of the capacitor C1 is grounded; the negative input end of the buffer is connected to its own output end and one end of the resistor R3; the other end of the resistor R2 is connected to the other end of the resistor R3, and the connection point between the resistor R2 and the resistor R3 is used to output a compensation signal.

[0023] In one embodiment, the pulse frequency modulation unit includes: a transconductance amplifier, a capacitor C2, a second switch, a first comparator, an AND gate, a first NOT gate, a high level generator, a first D flip-flop, and a second NOT gate;

[0024] The positive input terminal of the transconductance amplifier is connected to the compensation signal, the negative input terminal is connected to the first reference voltage, the output terminal of the transconductance amplifier is connected to the first plate of the capacitor C2, one end of the second switch and the negative input terminal of the first comparator; the second plate of the capacitor C2 is grounded; the other end of the second switch is grounded, and its control end is connected to the output end of the AND gate; the positive input terminal of the first comparator is connected to the second reference voltage, the output end of the first comparator is connected to the trigger end of the first D flip-flop and the input end of the first NOT gate; the output end of the first NOT gate is connected to an input end of the AND gate; the other input end of the AND gate is connected to the gate drive signal of the power tube; the D input end of the first D flip-flop is connected to the high level generator, and the Q output end of the first D flip-flop is used to output a valley selection signal; the input end of the second NOT gate is connected to the gate drive signal of the power tube, and the output end is connected to the reset end of the first D flip-flop.

[0025] In one embodiment, the valley detection unit includes: a second comparator and an adaptive delay circuit; the positive input terminal of the second comparator is connected to the switch node voltage of the power tube, the negative input terminal is connected to the threshold voltage, and the output terminal is connected to the input terminal of the adaptive delay circuit; the output of the adaptive delay circuit is used to output a valley mark signal.

[0026] In one embodiment, the dynamic threshold generating unit includes a counter, an increase / decrease judgment circuit, and a delay selection circuit;

[0027] The counter is used to receive the valley mark signal output by the valley detection unit, and output a valley counting signal reflecting the number of valleys in the current cycle according to the valley mark signal;

[0028] The increase / decrease judgment circuit receives the trough counting signal, and judges whether the trough number of the current cycle increases or decreases according to the recorded trough number of the previous cycle, and outputs a judgment signal reflecting the increase or decrease of the trough number of the current cycle;

[0029] The delay selection circuit is used to receive a valley counting signal, a judgment signal and a valley selection signal. If the judgment signal reflects that the current valley number increases compared with the valley number of the previous cycle, the valley selection signal is controlled to be delayed by a hysteresis time in the next cycle; if the judgment signal reflects that the current cycle valley number decreases compared with the valley number of the previous cycle, the valley selection signal is controlled to be advanced by a hysteresis time in the next cycle.

[0030] In one embodiment, the valley selection unit includes: a second D flip-flop and a third NOT gate; the D input terminal of the second D flip-flop is connected to the valley selection signal of the current cycle, the trigger terminal is connected to the valley mark signal, the Q output terminal outputs the power tube turn-on signal, and the reset terminal is connected to the output terminal of the third NOT gate; the input terminal of the third NOT gate is connected to the gate drive signal of the power tube.

[0031] The present invention also provides a valley locking method for a converter, comprising:

[0032] Detecting the number of valleys of the switching node voltage resonance of the power tube of the current cycle converter;

[0033] The detected trough number of the current cycle is compared with the trough number of the previous cycle. If the trough number of the current cycle increases than that of the previous cycle, the trough selection signal used to control the opening of the power tube in the next cycle is delayed by a hysteresis time; if the trough number of the current cycle is reduced than that of the previous cycle, the trough selection signal is controlled to be advanced by a hysteresis time in the next cycle.

[0034] The beneficial effects of the present invention are:

[0035] (1) Using the hysteresis compensation unit to slow down the frequency modulation speed of the control loop, so that the frequency modulation signal can be used as the time threshold for selecting the valley, preventing loop interference from causing the valley conduction to switch back and forth;

[0036] (2) Based on the increase or decrease of the number of valleys in the previous cycle and the current cycle, the time threshold is delayed or advanced by a hysteresis time so that a small range change in the input voltage or load will not cause repeated switching of the valley opening point. This hysteresis time changes dynamically with the number of valleys;

[0037] (3) Different troughs correspond to different time thresholds and hysteresis, so that a good locking effect can be achieved under different system parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 The waveform diagram of the key signals of a typical quasi-resonant control flyback converter;

[0039] Figure 2 It is a principle block diagram of the valley dynamic locking circuit of the present invention;

[0040] Figure 3 A circuit diagram of a hysteresis compensation unit in a valley locking circuit of the present invention;

[0041] Figure 4 A circuit diagram of a pulse frequency modulation unit in a valley locking circuit of the present invention;

[0042] Figure 5 It is a circuit diagram of a valley detection unit in the valley locking circuit of the present invention;

[0043] Figure 6 A circuit diagram of a dynamic threshold generating unit in a valley locking circuit of the present invention;

[0044] Figure 7 A circuit diagram of a valley selection unit in a valley locking circuit of the present invention;

[0045] Figure 8 This is a timing diagram of key signal waveforms of the valley locking circuit of the present invention.

[0046] Fig. 9 The flowchart is used to illustrate the locking method and circuit working principle of the present invention. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the following Figure 2 To Attachment Fig. 9 It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0048] like Figure 2 , which is a principle block diagram of the valley locking circuit of the present invention, the valley locking circuit 10 includes a hysteresis compensation unit 11, a pulse frequency modulation (PFM) unit 12, a valley detection unit 13, a dynamic threshold generating unit 14 and a valley selection unit 15.

[0049] The input end of the lag compensation unit 11 is connected to the control loop, and is used to input the error signal FB fed back by the control loop. After receiving the error signal FB, the lag compensation unit 11 provides a zero-pole pair to compensate the error signal FB, thereby forming a compensation signal FB_PFM whose phase lags relative to the error signal FB; the compensation signal FB_PFM is output to the pulse frequency modulation unit 12.

[0050] The pulse frequency modulation unit 12 modulates the charging current of the capacitor C2 disposed inside the pulse frequency modulation unit 12 according to the difference between the compensation signal FB_PFM and the first reference voltage REF1, so that the charging cycle of the capacitor C2 changes, and the valley selection signal VAEN of the current cycle is generated. In this embodiment, the modulation speed of the pulse frequency modulation unit 12 is slowed down by the compensation signal FB_PFM, so that the valley selection signal as a time reference remains unchanged in a short time, thereby enhancing the loop stability.

[0051] The dynamic threshold generating unit 14 is connected to the pulse frequency modulation unit 12. The dynamic threshold generating unit 14 is used to receive the valley selection signal VAEN, and based on the valley number corresponding to the valley selection signal VAEN of the current cycle and the valley number recorded in the previous cycle, determine to delay a hysteresis time or advance a hysteresis time on the basis of the valley selection signal VAEN of the next cycle, and superimpose the valley selection signal VAEN with the hysteresis time as the valley selection signal VAEN_NEXT of the next cycle.

[0052] The input end of the valley detection unit 13 is connected to the power tube M PThe switch node (ie, drain) of the output terminal is connected to the valley selection unit 15. The valley detection unit 13 compares the power tube M P The magnitude of the switch node voltage and the threshold voltage VTH is used to generate a valley mark signal VA representing a valley position.

[0053] The valley selection unit 15 is used to select the power transistor M in the current cycle according to the valley selection signal VAEN generated in the previous cycle. P Open when the nth trough appears.

[0054] Please refer to Figure 3 , Figure 3 The circuit diagram of the hysteresis compensation unit in the valley lock circuit of the present invention is shown. The hysteresis compensation 11 includes: a narrow pulse generator 111, a first switch 112, a resistor R1, a capacitor C1, a resistor R2, a buffer 113 and a resistor R3. One end of the first switch 112 is connected to the error signal FB and one end of the resistor R2, the other end of the first switch 112 is connected to one end of the resistor R1, and the control end of the first switch 112 is connected to the output end of the narrow pulse generator 111; the other end of the resistor R1 is connected to the positive input end of the buffer 113 and the first plate of the capacitor C1; the second plate of the capacitor C1 is grounded; the negative input end of the buffer 113 is connected to its own output end and one end of the resistor R3; the other end of the resistor R2 is connected to the other end of the resistor R3, and the connection point of the resistor R2 and the resistor R3 is used as an output end for outputting the compensation signal FB_PFM.

[0055] Assume that the pulse width generated by the narrow pulse generator 111 is T P , the pulse period is T C , then the transfer function from the error signal FB to the compensation signal FB_PFM can be expressed as:

[0056]

[0057] Wherein, s is the Laplace operator. By reasonably setting the resistance value of resistor R1, the resistance value of resistor R2, the resistance value of resistor R3, the capacitance value of capacitor C1, and the width and period of the narrow pulse, the required compensation effect (phase margin greater than 45 degrees) can be obtained.

[0058] Please refer to Figure 4 , Figure 4 1 is a circuit diagram of a pulse frequency modulation unit in a valley lock circuit of the present invention. The pulse frequency modulation unit 12 includes: a transconductance amplifier 121, a capacitor C2, a second switch 122, a first comparator 123, an AND gate 124, a first NOT gate 125, a high level generator 126, a first D flip-flop 127 and a second NOT gate 128.

[0059] The positive input terminal of the transconductance amplifier is connected to the compensation signal FB_PFM, and the negative input terminal is connected to the first reference voltage REF1. The output terminal of the transconductance amplifier 121 is connected to the first plate of the capacitor C2, one end of the second switch 122, and the negative input terminal of the first comparator 123; the second plate of the capacitor C2 is grounded; the other end of the second switch 122 is grounded, and its control terminal is connected to the output terminal of the AND gate 124; the positive input terminal of the first comparator 123 is connected to the second reference voltage REF2, the output terminal of the first comparator 123 is connected to the trigger terminal of the first D flip-flop 127 and the input terminal of the first NOT gate 125; the output terminal of the first NOT gate 125 is connected to one input terminal of the AND gate 124; the other input terminal of the AND gate 124 is connected to the power transistor M P The D input terminal of the first D flip-flop 127 is connected to the high level generator 126, and the Q output terminal of the first D flip-flop 127 outputs the current cycle valley selection signal; the input terminal of the second NOT gate 128 is connected to the power tube M P The gate driving signal is outputted and connected to the reset terminal of the first D flip-flop 127.

[0060] Assume that the gain of the transconductance amplifier 121 is G m , then the charging current I C for:

[0061] C =(FB_PFM-REF1)·G m

[0062] Assuming that the capacitance of the capacitor C2 is C2, the time required for the voltage of the first plate of the capacitor C2 to be charged to the second reference voltage REF2 at the positive input terminal of the first comparator 123 is:

[0063]

[0064] The voltage at the negative input terminal of the first comparator 123 is greater than the voltage at the positive input terminal, and its output terminal becomes low level, triggering the first D flip-flop 127, and the valley selection signal VAEN outputted by the Q output terminal of the first D flip-flop 127 becomes high level. After the valley selection signal VAEN becomes high level, the first valley flag signal VA is selected, giving the power tube M P The opening signal of the power tube M P The gate drive signal G_M P becomes high level, the power tube M P Open.

[0065] Drive signal G_M PThe high level causes the second NOT gate 128 to output a low level to reset the first D flip-flop 127, and the valley selection signal VAEN becomes a low level; at the same time, both input terminals of the AND gate 124 become high levels, so that its output terminal outputs a high level, closing the second switch 122. The charge of the first plate of the capacitor C2 is discharged to the ground, the comparator 123 outputs a high level, the first NOT gate 125 outputs a low level, the AND gate 124 outputs a low level, the second switch 122 is disconnected, the capacitor C2 is recharged, and the next stage of frequency modulation is started.

[0066] Please refer to Figure 5 , Figure 5 The circuit diagram of the valley detection circuit in the valley locking circuit of the present invention is shown in FIG. P The switching node voltage VDS (ie, the drain voltage) and the threshold voltage VTH are combined to generate a valley mark signal VA representing a valley position.

[0067] The valley detection unit includes: a second comparator 131 and an adaptive delay circuit 132. The positive input terminal of the second comparator 131 is connected to the switch node voltage VDS of the power tube, the negative input terminal is connected to the threshold voltage VTH, and the output terminal is connected to the input terminal of the adaptive delay circuit 132; the adaptive delay circuit 132 outputs a valley flag signal, wherein the threshold voltage VTH can be the input voltage of the converter, or a variable threshold close to the valley of the switch node voltage. In this embodiment, the threshold voltage VTH is the input voltage V IN The switch node voltage of the power tube of the converter working in DCM (discontinuous current mode) is VDS at the input voltage V IN Upper and lower resonance, the resonance period is fixed, such as Figure 1 As shown. The falling edge of the low level output by the second comparator 131 corresponds to 1 / 4 of each resonance period. The adaptive delay circuit 132 generates different delays according to different resonance periods, so that the falling edge of its output valley mark signal VA lags behind the falling edge of the output signal of the second comparator 131 by 1 / 4 resonance period, thereby ensuring that the falling edge of the valley mark signal VA is at 1 / 2 resonance period, that is, at the valley bottom.

[0068] Please refer to Figure 6 , Figure 6The circuit diagram of the dynamic threshold generating unit in the valley locking circuit of the present invention includes: a counter 141, a delay selection circuit 142 and an increase / decrease judgment circuit 143. The counter 141 receives the valley flag signal VA, and outputs a valley counting signal reflecting the number of valleys in the current cycle according to the valley flag signal VA, and outputs the valley counting signal to the increase / decrease judgment circuit 143 and the delay selection circuit 142; the increase / decrease judgment circuit 143 can be composed of a shift register to realize the recording of the number of valleys. If the number of valleys in the current cycle increases compared with the number of valleys in the previous cycle, a delay signal is output to the delay selection circuit 142; if the number of valleys in the current cycle decreases compared with the number of valleys in the previous cycle, an advance signal is output to the delay selection circuit 142. The delay signal and the advance signal are actually different levels of the same judgment signal. The delay selection circuit 142 controls the valley selection signal VAEN to delay a hysteresis time or advance a hysteresis time in the next cycle according to the high and low levels of the judgment signal. The delayed or advanced valley selection signal VAEN serves as the valley selection signal VAEN_NEXT of the next cycle, and the valley selection signal VAEN_NEXT serves as the valley selection signal VAEN in the next cycle.

[0069] Please refer to Figure 7 , Figure 7 The circuit diagram of the valley selection unit in the valley locking circuit of the present invention is shown in FIG. 1 . The valley selection unit 15 is used to select the power tube M of the current cycle according to the valley selection signal VAEN generated in the previous cycle. P Opened at the nth trough.

[0070] The valley selection unit 15 includes: a second D flip-flop 151 and a third NOT gate 152. The D input terminal of the second D flip-flop 151 inputs the valley selection signal VAEN of the current cycle, the trigger terminal inputs the valley mark signal VA, and the Q output terminal outputs the power tube ON signal; P The gate drive signal G_M P After the valley selection signal VAEN becomes high level, the valley mark signal VA first appears a falling edge, and the power tube turn-on signal ON becomes high level. After the power tube M passes through the driving circuit, P The gate drive signal G_M P becomes high level, the gate drive signal G_M P After becoming a high level, the power tube turn-on signal ON is reset to a low level.

[0071] like Figure 8 , is a timing diagram of key signal waveforms of the valley locking circuit of the present invention.

[0072] The valley mark signal VA is on the power tube M PThe switch node voltage V DS (ie, drain voltage) generates a low-level narrow pulse at the trough of resonance; the trough selection signal VAEN generates a low-level narrow pulse at the trough of resonance of the power tube M in each cycle; P The driving voltage signal G_M P The rising edge of the trough selection signal VAEN is reset to a low level, and then the pulse frequency modulation unit (PFM) controls when the trough selection signal VAEN becomes a high level within a single cycle; the first narrow pulse of the trough mark signal VA after the trough selection signal VAEN becomes a high level makes the power tube M P The driving voltage signal G_M P becomes high level.

[0073] In the first stage, the trough selection signal VAEN makes the power tube M P From the first wave valley to the second wave valley, the frequency is reduced, and the power tube M in the next cycle P The conduction time of the power tube M is lengthened to maintain energy conservation. If the low level time of the valley selection signal VAEN remains unchanged, as shown by the dotted line in the figure, the first valley will be selected again in the next cycle to turn on the power tube M. P In order to avoid this situation, the valley selection signal VAEN of the next cycle is delayed by a hysteresis time TD. 1,2 , so that the power tube M is still selected to be turned on in the second valley P .

[0074] In the second stage, as the input voltage of the flyback converter increases or the load becomes lighter, the valley selection signal VAEN selects the second valley to turn on the power tube M. P Change to select the third wave valley to open the power tube M P , the frequency decreases, and similarly, the power tube M of the next cycle P The conduction time becomes longer. If the low level time of the valley selection signal VAEN remains unchanged, the second valley will be selected again in the next cycle to turn on the power tube M. P In order to avoid this situation, the valley selection signal VAEN of the next cycle is delayed by a hysteresis time TD. 2,3 , so that the third valley is still selected to open the power tube M P .

[0075] In the third stage, the input voltage of the converter decreases or the load becomes heavier, and the valley selection signal VAEN selects the third valley to turn on the power tube M. P Change to select the second valley to open the power tube M P , the frequency increases, and the conduction time of the power tube in the next cycle becomes shorter. If the low level time of the valley selection signal VAEN remains unchanged, the third valley will be selected again in the next cycle to turn on the power tube M. P In order to avoid this situation, the valley selection signal VAEN is advanced by a hysteresis time TD.3,2 , so that the power tube M is still selected to be turned on in the second valley P Since the frequency change amplitude from the first valley opening to the second valley opening is greater than the frequency change amplitude from the second valley opening to the third valley opening, the hysteresis time TD needs to be set. 1,2 The time length is greater than the hysteresis time TD 2,3 , ensuring that there is enough hysteresis to satisfy energy conservation when switching between different troughs, so that the troughs do not switch repeatedly.

[0076] like Fig. 9 , is a flowchart of the valley locking method of the present invention. First, the valley number of each cycle is detected and recorded; second, the valley number of the current cycle is compared with the valley number of the previous cycle recorded. If the valley number decreases, the valley selection signal of the next cycle is advanced by a hysteresis time TD, and a new valley selection signal is generated for the valley selection of the next cycle; if the valley number increases, the valley selection signal of the next cycle is delayed by a hysteresis time TD, and a new valley selection signal is generated for the valley selection of the next cycle. The valley selection signal is generated by the error signal through the hysteresis compensation link and the frequency modulation link.

[0077] In addition, the hysteresis time may vary with different changes in the number of troughs and is not a fixed time.

[0078] It should be clear that the implementation methods of the present invention are not limited to this. According to the above content, in accordance with the common technical knowledge and customary means in the field, without departing from the above basic technical ideas of the present invention, the valley dynamic locking method and circuit of the present invention have other implementation methods; therefore, the present invention can also make other various forms of modification, replacement or change, all of which fall within the scope of protection of the present invention.

Claims

1. A valley locking method for a converter, characterized in that: include: Detecting the resonant waveform of the switch node voltage of the power tube of the converter in the current cycle to obtain the number of valleys of the resonant waveform; Compare the detected number of troughs of the current cycle with the number of troughs of the previous cycle; If the number of troughs in the current cycle increases compared to the number of troughs in the previous cycle, the time threshold for trough switching will be delayed by a hysteresis time in the next cycle; If the number of troughs in the current cycle is smaller than that in the previous cycle, the time threshold for trough switching is advanced by a hysteresis time in the next cycle; In one cycle, the hysteresis time corresponding to a smaller number of troughs is greater than the hysteresis time corresponding to a larger number of troughs.

2. The valley locking method for a converter according to claim 1, characterized in that: The time threshold of the valley switching is the moment when the rising edge or the falling edge of the valley selection signal used to control the turning on of the power tube is generated.

3. The valley locking method for a converter according to claim 1, characterized in that: The valley locking method further comprises the step of slowing down the modulation speed of the pulse frequency modulation unit by performing hysteresis compensation on the error signal fed back by the control loop.

4. A valley locking circuit for a converter, characterized in that: include: A pulse frequency modulation unit, a trough detection unit, a dynamic threshold generation unit and a trough selection unit; The pulse frequency modulation unit is used to generate a valley selection signal for controlling the opening of the power tube of the converter, and transmit the valley selection signal to the dynamic threshold generation unit and the valley selection unit; The valley detection unit is used to detect the voltage waveform of the switch node of the power tube of the converter and generate a valley mark signal indicating the position of the resonance valley; The dynamic threshold generating unit is used to receive the trough mark signal and the trough selection signal, and count the number of troughs in the current cycle according to the trough mark signal; if the number of troughs in the current cycle increases compared with the number of troughs in the previous cycle, the trough selection signal is controlled to be delayed by a hysteresis time in the next cycle; if the number of troughs in the current cycle decreases compared with the number of troughs in the previous cycle, the trough selection signal is controlled to be advanced by a hysteresis time in the next cycle; within a cycle, the hysteresis time corresponding to a smaller number of troughs is greater than the hysteresis time corresponding to a larger number of troughs; The valley selection unit is used to receive the valley flag signal and the valley selection signal, and output a power tube turning-on signal for turning on a power tube according to the valley flag signal and the valley selection signal.

5. The valley lock circuit for a converter as claimed in claim 4, characterized in that: It also includes a hysteresis compensation unit, wherein the input terminal of the hysteresis compensation unit is used to input the error signal fed back by the control loop, and to generate a compensation signal whose phase lags relative to the error signal according to the error signal; The pulse frequency modulation unit receives the compensation signal, and modulates the charging current of a capacitor disposed inside the pulse frequency modulation unit according to the difference between the compensation signal and a reference voltage, so that the charging cycle of the capacitor changes to generate the valley selection signal.

6. The valley locking circuit for a converter as claimed in claim 5, characterized in that: The hysteresis compensation unit includes: a narrow pulse generator, a first switch, a resistor R1, a capacitor C1, a resistor R2, a buffer and a resistor R3; one end of the first switch is connected to the error signal and one end of the resistor R2, the other end of the first switch is connected to one end of the resistor R1, and the control end of the first switch is connected to the output end of the narrow pulse generator; the other end of the resistor R1 is connected to the positive input end of the buffer and the first plate of the capacitor C1; the second plate of the capacitor C1 is grounded; the negative input end of the buffer is connected to its own output end and one end of the resistor R3; the other end of the resistor R2 is connected to the other end of the resistor R3, and the connection point between the resistor R2 and the resistor R3 is used to output the compensation signal.

7. The valley lock circuit for a converter as claimed in claim 6, characterized in that: The pulse frequency modulation unit includes: a transconductance amplifier, a capacitor C2, a second switch, a first comparator, an AND gate, a first NOT gate, a high level generator, a first D flip-flop and a second NOT gate; The positive input terminal of the transconductance amplifier is connected to the compensation signal, and the negative input terminal is connected to the first reference voltage. The output terminal of the transconductance amplifier is connected to the first plate of the capacitor C2, one end of the second switch and the negative input terminal of the first comparator; the second plate of the capacitor C2 is grounded; the other end of the second switch is grounded, and its control end is connected to the output terminal of the AND gate; the positive input terminal of the first comparator is connected to the second reference voltage, and the output terminal of the first comparator is connected to the trigger terminal of the first D flip-flop and the input terminal of the first NOT gate; the output terminal of the first NOT gate is connected to an input terminal of the AND gate; the other input terminal of the AND gate is connected to the gate drive signal of the power tube; the D input terminal of the first D flip-flop is connected to the high level generator, and the Q output terminal of the first D flip-flop is used to output the valley selection signal; the input terminal of the second NOT gate is connected to the gate drive signal of the power tube, and the output terminal is connected to the reset terminal of the first D flip-flop.

8. The valley lock circuit for a converter as claimed in claim 7, characterized in that: The valley detection unit includes: a second comparator and an adaptive delay circuit; the positive input terminal of the second comparator is connected to the switch node voltage of the power tube, the negative input terminal is connected to the threshold voltage, and the output terminal is connected to the input terminal of the adaptive delay circuit; the output of the adaptive delay circuit is used to output the valley mark signal.

9. The valley lock circuit for a converter as claimed in claim 8, characterized in that: The dynamic threshold generating unit includes a counter, an increase / decrease judgment circuit and a delay selection circuit; The counter is used to receive the valley mark signal output by the valley detection unit, and output a valley counting signal reflecting the number of valleys in the current cycle according to the valley mark signal; The increase / decrease judgment circuit receives the trough counting signal, and judges whether the trough number of the current cycle increases or decreases according to the recorded trough number of the previous cycle, and outputs a judgment signal reflecting the increase or decrease of the trough number of the current cycle; The delay selection circuit is used to receive the valley counting signal, the judgment signal and the valley selection signal. If the judgment signal reflects that the current valley number increases compared with the valley number of the previous cycle, the valley selection signal is controlled to be delayed by a hysteresis time in the next cycle; if the judgment signal reflects that the current cycle valley number decreases compared with the valley number of the previous cycle, the valley selection signal is controlled to be advanced by a hysteresis time in the next cycle.

10. The valley lock circuit for a converter as claimed in claim 9, characterized in that: The valley selection unit includes: a second D flip-flop and a third NOT gate; the D input terminal of the second D flip-flop is connected to the valley selection signal of the current cycle, the trigger terminal of the second D flip-flop is connected to the valley mark signal, the Q output terminal outputs a power tube turn-on signal, and the reset terminal is connected to the output terminal of the third NOT gate; the input terminal of the third NOT gate is connected to the gate drive signal of the power tube.

11. A valley locking method for a converter, characterized in that: include: Detecting the number of valleys of the switching node voltage resonance of the power tube of the converter in the current cycle; The detected trough number of the current cycle is compared with the trough number of the previous cycle. If the trough number of the current cycle increases compared with the trough number of the previous cycle, the trough selection signal used to control the opening of the power tube is delayed by a hysteresis time in the next cycle; if the trough number of the current cycle is reduced compared with the trough number of the previous cycle, the trough selection signal is controlled to be advanced by a hysteresis time in the next cycle; within a cycle, the hysteresis time corresponding to a smaller trough number is greater than the hysteresis time corresponding to a larger trough number.

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