Fan-in packaging structure and preparation method thereof

Abstract

The present invention provides a fan-in type packaging structure and a preparation method thereof, which relate to the field of semiconductor packaging technology. The fan-in type packaging structure includes a base chip, a structural carrier, a stacked chip, a wiring dielectric layer, a connection wiring layer, an extended wiring layer, a dielectric combination layer and solder balls, and the extended wiring layer and the base chip are staggered. Compared with the prior art, the present invention completes the stacking packaging of chips by mounting stacked chips in accommodating grooves, thereby improving the integration of chip packaging, and the provision of accommodating grooves also reduces the packaging height, which is conducive to the miniaturization of chips. In addition, by arranging the connection wiring layer and the extended wiring layer above the structural carrier, the extended wiring layer can increase the integration of the circuit layer, which can greatly increase the number of solder balls on the I / O end of the package, improve the wiring density and wiring area, and improve product performance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a fan-in packaging structure and a preparation method thereof. Background Art

[0002] With the rapid development of the semiconductor industry, wafer-level packaging has been categorized into fan-out and fan-in. Fan-out packaging involves dicing the wafer into individual dies, then mounting and encapsulating the dies. This rewiring of the dies creates more wiring area, allowing for more I / O pads and increasing density. However, fan-out packaging places higher demands on laser aperture opening and die placement (for example, equipment accuracy and package flatness), as well as requiring more molding compound and filler. Consequently, plastic encapsulation warpage continues to plague product yields.

[0003] Fan-in packaging involves plastic-sealing the entire wafer and then wiring each die on the wafer individually. Conventional technology limits the I / O pads for each die to the area directly above the surface of the corresponding die. Given the limited area of ​​the die, the number of I / O pads is limited by the spacing between the pads, which in turn limits the number of I / O solder balls that can be packaged on the surface of the die. This results in low wiring integration and a small wiring area, impacting product performance. Furthermore, existing fan-in packaging typically employs a single-chip structure or a multi-chip tiled structure, making chip stacking difficult and resulting in low chip integration. This results in a larger package volume when multi-chip packaging is required, hindering the miniaturization of packaged products. Summary of the Invention

[0004] The present invention provides, for example, a fan-in package structure and its fabrication method, which can significantly increase the number of solder balls on the package's I / O terminals, thereby achieving higher wiring integration and a larger wiring area, thereby improving product performance. It also enables chip stacking, thereby increasing product integration.

[0005] The embodiments of the present invention can be implemented as follows:

[0006] In one aspect, the present invention provides a fan-in package structure, comprising:

[0007] substrate chip;

[0008] A structural carrier plate is provided on one side of the base chip, wherein the structural carrier plate is provided with an accommodating groove;

[0009] A stacked chip mounted in the accommodating groove;

[0010] A wiring dielectric layer is provided on a side of the structural carrier away from the base chip;

[0011] A connection wiring layer and an extension wiring layer are provided in the wiring dielectric layer;

[0012] A dielectric combination layer is provided on a side of the wiring dielectric layer away from the substrate chip;

[0013] and, solder balls disposed on the dielectric combination layer;

[0014] In which, the connecting wiring layer is electrically connected to the base chip and the stacking chip at the same time, and the stacking chip and the base chip are arranged correspondingly, the connecting wiring layer and the stacking chip are arranged correspondingly, and the extended wiring layer and the base chip are staggered; the width W2 of the cutting street of the structural carrier is smaller than the width W1 of the cutting street when the wafer with the base chip is cut; the extended wiring layer is at least partially located in the cutting street area of ​​the base chip.

[0015] Furthermore, the dielectric combination layer includes a metal layer and a coating dielectric layer, the wiring dielectric layer is arranged on the structural carrier, the connection wiring layer and the extended wiring layer are both arranged in the wiring dielectric layer, and the connection wiring layer partially penetrates the wiring dielectric layer, the connection wiring layer and the extended wiring layer are at least partially exposed to the wiring dielectric layer, the coating dielectric layer is arranged on the wiring dielectric layer, the metal layer is arranged on the coating dielectric layer and is connected to the connection wiring layer and the extended wiring layer, the solder ball is arranged on the metal layer, and is electrically connected to the connection wiring layer or the extended wiring layer through the metal layer.

[0016] Furthermore, a first solder pad is provided on the front side of the base chip, and a conductive column is provided on the structural carrier. The conductive column passes through the structural carrier and extends to the first solder pad. One end of the conductive column is connected to the connection wiring layer, and the other end is connected to the first solder pad, so that the connection wiring layer is electrically connected to the connection wiring layer through the conductive column.

[0017] Furthermore, the fan-in packaging structure further includes an encapsulation body, which covers a side of the base chip away from the structural carrier.

[0018] Furthermore, a buffer layer is coated around the base chip, and the encapsulation body is coated outside the buffer layer, so that the buffer layer is filled between the structural carrier and the encapsulation body.

[0019] Furthermore, an adhesive film layer is provided between the structural carrier and the base chip.

[0020] Furthermore, the accommodating groove passes through the structural carrier, and a buffer glue layer is formed between the sidewall of the accommodating groove and the stacked chips.

[0021] Furthermore, there are multiple base chips, and the multiple base chips are arranged at intervals on one side of the structural carrier. The structural carrier is provided with multiple accommodating grooves, and each of the accommodating grooves is mounted with the stacked chip. The multiple stacked chips are arranged in a one-to-one correspondence with the multiple base chips.

[0022] In another aspect, the present invention provides a method for preparing a fan-in package structure, for preparing the aforementioned fan-in package structure, the method comprising:

[0023] providing a wafer with a die;

[0024] Mounting a structural carrier on the surface of the other side of the wafer;

[0025] Cutting grooves on the structural carrier plate to form accommodating recesses;

[0026] Mounting stacked chips in the accommodating groove;

[0027] forming a wiring dielectric layer on the structural carrier;

[0028] cutting the wafer along predetermined cutting paths to form substrate chips;

[0029] forming a connection wiring layer and an extension wiring layer in the wiring dielectric layer;

[0030] forming a dielectric combination layer on the wiring dielectric layer;

[0031] forming solder balls on the dielectric combination layer;

[0032] In which, the connecting wiring layer is electrically connected to the base chip and the stacking chip at the same time, and the stacking chip and the base chip are arranged correspondingly, the connecting wiring layer and the stacking chip are arranged correspondingly, and the extended wiring layer and the base chip are staggered; the width W2 of the cutting street of the structural carrier is smaller than the width W1 of the cutting street when the wafer with the base chip is cut; the extended wiring layer is at least partially located in the cutting street area of ​​the base chip.

[0033] Furthermore, after the step of cutting the wafer along the preset cutting streets, the preparation method further comprises:

[0034] Filling colloid around the base chip to form a buffer layer;

[0035] An encapsulation body is formed on a side of the base chip away from the structural carrier.

[0036] Furthermore, before the step of forming a wiring dielectric layer on the structural carrier, the preparation method further comprises:

[0037] Cutting grooves on the structural carrier to form conductive holes;

[0038] Conductive material is electroplated in the conductive hole to form a conductive pillar.

[0039] The beneficial effects of the embodiments of the present invention include, for example:

[0040] The method for preparing a fan-in packaging structure provided by an embodiment of the present invention is to set a structural carrier on one side of the base chip, groove the structural carrier to form an accommodating groove, and then mount the stacked chip in the accommodating groove. Then, a wiring dielectric layer is prepared on the side of the structural carrier away from the base chip, and a connection wiring layer and an extension wiring layer are arranged in the wiring dielectric layer. Then, the preparation of the dielectric combination layer and the solder ball is completed to realize fan-in packaging, wherein the connection wiring layer is electrically connected to the base chip and the stacked chip at the same time, the stacked chip and the base chip are correspondingly arranged, the connection wiring layer and the stacked chip are correspondingly arranged, and the extension wiring layer and the base chip are staggered, so that the wiring range of the extension wiring layer exceeds the upper space of the base chip and the stacked chip, greatly increasing the wiring area. Compared with the existing technology, the present invention completes the stacking packaging of chips by mounting the stacked chips in the accommodating groove, thereby improving the integration of the chip packaging. In addition, the setting of the accommodating groove also reduces the packaging height, which is conducive to the miniaturization of the chip. In addition, by arranging the connection wiring layer and the extended wiring layer above the structural carrier board, the extended wiring layer can increase the integration of the circuit layer, which can greatly increase the number of I / O end solder balls of the package, increase the wiring density and wiring area, and improve product performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 A schematic diagram of a fan-in packaging structure provided by an embodiment of the present invention;

[0043] Figure 2 A schematic diagram of a fan-in package structure provided by an embodiment of the present invention in another embodiment;

[0044] Figures 3 to 13 A process flow chart of a method for preparing a fan-in packaging structure provided in an embodiment of the present invention.

[0045] Icon: 100-fan-in packaging structure; 110-base chip; 111-first solder pad; 113-adhesive film layer; 115-wafer; 120-structure carrier; 121-accommodating groove; 123-conductive column; 125-buffer adhesive layer; 130-stacked chip; 131-second solder pad; 140-wiring dielectric layer; 150-connection wiring layer; 160-extension wiring layer; 170-dielectric combination layer; 171-metal layer; 173-coated dielectric layer; 175-solder ball; 180-base carrier; 190-encapsulation; 191-buffer layer. DETAILED DESCRIPTION

[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0047] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0048] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0049] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the invention is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present invention.

[0050] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.

[0051] As disclosed in the background art, the use of traditional fan-out packaging requires higher requirements for laser aperture opening and chip mounting (for example, equipment accuracy and package flatness) and requires more molding compounds and fillers. The problem of plastic package warpage has always plagued product yield.

[0052] Furthermore, with traditional fan-in packaging, the entire wafer is plastic-encapsulated and then wiring is performed on each die. The I / O pads for each die are confined to the area directly above the die's surface. With this limited die area, the number of I / O pads is limited by the spacing between the pads. This, in turn, limits the number of I / O solder balls that can be packaged on the die's surface, resulting in low wiring integration and a smaller wiring area, impacting product performance.

[0053] Finally, the existing fan-in packaging structure cannot complete chip stacking, and the chip integration is low, resulting in a large package volume when multi-chip packaging is required, which is not conducive to the miniaturization of packaged products.

[0054] In order to solve the above problems, the present invention provides a novel fan-in packaging structure and a preparation method thereof. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict. Specific embodiments

[0056] This embodiment provides a fan-in package structure 100 that can significantly increase the number of I / O solder balls on the package, thereby achieving higher wiring integration and a larger wiring area, improving product performance, and enabling chip stacking to improve product integration.

[0057] Please refer to Figure 1 This embodiment provides a fan-in package structure 100, including a base chip 110, a structural carrier 120, a stacked chip 130, a wiring dielectric layer 140, a connection wiring layer 150, an extension wiring layer 160, a dielectric combination layer 170, and solder balls 175. The structural carrier 120 is arranged on one side of the base chip 110, and a receiving groove 121 is provided on the structural carrier 120. The stacked chip 130 is mounted in the receiving groove 121. The wiring dielectric layer 140 is arranged on the side of the structural carrier 120 away from the base chip 110. On the other side, the connection wiring layer 150 and the extended wiring layer 160 are arranged in the wiring dielectric layer 140, the dielectric combination layer 170 is arranged on the side of the wiring dielectric layer 140 away from the base chip 110, and the solder balls 175 are arranged on the dielectric combination layer 170, wherein the connection wiring layer 150 is electrically connected to the base chip 110 and the stacked chip 130 at the same time, and the stacked chip 130 and the base chip 110 are arranged correspondingly, the connection wiring layer 150 and the stacked chip 130 are arranged correspondingly, and the extended wiring layer 160 is staggered with the base chip 110.

[0058] In this embodiment, the width of the connecting wiring layer 150 is less than or equal to the width of the base chip 110, and the extended wiring layer 160 can extend to the two side edges of the wiring dielectric layer 140, so that its width is greater than the width of the base chip 110, and it can be staggered with the base chip 110, so that the wiring range of the extended wiring layer 160 exceeds the upper space of the base chip 110 and the stacked chip 130, greatly increasing the wiring area. This embodiment completes the stacked packaging of the chips by mounting the stacked chips 130 in the accommodating groove 121, thereby improving the integration of the chip packaging. The provision of the accommodating groove 121 also reduces the package height, which is conducive to the miniaturization of the chip. In addition, by arranging the connecting wiring layer 150 and the extended wiring layer 160 above the structural carrier 120, the extended wiring layer 160 can increase the integration of the circuit layer, which can significantly increase the number of I / O solder balls of the package, improve the wiring density and wiring area, and improve product performance.

[0059] It should be noted that, in this embodiment, the connection wiring layer 150 and the extension wiring layer 160 can be formed together and adopt a copper layer structure with good conductive properties.

[0060] In this embodiment, the dielectric combination layer 170 includes a metal layer 171 and a coating dielectric layer 173. The wiring dielectric layer 140 is arranged on the structural carrier 120. The connection wiring layer 150 and the extension wiring layer 160 are both arranged in the wiring dielectric layer 140, and the connection wiring layer 150 partially penetrates the wiring dielectric layer 140. The connection wiring layer 150 and the extension wiring layer 160 are at least partially exposed from the wiring dielectric layer 140. The coating dielectric layer 173 is arranged on the wiring dielectric layer 140. The metal layer 171 is arranged through the coating dielectric layer 173 and is connected to the connection wiring layer 150 and the extension wiring layer 160. The solder ball 175 is arranged on the metal layer 171 and is electrically connected to the connection wiring layer 150 or the extension wiring layer 160 through the metal layer 171. Specifically, the metal layer 171 can be a plurality of copper pillar structures spaced apart from each other, so as to be connected to the connection wiring layer 150 and the extended wiring layer 160 respectively. A solder ball 175 is provided on each copper pillar structure. Since the connection wiring layer 150 and the extended wiring layer 160 are both connected to the metal layer 171, and the metal layer 171 is provided with a solder ball 175, the design here of increasing the wiring area by connecting the wiring layer 150 and the extended wiring layer 160 can also increase the number of solder balls 175, thereby greatly increasing the number of solder balls on the I / O end of the package.

[0061] It should be noted that, in this embodiment, the base chip 110 can be formed by cutting the wafer 115. Specifically, the structural carrier 120 is mounted on one side of the wafer 115 by wafer mounting, and then the wafer 115 is separated from the cutting path on the wafer by laser cutting or mechanical cutting, thereby forming the base chip 110. This cutting process is consistent with the conventional fan-in structure.

[0062] In this embodiment, a first pad 111 is further provided on the front surface of the substrate chip 110, and a conductive pillar 123 is further provided on the structural carrier 120. The conductive pillar 123 penetrates the structural carrier 120 and extends to the first pad 111. One end of the conductive pillar 123 is connected to the connection wiring layer 150, and the other end is connected to the first pad 111, so that the connection wiring layer 150 is electrically connected to the connection wiring layer 150 through the conductive pillar 123. Specifically, the conductive pillar 123 can be an electroplated copper layer. Specifically, a laser groove can be formed on the structural carrier 120 to penetrate to the first pad 111 to form a conductive hole, and then a conductive material can be electroplated in the conductive hole to form the conductive pillar 123.

[0063] Furthermore, the fan-in package structure further includes an encapsulation body 190, which is coated on a side of the base chip 110 away from the structural carrier 120. Specifically, the encapsulation body 190 is coated on the base chip 110, which can play a good protective role.

[0064] In this embodiment, a buffer layer 191 is further coated around the substrate chip 110, and the encapsulant 190 is coated outside the buffer layer 191, so that the buffer layer 191 fills the space between the structural carrier 120 and the encapsulant 190. Specifically, the buffer layer 191 is disposed between the encapsulant 190 and the structural carrier 120 and surrounds the substrate chip 110. During actual fabrication, the buffer layer 191 can be formed first, and then the encapsulant 190 can be formed on the buffer layer 191. The thermal expansion coefficient of the material of the buffer layer 191 is smaller than that of the substrate chip 110 and also smaller than that of the encapsulant 190. By providing the buffer layer 191, when the packaged product is subjected to stress, the buffer layer 191 can deform preferentially, absorb stress, and act as a buffer, thereby resolving the warping problem caused by the warping of the encapsulant 190.

[0065] In other preferred embodiments of the present invention, the encapsulation body 190 may also be a backing film layer, which can also play a role in protecting the chip.

[0066] In this embodiment, an adhesive film layer 113 is further provided between the structural carrier 120 and the base chip 110. Specifically, when mounting the structural carrier 120 on the wafer 115, a layer of adhesive film layer 113 can be first applied, and then the structural carrier 120 can be attached. The provision of the adhesive film layer 113 allows the structural carrier 120 to be fixedly bonded to the wafer 115. This not only facilitates the subsequent cutting of the wafer 115 to form the base chip 110, but also enhances the overall structural strength. Furthermore, in the subsequent process of cutting the wafer 115 and slotting to form the accommodating recess 121, the adhesive film layer 113 can also serve as a stop layer to prevent damage to the structural carrier 120 during cutting, and also prevent damage to the base chip 110 during slotting. Furthermore, the conductive pillars 123 here need to pass through the adhesive film layer 113 to reach the first pads 111.

[0067] In this embodiment, the accommodating groove 121 extends through the structural carrier 120, and a buffering adhesive layer 125 is formed between the sidewalls of the accommodating groove 121 and the stacked chip 130. Specifically, a second solder pad 131 is provided on the stacked chip 130, and the second solder pad 131 is connected to the connection wiring layer 150 to achieve electrical connection. The provision of the buffering adhesive layer 125 can provide a good buffering effect, effectively protecting the stacked chip 130.

[0068] In this embodiment, the structural carrier 120 is located in the middle of the packaging structure, which can play a good role in limiting support and balancing the structural stress at both ends, so that the strength of the entire packaging structure is better. At the same time, it can prevent warping at both ends during the manufacturing process, thereby ensuring the stability of the structure.

[0069] See also Figure 2 In other preferred embodiments of the present invention, there can be multiple base chips 110, and the multiple base chips 110 are arranged at intervals on one side of the structural carrier 120. The structural carrier 120 is provided with multiple accommodating grooves 121, and each accommodating groove 121 is mounted with a stacking chip 130. The multiple stacking chips 130 are arranged in a one-to-one correspondence with the multiple base chips 110.

[0070] This embodiment further provides a method for preparing a fan-in package structure 100, which is used to prepare the aforementioned fan-in package structure 100. The method comprises the following steps:

[0071] S1: Provide a wafer 115 with dies.

[0072] Specifically, see Figure 3A wafer 115 is taken, on which a chip circuit layout is pre-prepared to form multiple dies, with adjacent dies separated by a preset distance. First bonding pads 111 are provided on the multiple dies on the front side of the wafer 115, and the first bonding pads 111 are also pre-prepared.

[0073] It should be noted that the thickness of the wafer in this embodiment is between 600-800 microns and may not be ground at this point to ensure its structural strength.

[0074] S2: Mounting the structure carrier 120 on one side of the wafer 115 .

[0075] Specifically, see Figure 4 The structural carrier 120 is mounted on the front side of the wafer 115. During mounting, a layer of adhesive film 113 is first applied, and then the structural carrier 120 is mounted. The adhesive film 113 acts as an adhesive. The structural carrier 120 can also be made of glass, silicon oxide, metal, etc., and the adhesive film 113 is a thermosetting material such as a high molecular weight epoxy polymer or phenolic, aldehyde, melamine formaldehyde, epoxy, unsaturated polyester, silicone, etc.

[0076] S3: A groove 121 is formed on the structural carrier plate 120.

[0077] Specifically, see Figure 5 After the structural carrier 120 is mounted, a groove can be formed on the structural carrier 120 by etching or laser grooving to form an accommodating groove 121, wherein the size of the accommodating groove 121 needs to be larger than the size of the stacked chip 130.

[0078] It should be noted that, during the etching or laser grooving process, the adhesive film layer 113 can act as a stop layer, that is, as an etching stop layer or a laser grooving stop layer, it can prevent the etching liquid or laser from damaging the underlying substrate chip 110, thereby ensuring the safety of the substrate chip 110.

[0079] S4 : Mounting the stacked chip 130 in the receiving groove 121 .

[0080] Specifically, see Figure 6 After the accommodating groove 121 is formed, the stacked chip 130 can be mounted. The bottom of the stacked chip 130 is fixed in the accommodating groove 121 by using a glue layer or silver paste. After curing, the accommodating groove 121 is filled with colloid again so that the colloid covers the side walls and surrounding areas of the stacked chip 130 to form a buffer glue layer 125, which plays a role in protecting the stacked chip 130.

[0081] See also Figure 7After the stacked chips 130 are mounted, it is necessary to form conductive holes in the structural carrier 120, and then electroplating a conductive material in the conductive holes to form conductive pillars 123. Specifically, laser grooving can be used to burn the structural carrier 120 and the adhesive film layer 113 to form the conductive holes, exposing the first pads 111 on the surface of the base chip 110. Then, electroplating is used again to form a copper layer in the conductive holes to form the conductive pillars 123, thereby leading out the circuit layer of the base chip 110.

[0082] S5 : forming a wiring dielectric layer 140 on the structural carrier 120 .

[0083] Specifically, see Figure 8 After the conductive pillars 123 are prepared, a liquid dielectric layer material, such as polyimide, can be evenly coated on the structural carrier 120 using a coating machine by spin coating or other methods. The material is then soft-baked on a hot plate to form a film. Finally, an oven is used to heat the dielectric material to accelerate the curing to a fully mature and stable state, forming a wiring dielectric layer 140. The dielectric material here can also be silicon nitride or other materials such as silicon nitride.

[0084] S6 : cutting the wafer 115 along the predetermined dicing streets to form base chips 110 .

[0085] Specifically, see Figure 9 The wafer 115 is cut and separated from the scribe line position on the back side of the wafer 115 by a cutting method (laser cutting or mechanical cutting), thereby forming the substrate chip 110. The scribe line position on the back side of the wafer 115 can be cut according to the scribe line position map on the wafer surface. Before the wafer 115 is received, the wafer scribe line position and scribe line position are scanned, and the map is uploaded to the server. When the back side of the wafer is cut, the scribe line position is downloaded from the server to facilitate back side cutting. This avoids the cutting offset problem caused by the lack of scribe lines on the back side in traditional technologies.

[0086] See also Figure 10 After forming the discrete substrate chips 110, a colloid can be filled around the substrate chips 110 to form a buffer layer 191. The encapsulation body 190 is then formed on the side of the substrate chips 110 facing away from the structural carrier 120. Specifically, the colloid can be filled at the scribe lines using printing or dispensing. Once the colloid solidifies, it forms the buffer layer 191, which surrounds the substrate chips 110 and provides protection. Furthermore, the thermal expansion coefficient of the material of the buffer layer 191 is smaller than that of the substrate chips 110 and the subsequent encapsulation body 190. When subjected to stress, it deforms preferentially, absorbing stress and addressing the stress caused by warping of the encapsulation body 190 during plastic encapsulation.

[0087] It should be noted that during the process of cutting the wafer 115, the adhesive film layer 113 can also serve as a stop layer, that is, as a cutting stop layer, preventing the cutter from continuing to cut into the structural carrier 120, thereby ensuring the structural integrity of the structural carrier 120 and allowing subsequent processes to proceed smoothly.

[0088] S7 : forming a connection wiring layer 150 and an extension wiring layer 160 in the wiring dielectric layer 140 .

[0089] See also Figure 11 After the backside process is completed, the structural carrier 120 is flipped over so that the wiring dielectric layer 140 faces upward. Then, patterned grooves are formed on the wiring dielectric layer 140, such as by exposure and development to form patterned openings. A metal layer, which can be a copper layer, is electroplated in the openings to form the connection wiring layer 150 and the extension wiring layer 160. The copper layer can also be prepared by physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, or chemical plating.

[0090] In this embodiment, the connection wiring layer 150 is electrically connected to both the base chip 110 and the stacked chip 130, and the stacked chip 130 and the base chip 110 are disposed in correspondence with each other. The connection wiring layer 150 and the stacked chip 130 are disposed in correspondence with each other, and the extended wiring layer 160 is disposed in a staggered manner relative to the base chip 110. Specifically, when forming the connection wiring layer 150, the patterned openings expose the conductive pillars 123 and the second pads 131 of the stacked chip 130, thereby electrically connecting the connection wiring layer 150 to the base chip 110 through the conductive pillars 123 and directly electrically connecting to the stacked chip 130.

[0091] S8 : forming a dielectric combination layer 170 on the wiring dielectric layer 140 .

[0092] Specifically, see Figure 12 First, a cladding dielectric layer 173 is formed on the wiring dielectric layer 140, and then a metal layer 171 is provided through the cladding dielectric layer 173. After forming the connection wiring layer 150 and the expansion wiring layer 160, the dielectric material can be spin-coated again and solidified to form the cladding dielectric layer 173. Then, laser grooves / holes are formed in the cladding dielectric layer 173, and then a metal layer, such as a copper layer, is electroplated in the opening grooves using an electroplating process to form the metal layer 171. The metal layer 171 is exposed on the cladding dielectric layer 173 and is connected downward to the connection wiring layer 150 and the expansion wiring layer 160.

[0093] S9 : forming solder balls 175 on the dielectric combination layer 170 .

[0094] Specifically, see Figure 13A ball planting process is performed on the metal layer 171 by screen printing or ball planting to form solder balls 175. The solder balls 175 can be made of SnAg, SnAgCu, etc. Finally, a cutting process is performed again to cut the structure carrier 120 to form the final product.

[0095] It should be noted that during dicing, the width W2 of the dicing street on the structural carrier 120 is smaller than the width W1 of the dicing street on the wafer 115. This allows for a larger dicing street when forming the base chip 110. This in turn allows the extended wiring layer 160 to be offset from the base chip 110, enabling rewiring on the structural carrier 120 and increasing the wiring area and density. For example, the dicing street width W1 on the wafer 115 is 80 μm, while the dicing street width W2 on the structural carrier 120 is 10 μm, resulting in a final product with a width greater than that of the base chip 110.

[0096] It should also be noted that in this embodiment, the extended wiring layer 160 utilizes the distance difference between the scribe lines. Specifically, the extended wiring layer 160 is at least partially located in the scribe line area of ​​the substrate chip 110, thereby expanding its wiring area. Furthermore, the extended wiring layer 160 is at least partially located in the conventional scribe line area, making the scribe line area in this embodiment narrower than that of conventional processes. This frees up more space for the extended wiring layer 160 to perform wiring, further increasing the product's wiring area.

[0097] When multiple substrate chips 110 and stacked chips 130 are present in a single product, the number of substrate chips 110 corresponds to the number of stacked chips 130. Stacked chips 130 are upgraded based on the substrate chip 110. If a problem is discovered during tape-out testing of the substrate chip 110, the stacked chips 130 can be directly stacked to upgrade the substrate chip 110. The structural carrier 120 and the substrate carrier 180 are of the same size (e.g., 6 inches, 8 inches, 12 inches, 24 inches, etc.). For example, the substrate chip 110 measures 5x5 mm, and the stacked chips 130 measures 2x2 mm, resulting in a re-cut product size of 7x7 mm.

[0098] In summary, the method for preparing the fan-in package structure 100 provided in this embodiment comprises disposing a structural carrier 120 on one side of a base chip 110, slotting the structural carrier 120 to form an accommodating recess 121, mounting the stacked chip 130 in the accommodating recess 121, and then preparing a wiring dielectric layer 140 on the side of the structural carrier 120 away from the base chip 110. A connection wiring layer 150 and an extension wiring layer 160 are arranged in the wiring dielectric layer 140. Then, a dielectric combination layer 170 and solder balls 175 are prepared to achieve a fan-in package. The connection wiring layer 150 is electrically connected to both the base chip 110 and the stacked chip 130. The stacked chip 130 and the base chip 110 are disposed in correspondence with each other, the connection wiring layer 150 and the stacked chip 130 are disposed in correspondence with each other, and the extension wiring layer 160 is staggered with the base chip 110. This allows the wiring range of the extension wiring layer 160 to extend beyond the upper space of the base chip 110 and the stacked chip 130, significantly increasing the wiring area. Compared to existing technologies, this embodiment achieves chip stacking by mounting stacked chips 130 within accommodating recesses 121, improving the chip package's integration. The provision of accommodating recesses 121 also reduces package height, facilitating chip miniaturization. Furthermore, by arranging connecting wiring layer 150 and extended wiring layer 160 above structural carrier 120, extended wiring layer 160 increases the integration of the circuit layer, significantly increasing the number of I / O solder balls on the package, improving wiring density and area, and enhancing product performance.

[0099] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A fan-in packaging structure, characterized in that: include: substrate chip; A structural carrier plate is provided on one side of the base chip, wherein the structural carrier plate is provided with an accommodating groove; A stacked chip mounted in the accommodating groove; A wiring dielectric layer is provided on a side of the structural carrier away from the base chip; A connection wiring layer and an extension wiring layer are provided in the wiring dielectric layer; A dielectric combination layer is provided on a side of the wiring dielectric layer away from the substrate chip; and, solder balls disposed on the dielectric combination layer; In which, the connecting wiring layer is electrically connected to the base chip and the stacking chip at the same time, and the stacking chip and the base chip are arranged correspondingly, the connecting wiring layer and the stacking chip are arranged correspondingly, and the extended wiring layer and the base chip are staggered; the width W2 of the cutting street of the structural carrier is smaller than the width W1 of the cutting street when the wafer with the base chip is cut; the extended wiring layer is at least partially located in the cutting street area of ​​the base chip.

2. The fan-in package structure according to claim 1, wherein: The dielectric combination layer includes a metal layer and a coating dielectric layer, the wiring dielectric layer is arranged on the structural carrier, the connection wiring layer and the extended wiring layer are both arranged in the wiring dielectric layer, and the connection wiring layer partially penetrates the wiring dielectric layer, the connection wiring layer and the extended wiring layer are at least partially exposed from the wiring dielectric layer, the coating dielectric layer is arranged on the wiring dielectric layer, the metal layer is arranged through the coating dielectric layer and is connected to the connection wiring layer and the extended wiring layer, the solder ball is arranged on the metal layer and is electrically connected to the connection wiring layer or the extended wiring layer through the metal layer.

3. The fan-in package structure according to claim 1, wherein: A first pad is also provided on the front side of the base chip, and a conductive column is also provided on the structural carrier. The conductive column passes through the structural carrier and extends to the first pad. One end of the conductive column is connected to the connection wiring layer, and the other end is connected to the first pad, so that the connection wiring layer is electrically connected to the connection wiring layer through the conductive column.

4. The fan-in package structure according to claim 1, wherein: The fan-in packaging structure further includes an encapsulation body, which covers a side of the base chip away from the structural carrier.

5. The fan-in package structure according to claim 4, wherein: The base chip is further covered with a buffer layer, and the encapsulation body is covered outside the buffer layer, so that the buffer layer is filled between the structural carrier and the encapsulation body.

6. The fan-in package structure according to claim 1, wherein: An adhesive film layer is further provided between the structural carrier and the base chip.

7. The fan-in package structure according to claim 1, wherein: The accommodating groove passes through the structural carrier, and a buffer glue layer is formed between the sidewall of the accommodating groove and the stacked chips.

8. The fan-in package structure according to any one of claims 1 to 7, wherein: There are multiple base chips, and the multiple base chips are arranged at intervals on one side of the structural carrier. The structural carrier is provided with multiple accommodating grooves, and each of the accommodating grooves is mounted with the stacked chip. The multiple stacked chips are arranged in a one-to-one correspondence with the multiple base chips.

9. A method for preparing a fan-in package structure, for preparing the fan-in package structure according to any one of claims 1 to 8, characterized in that: The preparation method comprises: providing a wafer with a die; Mounting a structural carrier on one side of the wafer surface; Cutting grooves on the structural carrier plate to form accommodating recesses; Mounting stacked chips in the accommodating groove; forming a wiring dielectric layer on the structural carrier; cutting the wafer along predetermined cutting paths to form substrate chips; forming a connection wiring layer and an extension wiring layer in the wiring dielectric layer; forming a dielectric combination layer on the wiring dielectric layer; forming solder balls on the dielectric combination layer; cutting the structural carrier plate; In which, the connecting wiring layer is electrically connected to the base chip and the stacking chip at the same time, and the stacking chip and the base chip are arranged correspondingly, the connecting wiring layer and the stacking chip are arranged correspondingly, and the extended wiring layer and the base chip are staggered; the width W2 of the cutting street of the structural carrier is smaller than the width W1 of the cutting street when the wafer with the base chip is cut; the extended wiring layer is at least partially located in the cutting street area of ​​the base chip.

10. The method for preparing a fan-in package structure according to claim 9, wherein: After the step of cutting the wafer along the preset cutting streets, the preparation method further comprises: Filling colloid around the base chip to form a buffer layer; An encapsulation body is formed on a side of the base chip away from the structural carrier.

11. The method for preparing a fan-in package structure according to claim 9, wherein: Before the step of forming a wiring dielectric layer on the structural carrier, the preparation method further includes: Cutting grooves on the structural carrier to form conductive holes; Conductive material is electroplated in the conductive hole to form a conductive pillar.

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