An SGT-MOSFET cell, a manufacturing method thereof, and an electronic device

Abstract

An SGT-MOSFET cell comprises an N-type substrate (1), an N-epitaxial layer (2), a trench field oxide layer (3), a first isolation oxide layer (4A), a second isolation oxide layer (4B), a gate oxide layer (5), a first shield gate (6A), a second shield gate (6B), a P-well (7), an N+ source region (8), a dielectric layer (9), a back metal (10), a control gate (11), a trench (12), a front metal (13), and a contact hole (14), which are sequentially generated; the conductive polysilicon of the first shield gate (6A) is used for connecting the source potential, and the conductive polysilicon of the second shield gate (6B) is floating; thus, the electric field at the corner of the first shield gate (6A) in the middle of the trench (12) can be raised during use, while the electric field at the corner of the second shield gate (6B) and the bottom of the entire trench (12) can be reduced, so that the longitudinal electric field distribution of the drift region deviates from the wavy distribution and approaches a rectangular shape, the electric field distribution is optimized, and the breakdown voltage of the device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to an SGT-MOSFET cell, a manufacturing method thereof and an electronic device. BACKGROUND

[0002] The SGT-MOSFET (Split-Gate-Trench-MOSFET) structure has a charge coupling effect, introduces horizontal depletion on the basis of vertical depletion (P-Body / N-Epi junction) of a traditional trench MOSFET, changes the electric field distribution of the device from a triangular shape to a nearly rectangular wave shape. In the case of using the same doping concentration of an epitaxial specification, the device can obtain a higher breakdown voltage, and the structure is widely used in the field of medium and low voltage power devices.

[0003] As shown in Figure 1 is a schematic diagram of a cross-sectional structure of a traditional SGT-MOSFET (the passivation layer is not shown in the figure), in which 1 is an N+ substrate, 2 is an N- epitaxial layer, 3 is a field oxide layer, 4 is an isolation oxide layer between a shield gate and a control gate, 5 is a gate oxide layer, 6 is a shield gate, 7 is a P well, 8 is an N+ source region, 9 is a dielectric layer, 10 is a back metal, 11 is a control gate, 12 is a trench, 13 is a front metal, and 14 is a contact hole. A trench is first formed by etching, and then a shield electrode dielectric layer, usually a thick oxide layer, is grown in the trench to achieve charge balance. The breakdown voltage of the source and drain of the SGT-MOSFET with this structure is controlled by the thickness of the oxide layer, and the higher the breakdown voltage, the thicker the oxide layer thickness needs to be. For a 100V device, the oxide layer thickness has reached about 6000A. Therefore, the trench CD (critical dimension, which refers to the width of the trench) needs to be defined relatively wide (the trench CD of a 100V device needs to be more than 1um) in the design of the device. However, a mainstream direction of the design of the current SGT (shield gate transistor) device is to obtain a lower Rsp (on-resistance per unit area) by trying to reduce the size of the unit cell as much as possible. The characteristics of the traditional SGT-MOSFET structure make it difficult to further reduce the cell size, which obviously hinders the development of the device itself.

[0004] It should be noted that the information disclosed in the above background section is only for understanding the background of the present application, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The present application aims to overcome the shortcomings of the traditional SGT-MOSFET structure in the background art, which makes it difficult to further reduce the cell size and hinders the development of the device itself, and provides an SGT-MOSFET cell, a manufacturing method thereof and an electronic device.

[0006] To achieve the above object, the present application adopts the following technical solutions:

[0007] The SGT-MOSFET cell comprises an N-type substrate (1), an N-epitaxial layer (2), a trench field oxide layer (3), a first isolation oxide layer (4A), a second isolation oxide layer (4B), a gate oxide layer (5), a first shield gate (6A), a second shield gate (6B), a P-well (7), an N+ source region (8), a dielectric layer (9), a back metal (10), a control gate (11), a trench (12), a front metal (13), and a contact hole (14). The conductive polysilicon of the first shield gate (6A) is used to connect the source potential, and the conductive polysilicon of the second shield gate (6B) is floating. Thus, the electric field at the corner of the first shield gate (6A) in the middle of the trench (12) can be raised during use, and the electric field at the corner of the second shield gate (6B) and the bottom of the entire trench (12) can be reduced, so that the longitudinal electric field distribution of the drift region deviates from the wave-shaped distribution and approaches a rectangular shape, the electric field distribution is optimized, and the breakdown voltage of the device is improved.

[0008] Further, the control gate (11) is an N-type control gate (11), the first isolation oxide layer (4A) is located between the first shield gate (6A) and the control gate (11), and the second isolation oxide layer (4B) is located between the first shield gate (6A) and the second shield gate (6B).

[0009] Further, the thickness of the first isolation oxide layer (4A) between the first shield gate (6A) and the N-type control gate (11) is greater than the thickness of the second isolation oxide layer (4B) between the first shield gate (6A) and the second shield gate (6B).

[0010] Further, when the depth of the trench (12) is 9 microns, the breakdown voltage is 125V-150V.

[0011] Further, the thickness of the first isolation oxide layer (4A) between the first shield gate (6A) and the second shield gate (6B) and the control gate (11) is between 0.2 microns and 0.5 microns.

[0012] Further, the depth of the contact hole (14) into silicon is 0.3-0.6 microns.

[0013] A split gate trench metal oxide semiconductor field effect transistor is provided, comprising the SGT-MOSFET cell according to any one of the preceding embodiments.

[0014] A medium-low voltage power device is provided, comprising the split gate trench metal oxide semiconductor field effect transistor according to the preceding embodiment.

[0015] An electronic device is provided, comprising the medium-low voltage power device according to the preceding embodiment.

[0016] The application provides a manufacturing method of SGT-MOSFET, which comprises the following steps:

[0017] A. forming an N- epitaxial layer on an N+ substrate, and forming a groove on the N- epitaxial layer;

[0018] B. growing a field oxide layer on the sidewall of the groove;

[0019] C. depositing, doping and diffusing polycrystal for the first time, and etching the polycrystal to form a second shielding gate;

[0020] D. heat oxidation to form a second isolation oxide layer;

[0021] E. depositing, doping and diffusing polycrystal for the second time, and etching the polycrystal to form a first shielding gate;

[0022] F. etching the oxide layer to the top of the first shielding gate, then performing gate oxidation, and then depositing, doping and diffusing polycrystal, and polishing to remove the polycrystal and the oxide layer on the surface of the wafer to form a first isolation oxide layer and a control gate;

[0023] G. performing boron implantation and diffusion to form a P well, and then performing arsenic implantation and diffusion to form an N+ source region;

[0024] H. depositing to form a dielectric layer;

[0025] I. etching a contact hole into the silicon to form a contact hole, and performing P-type high-doped implantation on the contact hole;

[0026] J. performing front metal sputtering, photolithography and etching to form a front metal;

[0027] K. thinning the back and forming a back metal.

[0028] Further, the dielectric layer material in step H comprises two dielectric layers, i.e. a USG layer and a PSG layer, and the USG layer is deposited first, and then the PSG layer is deposited.

[0029] Further, the polishing in step F adopts chemical mechanical polishing (CMP).

[0030] Further, the control gate in step F adopts an N-type control gate.

[0031] The application has the following beneficial effects:

[0032] 1. In the case of the same groove depth, the SGT-MOSFET double-shielding gate structure can obtain a greater breakdown voltage than the traditional single-shielding gate structure, so that the groove depth can be reduced, and correspondingly, the epitaxial layer thickness can be reduced, so that the specific on-resistance can be reduced, and the chip area can be saved.

[0033] 2、The thickness of the trench field oxide layer of the structure is less than that of the conventional structure, so that smaller cell size and greater cell density can be obtained, and the specific on-resistance can be reduced, and the chip area can be saved. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a schematic diagram of a cross section of a SGT-MOSFET cell in the prior art;

[0035] Figure 2 is a schematic diagram of a cross section of a SGT-MOSFET cell in an embodiment of the present application;

[0036] Figure 3A is a schematic diagram of a cross section of a SGT-MOSFET cell after trench etching in an embodiment of the present application;

[0037] Figure 3B is a schematic diagram of a cross section of a SGT-MOSFET cell after field oxide layer formation in an embodiment of the present application;

[0038] Figure 3C is a schematic diagram of a cross section of a SGT-MOSFET cell after second shield gate formation in an embodiment of the present application;

[0039] Figure 3D is a schematic diagram of a cross section of a SGT-MOSFET cell after second isolation oxide layer formation in an embodiment of the present application;

[0040] Figure 3E is a schematic diagram of a cross section of a SGT-MOSFET cell after first shield gate formation in an embodiment of the present application;

[0041] Figure 3F is a schematic diagram of a cross section of a SGT-MOSFET cell after control gate formation in an embodiment of the present application;

[0042] Figure 3G is a schematic diagram of a cross section of a SGT-MOSFET cell after N+ source region formation in an embodiment of the present application;

[0043] Figure 3H is a schematic diagram of a SGT-MOSFET cell in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The embodiments of the present application will be described in detail below. It should be emphasized that the following description is only exemplary, and is not intended to limit the scope of the present application and its applications.

[0045] It is to be noted that when an element is referred to as being "fixed" or "set" on another element, it can be directly on the other element or indirectly on the other element with intervening elements. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or indirectly connected to the other element with intervening elements. Further, the connection can be for fixed or coupling or communication purposes.

[0046] It is to be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like, specify relative positions or orientations of an apparatus or element as shown in the drawings and are used for convenience in describing the present embodiments and the principles thereof, but do not limit the scope of the present application to the positions or orientations shown in the drawings. Thus, it is to be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like, are used in the description and in the claims not to limit the scope of the present application to the positions or orientations shown in the drawings, but to encompass different positions or orientations of the apparatus or element.

[0047] In addition, the terms "first", "second", "third", etc. are used herein only to describe different instances, and do not imply a relative importance or a specific number of the technical features indicated thereby. Thus, the features defined with "first", "second", "third", etc. can include one or more of the features explicitly or implicitly. In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0048] The problem of the electric field distribution in the conventional SGT-MOSFET drift region is that the longitudinal electric field distribution is not rectangular distribution but wavy distribution, mainly two peaks and one valley, wherein the first peak is located at the interface of the PN junction formed by the P well and the N-drift region, and the second peak is located at the corner of the trench bottom, i.e. in the epitaxial layer in front of the shielding gate of the trench bottom. The valley is located in the drift region outside the trench at the same height as the center of the shielding gate. Generally, the electric field of the second peak is greater than that of the first peak, and the difference between the second peak and the valley is large, generally about 1E5 (105) V / cm. The deeper the trench, the larger the difference between the second peak and the valley, and the less favorable for fully improving the breakdown voltage.

[0049] Since the breakdown voltage of the conventional structure cannot be fully improved, the chip area cannot be fully reduced, and thus the chip manufacturing cost cannot be fully reduced.

[0050] Referring to Figure 2 The SGT-MOSFET cell cross-sectional structure diagram of the embodiments of the present application is shown in Figure 2The structure is shown in the figure (the passivation layer is not drawn). In the figure, 1 is an N+ substrate, N+ represents a high N-type doping concentration, 2 is an N- epitaxial layer, 3 is a trench field oxide layer. 4A is a first isolation oxide layer, i.e. an isolation oxide layer between the first shielding gate and the control gate, 4B is a second isolation oxide layer, i.e. an isolation oxide layer between the first shielding gate and the second shielding gate. 5 is a gate oxide layer, the shielding gate includes a first shielding gate and a second shielding gate, 6A is the first shielding gate, 6B is the second shielding gate, 7 is a P well, 8 is an N+ source region, 9 is a dielectric layer, 10 is a back metal, 11 is a control gate, 12 is a trench, 13 is a front metal, and 14 is a contact hole. The structural features are that the thickness of the first isolation oxide layer 4A between the first shielding gate 6A and the control gate 11 is greater than the thickness of the second isolation oxide layer 4B between the first shielding gate 6A and the second shielding gate 6B. For an SGT-MOSFET of the same voltage level, the thickness of the trench field oxide layer 3 of the structure is less than the thickness of the trench field oxide layer of a conventional structure. In addition, the gate oxide layer is on both sides of the control gate, and the field oxide layer is on both sides of the first shielding gate and the second shielding gate. The contact hole is in the P well, the P well and the N+ source region are above the drift region (epitaxial layer), and the N+ source region is above the P well. The structure splits the conventional shielding gate into an upper shielding gate and a lower shielding gate, which is also called a double-shielding gate structure.

[0051] The SGT-MOSFET cell of the embodiment of the present application includes an N-type substrate (1), an N-epitaxial layer (2), a trench field oxide layer (3), a first isolation oxide layer (4A), a second isolation oxide layer (4B), a gate oxide layer (5), a first shielding gate (6A), a second shielding gate (6B), a P well (7), an N+ source region (8), a dielectric layer (9), a back metal (10), a control gate (11), a trench (12), a front metal (13), and a contact hole (14), which are sequentially generated. The conductive polysilicon of the first shielding gate (6A) is used to connect the source potential, and the conductive polysilicon of the second shielding gate (6B) is floating. Thus, the electric field at the corner of the first shielding gate (6A) in the middle of the trench (12) can be raised during use, while the electric field at the corner of the second shielding gate (6B) and the bottom of the entire trench (12) can be reduced, so that the longitudinal electric field distribution of the drift region deviates from the wave-shaped distribution and approaches a rectangle, the electric field distribution is optimized, and the breakdown voltage of the device is improved.

[0052] The control gate (11) is an N-type control gate (11), the first isolation oxide layer (4A) is located between the first shielding gate (6A) and the control gate (11), and the second isolation oxide layer (4B) is located between the first shielding gate (6A) and the second shielding gate (6B).

[0053] In Figure 2In the SGT-MOSFET cell profile structure in the figure, the oxidation of the trench sidewall is performed in a long trench, and an oxide layer with a certain thickness is grown on the sidewall. The second shielding gate, the second isolation oxide layer, the first shielding gate, the first isolation oxide layer, the control gate, the dielectric layer, and the metal are sequentially arranged in the long trench. The thickness of the field oxide layer is much greater than that of the gate oxide layer. The thickness of the field oxide layer is generally 2000-7000 angstroms, and the thickness of the gate oxide layer is generally 200-1000 angstroms.

[0054] In the embodiment of the present application, the N-type gate conductive polysilicon is used to connect the gate potential, the first shielding gate 6A conductive polysilicon is used to connect the source potential, and the second shielding gate 6B conductive polysilicon is floating. Since the first shielding gate 6A conductive polysilicon connects the source potential, the potential of the first shielding gate 6A conductive polysilicon is lower than that of the second shielding gate 6B conductive polysilicon when the device withstands voltage, so a large number of N-type impurities in the N-drift region are depleted with the electrons in the first shielding gate, which increases the electric field of the drift region outside the bottom of the first shielding gate 6A, thereby increasing the electric field of the entire middle part of the trench. In the traditional SGT-MOSFET cell structure, the electric field of the entire middle part of the trench is low. At the same time, since the second shielding gate 6B is floating, the second shielding gate 6B will be charged with high voltage when the device withstands voltage, which reduces the electric field at the bottom of the trench 12. In this way, by increasing the electric field at the corner of the first shielding gate 6A in the middle of the trench 12 and appropriately reducing the electric field at the corner of the second shielding gate 6B, that is, the electric field at the bottom of the entire trench 12, the longitudinal electric field distribution of the drift region deviates from the wave-shaped distribution and approaches a rectangle, which optimizes the electric field distribution and improves the breakdown voltage of the device. Under the same conditions, when the trench depth is 9 microns, the breakdown voltage of the SGT-MOSFET structure of the embodiment of the present application is increased from 100 V of the traditional structure to 125 V-150 V of the present structure, thereby increasing the breakdown voltage of the present structure by more than 25%.

[0055] The first shielding gate 6A and the drift region form a PN junction, which is depleted under the action of reverse voltage to withstand voltage. Since the main function of the first shielding gate 6A is to be depleted with the drift region to improve the electric field distribution and increase the breakdown voltage. The main function of the second shielding gate 6B is to reduce the peak electric field at the corner of the bottom of the trench, so as to make the longitudinal electric field distribution rectangular. Under the condition that the depth of the trench 12 is constant, the optimal depth of the first shielding gate 6A and the second shielding gate 6B can be set through simulation and process biasing, so as to achieve the highest breakdown voltage. However, under the condition that the depth of the trench 12 is constant, the breakdown voltage achieved by the different depths of the first shielding gate 6A and the second shielding gate 6B in the present case is greater than that achieved by the single shielding gate in the traditional structure.

[0056] The isolation oxide layer 4A between the two shielding gates and the N-type control gate 11 in the embodiment of the present application is the same as the conventional structure, and the thickness is between 0.2 microns and 0.5 microns. If the thickness of the isolation oxide layer 4B between the first shielding gate 6A and the second shielding gate 6B is too large, the breakdown voltage will be affected. Therefore, the thickness of the isolation oxide layer 4A between the first shielding gate 6A and the control gate 11 is larger than the thickness of the isolation oxide layer 4B between the first shielding gate 6A and the second shielding gate 6B, so that the breakdown voltage can be sufficiently improved.

[0057] In the case of the same trench depth, the SGT-MOSFET double shielding gate structure of the embodiment of the present application can obtain a larger breakdown voltage than the conventional single shielding gate structure, so that the trench depth can be reduced, and the thickness of the epitaxial layer can be reduced accordingly, so that the specific on-resistance can be reduced, and the chip area can be saved.

[0058] Since the conductive polysilicon of the first shielding gate 6A is connected to the source electrode, and the conductive polysilicon of the second shielding gate 6B is floating, the second shielding gate 6B will be charged with a high voltage when the device is subjected to a voltage, that is, the second shielding gate 6B will bear a part of the drain voltage. Therefore, for the SGT-MOSFET of the same voltage level, the thickness of the trench field oxide layer 3 of the structure is smaller than the thickness of the trench field oxide layer of the conventional structure. In one embodiment, the thickness of the trench field oxide layer 3 can be reduced from the thickness of the conventional structure (angstrom) to the thickness of the structure of 33%. Therefore, a smaller cell size and a larger cell density can be obtained, so that the specific on-resistance can be reduced, and the chip area can be further saved.

[0059] The embodiment of the present application also includes a split gate trench metal oxide semiconductor field effect transistor, which comprises the SGT-MOSFET cell described above; the embodiment of the present application also includes a medium and low voltage power device, which comprises the split gate trench metal oxide semiconductor field effect transistor described above; and the embodiment of the present application also includes an electronic device, which comprises the medium and low voltage power device described above. In the present application, the power device with a voltage of 30V-250V can be used in electronic devices such as energy storage and synchronous rectification.

[0060] The manufacturing method of the shielding gate MOSFET of the embodiment of the present application is as follows:

[0061] Please refer to Figure 3A , step A: forming an N-epitaxial layer on an N+ substrate, and forming a trench on the N-epitaxial layer. Figure 3A is a schematic view of the cross section after trench etching, in which 1 is an N+ substrate, 2 is an N-epitaxial layer, and 12 is a trench.

[0062] Please refer to Figure 3B , step B: growing a field oxide layer on the sidewall of the trench. Figure 3Bis a cross-sectional view after field oxide formation. In the figure, 1 is an N+ substrate, 2 is an N- epitaxial layer, 12 is a trench, and 3 is a field oxide layer.

[0063] Referring to Figure 3C , step C: a first polysilicon deposition, doping and poly diffusion, and etching of the polysilicon to form a second shield gate. Figure 3C is a cross-sectional view after formation of the second shield gate. In the figure, 1 is an N+ substrate, 2 is an N- epitaxial layer, 3A is a trench field oxide layer, 6B is a second shield gate, and 12 is a trench.

[0064] Referring to Figure 3D , step D: thermal oxidation to form a second isolation oxide layer. Figure 3D is a cross-sectional view after formation of the second isolation oxide layer. In the figure, 1 is an N+ substrate, 2 is an N- epitaxial layer, 3A is a trench field oxide layer, 4B is a second isolation oxide layer, 6B is a second shield gate, and 12 is a trench.

[0065] Referring to Figure 3E , step E: a second polysilicon deposition, doping and poly diffusion, and etching of the polysilicon to form a first shield gate. Figure 3E is a cross-sectional view after formation of the first shield gate. In the figure, 1 is an N+ substrate, 2 is an N- epitaxial layer, 3A is a field oxide layer, 4B is a second isolation oxide layer (isolation oxide layer between the first shield gate and the second shield gate), 6A is a first shield gate, 6B is a second shield gate, and 12 is a trench.

[0066] Referring to Figure 3F , step F: etching of the oxide layer to the level of the top of the first shield gate, followed by gate oxidation, and then a polysilicon deposition, doping and diffusion, and chemical mechanical polishing (CMP) to remove the polysilicon and oxide layer on the surface of the wafer to form a first isolation oxide layer and an N-type control gate. Figure 3F is a cross-sectional view after formation of the control gate. In the figure, 1 is an N+ substrate, 2 is an N- epitaxial layer, 3 is a trench field oxide layer, 4A is a first isolation oxide layer (isolation oxide layer between the shield gate and the N-type control gate), 4B is a second isolation oxide layer (isolation oxide layer between the first shield gate and the second shield gate), 5 is a gate oxide layer, 6A is a first shield gate, 6B is a second shield gate, 11 is an N-type control gate, and 12 is a trench.

[0067] Referring to Figure 3G , step G: boron implantation and diffusion to form a P-well, and then arsenic implantation and diffusion to form an N+ source region. Figure 3Gis a cross-sectional view after forming the N+ source region. In the figure, 1 is an N+ substrate, 2 is an N- epitaxial layer, 3 is a trench field oxide layer, 4A is a first isolation oxide layer (i.e. the isolation oxide layer between the shield gate and the N-type control gate), 4B is a second isolation oxide layer (i.e. the isolation oxide layer between the first shield gate and the second shield gate), 5 is a gate oxide layer, 6A is a first shield gate, 6B is a second shield gate, 7 is a P well, 8 is an N+ source region, 11 is an N-type control gate, and 12 is a trench.

[0068] Referring to Figure 3H , step H: depositing to form a dielectric layer, the material being a USG (un-doped silicon glass) layer and a PSG (phosphorus-doped silicon glass) layer. Figure 3H is a schematic view of the three-dimensional structure of the SGT-MOSFET cell according to the embodiment of the present application. In the figure, 1 is an N+ substrate, 2 is an N- epitaxial layer, 3 is a trench field oxide layer. 4A is a first isolation oxide layer, i.e. the isolation oxide layer between the shield gate and the N-type control gate, 4B is a second isolation oxide layer, i.e. the isolation oxide layer between the first shield gate and the second shield gate. 5 is a gate oxide layer, 6A is a first shield gate, 6B is a second shield gate, 7 is a P well, 8 is an N+ source region, 9 is a dielectric layer, 10 is a back metal, 11 is an N-type control gate, 12 is a trench, 13 is a front metal, and 14 is a contact hole. The dielectric layer includes two dielectric layers, i.e. a USG layer and a PSG layer, the USG layer being deposited first and then the PSG layer. The two dielectric layers function to block impurity ions from the outside from entering the chip.

[0069] Step I: etching the contact hole into silicon to form a contact hole, and performing P-type high-doped implantation of the contact hole. The depth of the contact hole into silicon is 0.3-0.6 microns.

[0070] Step J: sputtering, photoetching and etching of the front metal to form the front metal.

[0071] Step K: thinning the back and forming a back metal.

[0072] The embodiment of the present application has the following beneficial effects:

[0073] 1. In the case of the same trench depth, the SGT-MOSFET double shield gate structure according to the embodiment of the present application can obtain a greater breakdown voltage than the traditional single shield gate structure, so that the trench depth can be reduced, and correspondingly the epitaxial layer thickness can also be reduced, thus the specific on-resistance can be reduced and the chip area can be saved.

[0074] 2. The trench field oxide layer thickness of the structure is less than that of the traditional structure, so that a smaller cell size and a greater cell density can be obtained, thus the specific on-resistance can be reduced and the chip area can be further saved.

[0075] The background section of this document can include information about the problem or environment of the invention, not necessarily the prior art. Thus, the content of the background section is not an admission that the prior art is pertinent or that "what is already known has been thoroughly searched, found to be true, accurate and reliable." 37 C.F.R. § 1.97(g)(2)(i).

[0076] The above further describes the present application in conjunction with specific / preferred embodiments, and cannot be deemed to limit the specific implementation of the present application to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, they can make several substitutions or modifications to the described embodiments, and these substitutions or modifications shall be deemed to fall within the protection scope of the present application. In the description of the present application, the description of the terms "an embodiment", "some embodiments", "a preferred embodiment", "an example", "a specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. The illustrative description of the above terms in the present application does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. Those skilled in the art can combine and combine the different embodiments or examples described in the present application and the features of the different embodiments or examples, without contradiction. Although the embodiments of the present application and their advantages have been described in detail, it should be understood that various changes, substitutions and modifications can be made herein without departing from the scope of the patent application.

Claims

1. An SGT-MOSFET cell, characterized by, The SGT-MOSFET cell comprises an N-type substrate (1), an N-epitaxial layer (2), a trench field oxide layer (3), a first isolation oxide layer (4A), a second isolation oxide layer (4B), a gate oxide layer (5), a first shield gate (6A), a second shield gate (6B), a P-well (7), an N+ source region (8), a dielectric layer (9), a back metal (10), a control gate (11), a trench (12), a front metal (13), and a contact hole (14) which are sequentially formed.

2. The SGT-MOSFET cell of claim 1, wherein, The depth of the trench (12) is 9 microns, and the breakdown voltage is 125V-150V.

3. The SGT-MOSFET cell of claim 1, wherein, The thickness of the first isolation oxide layer (4A) between the first shield gate (6A) and the N-type control gate (11) is greater than the thickness of the second isolation oxide layer (4B) between the first shield gate (6A) and the second shield gate (6B).

4. The SGT-MOSFET cell of claim 1, wherein, The depth of the contact hole (14) into the silicon is 0.3-0.6 microns.

5. A split-gate trench metal oxide semiconductor field effect transistor, characterized by, The SGT-MOSFET cell comprises the SGT-MOSFET cell of any one of claims 1-4.

6. A medium-low voltage power device, characterized in that, The split gate trench MOSFET comprises the split gate trench MOSFET of claim 5.

7. An electronic device, comprising: The medium and low voltage power device comprises the medium and low voltage power device of claim 6.

8. A method of manufacturing an SGT-MOSFET, characterized by, The method comprises the following steps: A. Forming an N-epitaxial layer on an N+ substrate, and forming a trench on the N-epitaxial layer; B. Growing a field oxide layer on the sidewall of the trench; C. Depositing, doping, and diffusing a first polysilicon, and etching the polysilicon to form a second shield gate; D. Thermal oxidation to form a second isolation oxide layer; E. Depositing, doping, and diffusing a second polysilicon, and etching the polysilicon to form a first shield gate; F. Etching the oxide layer to a level flush with the top of the first shield gate, then performing gate oxidation, and then depositing, doping, and diffusing a polysilicon, and polishing to remove the polysilicon and the oxide layer on the surface of the wafer to form a first isolation oxide layer and a control gate; wherein the thickness of the first isolation oxide layer is greater than the thickness of the second isolation oxide layer; G. Forming a P-well by boron implantation and diffusion, and forming an N+ source region by arsenic implantation and diffusion; H. Depositing a dielectric layer; I. Etching a contact hole into the silicon to form a contact hole, and performing P-type high-dose implantation of the contact hole; J. Sputtering, photolithography, and etching a front metal to form the front metal; K. Thinning the back and forming a back metal.

9. The method of claim 8, wherein the SGT-MOSFET is formed by the steps of: The dielectric layer in step H comprises two layers of dielectric layers, namely a USG layer and a PSG layer, wherein the USG layer is deposited first, and then the PSG layer is deposited. ​ 10. The method of claim 8, wherein the SGT-MOSFET is formed by the steps of: The polishing in step F adopts chemical mechanical polishing (CMP). ​ 11. The method of claim 8, wherein the SGT-MOSFET is formed by the steps of: The control gate in step F is an N-type control gate. ​

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