A biasing circuit for a differential current steering DAC

Abstract

The application discloses a bias circuit suitable for a differential current steering DAC and belongs to the field of integrated circuit design, and comprises a clamping voltage generating module and a gate end bias voltage generating module. The clamping voltage generating module generates clamping voltage through an operational transconductance amplifier (OTA) and a current mirror network, and the clamping voltage is used as the input of a transimpedance amplifier and is used for clamping the output end voltage of a differential DAC switch current source array, so that the drain end voltage of a current source array current mirror tube is kept unchanged when different digital signals are input, and the matching of the DAC current source array and a reference current source is improved. The gate end bias voltage generating module generates the gate end bias voltage of a PMOS current source array and the gate end bias voltage of an NMOS current source array in the differential DAC through an operational amplifier (OP) and a current mirror network.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, in particular to a bias circuit suitable for differential current steering DAC. BACKGROUND

[0002] DAC (Digital to Analog Converter) is a link for data transmission between digital circuit and analog circuit, and its main function is to convert digital input quantity into analog output quantity. DAC has become an indispensable important functional module in today's rapid development of science and technology, and is involved in many fields such as communication technology, automation control technology and image processing technology.

[0003] In different application occasions, the performance of DAC has completely different requirements. For example, the products in the fields of video and audio generally have higher requirements on the time domain characteristics such as linearity, peak glitch and settling time of DAC output; in the communication field, whether the signals of adjacent channels will interfere with the signals of target channels is more critical, so it is necessary to pay special attention to the improvement of frequency domain characteristics such as spurious free dynamic range (SFDR) and bandwidth. In recent years, in order to adapt to the rapid development of digital signal processing system, the research and design of high-speed and high-performance DAC has become an important trend.

[0004] The conversion process of current steering DAC is realized by controlling a series of matched current sources through digital input signals, and the matching of current source array affects the linearity of DAC. For binary code current steering type DAC circuit, due to the different input bit weights, there are device mismatches and clock feedthrough in the current sources, and these non-ideal effects are easy to produce larger DNL and dynamic error, which must be carefully analyzed and handled in time. SUMMARY

[0005] The purpose of the present application is to provide a bias circuit suitable for differential current steering DAC to solve the problems in the background art.

[0006] To solve the above technical problems, the present application provides a bias circuit suitable for differential current steering DAC, which comprises a clamping voltage generating module and a gate end bias voltage generating module.

[0007] The clamping voltage generating module generates clamping voltage through operational transconductance amplifier (OTA) and current mirror network, which is input to the cross resistance amplifier to clamp the differential DAC switch current source array output end voltage.

[0008] The gate end bias voltage generating module generates the gate end bias voltage of PMOS current source array and the gate end bias voltage of NMOS current source array in differential DAC through operational amplifier (OP) and current mirror network.

[0009] In an embodiment, the clamp voltage generating module comprises PMOS tubes MP3~MP4, NMOS tubes MN4~MN5 and MN7~MN8, an operational transconductance amplifier OTA, resistors R3~R6, and a capacitor C2.

[0010] The source terminal of the PMOS tube MP3 and the source terminal of the PMOS tube MP4 are both connected to the power supply VDD, the gate terminal of the PMOS tube MP3 is connected to the gate terminal of the PMOS tube MP4, the drain terminal of the PMOS tube MP3 is connected to the gate terminal of the PMOS tube MP3 and the drain terminal of the NMOS tube MN4; the drain terminal of the PMOS tube MP4 is connected to the ground through the resistor R3 and the capacitor C2 in sequence.

[0011] The drain terminal of the NMOS tube MN8 is connected to the drain terminal of the PMOS tube MP4, the gate terminal is connected to the power supply VDD, and the source terminal is connected to the drain terminal of the NMOS tube MN7; the gate terminal of the NMOS tube MN7 is connected between the resistor R3 and the capacitor C2, and the source terminal is connected to the output terminal of the operational transconductance amplifier OTA through the resistor R4; the drain terminal of the NMOS tube MN5 is connected to the source terminal of the NMOS tube MN7, the gate terminal is connected to the gate terminal of the NMOS tube MN4, and the source terminal is connected to the ground; the source terminal of the NMOS tube MN4 is connected to the ground.

[0012] One end of the resistor R5 is connected to the power supply VDD, and the other end is connected to the ground through the resistor R6; the positive input terminal of the operational transconductance amplifier OTA is connected between the resistors R5 and R6, and the negative input terminal is connected to the output terminal of the operational transconductance amplifier OTA to form a feedback.

[0013] In an embodiment, the gate terminal bias voltage generating module comprises PMOS tubes MP1~MP2 and MP5, NMOS tubes MN2~MN3 and MN6, resistors R1~R2, a capacitor C1, and an operational amplifier OP.

[0014] The source terminal of the PMOS tube MP1 and the source terminal of the PMOS tube MP2 are both connected to the power supply VDD, the gate terminal of the PMOS tube MP1 is connected to the gate terminal of the PMOS tube MP2, and the drain terminal of the PMOS tube MP1 is connected to the drain terminal of the NMOS tube MN2 through the resistor R1; the gate terminal of the PMOS tube MP2 is connected to the drain terminal of the PMOS tube MP1, and the drain terminal of the PMOS tube MP2 is connected to the source terminal of the PMOS tube MP5.

[0015] The gate terminal of the PMOS tube MP5 is connected to the ground, and the drain terminal is connected to the drain terminal of the NMOS tube MN6; the gate terminal of the NMOS tube MN6 is connected to the power supply VDD, and the source terminal is connected to the drain terminal of the NMOS tube MN3; the gate terminal of the NMOS tube MN3 is connected to the output terminal of the operational amplifier OP, and the source terminal is connected to the ground; the gate terminal of the NMOS tube MN2 is connected to the gate terminal of the NMOS tube MN4 and the gate terminal of the NMOS tube MN5, and the source terminal is connected to the ground.

[0016] The first end of the resistor R2 is connected to the drain of the PMOS MP5, the drain of the NMOS MN6 and the positive input of the operational amplifier OP, and the second end is connected to the output of the operational amplifier OP through the capacitor C1.

[0017] In one embodiment, the bias circuit for the differential current steering DAC further comprises an NMOS MN1, the drain of the NMOS MN1 is connected to the gate of itself, the gate of the NMOS MN2, the gate of the NMOS MN4 and the gate of the NMOS MN5, and the source of the NMOS MN1 is grounded.

[0018] In the bias circuit for the differential current steering DAC provided by the present application, the bias circuit comprises a clamping voltage generating module and a gate bias voltage generating module. The clamping voltage generating module generates a clamping voltage through an operational transconductance amplifier OTA and a current mirror network, which is used as the input of a transimpedance amplifier, clamps the voltage at the output end of the differential DAC switching current source array, ensures that the voltage at the drain of the current mirror tube of the current source array remains unchanged when different digital signals are input, and improves the matching of the DAC current source array and the reference current source. The gate bias voltage generating module generates the gate bias voltage of the PMOS current source array and the gate bias voltage of the NMOS current source array in the differential DAC through an operational amplifier OP and a current mirror network. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a structural schematic diagram of the bias circuit for the differential current steering DAC provided by the present application. DETAILED DESCRIPTION

[0020] The bias circuit for the differential current steering DAC provided by the present application is further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are very simplified and use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0021] The bias circuit for the differential DAC provided by the present application has the structure as shown in Figure 1 which comprises a clamping voltage generating module and a gate bias voltage generating module.

[0022] The clamping voltage generating module comprises PMOS tubes MP3-MP4, NMOS tubes MN4-MN5 and MN7-MN8, an operational transconductance amplifier OTA, resistors R3-R6, and a capacitor C2. The source terminal of the PMOS tube MP3 and the source terminal of the PMOS tube MP4 are both connected to a power supply VDD, the gate terminal of the PMOS tube MP3 and the gate terminal of the PMOS tube MP4 are connected, the drain terminal of the PMOS tube MP3 is connected to the gate terminal of the PMOS tube MP3 and the drain terminal of the NMOS tube MN4; the drain terminal of the PMOS tube MP4 is connected to the ground through the resistor R3 and the capacitor C2 in sequence; the drain terminal of the NMOS tube MN8 is connected to the drain terminal of the PMOS tube MP4, the gate terminal of the NMOS tube MN8 is connected to the power supply VDD, and the source terminal of the NMOS tube MN8 is connected to the drain terminal of the NMOS tube MN7; the gate terminal of the NMOS tube MN7 is connected between the resistor R3 and the capacitor C2, and the source terminal of the NMOS tube MN7 is connected to the output terminal of the operational transconductance amplifier OTA through the resistor R4; the drain terminal of the NMOS tube MN5 is connected to the source terminal of the NMOS tube MN7, the gate terminal of the NMOS tube MN5 is connected to the gate terminal of the NMOS tube MN4, and the source terminal of the NMOS tube MN5 is connected to the ground; the source terminal of the NMOS tube MN4 is connected to the ground; one end of the resistor R5 is connected to the power supply VDD, and the other end of the resistor R5 is connected to the ground through the resistor R6; the positive input terminal of the operational transconductance amplifier OTA is connected between the resistors R5 and R6, and the negative input terminal of the operational transconductance amplifier OTA is connected to the output terminal of the operational transconductance amplifier OTA to form a feedback. The biasing circuit suitable for a differential current steering DAC further comprises an NMOS tube MN1, and the drain terminal of the NMOS tube MN1 is connected to the gate terminal of the NMOS tube MN1, the gate terminal of the NMOS tube MN4, and the gate terminal of the NMOS tube MN5, and the source terminal of the NMOS tube MN1 is connected to the ground.

[0023] The MOS tubes MN1, MN4, MN5, MP3, and MP4 form a current mirror network. By controlling the voltage division value of the power supply voltage VDD through the resistors R5 and R6, the resistance value of the resistor R4, and the mirror ratio of the MOS tubes MN4, MN5, MP3, and MP4, the MOS tubes MN5, MN7, and MP4 are ensured to be in the saturation region.

[0024] The clamping voltage generating module controls the voltage at the output terminal of the operational transconductance amplifier OTA to be equal to the voltage division VREF of the power supply voltage VDD through the resistors R5 and R6 by the clamping function of the operational transconductance amplifier OTA. The number of parallel MOS tubes of the transistors MN1, MN4, MN5, MP3, and MP4 is N1, N4, N5, P3, and P4 (N1>0, N4>0, N5>0, P3>0, P4>0) respectively. According to the MOS current mirror principle, the mirror current of the NMOS tube MN1 flowing through the NMOS tube MN1 is The current I flowing through the PMOS tube MP3 is MP3 The mirror current of the PMOS tube MP4 is According to the Kirchhoff's current law and the above formula, the current flowing through the resistor R4 is The drain terminal voltage of the NMOS tube MN5 is The drain current I flowing through the NMOS transistor MN7 MN7 is equal to the drain current I flowing through the PMOS transistor MP4 MP4 , μ n is the electron mobility, C OX is the gate oxide capacitance per unit area, is the width-length ratio of the MOS transistor, V GS_MN7 is the gate-source voltage of the NMOS transistor MN7, V THN is the threshold voltage of the MOS transistor; then the gate voltage of the NMOS transistor MN7

[0025] The gate bias voltage generating module comprises PMOS transistors MP1-MP2 and MP5, NMOS transistors MN2-MN3 and MN6, resistors R1-R2, a capacitor C1 and an operational amplifier OP. The source of the PMOS transistor MP1 and the source of the PMOS transistor MP2 are both connected to the power supply VDD, the gate of the PMOS transistor MP1 is connected to the gate of the PMOS transistor MP2, and the drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN2 through the resistor R1; the gate of the PMOS transistor MP2 is connected to the drain of the PMOS transistor MP1, and the drain of the PMOS transistor MP2 is connected to the source of the PMOS transistor MP5; the gate of the PMOS transistor MP5 is grounded, and the drain is connected to the drain of the NMOS transistor MN6; the gate of the NMOS transistor MN6 is connected to the power supply VDD, and the source is connected to the drain of the NMOS transistor MN3; the gate of the NMOS transistor MN3 is connected to the output of the operational amplifier OP, and the source is grounded; the gate of the NMOS transistor MN2 is simultaneously connected to the gate of the NMOS transistor MN4 and the gate of the NMOS transistor MN5, and the source is grounded; the first end of the resistor R2 is simultaneously connected to the drain of the PMOS transistor MP5, the drain of the NMOS transistor MN6 and the positive input of the operational amplifier OP, and the second end is connected to the output of the operational amplifier OP through the capacitor C1. The drain of the NMOS transistor MN1 is simultaneously connected to the gate of the NMOS transistor MN1 and the gate of the NMOS transistor MN2.

[0026] The MOS transistors MN1, MN2, MN3, MP1 and MP2 form a current mirror network. By controlling the size of the voltage VREF, the MOS transistors MN3 and MP2 are ensured to be in the saturation region.

[0027] The gate end bias voltage generating module controls the drain end voltage of the NMOS tube MN6 to be equal to the drain end voltage of the NMOS tube MN5 through the clamping function of the operational amplifier OP. The MOS tubes of the transistors MN1, MN2, MP1 and MP2 are connected in parallel, and the number of MOS tubes is N1, N2, P1 and P2 (N1>0, N2>0, P1>0, P2>0) respectively. According to the MOS tube current mirror principle, the mirror current of the NMOS tube MN2 is The drain end current I MP1 of the PMOS tube MP1 is equal to the drain end current I MN2 of the NMOS tube MN2, V GS_MP1 is the gate source voltage of the PMOS tube MP1, and the gate end voltage of the PMOS tube MP1 is According to the MOS tube current mirror principle, the current I MP1 of the PMOS tube MP1 is mirrored to the mirror current of the PMOS tube MP2, The drain end current I MN3 of the NMOS tube MN3 is equal to the drain end current I MP2 of the PMOS tube MP2, and the gate end voltage of the NMOS tube MN3 is

[0028] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any modification or change made by the person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A biasing circuit suitable for use in a differential current steering DAC, characterized by, It includes a clamping voltage generation module and a gate bias voltage generation module; The clamping voltage generation module generates a clamping voltage through a computational transconductance amplifier OTA and a current mirror network, which serves as the input of a transimpedance amplifier to clamp the output voltage of the differential DAC switching current source array. The gate bias voltage generation module generates the gate bias voltage of the PMOS current source array and the gate bias voltage of the NMOS current source array in the differential DAC through the operational amplifier OP and the current mirror network. The clamping voltage generation module includes PMOS transistors MP3~MP4, NMOS transistors MN4~MN5 and MN7~MN8, an operational transconductance amplifier OTA, resistors R3~R6, and capacitor C2; The source terminals of PMOS transistors MP3 and MP4 are both connected to the power supply VDD. The gate terminals of PMOS transistors MP3 and MP4 are connected. The drain terminal of PMOS transistor MP3 is connected to its own gate terminal and the drain terminal of NMOS transistor MN4. The drain terminal of PMOS transistor MP4 is grounded through resistor R3 and capacitor C2 in sequence. The drain of NMOS transistor MN8 is connected to the drain of PMOS transistor MP4. The gate of NMOS transistor MN8 is connected to the power supply VDD. The source of NMOS transistor MN8 is connected to the drain of NMOS transistor MN7. The gate of NMOS transistor MN7 is connected between resistor R3 and capacitor C2, and connected to voltage VBBC. The source of NMOS transistor MN7 is connected to the output of operational transconductance amplifier OTA through resistor R4. The drain of NMOS transistor MN5 is connected to the source of NMOS transistor MN7. The gate of NMOS transistor MN5 is connected to the gate of NMOS transistor MN4. The source of NMOS transistor MN5 is grounded. The source of NMOS transistor MN4 is grounded. One end of resistor R5 is connected to the power supply VDD, and the other end is grounded through resistor R6; the positive input terminal of the operational transconductance amplifier OTA is connected between resistors R5 and R6, and the negative input terminal is connected to its own output terminal to form feedback; The gate bias voltage generation module includes PMOS transistors MP1~MP2 and MP5, NMOS transistors MN2~MN3 and MN6, resistors R1~R2, capacitor C1, and operational amplifier OP; The source terminals of PMOS transistors MP1 and MP2 are both connected to the power supply VDD. The gate terminal of PMOS transistor MP1 is connected to the gate terminal of PMOS transistor MP2. The drain terminal of PMOS transistor MP1 is connected to the drain terminal of NMOS transistor MN2 through resistor R1. The gate terminal of PMOS transistor MP2 is connected to the drain terminal of PMOS transistor MP1. The drain terminal of PMOS transistor MP2 is connected to the source terminal of PMOS transistor MP5. The gate of PMOS transistor MP5 is grounded, and the drain of PMOS transistor MP5 is connected to the drain of NMOS transistor MN6. The gate of NMOS transistor MN6 is connected to the power supply VDD, and the source of NMOS transistor MN6 is connected to the drain of NMOS transistor MN3. The gate of NMOS transistor MN3 is connected to the output of operational amplifier OP, and the source of NMOS transistor MN3 is grounded. The gate of NMOS transistor MN2 is also connected to the gate of NMOS transistor MN4, and the source of NMOS transistor MN2 is grounded. The first end of the resistor R2 is connected with the drain of the PMOS MP5, the drain of the NMOS MN6 and the positive input of the operational amplifier OP, the second end is connected with the output of the operational amplifier OP through the capacitor C1, and the negative input of the operational amplifier OP is connected with the drain of the NMOS MN5; the gate bias voltage of the PMOS current source array is output from the drain of the PMOS MP1, and the gate bias voltage of the NMOS current source array is output from the gate of the NMOS MN3; The bias circuit suitable for the differential current steering DAC further comprises the NMOS MN1, the drain of the NMOS MN1, the gate of the NMOS MN1, the gate of the NMOS MN2, the gate of the NMOS MN4 and the gate of the NMOS MN5 are all connected with the current IBIN, and the source of the NMOS MN1 is connected with the ground.

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