A multi-mode analog baseband circuit

Abstract

The present invention discloses a multi-mode analog baseband circuit, which includes a high-pass filter, a variable gain amplifier, and an output driver buffer. The high-pass filter, the variable gain amplifier, and the output driver buffer are cascaded in sequence. By controlling the MOS transistor switch, the circuit is switched between the FMCW radar simulator circuit mode and the Doppler radar analog baseband circuit mode, and different frequency bands are switched in the FMCW radar analog baseband circuit mode. The high-pass filter is a second-order Two-Thomas type high-pass filter with an adjustable high-pass cut-off frequency. The variable gain amplifier is a three-stage variable gain amplifier with a DC offset cancellation feedback.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic communication, and particularly relates to a multi-mode analog baseband circuit. Background Art

[0002] The analog baseband is an important part of a radar transceiver system. It can amplify the intermediate frequency signal mixed out and filter out other useless interference signals. The analog baseband circuit is generally a circuit composed of a filter and a variable gain amplifier, where the filter includes a low-pass filter, a high-pass filter, and a band-pass filter. According to the requirements of the system, the structures of the analog baseband circuits of different systems are also different.

[0003] Currently, most radar systems only implement specific functions, such as Frequency-Modulated Continuous Wave (FMCW) radars and Doppler radars, etc. The functions of different radars are also different. If a certain product needs both the functions of an FMCW radar and a Doppler radar, then two radar chips need to be used in this product, and the cost of the product is relatively high. If a radar system can implement the functions of an FMCW radar and a Doppler radar, then the production cost can be greatly reduced. However, the working frequency bands of the analog basebands of FMCW radars and Doppler radars are different, and the intermediate frequency signal frequency of the Doppler radar is relatively low, usually in the range of a few hertz to several kilohertz. And the flicker noise of MOS transistors is relatively large in this frequency band range. Therefore, when designing the analog baseband circuit of the Doppler radar, it is necessary to consider how to reduce the flicker noise of the circuit. Currently, there is still no good solution for a multi-mode analog baseband circuit that can be used for both FMCW radars and Doppler radars.

[0004] The existing analog baseband part has the function of high-pass filtering (A 76–81-GHz Four-Channel Digitally Controlled CMOS), can be switched to different high-pass corner frequencies, and also has a gain adjustment function. This baseband circuit is only applicable to FMCW radars and not applicable to Doppler radars because the baseband signal frequency of the Doppler radar is only from a dozen hertz to a dozen kilohertz, while the minimum high-pass corner frequency of the analog baseband in this article is only one hundred kilohertz. In the baseband signal frequency range of the Doppler radar, the gain attenuation is very severe and it does not have an amplification function. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an analog baseband circuit that can be applicable to both FMCW radars and Doppler radars, can switch the working frequency band in the FMCW radar mode, and has lower noise in the Doppler radar mode.

[0006] The present invention is implemented by at least one of the following technical solutions.

[0007] A multi-mode analog baseband circuit includes a high-pass filter, a variable gain amplifier, and an output driving buffer; the high-pass filter, the variable gain amplifier, and the output driving buffer are cascaded in sequence, and the circuit is switched between the FMCW radar simulator circuit mode and the Doppler radar analog baseband circuit mode by controlling MOS transistor switches, and different frequency bands are switched in the FMCW radar analog baseband circuit mode.

[0008] Further, the variable gain amplifier is a three-stage variable gain amplifier with DC offset cancellation feedback, and each stage of chopper amplifier includes a chopper amplifier, an amplifier, several switches, capacitors, and resistors.

[0009] Further, the chopper amplifier includes a first chopper and a second chopper, and each chopper includes four NMOS transistors. The gates of the first NMOS transistor Q1 and the third NMOS transistor Q3 are connected to the clock CLK1, the gates of the second NMOS transistor Q2 and the fourth NMOS transistor Q4 are connected to the clock CLK2, the drains of the first NMOS transistor Q1 and the second NMOS transistor Q2 are connected to one end of the input VIN1, the drains of the third NMOS transistor Q3 and the fourth NMOS transistor Q4 are connected to the other end of the input VIN2, the sources of the first NMOS transistor Q1 and the fourth NMOS transistor Q4 are connected to one end of the output VOUT1, and the sources of the second NMOS transistor Q2 and the third NMOS transistor Q3 are connected to the other end of the output VOUT2; the inputs of the two choppers are respectively connected to the drain of the amplifier, and the outputs of the two choppers are respectively connected to the gate of the amplifier.

[0010] Further, the inputs of the two choppers are respectively connected to the drain of the amplifier, and the outputs of the two choppers are respectively connected to the gate of the amplifier.

[0011] Further, the chopper amplifier includes two of the above-mentioned choppers. The output terminals of the first chopper are respectively connected to the gates of the first amplifier transistor M1 and the second amplifier transistor M2. The second chopper is connected between the output of the first-stage amplifier and the input of the second-stage amplifier. The inputs of the two choppers are respectively connected to the drains of the first amplifier transistor M1 and the second amplifier transistor M2, and the outputs of the two choppers are respectively connected to one end of the gates of the third amplifier transistor M6 and the fourth amplifier transistor M7 connected to the first resistor R1 and the second resistor R2.

[0012] Further, the high-pass filter includes a first amplifier, a second amplifier, several capacitors, and several resistors. The input end of the analog baseband circuit is connected to a third capacitor C3. A first switch 1 is connected between the input end of the analog baseband circuit and a second capacitor C1. The other end of the first switch 1 is connected to the two output ends of the first amplifier. The other end of the third capacitor C3 is connected to one end of a fifth resistor R5. The other end of the fifth resistor R5 is connected to a bias voltage VBIAS. At the same time, the other end of the fifth resistor R5 is respectively connected to the input stage of the second amplifier.

[0013] A fourth capacitor C4 is respectively connected to the positive input end and the negative output end on one side of the first amplifier. The fourth capacitor C4 is connected in parallel with a first adjustable resistor R6. Capacitors and adjustable resistors corresponding to them are also connected to the positive input end and the negative output end on the other side of the first amplifier.

[0014] The negative end of the first amplifier is connected to the negative end of the second amplifier through a second adjustable resistor R7. The positive end of the first amplifier is connected to the positive end of the second amplifier through the second adjustable resistor R7. A fifth capacitor C5 is connected to the positive input end and the negative output end on one side of the second amplifier. Capacitors corresponding to them are also connected to the positive input end and the negative output end on the other side of the second amplifier. The positive input end on one side of the first amplifier and the negative output end on one side of the second amplifier are respectively connected to both ends of a third adjustable resistor R8. The positive input end on the other side of the first amplifier and the negative output end on the other side of the second amplifier are also respectively connected to corresponding adjustable resistors.

[0015] Further, the high-pass filter is a second-order Two-Thomas I type high-pass filter whose cut-off frequency can be adjusted.

[0016] Further, the amplifier is a two-stage amplifier circuit with Miller compensation and a common-mode negative feedback circuit.

[0017] Further, the first-stage amplifier circuit includes a common-source amplifier structure. The common-source amplifier structure includes a first active load transistor M3, a second active load transistor M4, and a current bias transistor M5. The source of the current bias transistor M5 is connected to the power supply voltage VDD. The drain of the current bias transistor M5 is connected to the sources of a first amplifying transistor M1 and a second amplifying transistor M2. The first amplifying transistor M1 and the second amplifying transistor M2 are also respectively connected to both ends of the input signal. The drains of the first active load transistor M3 and the second active load transistor M4 are connected to the drains of the first amplifying transistor M1 and the second amplifying transistor M2. The sources of the first active load transistor M3 and the second active load transistor M4 are connected to the ground voltage VSS. The gates of the first active load transistor M3 and the second active load transistor M4 are connected and connected to the drain of the M13 transistor.

[0018] Further, the second-stage amplifier circuit includes several amplifier transistors, a third active load transistor M8, a fourth active load transistor M9, and a bias current. The third amplifier transistor M6 and the fourth amplifier transistor M7 are respectively connected to the drains of the first amplifier transistor M1 and the second amplifier transistor M2. The drains of the third amplifier transistor M6 and the fourth amplifier transistor M7 are respectively connected to the drains of the third active load transistor M8 and the fourth active load transistor M9. The sources of the third active load transistor M8 and the fourth active load transistor M9 are connected to the power supply voltage VDD, and these two nodes are respectively used as output nodes VON and VOP. The output nodes VON and VOP are respectively connected to one ends of a first capacitor C1 and a second capacitor C2. The other ends of the first capacitor C1 and the second capacitor C2 are respectively connected to one ends of a first resistor R1 and a second resistor R2. The other ends of the first resistor R1 and the second resistor R2 are connected to the gates of the third amplifier transistor M6 and the fourth amplifier transistor M7. The first capacitor C1, the first resistor R1, the second capacitor C2, and the second resistor R2 are used for Miller compensation.

[0019] The third resistor R3 and the fourth resistor R4 are used to detect the common-mode voltage at both ends of the output. One ends of the third resistor R3 and the fourth resistor R4 are respectively connected to the other ends of the output points VOP and VON, and both are connected to the gate of M11. The gate of M12 is connected to the common-mode reference voltage VCM. The sources of the eighth amplifier transistor M11 and the ninth amplifier transistor M12 are both connected to the drain of the twelfth amplifier transistor M15. The source of the twelfth amplifier transistor M15 is connected to the power supply VDD. The gate of the twelfth amplifier transistor M15 is connected to the gates of the sixth amplifier transistor M9, the current bias transistor M5, the fifth amplifier transistor M8, and the seventh amplifier transistor M10. The tenth amplifier transistor M13 and the eleventh amplifier transistor M14 have their gates and drains connected. The drains of the tenth amplifier transistor M13 and the eleventh amplifier transistor M14 are respectively connected to the drains of the eighth amplifier transistor M11 and the ninth amplifier transistor M12. The sources of the tenth amplifier transistor M13 and the eleventh amplifier transistor M14 are connected to the ground VSS. And the drain of the tenth amplifier transistor M13 is also connected to the gates of the first active load transistor M3 and the second active load transistor M4. The gate and the drain of the seventh amplifier transistor M10 are connected, and a bias current is injected from the drain.

[0020] Compared with the existing technology, the beneficial effects of the present invention are as follows:

[0021] The present invention uses MOS transistor switches to switch the resistors and capacitors in the circuit and to close and open some circuit modules, thereby realizing the switching between different working modes of the FMCW radar analog baseband circuit and the switching between the FMCW radar analog baseband circuit and the Doppler radar analog baseband circuit, reducing the chip area and the production cost of the product. In addition, the present invention uses a chopper amplifier, which greatly reduces the noise of the circuit in the Doppler radar analog baseband circuit mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The embodiments of the present invention will be described in detail with reference to the accompanying drawings, and the above and other objects, features, and advantages of the present invention will become clearer, where:

[0023] Figure 1 It is a schematic structural diagram of an amplifier used in the analog baseband circuit of the embodiment;

[0024] Figure 2 It is a schematic structural diagram of a chopper used in the circuit of the embodiment;

[0025] Figure 3 It is a schematic structural diagram of a chopper amplifier used in the analog baseband circuit of the embodiment;

[0026] Figure 4a It is a partial schematic structural diagram of a multi-mode analog baseband circuit of the embodiment;

[0027] Figure 4b It is a schematic structural diagram of a three-stage variable gain amplifier of a multi-mode analog baseband circuit of the embodiment;

[0028] Figure 5 It is a simulation diagram of the amplitude-frequency curve of the FMCW radar analog baseband circuit with a high-pass cut-off frequency of 800 Hz in the multi-mode analog baseband circuit of the embodiment;

[0029] Figure 6 It is a simulation diagram of the amplitude-frequency curve of the FMCW radar analog baseband circuit with a high-pass cut-off frequency of 6.4 KHz in the multi-mode analog baseband circuit of the embodiment;

[0030] Figure 7 It is a simulation diagram of the amplitude-frequency curve of the Doppler radar analog baseband circuit in the multi-mode analog baseband circuit of the embodiment;

[0031] Figure 8 It is a simulation diagram of the equivalent input noise of the Doppler radar analog baseband circuit in the multi-mode analog baseband circuit of the embodiment. Specific embodiments

[0032] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments.

[0033] A multi-mode analog baseband circuit in this embodiment includes a high-pass filter, a three-stage variable gain amplifier with DC offset cancellation feedback, and an output driving buffer; the high-pass filter, the three-stage variable gain amplifier, and the output driving buffer are cascaded in sequence. Through the control of MOS transistor switches, the circuit can be switched between the FMCW radar simulator circuit mode and the Doppler radar analog baseband circuit mode, and different frequency bands can also be switched in the FMCW radar analog baseband circuit mode.

[0034] The variable gain amplifier with DC offset cancellation feedback in three stages, and each stage of the chopper amplifier includes a chopper amplifier, the amplifier, several switches, capacitors, resistors, etc.

[0035] As Figure 1 shown, the amplifier is a two-stage amplifier circuit (amplifier) with Miller compensation and a common-mode negative feedback circuit;

[0036] The first-stage amplifier circuit (amplifier) includes a common-source amplifier structure, and the common-source amplifier structure includes a first active load transistor M3, a second active load transistor M4, and a current bias transistor M5. The source of the current bias transistor M5 is connected to the power supply voltage VDD, the drain of the current bias transistor M5 is connected to the sources of the first amplifier transistor M1 and the second amplifier transistor M2, and the first amplifier transistor M1 and the second amplifier transistor M2 are also respectively connected to both ends of the input signal; the drains of the first active load transistor M3 and the second active load transistor M4 are connected to the drains of the first amplifier transistor M1 and the second amplifier transistor M2; the sources of the first active load transistor M3 and the second active load transistor M4 are connected to the ground voltage VSS; the gates of the first active load transistor M3 and the second active load transistor M4 are connected together and connected to the drain of the M13 transistor;

[0037] The second-stage amplifier circuit (amplifier) includes a third amplifier transistor M6, a fourth amplifier transistor M7, a third active load transistor M8, a fourth active load transistor M9, and a bias current; the third amplifier transistor M6 and the fourth amplifier transistor M7 are respectively connected to the drains of the first amplifier transistor M1 and the second amplifier transistor M2, the drains of the third amplifier transistor M6 and the fourth amplifier transistor M7 are respectively connected to the drains of the third active load transistor M8 and the fourth active load transistor M9, the sources of the third active load transistor M8 and the fourth active load transistor M9 are connected to the power supply voltage VDD, and these two nodes are respectively used as output nodes VON and VOP; the output nodes VON and VOP are respectively connected to one end of a first capacitor C1 and a second capacitor C2, the other ends of the first capacitor C1 and the second capacitor C2 are respectively connected to one end of a first resistor R1 and a second resistor R2, and the other ends of the first resistor R1 and the second resistor R2 are connected to the gates of the third amplifier transistor M6 and the fourth amplifier transistor M7. The first capacitor C1, the first resistor R1, the second capacitor C2, and the second resistor R2 are used for Miller compensation.

[0038] The third resistor R3 and the fourth resistor R4 are used to detect the common-mode voltage at both ends of the output. One end of the third resistor R3 and the fourth resistor R4 are respectively connected to the output points VOP and VON, and the other ends are both connected to the gate of M11. The gate of M12 is connected to the common-mode reference voltage VCM. The sources of M11 and M12 are both connected to the drain of M15. The source of M15 is connected to the power supply VDD. The gate of the M15 transistor is connected to the gates of the M9, M5, M8, and M10 transistors. The gates and drains of the M13 and M14 transistors are connected to each other. The drains of the M13 and M14 transistors are respectively connected to the drains of M11 and M12. The sources of the M13 and M14 transistors are connected to the ground VSS. And the drain of M13 is also connected to the gates of M3 and M4. The gate and drain of the M10 transistor are connected to each other, and a bias current is injected from the drain. Among them, the sizes of the first amplifier transistor M1, the second amplifier transistor M2, the first active load transistor M3, and the second active load transistor M4 in the input stage are relatively large to reduce mismatch and flicker noise. The first amplifier transistor M1 and the second amplifier transistor M2 are PMOS to reduce noise.

[0039] As Figure 3 shown, the chopper amplifier includes two such choppers. The input signal is up-converted by the chopper and then down-converted at the output to keep the input signal frequency unchanged while the offset voltage and noise are shifted to high frequencies. The output signal can filter out the offset voltage and noise after passing through a low-pass filter. Among them, the two input terminals of the first chopper serve as the two input terminals of the chopper amplifier. The output terminal of the first chopper is respectively connected to the gates of the first amplifier transistor M1 and the second amplifier transistor M2. The second chopper is connected between the output of the first-stage amplifier and the input of the second-stage amplifier. The inputs of the two choppers are respectively connected to the drains of the first amplifier transistor M1 and the second amplifier transistor M2. The outputs of the two choppers are respectively connected to one end of the gates of the third amplifier transistor M6 and the fourth amplifier transistor M7 connected to the first resistor R1 and the second resistor R2.

[0040] As Figure 2 shown, the chopper includes four NMOS transistors. The gates of the first NMOS transistor Q1 and the third NMOS transistor Q3 are connected to the clock CLK1. The gates of the second NMOS transistor Q2 and the fourth NMOS transistor Q4 are connected to the clock CLK2. The drains of the first NMOS transistor Q1 and the second NMOS transistor Q2 are connected to one input end VIN1. The drains of the third NMOS transistor Q3 and the fourth NMOS transistor Q4 are connected to the other input end VIN2. The sources of the first NMOS transistor Q1 and the fourth NMOS transistor Q4 are connected to one end of the output VOUT1. The sources of the second NMOS transistor Q2 and the third NMOS transistor Q3 are connected to the other end of the output VOUT2.

[0041] A square wave signal is input to the first NMOS transistor Q1 and the third NMOS transistor Q3, and an inverted square wave signal is input to the second NMOS transistor Q2 and the fourth NMOS transistor Q4. The two signals can be switched. In one cycle, the input signal VIN1 will be output at the output terminal VOUT1 for half a cycle and at the output terminal VOUT2 for the other half cycle. The same applies to VIN2. Through continuous switching, the input voltage is shifted to the vicinity of the corresponding square wave frequency.

[0042] The high-pass filter is a second-order Two-Thomas type I high-pass filter with an adjustable high-pass cut-off frequency. The high-pass filter includes a first amplifier, a second amplifier, several capacitors and several resistors, and the connection relationship is as follows:

[0043] The input end of the analog baseband circuit is connected to the third capacitor C3. A first switch 1 is connected between the input end of the analog baseband circuit and the third capacitor C3, and the other end of the first switch 1 is connected to the two output ends of the first amplifier; the other end of the third capacitor C3 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the bias voltage VBIAS. At the same time, the other end of the fifth resistor R5 is respectively connected to the input stage of the second amplifier;

[0044] A fourth capacitor C4 is respectively connected to the positive input end and the negative output end on one side of the first amplifier, and the fourth capacitor C4 is connected in parallel with a first adjustable resistor R6; corresponding capacitors and adjustable resistors are also connected to the positive input end and the negative output end on the other side of the first amplifier.

[0045] The negative output end of the first amplifier is connected to the negative input end of the second amplifier through a second adjustable resistor R7, and the positive output end of the first amplifier is connected to the positive input end of the second amplifier through a second adjustable resistor R7; a fifth capacitor C5 is connected to the positive input end and the negative output end on one side of the second amplifier, and corresponding capacitors are also connected to the positive input end and the negative output end on the other side; the positive input end on one side of the first amplifier and the negative output end on one side of the second amplifier are respectively connected to both ends of a third adjustable resistor R8; the positive input end on the other side of the first amplifier and the negative output end on the other side of the second amplifier are also respectively connected to corresponding adjustable resistors. The above is the connection relationship between the high-pass filter and the two-stage amplifier circuit.

[0046] The three-stage variable gain amplifier with DC offset cancellation feedback, each stage of the chopper amplifier includes a chopper amplifier, a third amplifier, several switches, capacitors, resistors, etc.

[0047] The connection relationship of each stage of the adjustable gain amplifier with DC offset cancellation is as follows:

[0048] The negative output terminal of the second amplifier is connected to the positive input terminal of the chopper amplifier through the fourth adjustable resistor R9, and the positive output terminal of the second amplifier is connected to the negative input terminal of the chopper amplifier through the corresponding adjustable resistor; a fifth adjustable resistor R10 is connected between the positive and negative input terminals on one side of the chopper amplifier, and a sixth adjustable resistor R11 is connected between the negative and positive input terminals on the other side of the chopper amplifier. A fourth switch 4 and a fifth switch 5 are also connected to both ends of the fifth adjustable resistor R10, and a sixth switch 6 and a seventh switch 7 are connected to both ends of the sixth adjustable resistor R11; the other ends of the fourth switch 4 and the fifth switch 5 are respectively connected to both ends of the sixth capacitor C6; one ends of the sixth switch 6 and the seventh switch 7 are respectively connected to the seventh capacitor C7, and the other ends are respectively connected to the negative input terminal, positive output terminal, positive input terminal, and negative output terminal of the third amplifier;

[0049] The positive and negative input terminals on one side of the chopper amplifier are connected to the second switch 2; a seventh adjustable resistor R12 is connected to both ends of the second switch 2, and the other end of the seventh adjustable resistor R12 is connected to the positive and negative output terminals on one side of the amplifier 3. The positive and negative input terminals on the other side of the chopper amplifier are connected to the third switch 3, and an eighth adjustable resistor R13 is connected to both ends of the third switch 3, and the other end of the eighth adjustable resistor R13 is connected to the positive and negative output terminals on the other side of the amplifier 3.

[0050] The structures of the second-stage adjustable gain amplifier and the third-stage adjustable gain amplifier are the same as those of the first-stage adjustable gain amplifier, and the output of the third-stage adjustable gain amplifier is further connected to the output buffer.

[0051] As Figure 4a 、 Figure 4b shown, in the working mode of the FMCW radar analog baseband circuit, switches 1, 4, 5, 10, 11, 16, and 17 are disconnected, and switches 2, 3, 6, 7, 8, 9, 12, 13, 14, 15, 16, 17, 18, and 19 are closed. The high-pass filter is a second-order high-pass filter, and its transfer function is:

[0052]

[0053] where H(s) is the system transfer function of the second-order high-pass filter, s represents a value in the transfer function, C3, C4, and C5 represent the capacitance values of the corresponding capacitors in the figure, and R6, R7, and R8 represent the resistance values of the corresponding resistors in the figure;

[0054] The cut-off frequency is:

[0055]

[0056] where fcut-off is the high-pass cut-off frequency, s represents a value in the transfer function, C4 and C5 represent the capacitance values of the corresponding capacitors in the figure, and R7 and R8 represent the resistance values of the corresponding resistors in the figure

[0057] In an embodiment of the present invention, according to the system specifications, appropriate capacitance and resistance values are selected through calculation. In this embodiment, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 are made equal, so that the gain of the high-pass filter is 0. R2, R3, and R4 in the circuit are variable capacitor arrays and can be switched to a circuit mode with a high-pass cut-off frequency of 800 Hz and a circuit mode with a high-pass cut-off frequency of 6.4 KHz. Then there are three variable gain amplifier circuits with DC offset cancellation feedback. The main amplifiers of the first stage and the second stage are amplifiers with chopping functions

[0058] The transfer function of the first-stage variable gain amplifier circuit is

[0059]

[0060] where A(s) VGA represents the transfer function of the amplifier, and H(s) VGA represents the system transfer function of the circuit after the DC offset circuit. C4 represents the capacitance value of the corresponding capacitor in the figure, and R9, R12, and R13 represent the resistance values of the corresponding resistors in the figure

[0061] In another embodiment of the present invention, according to the system requirements design, appropriate resistance and capacitance values are selected. The fourth adjustable resistor R9 in this embodiment is a variable resistor array. Switching the value of R9 can change the ratio of R9 to R10, thereby adjusting the gain of the variable gain amplifier. Since the high-pass cut-off frequency of this amplifier is affected by the relationship between R9, C6, R12, and R13, and the value of R9 will affect the gain of the circuit, and the values of R10 and C6 will affect the low-pass cut-off frequency of the circuit in the Doppler radar mode, the values of R10 and C6 are set to fixed values, the values of R10 and R11 are equal, and the values of C5 and C6 are equal. R12 and R13 are also variable resistor arrays. Switching different resistance values can switch different high-pass cut-off frequencies. Three levels of this structure can provide a roll-off of -60 dB / dec. In this mode, the MOS transistor gates in the chopper of the chopping amplifier are all applied with DC voltage bias signals instead of square wave signals, that is, chopping is not required. The output buffer is used to improve the load driving ability of the analog baseband circuit and convert the differential signal into a single-ended signal

[0062] In the operating mode of the Doppler radar analog baseband circuit, switches 2, 3, 6, 7, 8, 9, 12, 13, 14, 15, 18, and 19 are open, and switches 1, 4, 5, 10, 11, 16, and 17 are closed. When switch 1 is closed, the input and output of the second-order high-pass filter are short-circuited, and no signal passes through. The signal is directly input to the first-stage variable gain amplifier. The structure of the variable gain amplifier in this mode is different from that in the FMCW radar mode. In this mode, the feedback path is open and C6 is connected in parallel with R10 through a switch, thus forming a low-pass filter. The gain adjustment is also achieved by adjusting the R9 resistor array. At the same time, the gates of the MOS transistors of the choppers in the chopper amplifiers of the first-stage and second-stage variable gain amplifiers are input with a square wave signal of a high frequency of 100 KHz to reduce the noise of the circuit. The low-pass cut-off frequency in this circuit mode is approximately 1.6 KHz.

[0063] As Figure 5 shown, in the mode where the high-pass cut-off frequency of the FMCW radar analog baseband circuit is 800 Hz, the high-pass cut-off frequency of the circuit is approximately 800 Hz, and the circuit can achieve a gain adjustment of 20 dB - 80 dB with a step of 10 dB.

[0064] As Figure 6 shown, in the mode where the high-pass cut-off frequency of the FMCW radar analog baseband circuit is 6.4 KHz, the high-pass cut-off frequency of the circuit is approximately 6.4 KHz, and the circuit can achieve a gain adjustment of 20 dB - 80 dB with a step of 10 dB.

[0065] As Figure 7 shown, in the mode of the Doppler radar analog baseband circuit, the low-pass cut-off frequency of the circuit is approximately 1.6 KHz, and the circuit can achieve a gain adjustment of 20 dB - 80 dB with a step of 10 dB.

[0066] As Figure 8 shown, this simulation diagram is the equivalent input noise curve in the mode where the gain of the Doppler radar analog baseband circuit is 80 dB. The yellow curve is the equivalent input noise curve without using a chopper amplifier, and the red curve is the equivalent input noise curve with using a chopper amplifier. It can be seen that after using the chopper amplifier, the equivalent input noise of the circuit is greatly reduced.

[0067] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A multi-mode analog baseband circuit, characterized in that, it includes a high-pass filter, three variable gain amplifiers with DC offset cancellation feedback, and an output driving buffer; the high-pass filter, the three variable gain amplifiers with DC offset cancellation feedback, and the output driving buffer are cascaded in sequence. Through the control of MOS transistor switches, the circuit is switched between the FMCW radar simulator circuit mode and the Doppler radar analog baseband circuit mode, and different frequency bands are switched in the FMCW radar analog baseband circuit mode; each chopper amplifier of the three variable gain amplifiers with DC offset cancellation feedback includes a chopper, a two-stage amplifier circuit with Miller compensation and a common-mode negative feedback circuit, several switches, capacitors and resistors; the structures of the second-stage variable gain amplifier and the third-stage variable gain amplifier are the same as that of the first-stage variable gain amplifier, and the output of the third-stage variable gain amplifier is further connected to the output buffer; the input end of the first-stage variable gain amplifier is connected to the output end of the high-pass filter through a resistor R9, the input end of the second-stage variable gain amplifier is connected to the output end of the first-stage variable gain amplifier through a resistor R14, and the input end of the third-stage variable gain amplifier is connected to the output end of the second-stage variable gain amplifier through a resistor R19; the two-stage amplifier circuit with Miller compensation and a common-mode negative feedback circuit is the first-stage amplifier circuit and the second-stage amplifier circuit; the first-stage amplifier circuit includes a common-source amplifier structure, and the common-source amplifier structure includes a first active load transistor M3, a second active load transistor M4, and a current bias transistor M5. The source of the current bias transistor M5 is connected to the power supply voltage VDD, the drain of the current bias transistor M5 is connected to the sources of the first amplifier transistor M1 and the second amplifier transistor M2, and the first amplifier transistor M1 and the second amplifier transistor M2 are also respectively connected to both ends of the input signal; the drains of the first active load transistor M3 and the second active load transistor M4 are connected to the drains of the first amplifier transistor M1 and the second amplifier transistor M2; the sources of the first active load transistor M3 and the second active load transistor M4 are connected to the ground voltage VSS; the gates of the first active load transistor M3 and the second active load transistor M4 are connected together and connected to the drain of the M13 transistor; The second-stage amplifier circuit includes a third amplifying transistor M6, a fourth amplifying transistor M7, a third active load transistor M8, a fourth active load transistor M9, and a bias current. The third amplifying transistor M6 and the fourth amplifying transistor M7 are respectively connected to the drains of the first amplifying transistor M1 and the second amplifying transistor M2. The drains of the third amplifying transistor M6 and the fourth amplifying transistor M7 are respectively connected to the drains of the third active load transistor M8 and the fourth active load transistor M9. The sources of the third active load transistor M8 and the fourth active load transistor M9 are connected to the power supply voltage VDD. The drains of the third active load transistor M8 and the fourth active load transistor M9 are respectively used as output nodes VON and VOP. The output nodes VON and VOP are respectively connected to one ends of a first capacitor C1 and a second capacitor C2. The other ends of the first capacitor C1 and the second capacitor C2 are respectively connected to one ends of a first resistor R1 and a second resistor R2. The other ends of the first resistor R1 and the second resistor R2 are connected to the gates of the third amplifying transistor M6 and the fourth amplifying transistor M7. The first capacitor C1, the first resistor R1, the second capacitor C2, and the second resistor R2 are used for Miller compensation. The third resistor R3 and the fourth resistor R4 are used to detect the common-mode voltage at both ends of the output. One ends of the third resistor R3 and the fourth resistor R4 are respectively connected to the output points VOP and VON, and the other ends are both connected to the gate of M11. The gate of M12 is connected to the common-mode reference voltage VCM. The sources of M11 and M12 are both connected to the drain of M15. The source of M15 is connected to the power supply VDD. The gate of the M15 transistor is connected to the gates of the M9, M5, M8, and M10 transistors. The gates and drains of the M13 and M14 transistors are connected to each other. The drains of the M13 and M14 transistors are respectively connected to the drains of M11 and M12. The sources of the M13 and M14 transistors are connected to the ground VSS. And the drain of M13 is also connected to the gates of M3 and M4. The gate and drain of the M10 transistor are connected to each other, and the bias current is injected from the drain. The chopper amplifier includes a first chopper and a second chopper. The output end of the first chopper is respectively connected to the gates of the first amplifying transistor M1 and the second amplifying transistor M2. The second chopper is connected between the output of the first-stage amplifier and the input of the second-stage amplifier. The inputs of the two choppers are respectively connected to the drains of the first amplifying transistor M1 and the second amplifying transistor M2. The outputs of the two choppers are respectively connected to one ends of the gates of the third amplifying transistor M6 and the fourth amplifying transistor M7, which are connected to the first resistor R1 and the second resistor R2. Each chopper includes four NMOS transistors. The gates of the first NMOS transistor Q1 and the third NMOS transistor Q3 are connected to the clock CLK1. The gates of the second NMOS transistor Q2 and the fourth NMOS transistor Q4 are connected to the clock CLK2. The drains of the first NMOS transistor Q1 and the second NMOS transistor Q2 are connected to one input end VIN1. The drains of the third NMOS transistor Q3 and the fourth NMOS transistor Q4 are connected to the other input end VIN2. The sources of the first NMOS transistor Q1 and the fourth NMOS transistor Q4 are connected to one output end VOUT1. The sources of the second NMOS transistor Q2 and the third NMOS transistor Q3 are connected to the other output end VOUT2. The connection relationship of each stage of variable gain amplifier with DC offset cancellation is as follows: The negative output terminal of the high-pass filter is connected to the positive input terminal of the chopper amplifier through the fourth adjustable resistor R9, and the positive output terminal of the high-pass filter is connected to the negative input terminal of the chopper amplifier through the corresponding adjustable resistor; a fifth adjustable resistor R10 is connected between the positive input terminal and the negative output terminal on one side of the chopper amplifier, and a sixth adjustable resistor R11 is connected between the negative input terminal and the positive output terminal on the other side of the chopper amplifier. The fourth switch 4 and the fifth switch 5 are also connected to both ends of the fifth adjustable resistor R10, and the sixth switch 6 and the seventh switch 7 are also connected to both ends of the sixth adjustable resistor R11; the other ends of the fourth switch 4 and the fifth switch 5 are respectively connected to both ends of the sixth capacitor C6; one ends of the sixth switch 6 and the seventh switch 7 are respectively connected to the seventh capacitor C7, and the other ends are respectively connected to the negative input terminal, the positive output terminal, the positive input terminal, and the negative output terminal of the third amplifier. The positive and negative input terminals on one side of the chopper amplifier are connected to the second switch 2; a seventh adjustable resistor R12 is connected to both ends of the second switch 2, and the other end of the seventh adjustable resistor R12 is connected to the positive and negative output terminals on one side of the amplifier 3. The positive and negative input terminals on the other side of the chopper amplifier are connected to the third switch 3, and an eighth adjustable resistor R13 is connected to both ends of the third switch 3. The other end of the eighth adjustable resistor R13 is connected to the positive and negative output terminals on the other side of the amplifier 3.

2. A multi-mode analog baseband circuit according to claim 1, characterized in that, The high-pass filter includes a first amplifier, a second amplifier, several capacitors and several resistors. The input terminal of the analog baseband circuit is connected to the third capacitor C3. A first switch 1 is connected between the input terminal of the analog baseband circuit and the second capacitor C1, and the other end of the first switch 1 is connected to the two output terminals of the first amplifier; the other end of the third capacitor C3 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the bias voltage VBIAS. At the same time, the other end of the fifth resistor R5 is respectively connected to the input stage of the second amplifier. The positive input terminal and the negative output terminal on one side of the first amplifier are respectively connected to the fourth capacitor C4, and the fourth capacitor C4 is connected in parallel with the first adjustable resistor R6; the positive input terminal and the negative output terminal on the other side of the first amplifier are also connected to the corresponding capacitors and adjustable resistors. The negative terminal of the first amplifier is connected to the negative terminal of the second amplifier through the second adjustable resistor R7, and the positive terminal of the first amplifier is connected to the positive terminal of the second amplifier through the second adjustable resistor R7; a fifth capacitor C5 is connected between the positive input terminal and the negative output terminal on one side of the second amplifier, and the corresponding capacitors are also connected between the positive input terminal and the negative output terminal on the other side; the positive input terminal on one side of the first amplifier and the negative output terminal on one side of the second amplifier are respectively connected to both ends of the third adjustable resistor R8; the positive input terminal on the other side of the first amplifier and the negative output terminal on the other side of the second amplifier are also respectively connected to the corresponding adjustable resistors.

3. A multi-mode analog baseband circuit according to claim 1, characterized in that, The high-pass filter is a second-order Two-Thomas type I high-pass filter with an adjustable high-pass cut-off frequency.

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