SPAD Pixel Circuit and Method for Direct Time-of-Flight Sensor

Abstract

The present invention generally relates to sensing devices. In a specific embodiment, the present invention provides a SPAD pixel device that includes a p-type material that partially encloses an n-type material. The junction between the p-type material and the n-type material is three-dimensional and includes a horizontal region and a lateral region. The SPAD pixel device also includes an isolation structure that separates the SPAD pixel device from other devices. There are also other embodiments.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 992,617, filed on March 20, 2020, titled "SPAD PIXEL DESIGN FOR DIRECT TIME OF FLIGHT SENSOR", which is commonly owned and incorporated herein by reference for all purposes. Technical Field

[0003] The present invention generally relates to sensing devices. Background Art

[0004] The research and development of integrated microelectronics continue to make remarkable progress in sensor devices. There are many examples of photodiodes. For example, a photodiode is a p - n junction or a PIN structure. When photons of sufficient energy strike the diode, it generates electron - hole pairs. This mechanism is also known as the internal photoelectric effect. If the absorption occurs in the depletion region of the junction or within one diffusion length away from it, these carriers are swept out of the junction by the built - in electric field of the depletion region. Thus, as holes move towards the anode (electrons move towards the cathode), a photocurrent is generated. The total current through the photodiode is the sum of the dark current (the current generated in the absence of light) and the photocurrent, so the dark current must be minimized to maximize the sensitivity of the device.

[0005] Another example of a photodiode is called an "avalanche photodiode". An avalanche photodiode is a photodiode with a structure optimized for operation at a high reverse bias close to the reverse breakdown voltage. This avalanche photodiode allows individual photo - generated carriers to be multiplied by avalanche breakdown, resulting in internal gain within the photodiode, which improves the effective sensitivity of the device. One type of photodiode - commonly known as a Single - Photon Avalanche Diode (SPAD) device - has become popular and is used in various applications, such as LIDAR systems, which have become a mainstream component in consumer electronics, automotive, and other applications.

[0006] From the above, it can be seen that there is a great need for technologies for improving sensing devices. Summary of the Invention

[0007] The present invention generally relates to sensing devices. In a specific embodiment, the present invention provides an SPAD pixel device that includes a p - type material that partially encloses an n - type material. The junction between the p - type material and the n - type material is three - dimensional and includes a horizontal region and a lateral region. The SPAD pixel device also includes an isolation structure that separates the SPAD pixel device from other devices. There are also other embodiments.

[0008] According to an embodiment, the present invention provides a backside-illuminated (BSI) single-photon avalanche diode (SPAD) sensor device, the BSI SPAD sensor device including a silicon material having a front side and a back side. The device further includes a first deep trench structure positioned within the silicon material. The device further includes a second deep trench structure positioned within the silicon material. The device further includes an aperture positioned on the back side and between the first deep trench structure and the second deep trench structure. The device further includes an n-type material having a first top region and a first bottom region, the first bottom region being in contact with the front side. The first top region may include a first sidewall and a second sidewall. The n-type material is characterized by a first width. The device further includes an n-type contact directly coupled to the n-type material and positioned within the first bottom region. The device further includes a p-type material having a second top region and a second bottom region, the second bottom region enclosing the first top region. The p-type material is characterized by a second width greater than the first width. The device further includes a junction region constructed at an interface between the first top region and the second bottom region.

[0009] The device may include a first shallow trench structure in junction with the first deep trench structure and a second shallow trench structure in junction with the second deep trench structure. The device may include a first p-type contact in junction with the first shallow trench structure and a second p-type contact in junction with the second shallow trench structure.

[0010] The device may include a first p-type contact constructed within the first shallow trench structure and near the front side. The device may further include a second p-type contact constructed within the second shallow trench structure and near the front side.

[0011] The device may include a p+ region positioned near the back side. The device may include a plurality of light trapping structures constructed near the back side. The device may include a plurality of light trapping structures constructed near the front side. The junction region may include an avalanche region. The device may first include a first p-well structure partially enclosing the first deep trench structure and a second p-well structure partially enclosing the second deep trench structure. The silicon material may include epitaxially grown silicon material. The device may include a passivation layer covering the aperture. The p-type material is characterized by a graded doping profile. The device may include an n-well region partially covering the first bottom region of the n-type material.

[0012] According to another embodiment, the present invention provides a single-photon avalanche diode (SPAD) sensor device. The device includes a silicon material having a positive side and a back side. The device further includes a first isolation structure positioned within the silicon material and junctioned with the back side. The device further includes a second isolation structure positioned within the silicon material and junctioned with the back side. The device further includes an n-type material having a first top region and a first bottom region, the first bottom region being junctioned with the positive side. The first top region may include a first sidewall and a second sidewall. The n-type material is characterized by a first width. The device further includes an n-type contact directly coupled to the n-type material and positioned within the first bottom region. The device further includes a p-type material having a second top region and a second bottom region. The second bottom region encloses the first top region. The p-type material is characterized by a second width greater than the first width. The device further includes a junction region constructed at the interface between the first top region and the second bottom region.

[0013] The implementation may include one or more of the following features. The device may include an aperture positioned on the back side and between the first isolation structure and the second isolation structure. The device may include a passivation layer covering the aperture and the first isolation structure. The first isolation structure may include a first deep trench structure and a first p-well structure, the first p-well structure partially enclosing the first deep trench structure. The second isolation structure may include a second deep trench structure and a second p-well structure, the second p-well structure partially enclosing the second deep trench structure. The device may include a first shallow trench structure junctioned with the first p-well structure and a second shallow trench structure junctioned with the second p-well structure.

[0014] According to yet another embodiment, the present invention provides a frontside illuminated (FSI) single-photon avalanche diode (SPAD) sensor. The device further includes a silicon material having a positive side and a back side. The device further includes a first isolation structure positioned within the silicon material. The device further includes a second isolation structure positioned within the silicon material. The device further includes an aperture positioned on the positive side and constructed between the first isolation structure and the second isolation structure. The device further includes an n-type material having a first top region and a first bottom region, the first top region being junctioned with the back side. The first bottom region may include a first sidewall and a second sidewall. The n-type material is characterized by a first width. The device further includes an n-type contact directly coupled to the n-type material and positioned within the first top region. The device further includes a p-type material having a second top region and a second bottom region. The second top region encloses the first bottom region. The p-type material is characterized by a second width greater than the first width. The device further includes a junction region constructed at the interface between the first top region and the second bottom region.

[0015] In various embodiments, the first isolation structure may include a p-well region.

[0016] The present invention achieves many benefits over conventional techniques. For example, the present technology provides an easy-to-use process that relies on conventional techniques. In some embodiments, the method provides a higher device yield per wafer die using an integrated approach. Additionally, the method provides a process and system that are compatible with conventional process technologies without substantial modification of conventional equipment and processes. Preferably, the present invention provides improved CMOS integrated circuit devices and related methods for various uses. One or more of these benefits may be achieved according to embodiments. These and other benefits will be described more fully and specifically below in this specification.

[0017] The present invention achieves these and other benefits in the context of known technologies. However, a further understanding of the nature and advantages of the present invention can be achieved by reference to the later parts of the specification and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The following drawings are merely examples and should not unduly limit the scope of the claims herein. Those of ordinary skill in the art will recognize many other variations, modifications, and alternatives. It should also be understood that the examples and embodiments described herein are for illustrative purposes only, and those skilled in the art will envision various modifications or variations based on the examples and embodiments, and such modifications or variations will be included within the spirit and scope of the process and the appended claims.

[0019] Figure 1A and Figure 1B is a simplified diagram illustrating a BSI SPAD pixel device 100 according to an embodiment of the present invention.

[0020] Figure 1C is a simplified diagram illustrating the operation of an exemplary SPAD pixel device.

[0021] Figure 1D is a simplified diagram illustrating exemplary doping concentrations of a P-SPAD region 104 and an N-SPAD region 105 according to an embodiment of the present invention.

[0022] Figure 2A and Figure 2B is a simplified diagram illustrating a BSI SPAD pixel device 200 having an n-well region according to an embodiment of the present invention.

[0023] Figure 3A and Figure 3B is a simplified diagram illustrating a BSI SPAD pixel device 300 having a guard ring structure according to an embodiment of the present invention.

[0024] Figure 4Is a simplified diagram illustrating a BSI SPAD pixel device 400 with a passivation layer according to an embodiment of the present invention.

[0025] Figure 5 Is a simplified diagram illustrating a BSI SPAD pixel device 500 with an optical trapping structure according to an embodiment of the present invention.

[0026] Figure 6 Is a simplified diagram illustrating a BSI SPAD pixel device 600 with an optical trapping structure according to an embodiment of the present invention.

[0027] Figure 7 Is a simplified diagram illustrating a BSI SPAD pixel device 700 with a backside contact according to an embodiment of the present invention.

[0028] Figure 8 Is a simplified diagram illustrating a BSI SPAD pixel device 800 with a backside contact and an optical trapping structure according to an embodiment of the present invention.

[0029] Figure 9 Is a simplified diagram illustrating a shallow SPAD region of a BSI SPAD pixel device 900 according to an embodiment of the present invention.

[0030] Figure 10 Is a simplified diagram illustrating a BSI SPAD pixel device 1000 with a partial deep trench structure according to an embodiment of the present invention.

[0031] Figure 11 Is a simplified diagram illustrating a FSI SPAD pixel device 1100 according to an embodiment of the present invention.

[0032] Figure 12 Is a simplified diagram illustrating a SPAD pixel device 1200 according to an embodiment of the present invention. Detailed Description

[0033] The present invention generally relates to sensing devices. In a specific embodiment, the present invention provides a SPAD pixel device that includes a p-type material that partially encloses an n-type material. The junction between the p-type material and the n-type material is three-dimensional and includes a horizontal region and a lateral region. The SPAD pixel device also includes an isolation structure that separates the SPAD pixel device from other devices. There are also other embodiments.

[0034] The following description is provided to enable a person of ordinary skill in the art to make and use the invention and to incorporate it into the context of a particular application. Various modifications and various uses in different applications will be apparent to those skilled in the art, and the general principles defined herein can be applied to a wide range of embodiments. Thus, the invention is not intended to be limited to the embodiments presented, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0035] In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the invention may be practiced without necessarily being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail in order to avoid obscuring the invention.

[0036] The reader's attention is directed to all papers and documents that are filed concurrently with this specification, and these papers and documents are hereby incorporated by reference in their entirety and are made available to the public in connection with this specification. All features disclosed in this specification (including any appended claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent, or similar purpose, unless expressly stated otherwise. Thus, each feature disclosed herein is merely an example of a series of general equivalent or similar features.

[0037] Furthermore, no element in a claim that does not expressly state "means for performing a specified function" or "step for performing a particular function" should be construed as a "means" or "step" clause as specified in paragraph 6 of section 112 of Title 35 of the United States Code. In particular, the use of "step of..." or "act of..." in the claims herein is not intended to invoke the provisions of paragraph 6 of section 112 of Title 35 of the United States Code.

[0038] Note that if used, the labels left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise are used for convenience only and are not intended to imply any particular fixed direction. Instead, they are used to reflect the relative positions and / or orientations between various parts of an object.

[0039] Figure 1A and Figure 1B are simplified diagrams illustrating a BSI SPAD pixel device 100 according to an embodiment of the present invention. These diagrams provide only examples and should not unduly limit the scope of the claims. A person of ordinary skill in the art will recognize many variations, alternatives, and modifications. More specifically, Figure 1A is a cross-sectional view, Figure 1BIt is a bird's-eye view. In various embodiments, the BSI SPAD pixel device 100 is fabricated within the silicon material 101. For example, the silicon material 101 can be formed by an epitaxial growth process. As shown, an epitaxial material thickness ranging from about 3 μm to about 12 μm is grown using a high-temperature growth technique, etc. In one example, chemical vapor deposition (CVD) process is used for epitaxial growth. In various embodiments, the SPAD pixel device 100 can be configured on a semiconductor substrate that includes wirings and circuits for interconnecting a number of SPAD pixel devices. For example, the p-contacts (106A and 106B) and the n-contact (108) are coupled to the underlying circuits (not shown). As an example, the substrate can be a complementary metal-oxide silicon (CMOS) substrate, a blank or unpatterned substrate, a patterned hybrid substrate, etc. In one example, the semiconductor substrate has a number of CMOS cells for logic circuits and can also include a number of memory cells, interface units, and other circuit elements. As shown, the substrate has bonding regions and logic circuits, which can be configured as output, quenching, recharge circuits, etc. Of course, there can be other variations, modifications, and alternatives.

[0040] As an example, in Figure 1A it, the top side of the silicon material is referred to as the "back side", while the bottom side of the silicon material is referred to as the "front side". The terms "front" and "back" refer to the front side and the back side of the semiconductor wafer during the manufacturing process, during which various processes are performed on the front side of the wafer. BSI SPAD refers to the side where light (e.g., photons) enters the SPAD device. The aperture region 110 is located on the back side of the SPAD device 100. As described below, a microlens or other types of optical structures (e.g., nanostructures, anti-reflection coatings, color filters, bandpass filters, etc.) can be configured on the aperture region 110 of the BSI SPAD pixel device 100, and these optical structures help direct the incident light and signal photons to the target region, which is the junction between the n-type material 105 and the p-type material 104. A passivation layer (not shown) can be constructed around the aperture region. In one example, the passivation layer can include oxide materials, high-K dielectric materials (e.g., Al2O3, HfO2, Ta2O5, etc.), nitride materials (Si3N4, SiON, etc.), or polyimide materials, combinations thereof, etc.

[0041] The SPAD pixel device 100 is enclosed by an isolation structure that separates the device 100 from adjacent SPAD pixel devices. In various embodiments, the isolation structure includes a deep trench isolation (DTI) structure. For example, the DIT structures 102A-D (Figure 1B As shown in Figure 1B , four "walls" that enclose the SPAD pixel device 100 are formed. In one embodiment, the DTI structure includes a filling material, a surrounding material, and a surrounding insulating material. In one example, the filling material includes a metallic material, a semiconductor material, or an insulating material. In a preferred example, the filling material is tungsten. In one example, the surrounding material is Al2O3. Depending on the implementation, other materials may also be used. In one example, the surrounding insulating material includes an oxide or a nitride material, etc. In one example, the surrounding insulating material is SiO2.

[0042] The isolation structure may additionally include p-well regions 103A-D. In various embodiments, the p-well regions are characterized by p-type diffusion of boron. Depending on the implementation, other types of materials may also be used for p-type diffusion. For example, the p-well regions may be formed by multiple energy implantations on an epitaxial growth substrate rather than a substrate. Depending on the implementation, the isolation structure, which looks like the four boundary walls of the pixel device 100, may be implemented using a DTI structure and / or p-well regions. In Figure 1A Figure 1A , the DTI 102A and 102B extend from the top surface of the silicon material 101 all the way to the shallow trench isolation (STI) structures 107A and 107B, and the p-well regions 103A and 103B that interface with the lower portions of the DTI structures 102A and 102B. In certain embodiments (see Figure 10 below), the DTI structure only extends to the middle region of the silicon material, and the p-well regions extend between the DTI structure and the STI structure. In some implementations, the isolation structure may only include p-well regions and not include a DTI structure. In various embodiments, the p-well regions 103A and 103B may be formed by an implantation process that may use multiple energies ranging from a few hundred keV to a few MeV. The p-well regions may penetrate the entire epitaxial layer thickness to provide passivation and isolation.

[0043] Shallow trench isolation structures 107A and 107B are constructed below the deep trench isolation. In one example, the shallow trench isolation may include an oxide material as a filler. Depending on the implementation, the widths and other dimensions of the STI structures 107A and 107B are configured relative to the position of the n-type material 105. For example, the STI structures are within a width range (i.e., approximately the same width or narrower) relative to the DTI structure. P-type contact portions 106A and 106B (or sometimes referred to as "P+ " contact portions) are constructed at the bottom surface of the silicon material 101. The p-type contact portions 106A and 106B will be coupled to a metal contact portion (such as copper, tungsten, etc.) of a circuit (such as a pixel control circuit for reading the output signal of the SPAD pixel device). The n-type contact portion 108 shown in the figure is coupled to the n-type material 105. For example, the n-type contact portion 108 and the p-type contact portions 106A and 106B may be constructed using various types of implant materials (such as conductive implanted silicon).

[0044] The performance of the SPAD pixel device is mostly measured by its ability to collect photo-generated carriers at the avalanche region 120 located between the p-type material 104 and the n-type material 105. For example, the avalanche region refers to a region within a certain proximity of the junction defined by the interface between the p-type material 104 and the n-type material 105. A large junction area translates to a large avalanche region, which is used to collect photo-generated carriers, which translates to good performance. However, it is difficult to maintain the size of the junction because there is a trend to reduce the size of the SPAD pixel device (e.g., down to below 10 μm). Therefore, it should be understood that embodiments of the present invention provide a design for increasing the size of the junction between the p-type material 104 and the n-type material 105. For example, the p-type material 104 shown in the figure (which may be referred to as "P-SPAD") includes an inverted p-well. For example, the P-SPAD may be formed by an implantation process (such as with one or more implantation energies). As implemented in various embodiments, the region of the p-type material 104 is associated with a non-uniform doping concentration profile. For example, the doping concentration is maximum near the active junction region at the junction between the p-type material 104 and the n-type material 105.

[0045] As shown in the figure, the n-type material 105 may include an n-well. For example, the n-type material 105 may be referred to as "N-SPAD". The N-SPAD may be formed by an implantation process, which may use multiple implantation energy levels. An important aspect of the n-type material 105 is its size: as shown in the figure, the n-type material 105 is narrower than the p-type material 104. The junction between the p-type material 104 and the n-type material 105 includes a horizontal interface and a vertical interface, as Figure 1AAs shown. More specifically, the bottom surface of the p-type material 104 interfaces with the top surface of the n-type material 105. And because the p-type material 104 is wider and encloses the n-type material 105, the top sidewalls of the n-type material 105 also interface with the p-type material 104. Compared with traditional designs, the sidewall portion of the junction interface generates a lateral electric field and increases the total area for collecting photo-generated carriers. Depending on the implementation, the sizes of the N-SPAD and P-SPAD can vary, but the width of the P-SPAD is always greater than the width of the N-SPAD, and the P-SPAD includes a region that partially encloses the N-SPAD.

[0046] It should be noted that both the N-SPAD 105 and P-SPAD 104 fabricated using the implantation process have non-uniform doping concentrations. For example, the p-type material 104 is formed by a first implantation process, and the p-type material 104 is characterized by a radial concentration gradient around the center. In various embodiments, the P-SPAD 104 is implanted into the silicon from the front side by at least 200 nm to ensure that the avalanche region is far from the front side and to reduce the undesired dark count rate (DCR). That is, carriers generated from defects at the front side will not travel to the avalanche region. In various embodiments, the P-SPAD 104 may have a concentration gradient from the avalanche region 120 towards the back side. This results in a wider P-SPAD region and a higher electric field. This configuration shortens the carrier travel time from the epitaxial region 101 to the avalanche region 120 and makes the jitter smaller. For example, the concentration gradient in the P-SPAD 104 can be generated by annealing after implantation; the concentration gradient can also be generated by using multiple energies in the implantation.

[0047] In various embodiments, the n-type material 105 is also formed by a second implantation process, and certain n-type dopants are implanted into a portion of the p-type material. The n-type implantation is at least 1 μm away from the p-well regions 103A and 103B to avoid a direct carrier path from the p-well regions 103A and 103B to the n-type contact 108 without passing through the avalanche region. The placement of the n-type material 105 is also to prevent the avalanche region 120 from extending from the desired junction region to the front side.

[0048] For example, the implanted p-type material contains a boron material with a concentration density of 1E15 atoms / cm3 to 1E18 atoms / cm3. For example, the implanted n-type material includes a phosphorus entity or an arsenic entity with a concentration density of 1E17 atoms / cm3 to 1E19 atoms / cm3. Of course, there can be other variations, modifications, and substitutions. As shown, the implanted p-type material and the implanted n-type material are configured near the semiconductor substrate of the pixel element or near the bonding region.

[0049] Figure 1Cis a simplified diagram illustrating the operation of an exemplary SPAD pixel device. This diagram is merely an example and should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. As shown, photo-generated carriers travel through path 130 (indicated by the dashed pattern) to the avalanche region 120. Carriers generated by defects at the front surface travel along path 131 (indicated by the dotted pattern), and they do not reach the avalanche region 120. It should be understood that the lateral region of the avalanche region 120 can significantly improve photon / carrier detection without picking up unwanted carriers.

[0050] Figure 1D is a simplified diagram illustrating the exemplary doping concentrations of the P-SPAD region 104 and the N-SPAD region 105 according to an embodiment of the present invention. This diagram is merely an example and should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. In various implementations, the P-SPAD 104 is formed using an implantation process that produces a radial concentration profile, as illustrated by arrows 150A - 150E; that is, the doping concentration (of the p-type material) is maximum at the center, the doping concentration is lower at region 151 than at the center of the P-SPAD, and the doping concentration is lower at region 152 than at 151. For example, the radial concentration profile helps the avalanche region 102 capture photo-generated carriers. There are also other benefits. It should also be noted that the N-SPAD 105 can be a rectangular cube (as previously described), and thus shares an interface with the P-SPAD 104 that includes five (one top and four sides) junction interfaces. The N-SPAD 105 can also be constructed in other shapes. For example, the top region of the N-SPAD 105 enclosed by the P-SPAD 104 can be generally spherical (or conical) in shape, which does not have distinct sides but shares a large junction interface (and thus a large avalanche region) with the P-SPAD 104.

[0051] Figure 2A and Figure 2BFIG. 0 is a simplified diagram illustrating a BSI SPAD pixel device 200 having an n-well region according to an embodiment of the present invention. These figures are provided only as examples and should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. Various components are constructed within a silicon material 201, which may be formed by an epitaxial growth process. The boundaries of device 200 are defined by isolation structures. For example, the isolation structures may include DTI structures (202A and 202B) and p-well structures (203A and 203B). Device 200 is coupled to a semiconductor circuit via n-contact 208 and p-contacts 206A and 206B. The avalanche region is near the junction between a p-type material 204 (“P-SPAD”) and an n-type material 205 (“N-SPAD”). The junction is a three-dimensional structure that includes a horizontal interface region and four lateral (sidewall) interface regions. The three-dimensional nature of the junction translates into a large avalanche region capable of effectively collecting photo-generated carriers.

[0052] An n-well structure 209 is constructed around the n-type material 205. For example, the n-well structure 209 is characterized by a doping concentration of 1E16 to 1E18. It should be understood that the n-well structure 209 can improve the performance of device 200 and reduce the unwanted DCR by reducing the lateral electric field.

[0053] Figure 3A and Figure 3B FIG. 9 is a simplified diagram illustrating a BSI SPAD pixel device 300 having a guard ring structure according to an embodiment of the present invention. These figures are provided only as examples and should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. Various components are constructed within a silicon material 301, which may be formed by an epitaxial growth process. The boundaries of device 300 are defined by isolation structures. For example, the isolation structures may include DTI structures (202A and 202B) and p-well structures (303A and 303B). The isolation structures may also include STI structures 307A and 307B. Device 300 is coupled to a semiconductor circuit via n-contact 208 and p-contacts 306A and 306B. The avalanche region is near the junction between a p-type material 304 (“P-SPAD”) and an n-type material 305 (“N-SPAD”). The junction is a three-dimensional structure that includes a horizontal interface region and four lateral (sidewall) interface regions. The three-dimensional nature of the junction translates into a large avalanche region capable of effectively collecting photo-generated carriers. An n-well structure 309 is constructed around the n-type material 305. It should be understood that the n-well structure 309 can improve the performance of device 300 and reduce the unwanted DCR by reducing the lateral electric field. Additionally, a guard ring structure 310 (having Figure 3BA square-shaped structure (not shown) is constructed around the n-well structure 309 to reduce the undesired paths between the n-type contact 308 and the p-type contacts 306A and 306B. For example, the guard ring structure 310 is effective in reducing the undesired electric field near the front side and reducing the DCR.

[0054] Figure 4 FIG. 4 is a simplified diagram illustrating a BSI SPAD pixel device 400 with a passivation layer according to an embodiment of the present invention. This figure is merely an example and should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. Various components are constructed within the silicon material 401, which can be formed by an epitaxial growth process. The boundaries of the device 400 are defined by isolation structures. For example, the isolation structures may include DTI structures (402A and 402B) and p-well structures (403A and 403B). The isolation structures may also include STI structures 407A and 407B. The device 400 is coupled to a semiconductor circuit via n-contacts 408 and p-contacts 406A and 406B. The avalanche region is near the junction between the p-type material 404 ("P-SPAD") and the n-type material 405 ("N-SPAD"). The junction is a three-dimensional structure that includes a horizontal interface region and four lateral (sidewall) interface regions. The three-dimensional nature of the junction translates into a large avalanche region capable of effectively collecting photo-generated carriers. The device 400 also includes a passivation layer 410. In one example, the passivation layer 410 includes an oxide material, a high-K dielectric material (such as Al2O3, HfO2, Ta2O5, etc.), a nitride material (Si3N4, SiON, etc.), or a polyimide material, combinations thereof, etc. For example, the passivation layer 410 is formed by an atomic layer deposition (ALD) process.

[0055] Figure 5FIG. 0 is a simplified diagram illustrating a BSI SPAD pixel device 500 with a light-trapping structure according to an embodiment of the present invention. This figure is merely an example and should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. Various components are fabricated within a silicon material 501, which may be formed by an epitaxial growth process. The boundaries of device 500 are defined by isolation structures. For example, the isolation structures may include DTI structures (502A and 502B) and p-well structures (503A and 503B). The isolation structures may also include STI structures 507A and 507B. Device 500 is coupled to a semiconductor circuit via n-contact 508 and p-contacts 506A and 506B. The avalanche region is near the junction between a p-type material 504 (“P-SPAD”) and an n-type material 505 (“N-SPAD”). The junction is a three-dimensional structure that includes a horizontal interface region and four lateral (sidewall) interface regions. The three-dimensional nature of the junction allows for a large avalanche region that can effectively collect photo-generated carriers. Device 400 also includes a passivation layer 510.

[0056] Device 500 also includes light-trapping structures at both the front side and the back side. It should be understood that the back-side light-trapping structure may also be configured in other shapes. Device 500 also includes front-side nanostructures (such as 512A - 512C) that are configured for light trapping. In certain embodiments, device 500 also includes a metal reflector configured for the front side of device 500.

[0057] Figure 6 FIG. 7 is a simplified diagram illustrating a BSI SPAD pixel device 600 with a light-trapping structure according to an embodiment of the present invention. This figure is merely an example and should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. Various components are fabricated within a silicon material 601, which may be formed by an epitaxial growth process. The boundaries of device 600 are defined by isolation structures. For example, the isolation structures may include DTI structures (602A and 602B) and p-well structures (603A and 603B). The isolation structures may also include STI structures 607A and 607B. Device 600 is coupled to a semiconductor circuit via n-contact 608 and p-contacts 606A and 606B. The avalanche region is near the junction between a p-type material 604 (“P-SPAD”) and an n-type material 605 (“N-SPAD”). The junction is a three-dimensional structure that includes a horizontal interface region and four lateral (sidewall) interface regions. The three-dimensional nature of the junction allows for a large avalanche region that can effectively collect photo-generated carriers.

[0058] Device 600 also includes light-trapping structures at both the front side and the back side. For example, the back-side light-trapping structure 611 covers the aperture of device 600 and is characterized by a seesaw shape. The back-side light-trapping structure 611 can also be configured in other shapes. Device 600 also includes front-side nanostructures (such as 612A - 612C) that are configured for light trapping. Device 600 also includes a passivation layer 610.

[0059] Figure 7 FIG. 4 is a simplified diagram illustrating a BSI SPAD pixel device 700 with a back-side contact according to an embodiment of the present invention. This figure is merely an example and should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. Various components are constructed within a silicon material 701, which can be formed by an epitaxial growth process. The boundary of device 700 is defined by isolation structures. For example, the isolation structures can include DTI structures (702A and 702B). The device also includes STI structures 707A and 707B. Device 700 is coupled to a semiconductor circuit via an n-contact 708 and p-contacts 706A and 706B. The avalanche region is near the junction between a p-type material 704 (“P-SPAD”) and an n-type material 705 (“N-SPAD”). The junction is a three-dimensional structure that includes a horizontal interface region and four lateral (sidewall) interface regions. The three-dimensionality of the junction translates into a large avalanche region capable of effectively collecting photo-generated carriers. Device 700 also includes a passivation layer 710.

[0060] A p-type region 712 is constructed near the back side of device 700. It should be noted that the p-contacts 706A and 706B are constructed on the back side of device 700. In the case where the p-contacts are positioned away from the n-contact 708 and the n-type material 705, the width of the N-SPAD 705 can be larger (e.g., compared to the N-SPAD 805), which can translate into a larger junction region and a larger avalanche region. Device 700 also includes a passivation layer 710. In one example, the passivation layer 710 includes an oxide material, a high-K dielectric material (such as Al2O3, HfO2, Ta2O5, etc.), a nitride material (Si3N4, SiON, etc.), or a polyimide material, combinations thereof, etc.

[0061] Figure 8FIG. 0 is a simplified diagram illustrating a BSI SPAD pixel device 800 with a back contact portion and a light-trapping structure according to an embodiment of the present invention. This figure is merely an example and should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. Various components are fabricated within a silicon material 801, which may be formed by an epitaxial growth process. The boundaries of the device 800 are defined by isolation structures. For example, the isolation structures may include DTI structures (802A and 802B). The device also includes STI structures 707A and 707B. The device 800 is coupled to a semiconductor circuit via an n-contact portion 808 and p-contact portions 806A and 806B. The avalanche region is near the junction between a p-type material 804 (“P-SPAD”) and an n-type material 805 (“N-SPAD”). The junction is a three-dimensional structure that includes a horizontal interface region and four lateral (sidewall) interface regions. The three-dimensionality of the junction translates into a large avalanche region capable of effectively collecting photo-generated carriers.

[0062] A p-type region 812 that can be implanted is fabricated near the back side of the device 800. The p-contact portions 806A and 806B are fabricated on the back side of the device 700. In the case where the p-contact portions are positioned away from the n-contact portion 808 and the n-type material 805, the width of the N-SPAD 805 can be larger (e.g., compared to the N-SPAD 805), which can translate into a larger junction region and a larger avalanche region. The device 800 also includes a passivation layer 810. In one example, the passivation layer 810 includes an oxide material, a high-K dielectric material (e.g., Al2O3, HfO2, Ta2O5, etc.), a nitride material (Si3N4, SiON, etc.), or a polyimide material, a combination thereof, etc. The device 800 also includes a light-trapping structure at both the front side and the back side. For example, the back-side light-trapping structure 811 covers the aperture of the device 800 and is characterized by a seesaw shape. The back-side light-trapping structure 811 can also be fabricated in other shapes. The device 800 also includes front-side nanostructures (e.g., 812A - 812C) that are configured for light trapping. The device 800 also includes a passivation layer 810.

[0063] Figure 9FIG. 0 is a simplified diagram illustrating the shallow SPAD region of the BSI SPAD pixel device 900 according to an embodiment of the present invention. This figure is merely an example and should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. Various components are constructed within the silicon material 901, which can be formed by an epitaxial growth process. The boundary of the device 900 is defined by the isolation structure. For example, the isolation structure may include DTI structures (902A and 902B) and p-well structures (903A and 903B). The device 900 is coupled to the semiconductor circuit via the n-contact 908 and the p-contacts 907A and 907B. The avalanche region is near the junction between the p-type material 904 (“P-SPAD”) and the n-type material 905 (“N-SPAD”). As Figure 9 can be seen, the P-SPAD 904 and the N-SPAD 905 are characterized by a low profile (e.g., compared to the P-SPAD 904 and the N-SPAD 905). The junction is a three-dimensional structure that includes a horizontal interface region and four lateral (sidewall) interface regions. The three-dimensionality of the junction translates into a large avalanche region capable of effectively collecting photo-generated carriers. The device 900 also includes a passivation layer 910. In one example, the passivation layer 910 includes an oxide material, a high-K dielectric material (such as Al2O3, HfO2, Ta2O5, etc.), a nitride material (Si3N4, SiON, etc.), or a polyimide material, combinations thereof, etc. For example, the passivation layer 910 is formed by an atomic layer deposition (ALD) process. The device 900 also includes a passivation layer 910.

[0064] Figure 10 FIG. 6 is a simplified diagram illustrating the BSI SPAD pixel device 1000 with a partial deep trench structure according to an embodiment of the present invention. This figure is merely an example and should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. Various components are constructed within the silicon material 1001, which can be formed by an epitaxial growth process. The boundary of the device 1000 is defined by the isolation structure. For example, the isolation structure may include DTI structures (1002A and 1002B) and p-well structures (1003A and 1003B). For example, the DTI structures 1002A and 1002B are formed from the back side of the device 1000 and they do not extend all the way down to the front side: they intersect with the corresponding p-well structures 1003A and 1004B. The device 1000 is coupled to the semiconductor circuit via the n-contact 1008 and the p-contacts 1007A and 1007B. The avalanche region is near the junction between the p-type material 1004 (“P-SPAD”) and the n-type material 1005 (“N-SPAD”). The junction is a three-dimensional structure that includes a horizontal interface region and four lateral (sidewall) interface regions. The three-dimensionality of the junction allows for a large avalanche region capable of effectively collecting photo-generated carriers.

[0065] Device 1000 also includes light trapping structures at both the front and back sides. For example, the backside light trapping structure covers the aperture of device 1000 and includes nanostructures 1011A-C as shown. In various embodiments, the nanostructures 1011A-C keep photons inside the pixel device and increase the chance that these photons will be collected. It should be understood that the backside light trapping structure can also be configured in other shapes. Device 1000 also includes front side nanostructures (such as 1012A - 1012C) which are configured for light trapping. Device 1000 also includes a passivation layer 1010.

[0066] Figure 11 is a simplified diagram illustrating an FSI SPAD pixel device 1100 according to an embodiment of the present invention. This figure is merely an example and should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. As described above, the term "front side" refers to the front or top side of the semiconductor wafer during the manufacturing process, and the front side is at the bottom of device 1100 in Figure 11 Device 1100's FSI configuration means that the aperture (the location where photons enter device 1100) is on the front side (at the bottom of device 1100 in Figure 11 ). In various embodiments, the boundary of device 1100 is defined by isolation structures. For example, the isolation structures include DTI structures (1103A and 1103B) as shown. For example, the isolation structures can also include STI structures (1102A and 1102B) as shown. For example, DTI structures 1102A and 1102B are formed from the front side of device 1100 and they do not extend all the way through the epitaxial layer. Device 1100 is coupled to a semiconductor circuit via n-contact 1108 and p-contacts 1106A and 1170B. The avalanche region is near the junction between the p-type material 1109 ("P-SPAD") and the n-type material 1007 ("N-SPAD"). The junction is a three-dimensional structure which includes a horizontal interface region and four lateral (sidewall) interface regions. The three-dimensional nature of the junction allows for a large avalanche region that can effectively collect photo-generated carriers.

[0067] Figure 12is a simplified diagram illustrating a SPAD pixel device 1200 according to an embodiment of the present invention. This diagram is merely an example and should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. In addition to other structures, the device 1200 also includes a silicon material 1201. For example, the silicon material 1201 can be formed by an epitaxial growth process. The device 1200 is separated from other SPAD pixel devices (not shown here) by isolation structures 1202A and 1202B. Depending on the implementation, the isolation structure can include DTI, STI, p-well, and / or other structures. An aperture region 1210 is constructed at the surface and between the isolation structures. For example, various optical structures or isolation layers can be constructed at the aperture region 1210. As shown, an n-type material region (or "N-SPAD") 1204 is constructed side by side with a p-type material region (or "P-SPAD") 1205. For example, the N-SPAD 1204 and the P-SPAD 1205 can be formed by implantation or other processes. An avalanche region 1210 is formed near the junction between the N-SPAD 1204 and the P-SPAD 1205. As shown, a p-type contact 1208 is constructed at a position near the P-SPAD 1205. As Figure 12 shown, the N-SPAD 1204 is characterized in that the bottom region encloses a volume of a part of the P-SPAD 1205 - the bottom region of the N-SPAD 1204 is larger than the top region of the N-SPAD 1205. As described above, compared with the existing SPAD designs, the three-dimensional nature of the avalanche region allows for improved carrier capture. It should be understood that instead of the P-SPAD partially enclosing the N-SPAD - as illustrated in FIGS. 1 to Figure 11 illustrated - the device 1200 has an N-SPAD that partially encloses the P-SPAD. Variations of the device 1200 can include its other structures and arrangements, such as different isolation and contact configurations, and optical structures (passivation layers, optical elements, reflectors, etc.).

[0068] Although the above is a complete description of specific embodiments, various modifications, alternative constructions, and equivalents can be used. Therefore, the above description and illustration should not be considered as limiting the scope of the present invention, which is defined by the appended claims.

Claims

1. A back-illuminated (BSI) single-photon avalanche diode (SPAD) sensor device, comprising: A silicon material having a front side and a back side; A first deep trench structure positioned within the silicon material; A second deep trench structure positioned within the silicon material; An orifice positioned on the back side and between the first deep trench structure and the second deep trench structure; An n-type material having a cubic structure with a first top region and a first bottom region, the first bottom region interfacing with the back side, the first top region including a first sidewall and a second sidewall, the n-type material being characterized by a first width; an n-well structure is constructed around the first bottom region of the n-type material; a guard ring structure is constructed around the n-well structure and is located between the first deep trench structure and the second deep trench structure; An n-type contact directly coupled to the n-type material and positioned within the first bottom region; A p-type material having a concave three-dimensional structure inverted over the first top region of the cubic structure, the concave three-dimensional structure having a flat second top region and a second bottom region with a notch, the second bottom region enclosing the first top region, the second bottom region of the p-type material being higher than the top of the n-well structure, the p-type material being characterized by a second width greater than the first width; And A junction region constructed at the interface between the first top region and the second bottom region.

2. The device according to claim 1, further comprising a first shallow trench structure intersecting with the first deep trench structure and a second shallow trench structure intersecting with the second deep trench structure.

3. The device according to claim 2, further comprising a first p-type contact portion intersecting with the first shallow trench structure and a second p-type contact portion intersecting with the second shallow trench structure.

4. The device according to claim 2, further comprising: A first p-type contact constructed within and near the first shallow trench structure and the front side; And A second p-type contact constructed within and near the second shallow trench structure and the front side.

5. The device according to claim 1, further comprising a P+ region positioned within the vicinity of the positive side.

6. The device according to claim 1, further comprising a plurality of light trapping structures constructed within the vicinity of the back side.

7. The device according to claim 1, further comprising a plurality of light trapping structures constructed within the vicinity of the positive side.

8. The device according to claim 1, wherein, The junction region includes an avalanche region.

9. The device according to claim 1, first comprising a first P-well structure partially enclosing the first deep trench structure and a second P-well structure partially enclosing the second deep trench structure.

10. The device according to claim 1, wherein, The silicon material includes an epitaxially grown silicon material.

11. The device according to claim 1, further comprising a passivation layer covering the orifice.

12. The device according to claim 1, wherein, The p-type material is characterized by a graded doping profile.

13. The device according to claim 1, further comprising an N-well region partially covering the first bottom region of the n-type material.

14. A single-photon avalanche diode (SPAD) sensor device, comprising: A silicon material having a front side and a back side; A first isolation structure positioned within the silicon material and interfacing with the back side; A second isolation structure positioned within the silicon material and interfacing with the back side; An n-type material having a cubic structure with a first top region and a first bottom region, the first bottom region interfacing with the back side, the first top region including a first sidewall and a second sidewall, the n-type material being characterized by a first width; an n-well structure is constructed around the first bottom region of the n-type material; a guard ring structure is constructed around the n-well structure and is located between the first deep trench structure and the second deep trench structure; An n-type contact directly coupled to the n-type material and positioned within the first bottom region; A p-type material having a concave three-dimensional structure inverted over the first top region of the cubic structure, the concave three-dimensional structure having a flat second top region and a second bottom region with a notch, the second bottom region enclosing the first top region, the second bottom region of the p-type material being higher than the top of the n-well structure, the p-type material being characterized by a second width greater than the first width; And A junction region constructed at the interface between the first top region and the second bottom region.

15. The device according to claim 14, further comprising an orifice positioned on the back side and between the first isolation structure and the second isolation structure.

16. The device according to claim 15, further comprising a passivation layer covering the orifice and the first isolation structure.

17. The device according to claim 14, wherein, The first isolation structure includes a first deep trench structure and a first p-well structure, and the first p-well structure partially encloses the first deep trench structure; And The second isolation structure includes a second deep trench structure and a second p-well structure, and the second p-well structure partially encloses the second deep trench structure.

18. The device according to claim 17, further comprising a first shallow trench structure adjacent to the first p-well structure and a second shallow trench structure adjacent to the second p-well structure.

19. A front-illuminated (FSI) single-photon avalanche diode (SPAD) sensor device, comprising: A silicon material having a front side and a back side; A first isolation structure positioned within the silicon material; A second isolation structure positioned within the silicon material; An orifice positioned on the front side and constructed between the first isolation structure and the second isolation structure; An n-type material having a cubic structure with a first top region and a first bottom region, the first top region abutting the back side, the first bottom region including a first sidewall and a second sidewall, the n-type material being characterized by a first width; an n-well structure is constructed around the first bottom region of the n-type material; a guard ring structure is constructed around the n-well structure, and the guard ring structure is located between the first deep trench structure and the second deep trench structure; An n-type contact directly coupled to the n-type material and positioned within the first top region; A p-type material having a concave three-dimensional structure inverted over the first top region of the cubic structure, the concave three-dimensional structure having a flat second top region and a second bottom region with a notch, the second top region enclosing the first bottom region, the second bottom region of the p-type material being higher than the top of the n-well structure, the p-type material being characterized by a second width greater than the first width; And A junction region constructed at the interface between the first top region and the second bottom region.

20. The device according to claim 19, wherein, The first isolation structure includes a p-well region.

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