Chip, board, method and computing device for single target detection

Abstract

The present disclosure discloses a chip, a board card, a method and a computing device for single target detection. The computing device can be included in a combined processing device, which can further include an interface device and other processing devices. The computing device interacts with the other processing devices to jointly complete a user-specified computing operation. The combined processing device can further include a storage device connected to the computing device and the other processing devices, respectively, for storing data of the computing device and the other processing devices. The scheme of the present disclosure provides a hardware architecture for executing target detection instructions, which can simplify processing and improve the processing efficiency of the machine.

Description

Technical Field

[0001] This disclosure generally relates to the field of processors. More specifically, this disclosure relates to chips, boards, methods, and computing devices for single-target detection. Background Technology

[0002] In computer vision, object detection refers to scanning and searching for objects in point clouds, images, and videos (i.e., a series of images). Simply put, object detection is the localization and identification of objects within a scene. A typical example of object detection is detecting vehicles or other traffic participants in images or point clouds in intelligent transportation or autonomous driving systems.

[0003] Target tracking refers to tracking the movement of a target in animated images or videos, or in a series of point cloud data, or locking onto one or more specific moving targets in real time. In one approach, target tracking can be viewed as a series of target detections. For example, in traffic videos, to detect the trajectory of a car, target detection can be performed on each frame of the video, and then its positional changes can be observed, thereby achieving target tracking.

[0004] On the other hand, with the rapid development of deep learning, hardware architectures such as chips and processors suitable for deep learning processing have also made leaps and bounds. If object detection operations can be ported to hardware architectures suitable for deep learning processing, it is possible to accelerate object detection processing and improve the efficiency of processing tasks such as image processing and object tracking. Existing hardware and / or instruction sets cannot effectively support object detection-related operations. Summary of the Invention

[0005] In order to at least partially solve one or more of the technical problems mentioned in the background art, the present disclosure provides a computing device, a data processing method, a chip, and a board.

[0006] In a first aspect, this disclosure discloses a computing device including a control circuit and an arithmetic circuit, wherein: the control circuit is configured to parse a target detection instruction, the target detection instruction operating on data to be detected and target data, the target detection instruction indicating the detection of the positional distribution of a single target represented by the target data in the data to be detected as output data; and the arithmetic circuit includes a plurality of slave processing circuits, and the arithmetic circuit is configured to schedule a corresponding number of slave processing circuits to perform a target detection task according to the target detection instruction, wherein each scheduled slave processing circuit performs the target detection task for a portion of the data to be detected and the target data.

[0007] In a second aspect, this disclosure provides a chip that includes a computing device according to any of the embodiments of the first aspect.

[0008] In a third aspect, this disclosure provides a board including the chip of any of the embodiments of the second aspect above.

[0009] In a fourth aspect, this disclosure provides a method for a target detection task performed by a computing device according to any of the embodiments of the first aspect.

[0010] Using the computing device, data processing method, integrated circuit chip, and board provided above, this disclosure provides a scheme for executing object detection instructions on a hardware architecture including multiple slave processing circuits. The object detection task can be distributed across multiple slave processing circuits for execution, thereby fully utilizing the computational advantages of deep learning processing hardware architectures and improving machine processing efficiency through parallel computation. Attached Figure Description

[0011] The above and other objects, features, and advantages of exemplary embodiments of this disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0012] Figure 1 This diagram shows the structure of the board card according to an embodiment of this disclosure;

[0013] Figure 2 This diagram illustrates the structure of the combined processing apparatus according to an embodiment of the present disclosure.

[0014] Figure 3 A schematic diagram illustrating the internal structure of a processor core in a single-core or multi-core computing device according to embodiments of the present disclosure;

[0015] Figure 4 This diagram illustrates an exemplary structural schematic of a computing device according to an embodiment of the present disclosure.

[0016] Figure 5 A partial structural schematic diagram of the arithmetic circuit in a computing device according to an embodiment of this disclosure is shown;

[0017] Figure 6 A schematic diagram illustrating a target detection task in a first scenario according to an embodiment of this disclosure is shown;

[0018] Figure 7 A schematic diagram illustrating a target detection task in a second scenario according to an embodiment of this disclosure is shown;

[0019] Figure 8 A schematic diagram illustrating a target detection task in a third scenario according to an embodiment of this disclosure;

[0020] Figure 9 A partial structural schematic diagram of the slave processing circuit according to an embodiment of this disclosure is shown; and

[0021] Figure 10 An exemplary flowchart of a data processing method according to an embodiment of this disclosure is shown. Detailed Implementation

[0022] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0023] It should be understood that the terms "first," "second," "third," and "fourth," etc., that may appear in the claims, specification, and drawings of this disclosure are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "including" as used in the specification and claims of this disclosure indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0024] It should also be understood that the terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0025] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection."

[0026] The specific embodiments disclosed herein will now be described in detail with reference to the accompanying drawings.

[0027] Figure 1 A schematic diagram of the structure of a board 10 according to an embodiment of this disclosure is shown. Figure 1As shown, board 10 includes chip 101, which is a system-on-chip (SoC) integrating one or more combined processing units. These combined processing units are artificial intelligence computing units used to support various deep learning and machine learning algorithms, meeting the intelligent processing needs of complex scenarios in fields such as computer vision, speech, natural language processing, and data mining. In particular, deep learning technology is widely used in cloud intelligence. A significant characteristic of cloud intelligence applications is the large volume of input data, placing high demands on the platform's storage and computing capabilities. Board 10 in this embodiment is suitable for cloud intelligence applications, possessing massive off-chip storage, on-chip storage, and powerful computing capabilities.

[0028] Chip 101 is connected to external device 103 via external interface device 102. External device 103 may be, for example, a server, computer, camera, monitor, mouse, keyboard, network card, or Wi-Fi interface. Data to be processed can be transmitted from external device 103 to chip 101 via external interface device 102. The calculation results from chip 101 can be transmitted back to external device 103 via external interface device 102. Depending on the application scenario, external interface device 102 may have different interface forms, such as a PCIe interface.

[0029] The board 10 also includes a storage device 104 for storing data, which includes one or more memory cells 105. The storage device 104 is connected to and transmits data with the controller 106 and the chip 101 via a bus. The controller 106 in the board 10 is configured to regulate the state of the chip 101. Therefore, in one application scenario, the controller 106 may include a microcontroller (MCU).

[0030] Figure 2 This is a structural diagram illustrating the combined processing device in chip 101 of this embodiment. (As shown...) Figure 2 As shown, the combined processing device 20 includes a computing device 201, an interface device 202, a processing device 203, and a storage device 204.

[0031] The computing device 201 is configured to perform user-specified operations. It is mainly implemented as a single-core intelligent processor or a multi-core intelligent processor to perform deep learning or machine learning calculations. It can interact with the processing device 203 through the interface device 202 to jointly complete the user-specified operations.

[0032] Interface device 202 is used to transmit data and control commands between computing device 201 and processing device 203. For example, computing device 201 can obtain input data from processing device 203 via interface device 202 and write it to on-chip storage device of computing device 201. Further, computing device 201 can obtain control commands from processing device 203 via interface device 202 and write them to on-chip control cache of computing device 201. Alternatively or optionally, interface device 202 can also read data from storage device of computing device 201 and transmit it to processing device 203.

[0033] Processing device 203, as a general-purpose processing device, performs basic control including but not limited to data transfer, and starting and / or stopping computing device 201. Depending on the implementation, processing device 203 may be one or more types of processors, including but not limited to digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, computing device 201 disclosed herein can be considered as having a single-core structure or a homogeneous multi-core structure. However, when computing device 201 and processing device 203 are considered together, they are considered to form a heterogeneous multi-core structure.

[0034] Storage device 204 is used to store data to be processed. It may be DRAM or DDR memory, typically 16G or larger in size, and is used to store data of computing device 201 and / or processing device 203.

[0035] Figure 3 The diagram shows the internal structure of the processing core when the computing device 201 is a single-core or multi-core device. The computing device 301 is used to process input data such as computer vision, speech, natural language, and data mining. The computing device 301 includes three main modules: a control module 31, a processing module 32, and a storage module 33.

[0036] The control module 31 coordinates and controls the operation of the computation module 32 and the storage module 33 to complete the deep learning task. It includes an instruction fetch unit (IFU) 311 and an instruction decode unit (IDU) 312. The instruction fetch unit 311 fetches instructions from the processing device 203, and the instruction decode unit 312 decodes the fetched instructions and sends the decoding result as control information to the computation module 32 and the storage module 33.

[0037] The computation module 32 includes a vector operation unit 321 and a matrix operation unit 322. The vector operation unit 321 is used to perform vector operations and can support complex operations such as vector multiplication, addition, and nonlinear transformations; the matrix operation unit 322 is responsible for the core computations of deep learning algorithms, namely matrix multiplication and convolution.

[0038] The storage module 33 is used to store or move relevant data, including a neuron RAM (NRAM) 331, a weight RAM (WRAM) 332, and a direct memory access (DMA) module 333. The NRAM 331 stores the input neurons, output neurons, and intermediate results after computation; the WRAM 332 stores the convolution kernels of the deep learning network, i.e., the weights; the DMA 333 is connected to the DRAM 204 via bus 34 and is responsible for data transfer between the computing device 301 and the DRAM 204.

[0039] Based on the aforementioned hardware environment, in one aspect, this disclosure provides a computing device for executing a target detection task according to target detection instructions. A target detection task can generally be understood as detecting the location of target data within data to be detected. Taking vehicle detection as an example, the target detection task can be detecting the position of a target vehicle from multiple images. It is understood that there may be multiple target vehicles, meaning the target data can include multiple target objects, each representing a target vehicle. The target data can be various data characterizing target features, such as histogram data of a target vehicle image; correspondingly, the data to be detected can be histogram data of a traffic scene image. By using a sliding window approach, the target data is compared across the data to be detected, and the location of the target data within the data to be detected can be determined. Therefore, the target detection task can also be understood as detecting the similarity distribution of target data within the data to be detected, where the similarity value can be represented by the cumulative value of the alignment comparison between the target data and the data to be detected. It is understood that the target data and the data to be detected can be one-dimensional, two-dimensional, three-dimensional, or higher-dimensional data. For example, detecting a target vehicle in an image as mentioned above can be understood as a two-dimensional example, while detecting a target vehicle in point cloud data collected by radar can be understood as a three-dimensional example, and searching for a specific sequence in a character sequence can be understood as a one-dimensional example. This disclosed embodiment is not limited in this respect.

[0040] As can be seen, the sliding window method in object detection tasks is similar to the convolution operation in deep learning. Therefore, if we can make full use of the hardware environment suitable for deep learning and explore the possibility of parallel processing in object detection tasks, we can accelerate the operation and improve efficiency.

[0041] Figure 4 A schematic structural block diagram of a computing device 400 according to an embodiment of this disclosure is shown. It can be understood that this structure can be considered as... Figure 3 The refinement of the internal structure of a single processing core can also be viewed as the refinement of multiple cores. Figure 3 The diagram shows the functional partitioning based on the processing core. Figure 4 As shown, the computing device 400 of this embodiment can be used to perform target detection tasks. It may include a storage circuit 40, a control circuit 41 and a computing circuit 42, which are interconnected to transmit various data and instructions.

[0042] The function of control circuit 41 and Figure 3Similar to the control module 31, it may also include, for example, an instruction fetch unit (IFU) 411 and an instruction decode unit (IDU) 412. In various arithmetic operations, such as computation, the control circuit 41 can be configured to fetch computation instructions, parse them to obtain arithmetic instructions, and then send the arithmetic instructions to the arithmetic circuit 42 and the storage circuit 40. The computation instructions can be a form of hardware instruction and include one or more opcodes, each opcode representing one or more specific operations to be executed by the arithmetic circuit 42. These operations can include different types depending on the application scenario, such as arithmetic operations like addition or multiplication, logical operations, comparison operations, or table lookup operations, or any combination of the aforementioned operations. Correspondingly, the arithmetic instructions can be one or more microinstructions executed internally by the arithmetic circuit after parsing the computation instructions.

[0043] Furthermore, depending on the application scenario, the arithmetic instruction obtained after parsing the calculation instruction can be an arithmetic instruction decoded by the control circuit 41 or an arithmetic instruction not decoded by the control circuit 41. When the arithmetic instruction is an arithmetic instruction not decoded by the control circuit 41, the arithmetic circuit 42 may include a corresponding decoding circuit to perform the decoding of the arithmetic instruction, so as to obtain, for example, multiple microinstructions.

[0044] The arithmetic circuit 42 may include a main processing circuit 421 and multiple slave processing circuits 422. The main processing circuit and the slave processing circuits, as well as the multiple slave processing circuits, can communicate with each other through various connections.

[0045] The main processing circuit and the slave processing circuits can cooperate to achieve parallel computation. In this configuration, the main processing circuit can, for example, perform pre-processing on the input data, such as splitting the data, and receive intermediate results from multiple slave processing circuits and perform subsequent processing to obtain the final computation result of the computation instruction. The slave processing circuits can, for example, perform intermediate operations in parallel on the corresponding data (e.g., split data) according to the computation instruction to obtain multiple intermediate results, and transmit the multiple intermediate results back to the main processing circuit.

[0046] In different application scenarios, the connection between multiple slave processing circuits can be either a hard connection arranged by hardwires or a logical connection configured according to, for example, microinstructions, to form various topologies of slave processing circuit arrays. The embodiments disclosed herein are not limited in this respect.

[0047] By configuring the arithmetic circuit 42 into a master-slave structure (e.g., a master-multiple-slave structure, or a multi-master-multiple-slave structure, which is not limited in this disclosure), for the calculation instructions of forward operation, the data can be split according to the calculation instructions, so that the part with a large amount of calculation can be performed in parallel by multiple slave processing circuits to improve the calculation speed, save the calculation time, and thus reduce the power consumption.

[0048] To support computational functions, the main processing circuit and the slave processing circuit can include various computing circuits, such as vector operation units and matrix operation units. The vector operation unit is used to perform vector operations and can support complex operations such as vector multiplication, addition, and nonlinear transformations; the matrix operation unit is responsible for the core computations of deep learning algorithms, such as matrix multiplication and convolution.

[0049] Storage circuit 40 is used to store or move relevant data. In deep learning, storage circuitry can be used to store computational data such as neurons and weights, or to store computation results. Storage circuitry may include, for example, one or any combination of cache 402, register 404, and direct memory access (DMA) module 406. DMA module 406 can be used to interact with off-chip memory (not shown).

[0050] The foregoing describes an exemplary computing device according to embodiments of the present disclosure, in which the main processing circuit and the slave processing circuit may belong to different modules of the same processor or chip, or to different processors, and the present disclosure is not limited in this respect.

[0051] In one embodiment, the control circuit 41 may be configured to parse a target detection instruction, for example, using an instruction decoding unit 412. The target detection instruction operates on both the data to be detected and the target data. The target detection instruction instructs the positional distribution of a single target represented by the target data within the data to be detected as output data. Further, in this embodiment, the arithmetic circuit 42 may be configured to schedule a corresponding number of slave processing circuits 422 to perform target detection tasks according to the target detection instruction, wherein each scheduled slave processing circuit performs the aforementioned target detection task for a portion of the data to be detected and / or the target data.

[0052] In some embodiments, in order to make full use of the parallel computing resources of the computing device, the main processing circuit 421 in the arithmetic circuit 42 may be configured to determine the splitting scheme of the target detection task according to the target detection instructions and the processing capabilities of the slave processing circuits, in accordance with the splitting rules.

[0053] The amount of computation to be performed can be determined based on the target detection instructions. The target detection instructions may specify information such as the size of the data to be detected and the size of the target data. For example, the data to be detected can be one-dimensional, two-dimensional, or higher-dimensional data. In this disclosed embodiment, the target data may include only one target object, i.e., single-target detection. Similar to the data to be detected, the target object can be one-dimensional, two-dimensional, or higher-dimensional data.

[0054] The processing capacity of a slave processing circuit represents the available computing resources, which may include, for example, the number of available slave processing circuits, the amount of data that each slave processing circuit can process at one time, and so on.

[0055] Therefore, based on the amount of computation to be completed and the amount of available computing resources, the main processing circuit can determine the splitting scheme of the target detection task according to the splitting rules.

[0056] Specifically, the splitting scheme may include one or more of the following: the transmission method of the data to be detected and the target data, the splitting method of the data to be detected and the target data, and the number of times the data to be detected is reused (R). N The number of times the target data is reused, R S ,etc.

[0057] Figure 5 A partial structural schematic diagram of the computing circuitry in a computing device according to an embodiment of this disclosure is shown in order to describe various splitting schemes by illustrating the allocation, transmission, and processing of various data in the computing circuitry.

[0058] As shown in the figure, the operational circuit 500 (for example) Figure 4 In addition to the main processing circuit 510 and multiple slave processing circuits 520 described above, the arithmetic circuit 42) may also include a first storage circuit 530 and a second storage circuit 540.

[0059] The first storage circuit 530 can be used to store multicast data, meaning the data in the first storage circuit will be transmitted to multiple slave processing circuits via a broadcast bus, and these slave processing circuits will receive the same data. It is understood that broadcasting and multicasting can be implemented via a broadcast bus. Multicast refers to a communication method that transmits a single data set to multiple slave processing circuits; while broadcasting is a communication method that transmits a single data set to all slave processing circuits, and is a special case of multicast. Since both multicast and broadcasting correspond to one-to-many transmission methods, they are not specifically distinguished in this document; broadcasting and multicast can be collectively referred to as multicast, and those skilled in the art will understand their meaning from the context. The second storage circuit 540 can be used to store distributed data, meaning the data in the second storage circuit will be transmitted to different slave processing circuits respectively, and each slave processing circuit will receive different data. By providing the first storage circuit and the second storage circuit respectively, it is possible to support the transmission of data to be processed using different transmission methods, thereby reducing data throughput by multiplexing multicast data among multiple slave processing circuits.

[0060] In some embodiments, the main processing circuit 510 may be further configured to: determine one of the data to be detected and the target data as multicast data, and determine the other of the data to be detected and the target data as distribution data; store the multicast data in a first storage circuit 530 for transmission to a plurality of scheduled slave processing circuits 520 via a broadcast bus during operation; and store the split distribution data in a second storage circuit 540 for the scheduled slave processing circuits 520 to load the corresponding portion of the distribution data for operation.

[0061] Those skilled in the art will understand that, although Figure 5 The various processing and storage circuits are shown as separate modules, but depending on the configuration, the storage and processing circuits can also be combined into a single module. For example, the first storage circuit 530 can be combined with the main processing circuit 510, while the second storage circuit 540 can be shared by multiple slave processing circuits 520, with each slave processing circuit allocated an independent storage area to accelerate access. This disclosure embodiment is not limited in this respect.

[0062] This disclosure provides a detection scheme for a single target. Therefore, in some embodiments, the target data can be determined as multicast data, while the data to be detected can be determined as distributed data. Thus, the target data can be broadcast to all scheduled slave processing circuits, and multiple slave processing circuits can perform detection tasks for the same target in different distributed data to be detected.

[0063] As mentioned earlier, in object detection tasks, a sliding window approach is used to compare target data against the data to be detected. The accumulated value of the alignment comparison between the target data and the data to be detected represents the similarity between them, thereby determining the location of the target data within the data to be detected. For ease of description, the "similarity value" mentioned in this disclosure embodiment refers to each output value on the similarity distribution, which is the value obtained by accumulating the alignment comparison of the target data against the data to be detected each time. Each similarity value has a corresponding scanning window, the shape of which is equal to the shape of the target object. When alignment comparison accumulation is performed on a portion of the data within the scanning window, the resulting value is called "partial similarity".

[0064] When the data size being processed is large, for example, when the bit comparison and accumulation operation within a single scanning window cannot be completed in one operation, the processing circuit can be further used to: control the reading method of the data to be detected and / or the target data according to the reuse method of the data to be detected and / or the target data, so that the data to be detected and the target data can be simultaneously traversed throughout the entire scanning window to perform bit comparison and accumulation operations, obtain multiple partial similarities, and accumulate them to obtain the similarity value on the corresponding scanning window.

[0065] The following describes the task splitting schemes for object detection based on various possible scenarios.

[0066] Figure 6 A schematic diagram of an object detection task in a first scenario according to an embodiment of this disclosure is shown. For simplicity, the diagram uses object detection in a two-dimensional image as an example for description.

[0067] In the first scenario, the positional distribution of target data 620 needs to be detected within a single piece of data to be detected 610, where target data 620 includes only one target object. For example, detecting the positional distribution of the target object within a single frame image. In this scenario, target detection can be performed on different blocks of data to be detected on each of the multiple scheduled slave processing circuits 630 to obtain similarity values ​​at corresponding locations. For example, each slave processing circuit 630 can calculate similarity values ​​corresponding to different scanning windows in the data to be detected. The figure shows multiple scanning windows, with the data blocks corresponding to each scanning window being distributed to different slave processing circuits 630 to perform target detection operations with the same target data.

[0068] In these embodiments, the data blocks to be detected corresponding to different scanning windows in the data to be detected 610 can be distributed to multiple slave processing circuits, wherein the number of different scanning windows is equal to the number of times the target data is reused R. BThis is also equal to the number of slave processing circuits scheduled. At this point, each slave processing circuit performs bitwise comparison and accumulation operations on the distributed data block to be detected, using the same target data, to obtain the similarity value corresponding to one scanning window, totaling R. B The similarity value of each scanned window.

[0069] In some embodiments, the allocation of scanning windows may follow at least one of the following rules: satisfying the number of times R of multicast data (here, the target data) is reused. B The maximum value is reached; the multicast data is preferentially split into rounds of multiplexing based on the first dimension of the output data; when the size of the first dimension of the output data is less than a predetermined threshold, the second dimension of the output data is combined for rounds of multiplexing; and the number of times the multicast data is reused in each round of operation is greater than the minimum number of reuses M and does not exceed the maximum number of reuses N.

[0070] In one implementation, to fully utilize the transmission advantages of the broadcast bus and reduce data memory access, the multiplexing frequency R of multicast data is prioritized when determining the splitting scheme. B Reaching the maximum value, selectively satisfying the number of times R of distributed data is reused. D Since this disclosed embodiment performs single-target detection, the target data is used as multicast data, the data to be detected is used as distribution data, and there is no need to reuse the data to be detected; only the number of times the target data is reused, R, needs to be increased. B It has reached its maximum value.

[0071] Optionally or additionally, in one implementation, multicast data is preferentially split into round-multiplexed segments based on a first dimension of the output data (e.g., the lowest storage dimension, such as the width Wo dimension in the output two-dimensional image). In the object detection processing of this disclosure embodiment, the output data is the similarity values ​​of each scanning window, so the dimensionality of the output data can be determined based on the input data and the scanning step size. For example, when the number of scanning windows N in the W dimension... scan When the number of schedulable slave processing circuits Ns is greater than or equal to the number of slave processing circuits that can be scheduled, each row can be split into Ns units, and the similarity value of Ns scanning windows is counted in each round. Each slave processing circuit corresponds to one scanning window.

[0072] In some cases, N scan After splitting the data into units of Ns, the number of remaining blocks might be much smaller than Ns. If this method is still used, the hardware efficiency might be low in the final round of computation due to a large proportion of unused hardware. Therefore, optionally or additionally, in an implementation, the number of multicast data reuses in each round can be controlled to be greater than the minimum number of multicast data reuses M, but not exceeding the maximum number of multicast data reuses N. In the example above, N = Ns. M can be chosen empirically, for example, M = 4.

[0073] The rules above can be combined and expressed as the following logic:

[0074] Mode 0: If Wo ≥ N, then proceed to S0_1;

[0075] S0_1: Search along the Wo dimension in units of 2N, and split it in units of N. If Wo is greater than 2N, proceed to S0_2; if N+M < Wo ≤ 2N, proceed to S0_3; if N < Wo ≤ N+M, proceed to S0_4; otherwise, proceed to S0_5.

[0076] S0_2: Every N reuses, Wo = Wo - N, then enter S0_1;

[0077] S0_3: Reuse in two rounds, with each round reusing N times and Wo-N times respectively;

[0078] S0_4: Multiplexing is performed in two rounds, with each round reusing Wo-M times and M times respectively;

[0079] S0_5: Directly reuse Wo times.

[0080] Mode 1: If Wo < N, then proceed to S1_1;

[0081] S1_1: Search in the Ho dimension in units of 2[N / Wo], and split in units of [N / Wo]. If Ho > 2[N / Wo], proceed to S1_2; if [N / Wo] < H ≤ 2[N / Wo], proceed to S1_3; if Ho ≤ [N / Wo], proceed to S1_4.

[0082] S1_2: Every time [N / Wo]×Wo is reused, Ho = Ho - [N / Wo], then proceed to S1_1;

[0083] S1_3: Multiplexing is performed in two rounds, namely [N / Wo]×Wo times and (Ho-[N / Wo])×Wo times;

[0084] S1_4: Directly reuse Ho×Wo times.

[0085] In one example, if the data to be detected is a large 2D image of size W×H = 1024×800, and the target data is a small 2D image of size Tw×Th = 32×20, with a scanning step size of 1 in both the W and H directions, then the output data after target detection will be a 2D image of size Wo×Ho = 993×781. Assuming N = 64 and M = 4, according to mode 0, each row of output data will be split into 17 rounds of computation. In the first 16 rounds, the target data will be reused 64 times, and in the last round, the target data will be reused 33 times.

[0086] In another example, if the data to be detected is a large 2D image of size W×H = 1024×800, and the target data is a small 2D image of size Tw×Th = 32×20, with scanning strides of 32 and 20 in the W and H directions respectively, then the output data after target detection will be a 2D image of size Wo×Ho = 32×40. Assuming N = 64 and M = 4, according to mode 1, the entire output data will be split into 20 rounds of computation. In each round, the target data will be reused 64 times, and two lines of output data will be calculated in each round.

[0087] Furthermore, as mentioned earlier, when the data size being processed is large, for example, when a single processing circuit cannot complete the bit comparison and accumulation operation within a single scanning window in one operation, the reading method of the data to be detected and the target data can be controlled so that the data to be detected and the target data can be simultaneously traversed through the entire scanning window to perform bit comparison and accumulation operations through multiple operations, so as to obtain multiple partial similarities and accumulate them to obtain the similarity value on the corresponding scanning window.

[0088] Specifically, in some embodiments, the data to be detected and the target data within a single scan window can be split according to alignment requirements. Here, "alignment requirements" refers to the data size requirements imposed during computation, for example, to make full use of the hardware, such as filling the arithmetic unit. In one example, the alignment requirement is, for example, 64 bytes, so the data to be detected and the target data within a single scan window can both be split into 64-byte rows, so that each computation can fully utilize the scheduled slave processing circuitry.

[0089] In these embodiments, each processing circuit can perform bitwise comparison and accumulation operations on the distributed data line to be detected, using the corresponding target data line, to obtain partial similarity values ​​belonging to different scanning windows; and accumulate the partial similarity values ​​belonging to the same scanning window obtained in multiple operations to obtain the similarity value of the corresponding scanning window.

[0090] Taking a large 2D image (W×H = 1024×800) as the data to be detected and a small 2D image (Tw×Th = 32×20) as the target data as an example, assuming that the number of schedulable slave processing circuits in each round of computation is 64, and the alignment requirement is 64 data points (data bit width is not considered here), in one round of computation, the 64 slave processing circuits can calculate the similarity values ​​in 64 scanning windows. In this round of computation, the computation of each slave processing circuit for one scanning window can be further divided into multiple computations. Each computation processes and accumulates the alignment comparisons of one row of data to be detected and one row of target data, with each row containing 64 data points. Therefore, 10 computations are needed to obtain 10 partial similarity values. The sum of these 10 partial similarity values ​​can obtain the final similarity value for the corresponding scanning window.

[0091] The splitting rules for the data to be detected and the target data within a single scanning window can be similar to the previous allocation rules for the scanning window. Specifically, the data to be detected and the target data can be split according to the first dimension of the scanning window (e.g., width Sw). When the size of the first dimension of the scanning window is less than a predetermined threshold, the second dimension of the scanning window (e.g., height Sh) is also used for splitting. Furthermore, the size of the data rows obtained from the splitting in each operation is greater than the minimum computational cost Mc and does not exceed the maximum computational cost Nc.

[0092] The rules above can be combined and expressed as the following logic:

[0093] Mode 2: If Sw ≥ Nc, then proceed to S2_1;

[0094] S2_1: Search along the Sw dimension in units of 2Nc, and split in units of Nc. If Sw is greater than 2Nc, proceed to S2_2; if Nc+Mc<Sw≤2Nc, proceed to S2_3; if Nc<Sw≤Nc+Mc, proceed to S2_4; otherwise, proceed to S2_5.

[0095] S2_2: For each split Nc, Sw = Sw - N, then proceed to S2_1;

[0096] S2_3: The operation is performed in two steps, with each operation involving Nc and Sw-Nc respectively;

[0097] S2_4: Reuse in two steps, with each step involving Sw-Mc and Mc respectively;

[0098] S2_5: The direct computational complexity is Sw.

[0099] Mode 3: If Sw < Nc, then proceed to S3_1;

[0100] S3_1: Search along the Sh dimension in units of 2[Nc / Sw], and split in units of [Nc / Sw]. If Sh > 2[Nc / Sw], proceed to S3_2; if [Nc / Sw] < Sh ≤ 2[Nc / Sw], proceed to S3_3; if Sh ≤ [Nc / Sw], proceed to S3_4.

[0101] S3_2: For each split [Nc / Sw]×Sw, Sh=Sh-[Nc / Sw], proceed to S3_1;

[0102] S3_3: The operation is performed in two steps, namely [Nc / Sw]×Sw and (Sh-[Nc / Sw])×Sw;

[0103] S3_4: The direct computational complexity is Sh×Sw.

[0104] In one example, suppose the data to be detected is a large two-dimensional image of W×H = 1024×800, and the target data is a small two-dimensional image of Tw×Th = 64×20. The scanning step size is 1 in both the W and H directions, N = 64, M = 4, Nc = 64, and Mc = 4. According to Mode 2, for each 64×20 scanning window, the corresponding block of data to be detected and the target data are each split into 20 data rows. Each data row corresponds to 64 data points in the W dimension of the data to be detected and 64 data points in the Tw dimension of the target data, respectively.

[0105] Specifically, in the example above, the detection of a complete scan window can be achieved in 20 operations within the first round of 64 scan windows. In the first operation, 64 data points are taken from the W dimension of the data to be detected as a detection data row. Moving one step according to the scan step size, another 64 data points are taken, and so on, until 64 sets of 64 data points are taken, i.e., 64 detection data rows belonging to different scan windows are obtained. These 64 detection data rows are distributed to the 64 scheduled slave processing circuits. For the target data, only 64 data points (i.e., one target data row) are taken from the Tw direction of the target data and broadcast to the 64 scheduled slave processing circuits. Then, each slave processing circuit performs a bitwise comparison and accumulation operation on the received data to obtain a partial similarity value.

[0106] Next, in the second operation, the data is shifted down one row, and 64 rows of detection data are taken from the W dimension of the data to be detected and distributed to the 64 slave processing circuits. Then, after shifting down one row, 64 rows of data are taken from the Tw dimension of the target data and broadcast to these 64 slave processing circuits. Each slave processing circuit then performs a bitwise comparison and accumulation operation on the received data to obtain another partial similarity value, and accumulates this value with the previous partial similarity value.

[0107] This process is repeated until the 20th calculation. In this step, the row of data to be detected and the row of data to be detected, corresponding to the last row of the scanning window, are compared and accumulated to obtain the last partial similarity value. This value is then added to the previous partial similarity values ​​to obtain the final similarity value for the corresponding scanning window. Thus, in the first round of calculations, similarity values ​​for 64 scanning windows can be obtained through 20 calculations. In the next round of calculations, the similarity values ​​for the subsequent 64 scanning windows are calculated, and this process continues until the similarity values ​​for all scanning windows have been calculated, completing the object detection task.

[0108] For the case where Sw < Nc, a similar splitting method can be used as described in the previous rules, which will not be elaborated here.

[0109] Figure 7 A schematic diagram of an object detection task in a second scene according to an embodiment of this disclosure is shown. For simplicity, object detection in a two-dimensional image is also used as an example for description.

[0110] In the second scenario, the positional distribution of target data 720 needs to be detected among multiple data sets 710 to be detected. Similarly, the target data 720 includes only one target object. For example, detecting the positional distribution of the target object in multiple frames of images (video streams) to track the target. In this scenario, the data to be detected can be split into multiple detection data packets according to data batches. These detection data packets are grouped according to the order of computation rounds, with the number of detection data packets in each group corresponding to the total computational capacity of the slave processing circuits scheduled in the corresponding round. Specifically, target detection can be performed on different detection data packets on each of the multiple scheduled slave processing circuits 730 to obtain similarity values ​​on the corresponding detection data packets. For example, each slave processing circuit 730 can calculate different batches of data to be detected. The figure shows multiple detection image frames (i.e., detection data packets) corresponding to multiple batches, with each detection image frame distributed to a different slave processing circuit 730 to detect the positional distribution of the target object from them.

[0111] For example, assuming the data to be detected includes 128 frames of images, these 128 frames can be divided into 128 detection data packets, with each detection data packet corresponding to one frame of image. Assuming that 64 slave processing circuits can be scheduled in each round of computation, these 128 detection data packets can be divided into two groups. In the first round of computation, the first 64 detection data packets (the first 64 frames of images) are detected, with each slave processing circuit detecting one of the detection data packets. In the second round of computation, the last 64 detection data packets (the last 64 frames of images) are detected, with each slave processing circuit detecting one of the detection data packets.

[0112] When performing a target detection task for a single detection data packet in each slave processing circuit, the operation can be split in a similar manner to that described for the first scenario. The difference is that in the first scenario, the operation is split into multiple slave processing circuits, while here the operation task on the same slave processing circuit is split into multiple rounds of operation in time.

[0113] Specifically, on each slave processing circuit, when performing target detection on a single detection data packet, the similarity value corresponding to different scanning windows in the detection data packet can be calculated one by one. The figure shows multiple scanning windows 711. The data block to be detected corresponding to each scanning window is sent to the corresponding slave processing circuit 730 in chronological order to perform target detection operation with the target data 720, and obtain the similarity value 741 of the corresponding scanning window.

[0114] Furthermore, when a single processing circuit cannot complete the alignment comparison and accumulation operation within a single scanning window in one operation, the reading method of the data to be detected and the target data can be controlled. By performing multiple operations, the data to be detected and the target data are simultaneously traversed throughout the entire scanning window to perform alignment comparison and accumulation operations, obtaining multiple partial similarities and accumulating them to obtain the similarity value on the corresponding scanning window. The traversal method can be similar to that described above for the first scenario, and will not be detailed here.

[0115] Figure 8 A schematic diagram of an object detection task in a third scenario according to an embodiment of this disclosure is shown. For simplicity, object detection in a two-dimensional image is also used as an example for description.

[0116] In the third scenario, similar to the second scenario, it is also necessary to detect the positional distribution of target data 820 within multiple data sets 810 to be detected, and each target data set 820 also contains only one target object. For example, detecting the positional distribution of the target object across multiple frames of images (video streams) to track the target. In this scenario, the data to be detected can be split into multiple detection data packets according to data batches. The difference is that the number of detection data packets is smaller, for example, only half the number of processing circuits. In this case, the target detection task can be split into detecting the same detection data packet on multiple (e.g., Ng, where Ng can be 2, 4, etc.) processing circuits.

[0117] In some embodiments, the schedulable slave processing circuits can be grouped according to the number of detection data packets, with each group comprising Ng slave processing circuits that perform detection on the same detection data packet. For example, assuming the data to be detected includes 16 frames of images, i.e., 16 detection data packets, and the number of schedulable slave processing circuits is 64, the slave processing circuits can be divided into 16 groups, with 4 slave processing circuits in each group, each performing detection on the same frame of image.

[0118] When performing target detection on the same detection data packet (e.g., the same frame of image) in each group of slave processing circuits, round-by-round computation can be performed, referring to the splitting method described above for the first scenario. The difference is that in the first scenario, the computation is split across all schedulable slave processing circuits (e.g., 64 slave processing circuits), while in the third scenario, the computation is split across slave processing circuits within the slave processing circuit group (e.g., 4 slave processing circuits).

[0119] Specifically, within each slave processing circuit group, when performing target detection on a single detection data packet, target detection can be performed on different data blocks to be detected on each of the multiple slave processing circuits 830 within the group to obtain similarity values ​​at corresponding positions. For example, each slave processing circuit 830 within the group can calculate similarity values ​​corresponding to different scanning windows in the data to be detected. The figure shows multiple scanning windows 811, and the data blocks to be detected corresponding to each scanning window are distributed to different slave processing circuits 830 within the group to perform target detection operations with the same target data 820, obtaining similarity values ​​841 for the corresponding scanning windows.

[0120] Furthermore, when a single processing circuit cannot complete the alignment comparison and accumulation operation within a single scanning window in one operation, the reading method of the data to be detected and the target data can be controlled. By performing multiple operations, the data to be detected and the target data are simultaneously traversed throughout the entire scanning window to perform alignment comparison and accumulation operations, obtaining multiple partial similarities and accumulating them to obtain the similarity value on the corresponding scanning window. The traversal method can be similar to that described above for the first scenario, and will not be detailed here.

[0121] As can be seen from the above description, the first scenario can also be seen as a special case of the third scenario corresponding to Ng = the total number of scheduled slave processing circuits, for example, 64.

[0122] Figure 9 A partial structural schematic diagram of a slave processing circuit according to an embodiment of this disclosure is shown. In this embodiment, based on the requirements of the target detection computation task, each slave processing circuit 900 may include a comparison circuit 910 and an accumulation circuit 920.

[0123] In each operation, the comparison circuit 910 can be used to perform a bitwise comparison between the detection data row allocated to the current slave processing circuit and the corresponding target data row and output the comparison result.

[0124] In some implementations, the comparison circuit 910 may include multiple comparators 911, each comparator comparing a data to be detected in a detection data row assigned to the current processing circuit with a target data in a corresponding target data row, and outputting a comparison result indicating whether the two are the same. For example, when a data to be detected in a detection data row is the same as the corresponding target data in the target data row, it can output "1", otherwise it can output "0".

[0125] In each operation, the accumulator circuit 920 can be used to accumulate the comparison results from the comparison circuit to obtain a partial similarity value, and to accumulate the partial similarity value of the current round with the partial similarity value of the previous round. The comparison results indicate the similarity between the data to be detected and the target data; therefore, accumulating the comparison results allows for the statistical calculation of the similarity within the scanning window. When the data within the scanning window is split into multiple rows of detection data, it is necessary to accumulate the partial statistical values ​​for each row of detection data to obtain the similarity value for the entire scanning window.

[0126] In some implementations, the accumulation circuit 920 may include an adder circuit 921 and a register 922. The adder circuit 921 performs an addition operation on the comparison results of multiple comparators to obtain a partial similarity value for the current round. Further, the adder circuit 921 may also perform an addition operation on the partial similarity value of the current round and the partial similarity value of the previous round to update the partial similarity value. The adder circuit 921 may, for example, include a multi-level Wallace tree compressor group arranged in a multi-level tree structure; or the adder circuit 921 may include a multi-level adder group arranged in a multi-level tree structure, and the embodiments disclosed herein are not limited in this respect.

[0127] Register 922 can be used in conjunction with adder circuit 921 to store updated partial similarity values; that is, the register stores the latest accumulated result of partial similarity.

[0128] In some embodiments, such as in scenarios where each Ng slave processing circuit performs target detection on a single detection data set (e.g., the first and third scenarios), the main processing circuit can concatenate the similarity values ​​from the corresponding slave processing circuits based on the distribution of the detection data packets across the slave processing circuits to obtain the final target detection result. For example, the main processing circuit can concatenate the results from each Ng slave processing circuits to generate the target detection result for the corresponding detection data packet.

[0129] This disclosure also provides a method for performing data processing using the aforementioned computing device. Figure 10 An exemplary flowchart of a data processing method 1000 according to an embodiment of this disclosure is shown.

[0130] like Figure 10 As shown, in step 1010, the target detection instruction is parsed. The target detection instruction operates on both the data to be detected and the target data, and the target detection instruction instructs the positional distribution of a single target represented by the target data within the data to be detected as output data. This step can be, for example, performed by... Figure 4 The control circuit 41 is used to execute this.

[0131] Next, in step 1020, according to the target detection instruction, a corresponding number of slave processing circuits are scheduled to perform target detection tasks, wherein each scheduled slave processing circuit performs a target detection task for a portion of the data to be detected and / or the target data. This step can, for example, be performed by... Figure 4 The operation circuit 42 is used to execute it.

[0132] In some embodiments, the processing circuit includes a main processing circuit, multiple slave processing circuits, a first storage circuit, and a second storage circuit. Therefore, step 1020 may further include sub-step 1021, whereby the main processing circuit determines the target data as multicast data and the data to be detected as distribution data. The main processing circuit can determine a splitting scheme for the target detection task according to the target detection instructions and the processing capabilities of the slave processing circuits, following splitting rules. The splitting scheme includes one or more of the following: the transmission method of the data to be detected and the target data (e.g., broadcast, multicast, distribution, etc.), the splitting method of the data to be detected and the target data, the number of times the data to be detected is reused, and the number of times the target data is reused.

[0133] Step 1020 may further include sub-step 1022, in which the main processing circuit stores multicast data in a first storage circuit for transmission to multiple scheduled slave processing circuits via a broadcast bus during operation; and sub-step 1023, in which the main processing circuit stores the split distribution data in a second storage circuit for the scheduled slave processing circuits to load the corresponding portion of the distribution data for operation.

[0134] Step 1020 may further include sub-step 1024, in which the processing circuit performs a target detection operation on the transmitted data to be detected and target data and returns the result. Specifically, the target detection operation may include bitwise comparison and accumulation operations, as described above.

[0135] Step 1020 may further include sub-step 1025, which involves accumulating the partial similarity values ​​obtained from the processing circuits according to the splitting situation, and concatenating the similarity values ​​of the scanning windows obtained from each processing circuit. This step can be performed collaboratively by the processing circuits and the main processing circuit. For example, each processing circuit can accumulate the partial similarity values ​​belonging to the same scanning window obtained from multiple calculations to obtain the total similarity value for the entire scanning window. The main processing circuit can concatenate the similarity values ​​of the scanning windows obtained from the corresponding processing circuits according to the distribution of the detection data packets on the processing circuits to obtain the target detection result for the corresponding detection data packets.

[0136] Those skilled in the art will understand that the steps described in the method flowchart correspond to the various circuits of the computing device described above in conjunction with the accompanying drawings. Therefore, the features described above also apply to the method steps and will not be repeated here.

[0137] This disclosure also provides a chip that may include the computing device of any of the embodiments described above in conjunction with the accompanying drawings. Furthermore, this disclosure also provides a board that may include the aforementioned chip.

[0138] Depending on the application scenario, the electronic devices or apparatus disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablets, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, dashcams, navigators, sensors, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, autonomous driving terminals, vehicles, home appliances, and / or medical devices. The vehicles include airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound machines, and / or electrocardiographs. The electronic devices or apparatus disclosed herein can also be applied in fields such as the Internet, IoT, data centers, energy, transportation, public management, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and healthcare. Furthermore, the electronic devices or apparatus disclosed herein can also be used in application scenarios related to artificial intelligence, big data, and / or cloud computing, such as cloud computing, edge computing, and terminal applications. In one or more embodiments, the high-computing-power electronic devices or apparatuses according to the present disclosure can be applied to cloud devices (e.g., cloud servers), while the low-power electronic devices or apparatuses can be applied to terminal devices and / or edge devices (e.g., smartphones or cameras). In one or more embodiments, the hardware information of the cloud devices and the hardware information of the terminal devices and / or edge devices are compatible with each other, so that suitable hardware resources can be matched from the hardware resources of the cloud devices to simulate the hardware resources of the terminal devices and / or edge devices based on the hardware information of the terminal devices and / or edge devices, so as to complete the unified management, scheduling and collaborative work of end-to-cloud or cloud-edge-end integration.

[0139] It should be noted that, for the sake of brevity, this disclosure describes some methods and their embodiments as a series of actions and combinations thereof. However, those skilled in the art will understand that the solutions disclosed herein are not limited by the order of the described actions. Therefore, based on the disclosure or teachings of this document, those skilled in the art will understand that some steps can be performed in a different order or simultaneously. Furthermore, those skilled in the art will understand that the embodiments described in this disclosure can be considered optional embodiments, that is, the actions or modules involved are not necessarily essential for the implementation of one or more solutions disclosed herein. In addition, depending on the solution, the description of some embodiments in this disclosure may have different emphases. In view of this, those skilled in the art will understand that parts not described in detail in a certain embodiment of this disclosure can also be referred to the relevant descriptions of other embodiments.

[0140] In terms of specific implementation, based on the disclosure and teachings of this document, those skilled in the art will understand that several embodiments disclosed herein can also be implemented in other ways not disclosed herein. For example, regarding the various units in the electronic device or apparatus embodiments described above, this document has divided them based on logical functions, but in actual implementation, there may be other ways of division. As another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. Regarding the connection relationships between different units or components, the connections discussed above in conjunction with the accompanying drawings can be direct or indirect couplings between units or components. In some scenarios, the aforementioned direct or indirect couplings involve communication connections utilizing interfaces, where the communication interface can support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

[0141] In this disclosure, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network units. Furthermore, depending on actual needs, some or all of the units can be selected to achieve the purpose of the solution described in the embodiments of this disclosure. Additionally, in some scenarios, multiple units in the embodiments of this disclosure may be integrated into one unit or each unit may exist physically independently.

[0142] In other implementation scenarios, the integrated units described above can also be implemented in hardware, i.e., as specific hardware circuits, which may include digital circuits and / or analog circuits. The physical implementation of the circuit's hardware structure may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors. Therefore, the various devices described herein (e.g., computing devices or other processing devices) can be implemented using appropriate hardware processors, such as central processing units, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage units or storage devices can be any suitable storage medium (including magnetic storage media or magneto-optical storage media), such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), ROM, and RAM.

[0143] The foregoing can be better understood in accordance with the following terms:

[0144] Clause 1. A computing device, comprising a control circuit and an arithmetic circuit, wherein:

[0145] The control circuit is used to parse target detection instructions. The target detection instructions operate on both data to be detected and target data. The target detection instructions instruct the detection of the positional distribution of a single target represented by the target data within the data to be detected as output data.

[0146] The computing circuit includes multiple slave processing circuits, and the computing circuit is used to schedule a corresponding number of slave processing circuits to perform target detection tasks according to the target detection instruction, wherein each scheduled slave processing circuit performs the target detection task for a portion of the data to be detected and / or the target data.

[0147] Clause 2. The computing device according to Clause 1, wherein the arithmetic circuitry further comprises a main processing circuitry, the main processing circuitry being used for:

[0148] Based on the target detection command and the processing capability of the processing circuit, the splitting scheme of the target detection task is determined according to the splitting rules.

[0149] The splitting scheme includes one or more of the following: the transmission method of the data to be detected and the target data, the splitting method of the data to be detected and the target data, the number of times the data to be detected is reused, and the number of times the target data is reused.

[0150] Clause 3. The computing device according to Clause 2, wherein the arithmetic circuitry further includes a first storage circuit and a second storage circuit, and the main processing circuitry is further configured to:

[0151] The target data is identified as multicast data, and the data to be detected is identified as distribution data;

[0152] The multicast data is stored in the first storage circuit for transmission to the scheduled slave processing circuits via a broadcast bus during operation; and

[0153] The split distribution data is stored in the second storage circuit so that the scheduled slave processing circuit can load the corresponding part of the distribution data for processing.

[0154] Clause 4. The computing device pursuant to Clause 3, wherein the splitting rule includes at least one of the following:

[0155] The data to be detected is split into multiple detection data packets according to data batches and grouped according to the order of the operation rounds. The number of detection data packets in each detection data packet group corresponds to the total computing power of the slave processing circuits scheduled in the corresponding operation round; and

[0156] Based on the number of detected data packets, the scheduled slave processing circuits are grouped, and each slave processing circuit group performs target detection for the same detected data packet.

[0157] Clause 5. The computing device pursuant to Clause 4, wherein the splitting rule includes at least one of the following:

[0158] The multicast data is preferentially split into round-robin multiplexing based on the first dimension of the output data; when the size of the first dimension of the output data is less than a predetermined threshold, the second dimension of the output data is also used for round-robin multiplexing.

[0159] The number of times multicast data is reused in each round of computation is greater than the minimum number of times multicast data is reused M, but does not exceed the maximum number of times multicast data is reused N.

[0160] Clause 6. A computing device according to any one of Clauses 4-5, wherein the splitting rule includes at least one of the following:

[0161] According to alignment requirements, the data to be detected and the target data within a single scanning window are split into corresponding rows of detection data and rows of target data.

[0162] The data to be detected and the target data are first split according to the first dimension of the scanning window; when the size of the first dimension of the scanning window is less than a predetermined threshold, the second dimension of the scanning window is also used for splitting.

[0163] The size of the data rows obtained from the split in each operation is greater than the minimum computational cost Mc, but does not exceed the maximum computational cost Nc.

[0164] Clause 7. The computing device according to Clause 6, wherein the slave processing circuitry is further configured to:

[0165] The reading method of the data to be detected and the target data is controlled so that the data to be detected and the target data are simultaneously traversed through the entire scanning window to perform position comparison and accumulation operations through multiple calculations, so as to obtain multiple partial similarities and accumulate them to obtain the similarity value on the corresponding scanning window.

[0166] Clause 8. The computing device according to Clause 7, wherein each of the slave processing circuits includes a comparison circuit and an accumulation circuit, wherein:

[0167] The comparison circuit is used to perform a positional comparison between the allocated detection data row and the target data row and output the comparison result; and

[0168] The accumulation circuit is used to accumulate the comparison results of the comparison circuit to obtain a partial similarity value, and to accumulate the partial similarity value with the partial similarity value of the previous round to update the partial similarity value.

[0169] Clause 9. The computing device according to Clause 8, wherein the comparison circuit includes a plurality of comparators, each comparator being configured to compare a data to be detected in a detection data row assigned to the processing circuit with a target data in a corresponding target data row, and output a comparison result indicating whether the two are the same.

[0170] Clause 10. The computing device according to Clause 9, wherein the accumulation circuit includes an adder circuit and a register, wherein:

[0171] The addition circuit is used to perform an addition operation on the comparison results of the plurality of comparators to obtain a partial similarity value for the current round, and to perform an addition operation on the partial similarity value of the current round and the partial similarity value of the previous round to update the partial similarity value; and

[0172] The register is used to store the updated partial similarity values.

[0173] Clause 11. The computing device according to any one of Clauses 4-10, wherein the main arithmetic circuitry is further configured to:

[0174] Based on the allocation of the detection data packet on the scheduled slave processing circuits, the similarity values ​​output by multiple slave processing circuits corresponding to the same detection data packet are concatenated to generate the final detection result of the detection data packet.

[0175] Clause 12. A chip comprising a computing device according to any one of Clauses 1-11.

[0176] Clause 13. A board including the chip described in Clause 12.

[0177] Clause 14. A method for performing a target detection task using any of the computing devices described in Clauses 1-11.

[0178] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. A computing device, comprising a control circuit and an arithmetic circuit, wherein: The control circuit is used to parse target detection instructions. The target detection instructions operate on both data to be detected and target data. The target detection instructions instruct the detection of the positional distribution of a single target represented by the target data within the data to be detected as output data. The computing circuit includes multiple slave processing circuits, and the computing circuit is used to schedule a corresponding number of slave processing circuits to perform target detection tasks according to the target detection instruction, wherein each scheduled slave processing circuit performs the target detection task for a portion of the data to be detected and / or the target data; The arithmetic circuit further includes a main processing circuit, which is used for: Based on the target detection command and the processing capability of the processing circuit, the splitting scheme of the target detection task is determined according to the splitting rules. The splitting scheme includes one or more of the following: the transmission method of the data to be detected and the target data, the splitting method of the data to be detected and the target data, the number of times the data to be detected is reused and the number of times the target data is reused; The arithmetic circuit further includes a first storage circuit and a second storage circuit, and the main processing circuit is further used for: The target data is identified as multicast data, and the data to be detected is identified as distribution data; The multicast data is stored in the first storage circuit so that it can be transmitted to the scheduled slave processing circuits via a broadcast bus during operation. as well as The split distribution data is stored in the second storage circuit so that the scheduled slave processing circuit can load the corresponding part of the distribution data for processing.

2. The computing device according to claim 1, wherein the splitting rule includes at least one of the following: The data to be detected is split into multiple detection data packets according to data batches and grouped according to the order of the operation rounds. The number of detection data packets in each detection data packet group corresponds to the total computing power of the slave processing circuits scheduled in the corresponding operation round; and Based on the number of detected data packets, the scheduled slave processing circuits are grouped, and each slave processing circuit group performs target detection for the same detected data packet.

3. The computing device according to claim 2, wherein the splitting rule includes at least one of the following: The multicast data is preferentially split into round-robin multiplexing based on the first dimension of the output data; when the size of the first dimension of the output data is less than a predetermined threshold, the second dimension of the output data is also used for round-robin multiplexing. The number of times multicast data is reused in each round of computation is greater than the minimum number of times multicast data is reused M, but does not exceed the maximum number of times multicast data is reused N.

4. The computing device according to claim 2, wherein the splitting rule includes at least one of the following: According to alignment requirements, the data to be detected and the target data within a single scanning window are split into corresponding rows of detection data and rows of target data. The data to be detected and the target data are first split according to the first dimension of the scanning window; when the size of the first dimension of the scanning window is less than a predetermined threshold, the second dimension of the scanning window is also used for splitting. The size of the data rows obtained from the split in each operation is greater than the minimum computational cost Mc, but does not exceed the maximum computational cost Nc.

5. The computing device of claim 4, wherein the slave processing circuitry is further configured to: The reading method of the data to be detected and the target data is controlled so that the data to be detected and the target data are simultaneously traversed through the entire scanning window to perform position comparison and accumulation operations through multiple calculations, so as to obtain multiple partial similarities and accumulate them to obtain the similarity value on the corresponding scanning window.

6. The computing device of claim 5, wherein each of the slave processing circuits includes a comparison circuit and an accumulation circuit, wherein: The comparison circuit is used to perform a positional comparison between the allocated detection data row and the target data row and output the comparison result; and The accumulation circuit is used to accumulate the comparison results of the comparison circuit to obtain a partial similarity value, and to accumulate the partial similarity value with the partial similarity value of the previous round to update the partial similarity value.

7. The computing device of claim 6, wherein the comparison circuit comprises a plurality of comparators, each comparator being configured to compare a data to be detected in a detection data row allocated to the processing circuit with a target data in a corresponding target data row, and output a comparison result indicating whether the two are the same.

8. The computing device according to claim 7, wherein the accumulation circuit comprises an adder circuit and a register, wherein: The addition circuit is used to perform an addition operation on the comparison results of the plurality of comparators to obtain the partial similarity value of the current round, and to perform an addition operation on the partial similarity value of the current round and the partial similarity value of the previous round to update the partial similarity value; as well as The register is used to store the updated partial similarity values.

9. The computing device according to any one of claims 2-8, wherein the main processing circuitry is further configured to: Based on the allocation of the detection data packet on the scheduled slave processing circuits, the similarity values ​​output by multiple slave processing circuits corresponding to the same detection data packet are concatenated to generate the final detection result of the detection data packet.

10. A chip comprising a computing device according to any one of claims 1-9.

11. A circuit board comprising the chip according to claim 10.

12. A method for performing a target detection task using the computing device according to any one of claims 1-9.

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