Self-Aligned Double-Groove Shield-Gate MOSFET Structure and Its Manufacturing Method

Abstract

The present invention discloses a self-aligned dual-groove shielded-gate MOSFET structure and a manufacturing method thereof. After forming a first semiconductor layer of a first conductivity type, a body region layer of a second conductivity type, and a source region layer of the first conductivity type on a substrate, by using different etching selectivity ratios between a first hard mask and a fourth hard mask and combining with a sidewall process, an array of multiple self-aligned gate trenches and source trenches is formed in the first semiconductor layer in an alternating manner. A shielded gate and a gate are formed in the gate trenches, a second semiconductor layer of the second conductivity type is formed in the source trenches, a sidewall structure is formed on the first semiconductor layer between the gate trenches and the source trenches, and an adhesive layer is formed between the sidewalls. The present invention can save photomasks, reduce the device area, further reduce resistance and parasitic capacitance, increase the current amount and the switching speed, and improve the device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a self-aligned dual-groove shield-gate MOSFET structure and a manufacturing method thereof. Background Art

[0002] Compared with a planar MOSFET, a trench MOSFET can provide a shorter current path between the source and the drain, thereby reducing the on-resistance, allowing more current to flow through the switch, and significantly reducing the power loss. Reducing the spacing between structures in a MOSFET device enables the MOSFET device to have a smaller die area, further reducing the resistance per unit area and increasing the current density. However, as the device area continues to shrink, it also brings an increase in the number of processing steps and the number of photomasks in the manufacturing process, which undoubtedly increases the manufacturing cost. In addition, due to the existence of overlay errors, the short-circuit resistance also increases. Summary of the Invention

[0003] The object of the present invention is to overcome the above-mentioned defects existing in the prior art, and to provide a self-aligned dual-groove shield-gate MOSFET structure and a manufacturing method thereof.

[0004] To achieve the above object, the technical solution of the present invention is as follows:

[0005] The present invention provides a self-aligned dual-groove shield-gate MOSFET structure, including:

[0006] A first semiconductor layer of a first conductivity type covering the upper surface of the substrate;

[0007] A source region layer of a first conductivity type formed in the first semiconductor layer and located within the upper surface of the first semiconductor layer, and a body region layer of a second conductivity type located under the source region layer;

[0008] An array of a plurality of gate trenches and source trenches entering the first semiconductor layer side by side from the upper surface of the first semiconductor layer and formed in an alternating manner. A shield gate, an isolation layer, and a gate electrode are formed in the gate trench from bottom to top. Gate oxide layers are formed between the shield gate and the inner wall of the gate trench and between the gate electrode and the inner wall of the gate trench. A second semiconductor layer of a second conductivity type is formed in the source trench;

[0009] A plurality of sidewall structures protruding from the upper surface of the first semiconductor layer and located between every two adjacent gate trenches and source trenches, and an adhesive layer formed between the sidewalls;

[0010] Wherein, the source trench is self-alignedly formed between every two adjacent gate trenches through an opening between every two adjacent sidewalls.

[0011] Further, the bottom end of the gate trench is located in the first semiconductor layer below the body region layer, and the bottom end of the source trench is flush or non-flush with the bottom end of the gate trench.

[0012] Further, the top end of the gate protrudes above the upper surface of the first semiconductor layer and is located between the sidewalls, and the bottom end of the gate is located in the first semiconductor layer below the body region layer.

[0013] Further, the sidewall includes a connected first sidewall and a second sidewall; wherein, the first sidewall is disposed adjacent to both sides of the gate trench, the second sidewall is formed outside the first sidewall and is disposed adjacent to both sides of the source trench, and the horizontal width of the source region layer between the source trench and the gate trench is determined by the horizontal width of the second sidewall.

[0014] Further, it further includes: a top metal layer covering the upper surfaces of the sidewall and the adhesion layer.

[0015] The present invention further provides a manufacturing method of a self-aligned double-groove shield gate MOSFET structure, including:

[0016] Providing a substrate and forming a first semiconductor layer of a first conductivity type covering the upper surface of the substrate;

[0017] Forming a source region layer of a first conductivity type within the upper surface of the first semiconductor layer and forming a body region layer of a second conductivity type below the source region layer in the first semiconductor layer;

[0018] Forming a plurality of first hard mask layer patterns on the upper surface of the first semiconductor layer;

[0019] Conformally forming a second hard mask layer on the first hard mask layer pattern and performing etch-back to form second hard mask layer patterns on both sides of the first hard mask layer pattern and exposing the top of the first hard mask layer pattern and the upper surface of the first semiconductor layer between two adjacent second hard mask layer patterns on the adjacent side;

[0020] Covering and forming a third hard mask layer on the exposed upper surface of the first semiconductor layer and performing etch-back to form a third hard mask layer pattern between two adjacent second hard mask layer patterns on the adjacent side;

[0021] Removing the second hard mask layer pattern, and then forming first sidewall structures on both sides of the first hard mask layer pattern and both sides of the third hard mask layer pattern respectively;

[0022] Using the first sidewall as a mask, a gate trench is formed downward on the upper surface of the exposed first semiconductor layer, a gate oxide layer is formed on the inner wall of the gate trench, and a shield gate, an isolation layer, and a gate electrode are formed from bottom to top in the gate trench within the gate oxide layer;

[0023] A fourth hard mask layer is formed to cover the gate trench and etched back to form a fourth hard mask layer pattern between the two first sidewalls located on adjacent sides;

[0024] The first hard mask layer pattern and the third hard mask layer pattern are removed, and then source trenches self-aligned between the gate trenches are formed downward on the upper surface of the exposed first semiconductor layer, and a second semiconductor layer of the second conductivity type is formed in the source trenches;

[0025] The fourth hard mask layer pattern is removed, and an adhesion layer located between the first sidewalls is formed to cover the exposed gate trenches and source trenches.

[0026] Further, the step of using the first sidewall as a mask, forming a gate trench downward on the upper surface of the exposed first semiconductor layer, forming a gate oxide layer on the inner wall of the gate trench, and forming a shield gate, an isolation layer, and a gate electrode from bottom to top in the gate trench within the gate oxide layer specifically includes:

[0027] Using the first sidewall, the first hard mask layer pattern, and the third hard mask layer pattern as a common mask, a gate trench is etched downward on the upper surface of the first semiconductor layer exposed between the first sidewalls, and the bottom end of the gate trench is located in the first semiconductor layer below the body region layer;

[0028] A first gate oxide layer material is deposited on the inner wall of the gate trench, a shield gate material is filled in the gate trench within the first gate oxide layer and etched back to form a shield gate; then, an isolation layer material is continuously filled in the gate trench and etched back to form an isolation layer; next, a second gate oxide layer material is deposited on the inner wall of the gate trench above the isolation layer, and a gate electrode material is filled in the gate trench within the second gate oxide layer and etched back to form a gate electrode, and the top end of the gate electrode protrudes above the upper surface of the first semiconductor layer and is located between the first sidewalls, and at the same time the bottom end of the gate electrode is located in the first semiconductor layer below the body region layer, and the gate oxide layer includes the first gate oxide layer and the second gate oxide layer.

[0029] Further, removing the patterns of the first hard mask layer and the third hard mask layer, then forming source trenches self-aligned between the gate trenches downward on the upper surface of the exposed first semiconductor layer, and forming a second semiconductor layer of a second conductivity type in the source trenches, specifically includes:

[0030] By etch-back, removing the patterns of the first hard mask layer and the third hard mask layer, and then, using the first sidewall and the pattern of the fourth hard mask layer as a common mask, forming source trenches self-aligned between the gate trenches downward on the upper surface of the first semiconductor layer exposed between the first sidewalls, and making the bottom end of the source trenches flush or non-flush with the bottom end of the gate trenches;

[0031] After that, filling the source trenches with a second semiconductor layer material and performing etch-back to form a second semiconductor layer of a second conductivity type in the source trenches, and making the top end of the second semiconductor layer flush with the upper surface of the first semiconductor layer.

[0032] Further, removing the patterns of the first hard mask layer and the third hard mask layer, then forming source trenches self-aligned between the gate trenches downward on the upper surface of the exposed first semiconductor layer, and forming a second semiconductor layer of a second conductivity type in the source trenches, specifically includes:

[0033] By etch-back, removing the patterns of the first hard mask layer and the third hard mask layer, and forming second sidewall structures on the outer sides of the first sidewalls located on both sides of the pattern of the fourth hard mask layer;

[0034] Then, using the second sidewalls, the first sidewalls and the pattern of the fourth hard mask layer as a common mask, forming source trenches self-aligned between the gate trenches downward on the upper surface of the first semiconductor layer exposed between the second sidewalls, and making the bottom end of the source trenches flush or non-flush with the bottom end of the gate trenches;

[0035] After that, filling the source trenches with a second semiconductor layer material and performing etch-back to form a second semiconductor layer of a second conductivity type in the source trenches, and making the top end of the second semiconductor layer flush with the upper surface of the first semiconductor layer;

[0036] Wherein, when forming the second sidewalls, by adjusting the horizontal width of the second sidewalls, the horizontal width of the source region layer located between the source trenches and the gate trenches is adjusted.

[0037] Further, it further includes: forming a top metal layer covering the upper surfaces of the first sidewalls and the adhesion layer.

[0038] As can be seen from the above technical solutions, in the present invention, a second hard mask layer is conformally formed on the first hard mask layer pattern, and the second hard mask layer pattern is formed on both sides of the first hard mask layer pattern by etch-back. The third hard mask layer pattern can be self-aligned between the second hard mask layer patterns. Without using one photomask, the pitch is reduced, the MOSFET device has a smaller die area, the resistance per unit area is further reduced, the current density is increased, and the cost is significantly reduced. At the same time, since there is no overlay error, the short-circuit resistance can be effectively reduced. In this way, by stepwise removing the second hard mask layer pattern, the first hard mask layer pattern, and the third hard mask layer pattern, the source trenches can be accurately self-aligned between the gate trenches, effectively reducing the resistance, minimizing the parasitic capacitance, and increasing the switching speed. In addition, when forming the source trenches, a second sidewall with an adjustable width can be additionally formed outside the first sidewall to adjust the formation width of the source trenches, so as to adjust the horizontal width of the source region layer located between the source trenches and the gate trenches, thereby further improving the device performance. Description of the Drawings

[0039] Figure 1 Schematic diagram of a self-aligned dual-gate shielded gate MOSFET structure according to a preferred embodiment of the present invention;

[0040] Figure 2 Flowchart of a manufacturing method of a self-aligned dual-gate shielded gate MOSFET structure according to a preferred embodiment of the present invention;

[0041] Figures 3 - 7 According to a preferred embodiment of the present invention Figure 2 Schematic diagram of process steps when manufacturing a self-aligned dual-gate shielded gate MOSFET structure by the method. Detailed Embodiments

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings understood by those of ordinary skill in the art in the technical field to which the present invention belongs. The words such as "including" used herein mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items.

[0043] Unless otherwise specifically indicated hereinafter, the various parts of the MOSFET device can be made of materials well-known to those skilled in the art. Semiconductor materials can include, for example, group III-V semiconductors such as GaAs, InP, GaN, SiC, and group IV semiconductors such as Si, Ge, etc. The gate conductor can be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x , Ni3Si, Pt, Ru, W, and combinations of the various conductive materials, etc. The gate dielectric can be composed of SiO2 or materials with a dielectric constant greater than that of SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, titanates, etc. Moreover, the gate dielectric can not only be formed of materials well-known to those skilled in the art but also materials developed in the future for gate dielectrics.

[0044] The first conduction type can be one of N-type and P-type, and the second conduction type can be the other of N-type and P-type. The N-type can be formed by implanting an N-type dopant (such as P, As, etc.) into the semiconductor material. The P-type can be formed by implanting a P-type dopant (such as B, etc.) into the semiconductor material. The above can be understood with reference to well-known techniques.

[0045] The following will further elaborate on the specific embodiments of the present invention in conjunction with the accompanying drawings.

[0046] Please refer to Figure 1 , Figure 1 , which is a schematic diagram of a self-aligned double-groove shielded-gate MOSFET structure according to a preferred embodiment of the present invention. As Figure 1 shown, a self-aligned double-groove shielded-gate MOSFET structure of the present invention includes:

[0047] A first semiconductor layer 11 of a first conductivity type covering the upper surface of a substrate 10; a source region layer 14 of the first conductivity type formed in the first semiconductor layer 11 and within the upper surface 111 of the first semiconductor layer 11, and a body region layer 13 of a second conductivity type located below the source region layer 14; an array of a plurality of gate trenches 12 and source trenches 20 entering the first semiconductor layer 11 side by side from the upper surface 111 of the first semiconductor layer 11 and formed in an alternating manner, a shielding gate 122, an isolation layer 123, and a gate 124 are formed in the gate trench 12 from bottom to top, a gate oxide layer 121 is formed between the shielding gate 122 and the inner wall of the gate trench 12 and between the gate 124 and the inner wall of the gate trench 12, a second semiconductor layer 201 of the second conductivity type is formed in the source trench 20; a plurality of sidewall 15 structures protruding from the upper surface 111 of the first semiconductor layer 11 and located between every two adjacent gate trenches 12 and source trenches 20, and an adhesive layer 19 formed between the sidewalls 15.

[0048] Wherein, the source trench 20 is formed between every two adjacent gate trenches 12 by an opening between every two adjacent sidewalls 15 in a self-aligned manner.

[0049] Wherein, the gate oxide layer 121 may include a first gate oxide layer 1211 formed between the shielding gate 122 and the inner wall of the gate trench 12, and a second gate oxide layer 1212 formed between the gate 124 and the inner wall (sidewall) of the gate trench 12.

[0050] Please refer to Figure 1 . In a preferred embodiment, the substrate 10 may be a silicon substrate 10 (N+ substrate) of a first conductivity type with heavy doping N+, and a first semiconductor layer 11 of a first conductivity type with light doping N- is adopted on the silicon substrate 10. The first semiconductor layer 11 may be, for example, an epitaxial single-crystalline silicon layer grown on the silicon substrate 10, and the first semiconductor layer 11 (N-EPI) is lightly doped with N-type.

[0051] The body region layer 13 may be a body region layer 13 (P-body) of a second conductivity type with light doping P-type in the first semiconductor layer 11. The source region layer 14 may be a source region layer 14 of a first conductivity type with heavy doping N+ in the first semiconductor layer 11.

[0052] In a preferred embodiment, the gate 124 may adopt a polysilicon gate 124 (Gate poly 2) of a first conductivity type with heavy doping N+.

[0053] In a preferred embodiment, the shielding gate 122 may adopt a polysilicon shielding gate 122 (poly 1) of a first conductivity type with heavy doping N+.

[0054] The second semiconductor layer 201 serves as a source contact conductor and can be a second semiconductor layer 201 of a second conductive type with P-type doping.

[0055] In a preferred embodiment, the second semiconductor layer 201 can be an epitaxial single-crystalline silicon layer grown in the source trench 20 and doped with P-type, that is, the second semiconductor layer 201 can be a P-type doped epitaxial single-crystalline silicon layer (P EPI).

[0056] In a preferred embodiment, the adhesive layer 19 can be prepared from at least one material such as Ti, TiN, and TaN.

[0057] The sidewall 15 can be prepared from conventional materials used in the sidewall process.

[0058] In a preferred embodiment, a top metal layer 18 is further covered on the upper surfaces of the sidewall 15 and the adhesive layer 19. The top metal layer 18 can be prepared from, for example, W or Al.

[0059] In other preferred embodiments, structures such as an interlayer dielectric layer and a metal interconnect layer can be further provided on the top metal layer 18.

[0060] Please refer to Figure 1 . In a preferred embodiment, the bottom ends of the gate trench 12 and the source trench 20 are disposed in the first semiconductor layer 11 below the body region layer 13. Among them, the bottom end of the source trench 20 and the bottom end of the gate trench 12 can be flush in the horizontal direction. Or, the bottom end of the source trench 20 and the bottom end of the gate trench 12 may not be flush in the horizontal direction.

[0061] Furthermore, the bottom end of the source trench 20 can be further disposed to extend into the substrate 10 having a first conductive type. The gate 124 and the shield gate 122 are isolated from the first semiconductor layer 11 through a gate oxide layer 121, and the gate 124 and the shield gate 122 are isolated from each other through an isolation layer 123. The second semiconductor layer 201 of the second conductive type serving as the source contact conductor is connected to the substrate 10 to promote the reduction of resistance and parasitic capacitance. The above structure of the present invention can reduce the device area, provide a shorter current path between the source and the drain, further reduce the resistance per unit area, and increase the current density, thereby reducing the on-resistance, allowing more current to pass through the switch, and thus significantly reducing the power loss.

[0062] In a preferred embodiment, the top end of the gate 124 can protrude above the upper surface 111 of the first semiconductor layer 11 and be located between the sidewalls 15.

[0063] In a preferred embodiment, the bottom end of the gate 124 can be located in the first semiconductor layer 11 below the body region layer 13.

[0064] In a preferred embodiment, the sidewall 15 may include a first sidewall 16 and a second sidewall 17 connected in the horizontal direction. Among them, the first sidewall 16 is disposed on both sides of the gate trench 12; the second sidewall 17 is located outside the first sidewall 16 and is disposed on both sides of the source trench 20. Thus, the horizontal width of the source region layer 14 between the source trench 20 and the gate trench 12 can be determined by the horizontal width of the second sidewall 17. Whether to provide the second sidewall 17 structure and the width of the second sidewall 17 can be determined according to design requirements.

[0065] Next, with reference to the accompanying drawings, a manufacturing method of a self-aligned dual-groove shielded gate MOSFET structure according to the present invention will be described in detail.

[0066] A manufacturing method of a self-aligned dual-groove shielded gate MOSFET structure according to the present invention can be used to manufacture the above Figure 1 self-aligned dual-groove shielded gate MOSFET structure, and the method may include the following steps:

[0067] Step S1: Provide a substrate and form a first semiconductor layer of a first conductivity type covering the upper surface of the substrate.

[0068] Please refer to Figure 3 . In a preferred embodiment, an N+-type heavily doped silicon substrate 10 of the first conductivity type can be used, and an N-type lightly doped first semiconductor layer 11 of the first conductivity type can be used on the silicon substrate 10. The first semiconductor layer 11 can be, for example, an epitaxial single-crystalline silicon layer grown on the silicon substrate 10 and can be lightly doped with N-type by an ion implantation process.

[0069] Step S2: Form a source region layer of a first conductivity type within the upper surface of the first semiconductor layer, and form a body region layer of a second conductivity type underlying the source region layer.

[0070] Please refer to Figure 3 . In a preferred embodiment, an ion implantation process can be used to perform P-type light doping from the upper surface 111 of the first semiconductor layer 11 into the first semiconductor layer 11 to form a body region layer 13 of the second conductivity type.

[0071] Then, an ion implantation process can be used to perform N+-type heavy doping from the upper surface 111 of the first semiconductor layer 11 into the first semiconductor layer 11 to form a source region layer 14 of the first conductivity type on the upper surface 111 of the first semiconductor layer 11 above the body region layer 13.

[0072] Step S3: Form a plurality of first hard mask layer patterns on the upper surface of the first semiconductor layer.

[0073] Please refer to Figure 3。In a preferred embodiment, a first hard mask layer material is deposited uniformly on the upper surface 111 of the first semiconductor layer 11. Then, a photoresist layer is formed on the first hard mask layer. Subsequently, through photolithography and etching, a plurality of first hard mask layer patterns 21 (HM 1) are formed on the upper surface 111 of the first semiconductor layer 11. After that, the residual photoresist on the first hard mask layer patterns 21 is removed.

[0074] The first hard mask layer material can be a conventional hard mask layer material. For example, the first hard mask layer material can be one or more of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, etc.

[0075] Step S4: Conformally form a second hard mask layer on the first hard mask layer patterns, and perform an etch-back to form second hard mask layer patterns on both sides of the first hard mask layer patterns, and expose the top of the first hard mask layer patterns and the upper surface of the first semiconductor layer 11 between two second hard mask layer patterns on the adjacent sides.

[0076] Please refer to Figure 4 。In a preferred embodiment, a conformal CVD process can be used to conformally deposit a second hard mask layer material on the first hard mask layer patterns 21 and the exposed upper surface 111 of the first semiconductor layer 11. Then, an etch-back is performed on the second hard mask layer to form second hard mask layer patterns 22 (HM 2) on both sides of each first hard mask layer pattern 21, and expose the top of the first hard mask layer patterns 21 and the upper surface 111 of the first semiconductor layer 11 between two second hard mask layer patterns 22 on the adjacent sides, that is, between two second hard mask layer patterns 22 inside two adjacent first hard mask layer patterns 21.

[0077] When depositing the second hard mask layer, the width required for depositing the third hard mask layer in the future can be reserved through thickness control during deposition.

[0078] The second hard mask layer material can be a conventional hard mask layer material. For example, the second hard mask layer material can be one or more of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, etc.

[0079] Step S5: Cover and form a third hard mask layer on the exposed upper surface of the first semiconductor layer, and perform an etch-back to form a third hard mask layer pattern between two second hard mask layer patterns on the adjacent sides.

[0080] Please refer to Figure 4。In a preferred embodiment, a conventional process can be adopted to deposit a third hard mask layer material comprehensively on the upper surface 111 of the exposed first semiconductor layer 11 between two second hard mask layer patterns 22 on adjacent sides, completely filling the gap between the two second hard mask layer patterns 22 on adjacent sides to form a third hard mask layer covering the upper surface 111 of the first hard mask layer pattern 21, the second hard mask layer pattern 22, and the first semiconductor layer 11. Then, by etching back the third hard mask layer material, a third hard mask layer pattern 23 (HM 3) can be formed between the two second hard mask layer patterns 22 on adjacent sides. By conformally forming the second hard mask layer on the first hard mask layer pattern 21 and forming the second hard mask layer patterns 22 on both sides of the first hard mask layer pattern 21 by etching back, the third hard mask layer pattern 23 can be self-aligned between the second hard mask layer patterns 22, achieving a pitch reduction while saving one photomask.

[0081] The third hard mask layer material can be a conventional hard mask layer material. For example, the third hard mask layer material can be one or more of silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.

[0082] Step S6: Remove the second hard mask layer pattern, and then form first sidewall structures on both sides of the first hard mask layer pattern and on both sides of the third hard mask layer pattern respectively.

[0083] Please refer to Figure 5 。In a preferred embodiment, the different etching selectivity ratios between the second hard mask layer material and the first hard mask layer material and the third hard mask layer material can be utilized to remove the second hard mask layer pattern 22 between the first hard mask layer pattern 21 and the third hard mask layer pattern 23, exposing the upper surface 111 of the first semiconductor layer 11 between the first hard mask layer pattern 21 and the third hard mask layer pattern 23.

[0084] Then, a sidewall process can be adopted to deposit sidewall material comprehensively on the upper surface 111 of the first hard mask layer pattern 21, the third hard mask layer pattern 23, and the exposed first semiconductor layer 11, and perform etching back to form first sidewall 16 structures on both sides of each first hard mask layer pattern 21 and on both sides of each third hard mask layer pattern 23 respectively.

[0085] When forming the first sidewall 16, the horizontal width of the first sidewall 16 formed by etching back can be adjusted by controlling the deposition thickness of the first sidewall material, so as to adjust the spacing between the two first sidewalls 16 inside two adjacent first hard mask layer patterns 21 and third hard mask layer patterns 23, thereby enabling adjustment of the horizontal width of the gate trench 12 formed by subsequent etching.

[0086] The material of the sidewall 15 can be a conventional sidewall material that has a different etching selectivity ratio between the material of the first hard mask layer and the material of the third hard mask layer.

[0087] Step S7: Using the first sidewall as a mask, form a gate trench downward on the upper surface of the exposed first semiconductor layer, form a gate oxide layer on the inner wall of the gate trench, and form a shielding gate, an isolation layer, and a gate electrode from bottom to top in the gate trench within the gate oxide layer.

[0088] Please refer to Figure 5 . In a preferred embodiment, after forming the first sidewall 16, the first sidewall 16 can be used as a mask, that is, the combined pattern of the first sidewall 16 and the first hard mask layer pattern 21, and the combined pattern of the first sidewall 16 and the third hard mask layer pattern 23 are used as a common mask, and etching is performed downward on the upper surface 111 of the first semiconductor layer 11 exposed between every two adjacent first sidewalls 16, forming a plurality of parallel deep trenches as gate trenches 12 in the first semiconductor layer 11, and making the bottom end of the gate trench 12 located in the first semiconductor layer 11 below the body region layer 13.

[0089] Then, deposit a first gate oxide layer material on the inner wall surface of the gate trench 12 and on the surfaces of the first sidewall 16 and the structures of the first hard mask layer pattern 21 and the third hard mask layer pattern 23, and further fill the shielding gate material in the gate trench 12 within the first gate oxide layer material, which can fill the gap between the first sidewalls 16, so that the shielding gate material covers the first gate oxide layer material.

[0090] Next, by etching back the shielding gate material, a first gate oxide layer 1211 can be formed on the inner wall of the gate trench 12, and a shielding gate 122 can be formed in the lower part of the gate trench 12 within the gate oxide layer 121.

[0091] When etching back the shielding gate 122 material, by controlling the etching back time, the top end of the shielding gate 122 can be made to be in the first semiconductor layer 11 below the body region layer 13.

[0092] Then, continue to fill the isolation layer material in the gate trench 12 and perform etching back to form an isolation layer 123 on the top surface of the shielding gate 122.

[0093] When etching back the isolation layer 123 material, by controlling the etching back time, the top surface of the isolation layer 123 can be made to be in the first semiconductor layer 11 below the body region layer 13.

[0094] Please refer to Figure 6Next, a second gate oxide layer material is deposited on the inner wall of the gate trench 12 above the isolation layer 123. Then, the remaining upper part of the gate trench 12 within the second gate oxide layer 1212 is continuously filled with a gate material, and etch-back is performed to form a second gate oxide layer 1212 on the sidewall of the gate trench 12 above the isolation layer 123, and a gate 124 is formed in the remaining upper part of the gate trench 12 on the isolation layer 123.

[0095] When performing etch-back on the gate 124 material, by controlling the etch-back time, the top ends of the gate 124 and the second gate oxide layer 1212 can protrude above the upper surface 111 of the first semiconductor layer 11 and be located between the first sidewalls 16, that is, the top ends of the gate 124 and the second gate oxide layer 1212 are located at a position below the upper ends of the first sidewalls 16. For example, the top ends of the gate 124 and the second gate oxide layer 1212 can be located at a position below the middle of the height of the first sidewalls 16. However, it is not limited thereto.

[0096] Meanwhile, by controlling the deposition thickness of the isolation layer 123 material, the bottom end of the formed gate 124 can be located in the first semiconductor layer 11 below the body region layer 13.

[0097] The gate oxide layer 121 in the gate trench 12 may include a first gate oxide layer 1211 and a second gate oxide layer 1212.

[0098] The gate 124 material can be, for example, N+-heavily doped polysilicon.

[0099] Step S8: A fourth hard mask layer is formed and covered on the gate trench, and etch-back is performed to form a fourth hard mask layer pattern between two first sidewalls on adjacent sides.

[0100] Please refer to Figure 6 。In a preferred embodiment, a fourth hard mask layer material is deposited comprehensively on the surface of the device structure formed in the previous step to fill the gap between two adjacent first sidewalls 16 above the gate trench 12, so as to completely cover the top ends of the gate 124 and the gate oxide layer 121 exposed on the gate trench 12.

[0101] Then, etch-back is performed on the fourth hard mask layer material to form a fourth hard mask layer pattern 24 (HM 4) between two first sidewalls on adjacent sides, that is, between two first sidewalls 16 inside two adjacent first hard mask layer patterns 21 and third hard mask layer patterns 23.

[0102] The fourth hard mask layer material can be TEOS oxide (tetraethoxysilane oxide).

[0103] Step S9: Remove the first hard mask layer pattern and the third hard mask layer pattern, and then form source trenches self-aligned between the gate trenches downward on the upper surface of the exposed first semiconductor layer, and form a second semiconductor layer of a second conductivity type in the source trenches.

[0104] Please refer to Figure 7 . In a preferred embodiment, the first hard mask layer pattern 21 and the third hard mask layer pattern 23 can be removed by back etching by utilizing the different etching selectivity ratios between the first hard mask layer material and the third hard mask layer material and the first sidewall 16 and the fourth hard mask layer material.

[0105] Then, a sidewall process can be adopted to further form a second sidewall 17 structure on the outer sides of the two first sidewalls 16 located on both sides of each fourth hard mask layer pattern 24, that is, on both sides of each gate trench 12. The first sidewall 16 and the second sidewall 17 together form a sidewall 15 structure.

[0106] Next, with the second sidewall 17, the first sidewall 16 and the fourth hard mask layer pattern 24 as a common mask, a plurality of deep trenches self-aligned between the gate trenches 12 are formed downward on the upper surface 111 of the first semiconductor layer 11 exposed between every two adjacent second sidewalls 17 to form source trenches 20, and the bottom end of the source trench 20 is flush or not flush with the bottom end of the gate trench 12.

[0107] Furthermore, the bottom end of the source trench 20 can also extend into the substrate 10 of the first conductivity type.

[0108] After that, the source trench 20 is filled with a second semiconductor layer material. Then, the second semiconductor layer material is back etched to form a second semiconductor layer 201 in the source trench 20, and the top end of the second semiconductor layer 201 is flush or substantially flush with the upper surface 111 of the first semiconductor layer 11.

[0109] In a preferred embodiment, the second semiconductor layer 201 can be filled by growing an epitaxial single crystal silicon layer in the source trench 20 and performing P-type doping to have a second conductivity type.

[0110] After forming the first semiconductor layer 11 of the first conductivity type, the body region layer 13 of the second conductivity type, and the source region layer 14 of the first conductivity type, the present invention utilizes the different etching selectivity ratios between the first hard mask to the fourth hard mask and combines with the sidewall process, so as to realize forming an array of self-aligned multiple gate trenches 12 and source trenches 20 in the first semiconductor layer 11 in an alternating manner. The present invention not only saves photomasks, reduces the processing steps in the manufacturing process, significantly reduces the manufacturing cost, but also reduces the device area and eliminates the overlay error, thereby bringing a reduction in the on-resistance, allowing more current to pass through the switch, and thus significantly reducing the power loss.

[0111] Among them, when forming the second sidewall 17, by controlling the deposition thickness of the material of the second sidewall 17, the horizontal width of the second sidewall 17 formed by etch-back is adjusted to adjust the spacing between two second sidewalls 17 located inside two adjacent first sidewalls 16, so that the horizontal width of the source region layer 14 located between the source trench 20 and the gate trench 12 can be adjusted. At the same time, fine adjustment of the device area can also be achieved.

[0112] As another specific embodiment, according to design requirements, the step of forming the second sidewall 17 can also be omitted, and only the width adjustment of the first sidewall 16 is used as a means for adjusting the device structure. In this case, after removing the first hard mask layer pattern 21 and the third hard mask layer pattern 23, the first sidewall 16 and the fourth hard mask layer pattern 24 are used as a common mask, and a source trench 20 self-aligned between the gate trenches 12 is formed downward on the upper surface 111 of the first semiconductor layer 11 exposed between the first sidewalls 16.

[0113] Step S10: Remove the fourth hard mask layer pattern, cover and form an adhesion layer located between the first sidewalls on the exposed gate trench and source trench, and form a top metal layer covering the upper surfaces of the first sidewalls and the adhesion layer.

[0114] Please refer to Figure 7 . In a preferred embodiment, the different etching selectivity ratios between the fourth hard mask layer material and the materials of the first sidewall 16 and the second sidewall 17 can be utilized to remove the fourth hard mask layer pattern 24 by etch-back, exposing the top of the gate 124.

[0115] Please refer to Figure 1 . Then, an adhesion layer material is deposited comprehensively on the surface of the device structure formed above, filling the voids between the second sidewalls 17, and after etch-back, an adhesion layer 19 located between the first sidewalls 16 is formed to cover the gate 124 of the exposed gate trench 12 and the conductive second semiconductor layer 201 of the source trench 20.

[0116] Among them, the adhesion layer 19 located above the gate trench 12 is in direct contact with the first sidewall 16, and the adhesion layer 19 located above the source trench 20 is in direct contact with the second sidewall 17.

[0117] The adhesion layer 19 can be prepared from at least one of Ti, TiN, and TaN.

[0118] Then, a metal material can be deposited on the surface of the device structure formed above to form a top metal layer 18 covering the upper surfaces of the first sidewall 16 (sidewall 15) and the adhesion layer 19, and then patterning is performed.

[0119] The top metal layer 18 can be fabricated using metals such as W or Al.

[0120] After that, processes for forming structures such as the interlayer dielectric layer and the metal interconnect layer can be continued on the top metal layer 18.

[0121] In summary, in the present invention, by conformally forming the second hard mask layer on the first hard mask layer pattern 21 and forming the second hard mask layer patterns 22 on both sides of the first hard mask layer pattern 21 through etch-back, the third hard mask layer pattern 23 can be self-alignedly formed between the second hard mask layer patterns 22. Without using an additional photomask, the pitch is reduced, enabling the MOSFET device to have a smaller die area, thereby further reducing the resistance per unit area, increasing the current density, and significantly reducing the cost. At the same time, since there is no overlay error, the short-circuit resistance can be effectively reduced. Thus, by stepwise removing the second hard mask layer patterns 22, the first hard mask layer pattern 21, and the third hard mask layer pattern 23, the source trenches 20 can be precisely self-alignedly formed between the gate trenches 12, effectively reducing the resistance, decreasing the parasitic capacitance, and increasing the switching speed. Additionally, when forming the source trenches 20, a second sidewall 17 with an adjustable width can be formed on the outside of the first sidewall 16 to adjust the formation width of the source trenches 20, thereby adjusting the horizontal width of the source region layer 14 located between the source trenches 20 and the gate trenches 12, further improving the device performance.

[0122] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes are within the scope and spirit of the present invention as defined in the claims. Moreover, the present invention described herein can have other embodiments and can be implemented or realized in various ways.

Claims

1. A manufacturing method of a self-aligned double-groove shield-gate MOSFET structure, characterized in that Including: Providing a substrate, and forming a first semiconductor layer of a first conductivity type covering the upper surface of the substrate; Forming a source region layer of the first conductivity type within the upper surface of the first semiconductor layer, and forming a body region layer of a second conductivity type underlying the source region layer in the first semiconductor layer; Forming a plurality of first hard mask layer patterns on the upper surface of the first semiconductor layer; Conformally forming a second hard mask layer on the first hard mask layer patterns, and performing etch-back to form second hard mask layer patterns on both sides of the first hard mask layer patterns, and exposing the top of the first hard mask layer patterns and the upper surface of the first semiconductor layer between two adjacent second hard mask layer patterns on the adjacent sides; Covering and forming a third hard mask layer on the exposed upper surface of the first semiconductor layer, and performing etch-back to form a third hard mask layer pattern between two adjacent second hard mask layer patterns on the adjacent sides; Removing the second hard mask layer patterns, and then forming first sidewall structures on both sides of the first hard mask layer patterns and on both sides of the third hard mask layer patterns respectively; Using the first sidewall as a mask, forming a gate trench downward on the exposed upper surface of the first semiconductor layer, forming a gate oxide layer on the inner wall of the gate trench, and forming a shielding gate, an isolation layer and a gate from bottom to top in the gate trench within the gate oxide layer; Covering and forming a fourth hard mask layer on the gate trench, and performing etch-back to form a fourth hard mask layer pattern between two adjacent first sidewalls; Removing the first hard mask layer patterns and the third hard mask layer patterns, and then forming source trenches self-aligned between the gate trenches downward on the exposed upper surface of the first semiconductor layer, and forming a second semiconductor layer of the second conductivity type in the source trenches; Removing the fourth hard mask layer patterns, and covering and forming an adhesion layer between the first sidewalls on the exposed gate trenches and source trenches.

2. The manufacturing method of the self-aligned dual-gate shielded gate MOSFET structure according to claim 1, characterized in that, The step of using the first sidewall as a mask, forming a gate trench downward on the exposed upper surface of the first semiconductor layer, forming a gate oxide layer on the inner wall of the gate trench, and forming a shielding gate, an isolation layer and a gate from bottom to top in the gate trench within the gate oxide layer specifically includes: Using the first sidewall, the first hard mask layer patterns and the third hard mask layer patterns as a common mask, etching downward to form a gate trench on the upper surface of the first semiconductor layer exposed between the first sidewalls, and making the bottom end of the gate trench located in the first semiconductor layer below the body region layer; Deposit a first gate oxide layer material on the inner wall of the gate trench, fill the gate trench within the first gate oxide layer with a shielding gate material, and perform etch-back to form a shielding gate; then, continue to fill the gate trench with an isolation layer material and perform etch-back to form an isolation layer; next, deposit a second gate oxide layer material on the inner wall of the gate trench above the isolation layer, and fill the gate trench within the second gate oxide layer with a gate material and perform etch-back to form a gate, and make the top end of the gate protrude above the upper surface of the first semiconductor layer and be located between the first sidewalls, and at the same time make the bottom end of the gate be in the first semiconductor layer below the body region layer, and the gate oxide layer includes the first gate oxide layer and the second gate oxide layer.

3. The manufacturing method of the self-aligned double-groove shield-gate MOSFET structure according to claim 1, characterized in that, Remove the first hard mask layer pattern and the third hard mask layer pattern, and then form a source trench self-aligned between the gate trenches downward on the exposed upper surface of the first semiconductor layer, and form a second semiconductor layer of a second conductivity type in the source trench. Specifically, it includes: Remove the first hard mask layer pattern and the third hard mask layer pattern by etch-back, and then, using the first sidewalls and the fourth hard mask layer pattern as a common mask, form a source trench self-aligned between the gate trenches downward on the exposed upper surface of the first semiconductor layer between the first sidewalls, and make the bottom end of the source trench flush or non-flush with the bottom end of the gate trench; After that, fill the source trench with a second semiconductor layer material and perform etch-back to form a second semiconductor layer of a second conductivity type in the source trench, and make the top end of the second semiconductor layer flush with the upper surface of the first semiconductor layer.

4. The manufacturing method of the self-aligned double-groove shield-gate MOSFET structure according to claim 1, characterized in that, Remove the first hard mask layer pattern and the third hard mask layer pattern, and then form a source trench self-aligned between the gate trenches downward on the exposed upper surface of the first semiconductor layer, and form a second semiconductor layer of a second conductivity type in the source trench. Specifically, it includes: Remove the first hard mask layer pattern and the third hard mask layer pattern by etch-back, and form a second sidewall structure on the outer sides of the first sidewalls located on both sides of the fourth hard mask layer pattern; Then, using the second sidewalls, the first sidewalls and the fourth hard mask layer pattern as a common mask, form a source trench self-aligned between the gate trenches downward on the exposed upper surface of the first semiconductor layer between the second sidewalls, and make the bottom end of the source trench flush or non-flush with the bottom end of the gate trench; After that, fill the source trench with a second semiconductor layer material and perform etch-back to form a second semiconductor layer of a second conductivity type in the source trench, and make the top end of the second semiconductor layer flush with the upper surface of the first semiconductor layer; Wherein, when forming the second sidewalls, adjust the horizontal width of the second sidewalls to adjust the horizontal width of the source region layer located between the source trench and the gate trench.

5. The manufacturing method of the self-aligned double-groove shield-gate MOSFET structure according to claim 1, characterized in that, It further includes: Form a top metal layer covering the upper surfaces of the first sidewalls and the adhesive layer.

6. A self-aligned double-groove shield gate MOSFET structure, characterized in that, The MOSFET structure is obtained by the manufacturing method according to any one of the foregoing claims 1-5, and includes: A first semiconductor layer of a first conductivity type covering the upper surface of the substrate; A source region layer of a first conductivity type formed in the first semiconductor layer and located within the upper surface of the first semiconductor layer, and a body region layer of a second conductivity type located under the source region layer; An array of a plurality of gate trenches and source trenches entering the first semiconductor layer side by side from the upper surface of the first semiconductor layer and formed in an alternating manner. A shielding gate, an isolation layer, and a gate electrode are formed in the gate trench from bottom to top. A gate oxide layer is formed between the shielding gate and the inner wall of the gate trench and between the gate electrode and the inner wall of the gate trench. A second semiconductor layer of a second conductivity type is formed in the source trench; A plurality of sidewall structures protruding from the upper surface of the first semiconductor layer and located between every two adjacent gate trenches and source trenches, and an adhesive layer formed between the sidewalls; Wherein, the source trench is formed between every two adjacent gate trenches by an opening between every two adjacent sidewalls in a self-aligned manner.

7. The self-aligned dual-gate shielded-gate MOSFET structure according to claim 6, wherein The bottom end of the gate trench is located in the first semiconductor layer below the body region layer, and the bottom end of the source trench is flush or not flush with the bottom end of the gate trench.

8. The self-aligned double-groove shield-gate MOSFET structure according to claim 6, wherein The top end of the gate electrode protrudes from the upper surface of the first semiconductor layer and is located between the sidewalls, and the bottom end of the gate electrode is located in the first semiconductor layer below the body region layer.

9. The self-aligned dual-gate shielded-gate MOSFET structure according to claim 6, wherein The sidewall includes a connected first sidewall and a second sidewall; wherein, the first sidewall is disposed adjacent to both sides of the gate trench, the second sidewall is formed outside the first sidewall and is disposed adjacent to both sides of the source trench, and the horizontal width of the source region layer between the source trench and the gate trench is determined by the horizontal width of the second sidewall.

10. The self-aligned double-groove shield-gate MOSFET structure according to claim 6, wherein, Further includes: A top metal layer covering the upper surfaces of the sidewalls and the adhesive layer.

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