A fine-grid buried-gate electrode structure for a heterojunction battery and a method for preparing the same

Abstract

The present invention discloses a heterojunction battery fine grid buried grid electrode structure and a preparation method thereof, comprising a doped body, a first transparent conductive oxide film arranged on the front and / or back of the doped body, and a first metal conductive layer arranged on the surface of the transparent conductive oxide film, wherein the first metal conductive layer comprises a first fine grid and a first main grid, and the first fine grid and the first main grid are both connected to the first transparent conductive oxide film; further comprising a second metal conductive layer, the second metal conductive layer comprises a second main grid, and the second main grid is connected to the first main grid; a transparent wrapping layer is arranged outside the transparent conductive oxide film, and the first fine grid and the first main grid are both wrapped in the transparent wrapping layer, and the second main grid is exposed outside the transparent wrapping layer. The present invention can protect low-cost grid lines, enhance the contact between grid lines and TCO layers, and enhance light collection, thereby improving the efficiency of solar cells, reducing battery costs, and improving power generation reliability.

Description

Technical Field

[0001] The invention relates to the field of batteries, and in particular to a fine-grid buried-gate electrode structure of a heterojunction battery and a preparation method thereof. Background Art

[0002] Heterojunction battery technology has the advantages of high efficiency, no attenuation, simple production process, and low process temperature. It stands out among many battery technology routes and is considered to be the next generation mainstream battery after Perc. However, there are still many problems in large-scale mass production, which affect its cost and efficiency improvement. Some representative problems are as follows:

[0003] 1. The current heterojunction battery is sensitive to high temperature, so the process temperature control after amorphous silicon film formation is relatively high, generally not exceeding 240°C, which puts stringent requirements on the paste for preparing the main grid line, and low-temperature paste must be used. Low-temperature silver paste has the characteristics of low resistance and low-temperature drying, but because it is generally used in combination with flaky silver powder and spherical silver powder, the printing performance is relatively poor, which has certain limitations on the screen design, resulting in a large amount of silver paste, which in turn raises the cost of the battery. Compared with Perc (13mg / w), the amount of silver paste used in heterojunction (26mg / w) is about twice as high. Therefore, the industry has begun to research and develop low-cost low-temperature silver paste, including but not limited to the use of low-solid content silver paste, silver-coated copper, copper paste, carbon paste, etc. However, the actual electrical performance of silver-coated copper, copper paste and other materials that are close to silver paste has always been questionable in terms of reliability due to the easy oxidation of copper, which limits the large-scale application of these materials.

[0004] 2. Contact between the grid line and the battery:

[0005] The TCO film of heterojunction batteries generally uses materials such as ITO and IWO. These materials generally need to take into account both conductivity and light transmittance, but they are relatively expensive, and their cost accounts for a large proportion of battery materials. Generally speaking, to improve its conductive properties, it is necessary to increase the doping and carrier concentration, but too high a carrier concentration will widen its optical band gap and increase visible light absorption, so there is a seesaw effect between conductivity and light transmittance. In terms of film layer design, due to the contact between the doping layer and the TCO layer, and the TCO layer and the gate line, generally speaking, a higher conductivity is required, so light transmittance is difficult to guarantee.

[0006] In conventional heterojunction cells, since the gate wire is attached to the outer layer of TCO, only the bottom of the gate wire is in contact with TCO, and the contact area is small. If the gate wire is thinned, the contact between the gate wire and TCO will deteriorate, the contact resistance will increase, the ability to collect current will deteriorate, and the efficiency of the battery will be adversely affected.

[0007] 3. Light Collection

[0008] When sunlight hits the grid lines, it will be reflected by the grid lines. This part of the light cannot fall on the battery, resulting in waste and reducing the power generation efficiency. Summary of the invention

[0009] In order to solve the defects of the above-mentioned prior art, the present invention provides a heterojunction battery fine gate buried gate electrode structure and a preparation method thereof. The present invention can protect the low-cost gate line, enhance the contact between the gate line and the TCO layer and enhance the light collection, improve the efficiency of solar cells, reduce the battery cost, and improve the reliability of power generation.

[0010] To achieve the above technical objectives, the present invention adopts the following technical solutions: a heterojunction battery fine-grid buried-gate electrode structure, characterized in that it includes a doped body, a first transparent conductive oxide film disposed on the front and / or back side of the doped body, and a first metal conductive layer disposed on the surface of the first transparent conductive oxide film, the first metal conductive layer includes a first fine grid and a first main grid, and the first fine grid and the first main grid are both connected to the first transparent conductive oxide film;

[0011] It also includes a second metal conductive layer, the second metal conductive layer includes a second main grid, and the second main grid is attached to the first main grid;

[0012] A transparent wrapping layer is disposed outside the first transparent conductive oxide film, and the first fine grid and the first main grid are both wrapped in the transparent wrapping layer, and the second main grid is exposed outside the transparent wrapping layer.

[0013] Furthermore, the transparent wrapping layer includes a second transparent conductive oxide film and a third transparent conductive oxide film, the second transparent conductive oxide film is formed on the first transparent conductive oxide film, and the third transparent conductive oxide film is formed on the second transparent conductive oxide film; the second transparent conductive oxide film wraps the first fine grid and the first main grid, and the second main grid is exposed outside the second transparent conductive oxide film and outside the third transparent conductive oxide film.

[0014] A method for preparing a fine-gate buried-gate electrode structure of a heterojunction battery comprises the following steps:

[0015] Prepare the first thin film: form the first transparent conductive oxide thin film on the front side and / or the back side of the dopant;

[0016] Preparing a first conductive layer: forming the first metal conductive layer on the first transparent conductive oxide film, so that the first fine grid and the first main grid are both connected to the first transparent conductive oxide film;

[0017] Preparing a transparent wrapping layer: forming the transparent wrapping layer outside the first transparent conductive oxide film and exposing the first main grid;

[0018] Prepare the second conductive layer: form the second metal conductive layer on the first main grid, so that one side of the second main grid is attached to and connected to the first main grid, and the other opposite side is exposed outside the transparent wrapping layer.

[0019] A method for preparing a fine-gate buried-gate electrode structure of a heterojunction battery comprises the following steps:

[0020] Prepare the first thin film: form the first transparent conductive oxide thin film on the front side and / or the back side of the dopant;

[0021] Preparing a first conductive layer: forming the first metal conductive layer on the first transparent conductive oxide film, so that the first fine grid and the first main grid are both connected to the first transparent conductive oxide film;

[0022] Preparing a transparent wrapping layer: forming the transparent wrapping layer outside the first transparent conductive oxide film;

[0023] Prepare the second conductive layer: groove the transparent wrapping layer at the position of the first main grid to expose the first main grid, and form the second metal conductive layer on the first main grid so that one side of the second main grid is attached to the first main grid and the other opposite side is exposed outside the transparent wrapping layer.

[0024] Furthermore, the preparation of the transparent film comprises the following sub-steps:

[0025] Preparing a second thin film: forming the second transparent conductive oxide thin film outside the first transparent conductive oxide thin film, and exposing the first main grid;

[0026] Preparing a third thin film: forming the third transparent conductive oxide thin film outside the second transparent conductive oxide thin film, and exposing the first main grid.

[0027] Furthermore, before preparing the second film, the following steps are also included: placing a shielding member on the first main grid, the shielding member shielding the first main grid so that the first main grid is avoided when forming the second transparent conductive oxide film and the third transparent conductive oxide film.

[0028] Furthermore, the preparation of the transparent wrapping layer comprises the following sub-steps:

[0029] Preparing a second thin film: forming the second transparent conductive oxide thin film outside the first transparent conductive oxide thin film;

[0030] Preparing a third thin film: forming the third transparent conductive oxide thin film outside the second transparent conductive oxide thin film.

[0031] Furthermore, the second transparent conductive oxide film and the third transparent conductive oxide film are both formed on the entire surface.

[0032] Furthermore, the total thickness of the first transparent conductive oxide film, the second transparent conductive oxide film, and the third transparent conductive oxide film is 70-130 nm.

[0033] Furthermore, the thickness of the first metal conductive layer is 5-20 μm, the thickness of the second metal conductive layer is 5-20 μm, and the total thickness of the first metal conductive layer and the second metal conductive layer is 20-40 μm.

[0034] In summary, the present invention has achieved the following technical effects:

[0035] The present invention includes a silicon wafer body and a deposited intrinsic layer (amorphous silicon) and a doping layer (amorphous silicon or microcrystalline silicon), which are called a doping body (doping 01); a first transparent conductive oxide film (TCO01) is formed on doping 01; a first metal conductive layer is a gate line 01 including a first main grid and a first fine grid, which is formed on TCO01; a second metal conductive layer is a gate line 02 including only a second main grid, which is formed on the gate line 01; a second transparent conductive oxide film (TCO02) is formed on TCO01, and covers and shields the portion outside the gate line 02; a third transparent conductive oxide film (TCO03) is formed on TCO02, and covers and shields the portion outside the gate line 02, so that the fine grid portion is wrapped and has multi-faceted contact with the TCO layer, thereby enhancing the conductivity and improving the battery efficiency;

[0036] In the present invention, the light irradiates the first fine grid part, is reflected to the film layer interface (TCO03), and then is reflected again to enter the battery, thereby improving the utilization rate of the incident light and improving the battery performance;

[0037] The present invention adopts a packaging form to isolate water and oxygen as well as acetic acid components produced by the hydrolysis of EVA in the component, thereby effectively improving reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of the partial structure of an existing traditional crystalline silicon heterojunction solar cell;

[0039] Figure 2 It is a partial schematic diagram of a fine-gate buried-gate electrode structure of a heterojunction battery according to an embodiment of the present invention;

[0040] Figure 3 It is a schematic diagram of the battery grid structure;

[0041] Figure 4 It is a schematic cross-sectional view of the first fine grid portion of the double-sided grid line 01 of the present invention;

[0042] Figure 5 It is a partial cross-sectional schematic diagram of the first main grid and the second main grid on both sides of the present invention. DETAILED DESCRIPTION

[0043] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0044] This specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed. However, as long as they are within the scope of the claims of the present invention, they are protected by the patent law.

[0045] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0046] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0047] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0048] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0049] like Figure 1 Shown is a schematic diagram of the partial structure of an existing traditional crystalline silicon heterojunction solar cell.

[0050] like Figure 2 As shown, a fine-grid buried-gate electrode structure of a heterojunction battery comprises a doped body, a first transparent conductive oxide film disposed on the front and / or back side of the doped body, and a first metal conductive layer disposed on the surface of the transparent conductive oxide film, wherein the first metal conductive layer comprises a first fine grid and a first main grid, and the first fine grid and the first main grid are both connected to the first transparent conductive oxide film;

[0051] It also includes a second metal conductive layer, the second metal conductive layer includes a second main grid, and the second main grid is attached and bonded to the first main grid;

[0052] A transparent wrapping layer is arranged outside the transparent conductive oxide film, and the first fine grid and the first main grid are both wrapped in the transparent wrapping layer, and the second main grid is exposed outside the transparent wrapping layer.

[0053] Furthermore, the transparent wrapping layer includes a second transparent conductive oxide film and a third transparent conductive oxide film, the second transparent conductive oxide film is formed on the first transparent conductive oxide film, and the third transparent conductive oxide film is formed on the second transparent conductive oxide film; the second transparent conductive oxide film wraps the first fine grid and the first main grid, and the second main grid is exposed outside the second transparent conductive oxide film and outside the third transparent conductive oxide film.

[0054] In this embodiment, the doped body (doping 01) includes a silicon wafer body, a deposited intrinsic layer, and a doped layer.

[0055] Among them, the silicon wafer body is cleaned and texturized. According to the specific production process route, it can be a double-sided textured silicon wafer or a single-sided polished and single-sided textured silicon wafer. The first transparent conductive oxide film is formed on the textured surface. That is, the electrode structure of this patent can be used for the front side of the heterojunction battery, and can also be used for the back side of the heterojunction battery, or for both the front and back sides at the same time, and the effects can be superimposed.

[0056] The intrinsic layer is amorphous silicon, the doped layer is amorphous silicon or microcrystalline silicon, the amorphous silicon intrinsic layer and the doped layer include: an intrinsic amorphous silicon layer, an n-type doped layer, and a p-type doped layer, the n-type doped layer is selected from one or a combination of two or more of n-type amorphous silicon, n-type microcrystalline silicon, and n-type nanocrystalline silicon, and the p-type doped layer is selected from one or a combination of two or more of p-type amorphous silicon, p-type microcrystalline silicon, and p-type nanocrystalline silicon.

[0057] Three layers of transparent conductive oxide films are used as TCO (transparent conductive oxide) layers, namely, a first transparent conductive oxide film, a second transparent conductive oxide film, and a third transparent conductive oxide film, corresponding to TCO01, TCO02, and TCO03 layers. The materials of the three layers of TCO are selected from one or more TCO materials such as ITO (tin-doped indium oxide), IWO (tungsten-doped indium oxide), AZO (aluminum-doped zinc oxide), and IZO (indium zinc oxide). Since TCO materials may have different formulas and codes, all materials used for heterojunction batteries and having the same functions are included here; the materials selected for TCO01, TCO02, and TCO03 may be the same or different; the process parameters selected for TCO01, TCO02, and TCO03 may be the same or different, and may be selected from one or both of PVD (physical vapor deposition) and RPD (reactive ion deposition).

[0058] At the same time, the in-layer processes of TCO01, TCO02, and TCO03 can be consistent, or they can be fine-tuned to form a gradient film layer; for example, for light trapping design: the refractive index of TCO03 is lower than that of TCO02, and the refractive index of TCO02 is not higher than that of TCO01, so as to form a refractive index gradient and enhance the light trapping performance.

[0059] The two metal conductive layers are the first metal conductive layer and the second metal conductive layer, which serve as gate line 01 and gate line 02 respectively. Gate line 01 includes a first main gate and a first fine gate, and gate line 02 includes a second main gate. The second main gate is formed on the first main gate and serves as an electrode.

[0060] TCO01 is a whole-surface coating method that covers the front and / or back of the dopant, and then forms the gate line 01; TCO02 and TCO03 have multiple implementation methods: a shielding member can be used to cover the first main grid position of the gate line 01, so that the first fine grid and TCO01 positions are exposed, and TCO02 and TCO03 are formed by PVD or RPD. After removing the shielding member, the first main grid is the exposed part, and the first fine grid and TCO01 are wrapped by TCO02 and TCO03, so that the first main grid is exposed, which is convenient for the subsequent formation of the second main grid of the gate line 02 on the first main grid. TCO02 and TCO03 can also be sputtered on the entire surface first to completely cover TCO01, the first main grid and the first fine grid. Then, before forming the gate line 02, use a laser to make grooves on the TCO02 and TCO03 film layers. The groove depth is 20-70nm, but it is necessary to ensure that the remaining thickness of TCO is 10-50nm and expose the first main grid part of the gate line 01. Then, prepare the gate line 02 on the first main grid.

[0061] The materials of the gate lines 01 and 02 are selected from one or more of silver, silver paste, copper, and aluminum; the materials selected for the gate lines 01 and 02 can be the same or different. The thickness of the gate lines 01 and 02 is 5-20 μm, and the total thickness of the gate lines 01 and 02 is 20-40 μm. The line width of the first fine grid of the gate line 01 is 20-100 μm, and the pad width of the first main grid is 0.3-2 mm; the pad width of the second main grid of the gate line 02 is 0.3-2 mm, which is the same as the first main grid.

[0062] The process method for preparing gate lines 01 and 02 can be one or a combination of electroplating, sputtering, evaporation, screen printing, and inkjet printing; the shape and spacing of the metal conductive layer are designed according to the process requirements. Preferably, the spacing and shape of the metal conductive layer are consistent with the gate line requirements on the heterojunction battery.

[0063] like Figure 1 is a schematic diagram of the relationship between the first fine gate and the TCO in the prior art, such as Figure 2 The figure shows the relationship between the first fine grid and TCO of the present invention. In the structure of the present invention, the first fine grid of the gate line 01 is located on TCO01, and TCO02 is formed on TCO01, and covers and shields the portion outside the gate line 02; TCO03 is formed on TCO02, and covers and shields the portion outside the gate line 02, forming a form in which the first fine grid and the first main grid are completely wrapped, and the second main grid is exposed. TCO03 and TCO02 are used to isolate water and oxygen as well as the acetic acid component of the EVA hydrolysis in the component, which can effectively improve the reliability; at the same time, the gate line 02 is formed on the gate line 01, and the second main grid of the gate line 02 overlaps with the first main grid of the gate line 01 in vertical projection; as shown in FIG. Figure 1It can be seen that only one surface of the first fine grid and the TCO is in contact and only one surface is conductive. Figure 2 As shown, the gate line 01 is wrapped by TCO01 and TCO02. The gate line 01 can be in contact with the conductive film (TCO01 and TCO02) all around, which enhances the conductivity, improves the battery efficiency, and expands the space for the thinning of the gate line. In addition, under the premise of sufficient conductivity, TCO03 has more options and can use materials with poor conductivity but low cost, such as AZO, SiNx, etc., which can effectively reduce costs. Figure 1 and Figure 2 , Figure 1 In the prior art, the light is directly reflected after being irradiated by the first fine grid. Figure 2 In this patent, light irradiates the first fine grid part, reflects to the film layer interface (TCO03), and then reflects again to enter the interior of the battery, thereby improving the utilization rate of the incident light and enhancing the battery performance.

[0064] like Figure 3 FIG. 1 is a schematic diagram showing the relationship between the first fine gate and the first main gate of the prepared gate line 01. Figure 4 FIG. 1 is a schematic cross-sectional view of the first fine grid portion of the double-sided grid line 01. Figure 5 Shown is a partial cross-sectional schematic diagram of a double-sided first main grid and a second main grid, where double-sided refers to the front side and the back side.

[0065] A method for preparing a fine-gate buried-gate electrode structure of a heterojunction battery comprises the following steps:

[0066] Prepare the first thin film: form TCO01 on the front side and / or the back side of the dopant;

[0067] Prepare the first conductive layer: form a gate line 01 on TCO01, so that the first fine gate and the first main gate are both connected to TCO01;

[0068] Preparing a transparent wrapping layer: forming the transparent wrapping layer outside TCO01 and exposing the first main grid;

[0069] Prepare the second conductive layer: form a gate line 02 on the first main grid, so that one side of the second main grid is connected to the first main grid, and the other opposite side is exposed outside the TCO03.

[0070] Wherein, the preparation of the transparent film comprises the following sub-steps:

[0071] Preparing a second thin film: forming the second transparent conductive oxide thin film outside the first transparent conductive oxide thin film, and exposing the first main grid;

[0072] Preparing a third thin film: forming the third transparent conductive oxide thin film outside the second transparent conductive oxide thin film, and exposing the first main grid.

[0073] In this method, before preparing the second film, the following steps are also included: placing a shielding member on the first main grid, the shielding member shielding the first main grid so that the first main grid is avoided when TCO02 and TCO03 are formed, so that TCO02 will not be formed at the position of the first main grid, and TCO03 will not be formed by continuous shielding in subsequent steps. After removing the shielding member, the first main grid is exposed, so as to facilitate the formation of the second main grid on the first main grid.

[0074] A method for preparing a fine-gate buried-gate electrode structure of a heterojunction battery comprises the following steps:

[0075] Prepare the first thin film: form TCO01 on the front side and / or the back side of the dopant;

[0076] Prepare the first conductive layer: form a gate line 01 on TCO01, so that the first fine gate and the first main gate are both connected to TCO01;

[0077] Preparing a transparent wrapping layer: forming the transparent wrapping layer outside TCO01;

[0078] Prepare the second conductive layer: groove TCO02 and TCO03 at the position of the first main grid to expose the first main grid, form grid line 02 on the first main grid, so that one side of the second main grid is connected to the first main grid and the other opposite side is exposed outside the transparent wrapping layer.

[0079] The preparation of the transparent wrapping layer comprises the following sub-steps:

[0080] Prepare the second film: form TCO02 outside TCO01;

[0081] Preparation of the third film: Formation of TCO03 outside TCO02.

[0082] In this method, TCO02 and TCO03 are formed on the entire surface. The front side formation means that TCO02 and TCO03 are also formed at the position of the first main grid. Then, grooves are cut at the position of the first main grid to dig out TCO02 and TCO03 to expose the first main grid, so as to facilitate the formation of the second main grid on the first main grid.

[0083] The thickness of each of TCO01, TCO02 and TCO03 is 20-70nm, ensuring that the total thickness of the three layers of TCO01, TCO02 and TCO03 is 70-130nm.

[0084] The thickness of the gate line 01 is 5-20 μm, the thickness of the gate line 02 is 5-20 μm, and the total thickness of the gate line 01 and the gate line 02 is 20-40 μm.

[0085] Embodiment 1:

[0086] The N-type silicon wafer is cleaned and textured by chemicals, and a 3-10μm pyramid surface is formed on both sides of the silicon wafer. Amorphous silicon is deposited on the textured surface using PECVD, and an intrinsic amorphous silicon thin film layer and n-type doped amorphous silicon are deposited on the front side, and then an intrinsic amorphous silicon thin film layer and p-type doped amorphous silicon are deposited on the back side.

[0087] A first transparent conductive oxide film, namely ITO film, is deposited on the front of the silicon wafer using the PVD method as TCO01. The film thickness is 45nm, the refractive index is 3.3, and the test square resistance is 70Ω / □. Using the printing process, a layer of silver-coated copper paste is printed on the deposited ITO film layer to form the first metal conductive layer, namely gate line 01. Gate line 01 includes a main gate and a fine gate. The thickness of the main gate and the fine gate are both 20μm, the width of the fine gate line is 30μm, and the width of the main gate line is 0.9mm. The battery is low-temperature baked at a temperature of 110℃ for 5min. A shielding member is installed on the carrier board. The shape of the shielding member just covers the main grid of the gate line 01 and exposes the fine grid to prevent the main grid from being sputtered by ITO. The second transparent conductive oxide film and the third transparent conductive oxide film are deposited on the front of the silicon wafer by PVD method again, that is, TCO02 and TCO03 are deposited in sequence. TCO02 is ITO with a film thickness of 45nm, a refractive index of 3.1, and a test square resistance of 50Ω / □. TCO03 is AZO with a film thickness of 40nm, a refractive index of 3.01, and a test square resistance of 40Ω / □. The shielding member is removed to expose the main grid of the gate line 01. Then the cell is sent to the printer to print the gate line 02 on the front and dry it. That is, the gate line 02 is printed at the main grid position of the gate line 01. The gate line 02 only includes the main grid. The thickness of the gate line 02 is 5μm, and the line width is consistent with the main grid line width of the gate line 01, which is 0.9mm.

[0088] Repeat the above coating and printing steps on the back side. Finally, cure the obtained cell at 200°C for 30 minutes.

[0089] Embodiment 2:

[0090] The N-type silicon wafer is cleaned and textured by chemicals, and a 3-10μm pyramid surface is formed on both sides of the silicon wafer. Amorphous silicon is deposited on the textured surface using PECVD, and an intrinsic amorphous silicon thin film layer and n-type doped amorphous silicon are deposited on the front side, and then an intrinsic amorphous silicon thin film layer and p-type doped amorphous silicon are deposited on the back side.

[0091] A first transparent conductive oxide film, an ITO film, is deposited on the front of the silicon wafer using the PVD method as TCO01. The film thickness is 30nm and the refractive index is 3.3. In order to ensure good contact between ITO and amorphous silicon, the flow rate of oxygen in the film forming process increases during the deposition of TCO01. Using the printing process, copper paste is printed on TCO01 as gate line 01. Gate line 01 includes a main gate and a fine gate. The thickness of the main gate and the fine gate are both 13μm, the width of the fine gate line is 30μm, and the width of the main gate line is 1.3mm. The battery is low-temperature baked in a nitrogen atmosphere at a temperature of 110°C for 5 minutes. The PVD method is used again to deposit the second transparent conductive oxide film and the third transparent conductive oxide film on the front side of the silicon wafer, that is, TCO02 and TCO03 are deposited in sequence. The film thickness of TCO02 and TCO03 are 20nm and 20nm respectively. The refractive index of TCO02 is 3.1, and the test square resistance is 50Ω / □. The refractive index of TCO03 is 3.01, and the test square resistance is 40Ω / □. In order to obtain good light transmittance, when depositing TCO02 and TCOO3, the amount of oxygen in the film forming process is increased in sequence compared with TCO01. After the coating of TCO01, TCO02 and TCOO3 is completed, the main gate part of the gate line 01 is grooved using a laser to expose the main gate of the gate line 01 without penetrating TCO01. Take out the battery cell, use the printing process to print silver paste on the main grid of grid line 01 as grid line 02, grid line 02 only includes the main grid, and the position of the main grid of grid line 02 is superimposed on the main grid of grid line 01, the thickness of the main grid of grid line 02 is 13μm, and the width of the main grid of grid line 02 is the same as that of the main grid of grid line 01, which is 1.3mm. The battery is low-temperature baked at a temperature of 110°C for 5 minutes.

[0092] Repeat the above coating and printing steps on the back side, and finally, cure the obtained cell at 170° C. for 45 min.

[0093] Embodiment 3:

[0094] The N-type silicon wafer is cleaned and textured by chemicals, and a 3-10μm pyramid surface is formed on both sides of the silicon wafer. Amorphous silicon is deposited on the textured surface using PECVD, and an intrinsic amorphous silicon thin film layer and n-type doped amorphous silicon are deposited on the front side, and then an intrinsic amorphous silicon thin film layer and p-type doped amorphous silicon are deposited on the back side.

[0095] A first transparent conductive oxide film, that is, an ITO film, is deposited on the front of the silicon wafer using the PVD method as TCO01, with a film thickness of 30nm and a refractive index of 3.3. A copper film is deposited on TCO01 using the PVD process and a copper target, wherein a shield is placed on the surface of the silicon wafer before depositing the copper film, and the shield is hollowed out at the position of the gate line 01, exposing the position of the gate line 01 to facilitate the deposition of the copper film, so that a copper film is formed at the position of the gate line 01, and TCO01 is still exposed after removing the shield. The formed gate line 01 includes a main gate and a fine gate, and the thickness of the main gate and the fine gate are both 5μm, the width of the fine gate line is 15μm, and the width of the main gate line is 1.5mm. The second transparent conductive oxide film and the third transparent conductive oxide film are deposited on the front of the silicon wafer by PVD method again, that is, TCO02 and TCO03 are deposited in sequence. The film thickness of TCO02 and TCO03 is 30nm and 40nm respectively. The refractive index of TCO02 is 3.1 and the test square resistance is 50Ω / □. The refractive index of TCO03 is 3.01 and the test square resistance is 40Ω / □. After the coating of TCO01, TCO02 and TCOO3 is completed, the main grid part of the gate line 01 is grooved by laser to expose the main grid of the gate line 01 without penetrating TCO01. Take out the battery cell, use the printing process to print silver paste as the gate line 02 at the main grid position of the gate line 01, the gate line 02 includes the main grid, the main grid thickness of the gate line 02 is 20μm, and the main grid line width of the gate line 02 is consistent with the main grid line width of the gate line 01, which is 1.5mm. The battery is low-temperature baked at a temperature of 110℃ for 5min.

[0096] Repeat the above coating and printing steps on the back side. Finally, cure the obtained cell at 230° C. for 8 min.

[0097] The results of the examples are compared in the following table (normalized with conventional heterojunction cells as comparative examples):

[0098] Table 1 Performance and cost test results of Example 1, Example 2 and conventional heterojunction cells

[0099]

[0100]

[0101] It can be seen from Table 1 that, taking the comparative example as the baseline standard, in the field of batteries, an increase of 20 mA in Isc, an increase of 0.1% in Eta, and a reduction of a few cents in cost are already significant changes. It can be seen that the Isc (short-circuit current) and Eta (efficiency) of Examples 1, 2, and 3 are all improved. The main reason is that the secondary reflection of the gate line increases the photocurrent, and the contact area between the gate line and the TCO film layer increases and becomes better; in addition, due to the thinning of the gate line and the use of the lower-priced AZO, especially the use of cheap silver-coated copper paste, copper paste and PVD copper plating in the gate line 01, the material cost is reduced, and the cost per watt is significantly reduced; and although the gate line uses easily oxidized copper components, the TCO film tightly wraps the metal components to reduce the influence of external water and oxygen. From the perspective of reliability, there is no obvious deterioration compared with the comparative example, but rather an improvement, which can prove that the TCO wrapping method has a protective effect on the gate line.

[0102] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are within the scope of the technical solution of the present invention.

Claims

1. A fine-grid buried-gate electrode structure for a heterojunction battery, characterized in that: It includes a dopant, a first transparent conductive oxide film disposed on the front and / or back side of the dopant, and a first metal conductive layer disposed on the surface of the first transparent conductive oxide film, wherein the first metal conductive layer includes a first fine grid and a first main grid, and the first fine grid and the first main grid are both connected to the first transparent conductive oxide film; It also includes a second metal conductive layer, the second metal conductive layer includes a second main grid, and the second main grid is attached to the first main grid; A transparent wrapping layer is disposed outside the first transparent conductive oxide film, and the first fine grid is wrapped in the transparent wrapping layer, the first main grid is exposed from the transparent wrapping layer, and the second main grid is exposed outside the transparent wrapping layer; The transparent wrapping layer includes a second transparent conductive oxide film and a third transparent conductive oxide film, wherein the second transparent conductive oxide film is formed on the first transparent conductive oxide film, and the third transparent conductive oxide film is formed on the second transparent conductive oxide film; the second transparent conductive oxide film wraps the first fine grid, the first main grid is exposed from the second transparent conductive oxide film, and the second main grid is exposed outside the second transparent conductive oxide film and outside the third transparent conductive oxide film; The total thickness of the first transparent conductive oxide film, the second transparent conductive oxide film, and the third transparent conductive oxide film is 70-130 nm; The light hits the first fine grid part, is reflected by the third transparent conductive oxide film, and then is reflected again and enters the battery; The electrode structure is used on the front side of a heterojunction battery, or on the back side of a heterojunction battery, or on both the front side and the back side.

2. The method for preparing a fine-gate buried-gate electrode structure of a heterojunction battery according to claim 1, characterized in that: The following steps are involved: Prepare the first thin film: form the first transparent conductive oxide thin film on the front side and / or the back side of the dopant; Preparing a first conductive layer: forming the first metal conductive layer on the first transparent conductive oxide film, so that the first fine grid and the first main grid are both connected to the first transparent conductive oxide film; Preparing a transparent wrapping layer: forming the transparent wrapping layer outside the first transparent conductive oxide film and exposing the first main grid; Prepare the second conductive layer: form the second metal conductive layer on the first main grid, so that one side of the second main grid is attached to and connected to the first main grid, and the other opposite side is exposed outside the transparent wrapping layer.

3. The method for preparing a fine-gate buried-gate electrode structure of a heterojunction battery according to claim 1, characterized in that: The following steps are involved: Prepare the first thin film: form the first transparent conductive oxide thin film on the front side and / or the back side of the dopant; Preparing a first conductive layer: forming the first metal conductive layer on the first transparent conductive oxide film, so that the first fine grid and the first main grid are both connected to the first transparent conductive oxide film; Preparing a transparent wrapping layer: forming the transparent wrapping layer outside the first transparent conductive oxide film; Prepare the second conductive layer: groove the transparent wrapping layer at the position of the first main grid to expose the first main grid, and form the second metal conductive layer on the first main grid so that one side of the second main grid is attached to the first main grid and the other opposite side is exposed outside the transparent wrapping layer.

4. The method for preparing a fine-grid buried-gate electrode structure of a heterojunction battery according to claim 2, characterized in that: The preparation of the transparent wrapping layer comprises the following sub-steps: Preparing a second thin film: forming the second transparent conductive oxide thin film outside the first transparent conductive oxide thin film, and exposing the first main grid; Preparing a third thin film: forming the third transparent conductive oxide thin film outside the second transparent conductive oxide thin film, and exposing the first main grid.

5. The method for preparing a fine-gate buried-gate electrode structure of a heterojunction battery according to claim 4, characterized in that: Before preparing the second film, the method further includes the following steps: placing a shielding member on the first main grid, the shielding member shielding the first main grid so that the first main grid is avoided when forming the second transparent conductive oxide film and the third transparent conductive oxide film.

6. The method for preparing a fine-gate buried-gate electrode structure of a heterojunction battery according to claim 3, characterized in that: The preparation of the transparent wrapping layer comprises the following sub-steps: Preparing a second thin film: forming the second transparent conductive oxide thin film outside the first transparent conductive oxide thin film; Preparing a third thin film: forming the third transparent conductive oxide thin film outside the second transparent conductive oxide thin film.

7. The method for preparing a fine-gate buried-gate electrode structure of a heterojunction battery according to claim 6, characterized in that: The second transparent conductive oxide film and the third transparent conductive oxide film are both formed on the entire surface.

8. The method for preparing a fine-gate buried-gate electrode structure of a heterojunction battery according to any one of claims 5 to 7, characterized in that: The thickness of the first metal conductive layer is 5-20 μm, the thickness of the second metal conductive layer is 5-20 μm, and the total thickness of the first metal conductive layer and the second metal conductive layer is 20-40 μm.

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