A high-precision and high-linearity analog-to-digital converter with low power consumption and small layout

Abstract

The present invention discloses a high-precision and high-linearity analog-to-digital converter with low power consumption and small layout. First, a digital-to-analog conversion module performs digital-to-analog conversion processing on a reference analog signal and outputs a target analog signal to the subsequent stage. Then, a sampling and comparison module and a logic control module cooperate to process the target analog signal and an initial analog signal to achieve ADC quantization. During the quantization process, a dynamic common-mode adjustment capacitor array is used to trim the common-mode voltage of the input signal pair, achieving the effect that the common-mode voltage is relatively constant during the quantization process. By setting the digital-to-analog conversion module, the present invention realizes accurate digital-to-analog conversion while achieving high-precision analog-to-digital conversion. The high linearity of the ADC is achieved by improving the linearity of the output voltage of the sampling switch and the linearity of the ADC quantization output conversion. Based on the specific circuit connection structure of the above two points, the layout area of the integrated circuit is saved, and the adaptability of the analog-to-digital converter in the aspect of the increasing integration degree of the integrated circuit is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital conversion / digital-to-analog conversion, and particularly to a high-precision and high-linearity analog-to-digital converter with low power consumption and small layout. Background Art

[0002] Traditional high-precision successive approximation analog-to-digital converters (ADCs) generally include a digital-to-analog converter, capacitors, a comparator, and a logic control module. Since they contain capacitors and most of the digital-to-analog converters inside are also in the form of capacitors, the overall structure occupies a relatively large layout area. In addition, when traditional ADCs process a pair of signals with common-mode voltage changes, the approaching voltages at the positive and negative ends of the upper plate of the capacitor will change with the common-mode voltage change of the input signal pair. The change in the common-mode voltage will affect the dynamic performance of the intermediate comparator or the intermediate-stage amplifier, and further affect the quantization residual voltage and quantization accuracy of the ADC. In addition, traditional ADCs use a binary approximation method. The capacitor array flips the voltages of the lower plates of the capacitors from large to small in sequence according to the result output by the comparator. The deviation of the capacitor ratio will seriously affect the linearity of the output signal as the input signal repeats. Summary of the Invention

[0003] Object of the Invention: In order to overcome the deficiencies in the prior art, the present invention provides a high-precision and high-linearity analog-to-digital converter with low power consumption and small layout, which can achieve accurate digital-to-analog conversion while satisfying high-precision and high-linearity analog-to-digital conversion on the premise of basically not increasing power consumption and layout area.

[0004] Technical Solution: To achieve the above object, a high-precision and high-linearity analog-to-digital converter with low power consumption and small layout of the present invention realizes high-precision analog-to-digital conversion and accurate digital-to-analog conversion through an analog-to-digital converter based on an adjustable common-mode voltage circuit. The analog-to-digital converter includes a digital-to-analog conversion module, a sampling and comparison module, a logic control module, and a capacitor trimming control module. Among them, the positive and negative end capacitor arrays of the capacitors in the sampling and comparison module both adopt a segmented reference voltage structure. Any one capacitor array includes a plurality of common-mode adjustment capacitors and a plurality of quantization capacitors. The analog-to-digital conversion based on the adjustable common-mode voltage circuit specifically includes the following steps:

[0005] Step 1, receiving an external first target control signal, a second target control signal, and a reference analog signal through the digital-to-analog conversion module: performing digital-to-analog conversion processing on the reference analog signal through the first target control signal and the second target control signal and outputting a target analog signal to the subsequent stage. Among them, the digital-to-analog conversion module includes two-stage voltage division units.

[0006] Step 2, Sampling stage: The sampling comparison module samples the external initial analog signal and the target analog signal output by the digital-to-analog conversion module, and simultaneously samples the reference common-mode voltage signal. After comparison and processing by the comparison unit, an intermediate digital signal is output to the subsequent stage;

[0007] Step 3, Quantization stage: The logic control module receives the input signal, the intermediate digital signal output by the sampling comparison module, and the external clock signal, enable signal, and initial control signal: performs logic processing on the intermediate digital signal and outputs a first digital signal and a second digital signal to the subsequent stage, and performs logic processing on the initial control signal and outputs the first target control signal and the second target control signal to the digital-to-analog conversion module, and adjusts the quantization capacitor to achieve ADC quantization;

[0008] Step 4, Common-mode voltage adjustment stage: The capacitor trimming control module receives the intermediate digital signal output by the sampling comparison module and adjusts the common-mode adjustment capacitor so that the current common-mode voltage value gradually approaches the common-mode voltage value of the reference voltage.

[0009] Further, the sampling stage in Step 2 specifically includes the following steps: First, sample the input signal through the lower plate of the full capacitor, and simultaneously sample the common-mode voltage signal of the reference voltage through the upper plate of the capacitor; after the sampling is completed, the sampling switch on the upper plate is first disconnected, and then the sampling switch on the lower plate is disconnected. C5 and C of the unilateral capacitor 5C The lower plate is connected to the high reference voltage VREF, and the other capacitors are connected to the low reference voltage GND. Among them, the least significant bit capacitor can not only operate, but also be connected to multiple proportional reference voltages.

[0010] Further, the sampling switch uses a bootstrap sampling switch, and improves the linearity of the sampling switch output voltage by changing the substrate connection to the source method, specifically by connecting a PMOS transistor in parallel at the MSW transistor.

[0011] Further, the circuit architecture design of the sampling switch: uses the arrangement design of transistors in the circuit, specifically adopts the design of bidirectional elements.

[0012] Further, the digital-to-analog conversion module includes: a first voltage division unit and a second voltage division unit connected to the first voltage division unit; the first voltage division unit includes: a first switch sub-unit, a first impedance sub-unit, and a second switch sub-unit connected in sequence; the second voltage division unit includes: a second impedance sub-unit and a third switch sub-unit connected to the second impedance sub-unit;

[0013] One end of the first impedance sub-unit is connected to the external reference analog signal, and the other end of the first impedance sub-unit is grounded; the first switch sub-unit and the second switch sub-unit are controlled by the first target control signal to perform voltage division processing on the reference analog signal to obtain a first intermediate voltage and a second intermediate voltage;

[0014] One end of the second impedance sub-unit is connected to the first intermediate voltage, and the other end of the second impedance sub-unit is connected to the second intermediate voltage; the third switch sub-unit is controlled by the second target control signal, and the difference between the first intermediate voltage and the second intermediate voltage is divided to obtain the target analog signal.

[0015] Furthermore, the first impedance subunit includes: two M resistors;

[0016] The second impedance subunit includes: 2 N resistors; wherein, M and N are both integers greater than or equal to 1, and M+N is an integer greater than or equal to 10.

[0017] Furthermore, the first switch subunit includes: M first control switches, each of the first control switches being sequentially connected to a series node between two adjacent resistors of the first impedance sub-unit;

[0018] The second switch subunit includes: M second control switches, each of the second control switches being sequentially connected to a series node between two adjacent resistors of the first impedance sub-unit;

[0019] The first control switch and the second control switch are staggered by one series node.

[0020] Furthermore, the third switch subunit includes: 2 N A third control switch is provided, and each of the third control switches is sequentially connected to a series node between two adjacent resistors of the second impedance sub-unit.

[0021] Furthermore, the comparison unit includes: a current adder, a pre-amplifier and a dynamic latch connected in sequence.

[0022] Furthermore, the analog-to-digital converter further includes: a buffer module, configured to perform buffering and adjustment on the target analog signal.

[0023] Beneficial effects: The low-power, small-size, high-precision, high-linearity analog-to-digital converter of the present invention has at least the following advantages:

[0024] (1) By setting up a digital-to-analog conversion module, high-precision analog-to-digital conversion and accurate digital-to-analog conversion are achieved simultaneously.

[0025] (2) The high linearity of the ADC is achieved by improving the linearity of the output voltage of the sampling switch and the linearity of the quantization output conversion of the ADC; specifically, by using an adjustable common-mode voltage circuit to adjust the common-mode voltage of the non-differential signal, the effect of relatively constant common-mode voltage during quantization is achieved; by adopting a capacitor array connection structure with multiple capacitors and segmented references, the linearity of the quantization output conversion of the ADC is improved without substantially increasing power consumption; by changing the substrate connection method of the bootstrap sampling switch and the design of the circuit architecture, the linearity of the output voltage of the sampling switch is improved, and at the same time, accurate judgment of the voltage level and potential is achieved.

[0026] (3) Based on the specific circuit connection structure of the above two points, the layout area of the integrated circuit is saved, and the adaptability of the analog-to-digital converter in the aspect of the increasing integration degree of the integrated circuit is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG Figure 1 is the circuit schematic diagram of a high-precision and high-linearity analog-to-digital converter with low power consumption and small layout area according to the present invention;

[0028] FIG Figure 2 is the circuit schematic diagram of the adjustable common-mode voltage circuit;

[0029] FIG Figure 3 is the simplified circuit schematic diagram of the circuit with a segmented reference voltage structure;

[0030] FIG Figure 4 is the circuit schematic diagram of a bootstrap sampling switch in the present invention;

[0031] FIG Figure 5 is the simplified schematic diagram of the principle of the digital-to-analog conversion module. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] The present invention will be further described in detail below with reference to the accompanying drawings.

[0033] As described in Figure 1 a high-precision and high-linearity analog-to-digital converter with low power consumption and small layout area, while achieving high-precision analog-to-digital conversion, accurate digital-to-analog conversion is also achieved through an analog-to-digital converter based on an adjustable common-mode voltage circuit. The analog-to-digital converter includes a digital-to-analog conversion module 1, a sampling and comparison module 2, a logic control module 3, and a capacitor trimming control module 4; wherein, the positive and negative terminal capacitor arrays of the capacitor 5 in the sampling and comparison module 2 both adopt a segmented reference voltage structure; any one of the capacitor arrays includes a plurality of common-mode adjustment capacitors and a plurality of quantization capacitors.

[0034] The analog-to-digital conversion based on the adjustable common-mode voltage circuit specifically includes the following steps:

[0035] Step 1: Receive the external first target control signal, second target control signal, and reference analog signal through the digital-to-analog conversion module 1: Perform digital-to-analog conversion processing on the reference analog signal through the first target control signal and the second target control signal and output a target analog signal to the subsequent stage; wherein, the digital-to-analog conversion module includes two-stage voltage division units.

[0036] Step 2: Sampling stage: Sample the external initial analog signal and the target analog signal output by the digital-to-analog conversion module 1 through the sampling and comparison module 2, and simultaneously sample the reference common-mode voltage signal, perform comparison processing through the comparison unit 6, and output an intermediate digital signal to the subsequent stage.

[0037] Step 3: Quantization stage: Receive the input signal, the intermediate digital signal output by the sampling and comparison module 2, and the external clock signal, enable signal, and initial control signal through the logic control module 3: Perform logic processing on the intermediate digital signal and output a first digital signal and a second digital signal to the subsequent stage, and perform logic processing on the initial control signal and output the first target control signal and the second target control signal to the digital-to-analog conversion module 1, and adjust the quantization capacitor to achieve ADC quantization.

[0038] Step 4: Common-mode voltage adjustment stage: Receive the intermediate digital signal output by the sampling and comparison module 2 through the capacitor trimming control module 4, and adjust the common-mode adjustment capacitor so that the current common-mode voltage value gradually approaches the common-mode voltage value of the reference voltage.

[0039] As shown in Figure 2 a schematic diagram of an embodiment, the positive and negative terminal capacitor arrays of the capacitor are respectively used to receive the external initial analog signal and the target analog signal output by the digital-to-analog conversion module 1, marked as VINP and VINN here. Both the positive and negative terminal capacitor arrays include a single-column quantization capacitor 52 / 53 and a single-column common-mode adjustment capacitor 51 / 54. The quantization capacitor is used to achieve the normal ADC quantization process, and the common-mode adjustment capacitor is used to adjust the current common-mode voltage to gradually approach the common-mode voltage of the reference voltage. The common-mode voltage of the reference voltage is marked as VCM in the figure.

[0040] The sampling stage in Step 2 specifically includes the following steps: First, sample the input signal through the lower plate of the full capacitor, and simultaneously sample the common-mode voltage signal of the reference voltage through the upper plate of the capacitor; after the sampling is completed, the sampling switch 4 on the upper plate is first disconnected, and then the sampling switch 4 on the lower plate is disconnected. The C of the single-sided capacitor n and C nCThe lower plate of the capacitor is connected to the high reference voltage VREF, and the other capacitor is connected to the low reference voltage GND. According to the law of conservation of charge, at this time, the input voltages VP and VN at both ends of the comparator are VREF - VINP and VREF - VINN respectively. Subsequently, the capacitor trimming control circuit will extract the common-mode voltage of the upper plate of the capacitor, and by adjusting the common-mode adjustment capacitors on both sides, gradually approximate the current common-mode voltage to the VCM voltage. After the common-mode adjustment of the input signal is completed, the normal ADC quantization process begins; it can solve the non-linear error introduced by the common-mode voltage deviation in the process of high-precision ADC design. Of course, the above action logic is not limited to the content of this embodiment figure. Its essence is to extract part of the capacitor in the quantization capacitor to adjust the successively approximated common-mode voltage, and the common-mode adjustment stage is not limited to being carried out immediately after the sampling ends. This debugging process can be carried out at any stage during the quantization process.

[0041] As shown in the appendix Figure 3 In an embodiment as described above, the least significant bit capacitor can not only operate, but also be connected to multiple proportional reference voltages nVREF. Then VCM = (VREF + nVREF) / 2, where n ∈ U, 1 > n ≥ 0, and U is the set of proportional numbers. In the figure, U = {0.75, 0.5, 0.25, 0}. Based on the action logic of the traditional binary approximation method, the effective flipping achieved by the second largest capacitor can only be 0.25VREF or 0. However, when based on the multi-capacitor multi-reference analog-to-digital converter structure, the flipping of the largest capacitor can be 0.5VREF, 0.375VREF, 0.25VREF, 0.125VREF, and 0. Therefore, when a voltage flip of 0.25VREF is required, the voltage of the lower plate of the largest capacitor can be flipped, rather than only the second largest capacitor. Based on this action method, to a certain extent, the correlation between the input signal and the capacitor array error is disrupted, which plays a role in improving the linearity of the ADC quantization output.

[0042] The sampling switch 4 adopts a bootstrap sampling switch to improve the linearity of the sampling switch output voltage by changing the substrate connection to the source method. Specifically, as Figure 4 shown, a PMOS transistor is connected in parallel at the MSW transistor to reduce the impedance. In the figure, M1, M2, M4, C1, M6, and M5 form a gate voltage bootstrap circuit, M9 and M3 are charge discharge paths, M7 and MSW are sampling switch transistors, and the formula for the sum of resistors in parallel:

[0043]

[0044] On the basis of ensuring the stability of the working transistor without changing the substrate grounding state, the linearity of the sampling switch output voltage can be greatly improved, resulting in the resistance hardly changing with the input voltage.

[0045] Circuit architecture design of the sampling switch 4: A relatively simple circuit architecture is adopted, mainly using the arrangement design architecture of transistors in the circuit. Specifically, a bidirectional element design is used, which can simultaneously generate corresponding resistance values and the function of an inverter to accurately judge the voltage level and potential.

[0046] As shown in the appendix Figure 5 The digital-to-analog conversion module includes: a first voltage division unit 1-1 and a second voltage division unit 1-2 connected to the first voltage division unit 1-1; the first voltage division unit 1-1 includes: a first switch sub-unit 1-11, a first impedance sub-unit 1-12, and a second switch sub-unit 1-13 connected in sequence; the second voltage division unit 1-2 includes: a second impedance sub-unit 1-21 and a third switch sub-unit 1-22 connected to the second impedance sub-unit 1-21;

[0047] Among them, one end of the first impedance sub-unit 1-12 is connected to the external reference analog signal, and the other end of the first impedance sub-unit 1-12 is grounded; the first switch sub-unit 1-11 and the second switch sub-unit 1-13 are controlled by the first target control signal to perform voltage division processing on the reference analog signal to obtain a first intermediate voltage and a second intermediate voltage;

[0048] One end of the second impedance sub-unit 1-21 is connected to the first intermediate voltage, and the other end of the second impedance sub-unit 1-21 is connected to the second intermediate voltage; the third switch sub-unit 1-22 is controlled by the second target control signal to perform voltage division processing on the difference between the first intermediate voltage and the second intermediate voltage to obtain the target analog signal.

[0049] The first impedance sub-unit 1-12 includes: 2 M resistors connected in series;

[0050] The second impedance sub-unit 1-21 includes: 2 N resistors connected in series;

[0051] Among them, both M and N are integers greater than or equal to 1, and M + N is an integer greater than or equal to 10.

[0052] The first switch sub-unit 1-11 includes: 2 M first control switches, and each of the first control switches is respectively connected to the series node between two adjacent

[0053] resistors of the first impedance sub-unit 1-12; Msecond control switches, each of the second control switches being sequentially connected to a series node between two adjacent resistors of the first impedance sub-units 1-12;

[0054] The first control switch and the second control switch are staggered by one series node.

[0055] The third switch subunit 1-22 includes: N third control switches, each of the third control switches is sequentially connected to a series node between two adjacent resistors of the second impedance sub-unit 1 - 21 .

[0056] The comparison unit 6 includes: a current adder, a pre-amplifier and a dynamic latch connected in sequence.

[0057] The analog-to-digital converter further includes a buffer module 7 , the input end of which is connected to the output end of the digital-to-analog conversion module 1 , for buffering and regulating the target analog signal.

[0058] The above description is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the above principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A high-precision and high-linearity analog-to-digital converter with low power consumption and small layout, characterized in that: While achieving high-precision analog-to-digital conversion through an analog-to-digital converter based on an adjustable common-mode voltage circuit, precise digital-to-analog conversion is also realized. The analog-to-digital converter includes a digital-to-analog conversion module (1), a sampling and comparison module (2), a logic control module (3), and a capacitor trimming control module (4); wherein, the positive and negative terminal capacitor arrays of the capacitor (5) in the sampling and comparison module (2) both adopt a circuit structure with segmented reference voltages; any one of the capacitor arrays includes a plurality of common-mode adjustment capacitors and a plurality of quantization capacitors; The analog-to-digital conversion based on the adjustable common-mode voltage circuit specifically includes the following steps: Step 1, receive the external first target control signal, second target control signal, and reference analog signal through the digital-to-analog conversion module (1): Through the first target control signal and the second target control signal, perform digital-to-analog conversion processing on the reference analog signal and output a target analog signal to the subsequent stage; wherein, the digital-to-analog conversion module includes two-stage voltage division units; Step 2, sampling stage: Sample the external initial analog signal and the target analog signal output by the digital-to-analog conversion module (1) through the sampling and comparison module (2), and at the same time sample the reference common-mode voltage signal, perform comparison processing through the comparison unit (6), and output an intermediate digital signal to the subsequent stage; Step 3, quantization stage: Receive the input signal through the logic control module (3), the intermediate digital signal output by the sampling and comparison module (2), and the external clock signal, enable signal, and initial control signal: Perform logic processing on the intermediate digital signal and output a first digital signal and a second digital signal to the subsequent stage, and perform logic processing on the initial control signal and output the first target control signal and the second target control signal to the digital-to-analog conversion module (1), and adjust the quantization capacitors to achieve ADC quantization; Step 4, common-mode voltage adjustment stage: Receive the intermediate digital signal output by the sampling and comparison module (2) through the capacitor trimming control module (4), and adjust the common-mode adjustment capacitors so that the current common-mode voltage value gradually approaches the common-mode voltage value of the reference voltage.

2. The high-precision and high-linearity analog-to-digital converter with low power consumption and small layout according to claim 1, wherein: The sampling stage in step two specifically includes the following steps: First, sample the input signal through the sampling of the lower plate of the fully capacitive structure, and simultaneously sample the common-mode voltage signal of the reference voltage through the upper plate of the capacitor; after sampling, the sampling switch on the upper plate is first disconnected, and then the sampling switch on the lower plate is disconnected. C5 and C of the single-sided capacitor 5C The lower plate is connected to the high reference voltage VREF, and the other capacitors are connected to the low reference voltage GND. Among them, the least significant bit capacitor can not only operate, but also be connected to multiple proportional reference voltages.

3. A high-precision and high-linearity analog-to-digital converter with low power consumption and small layout area according to claim 2, characterized in that: The sampling switch adopts a bootstrap sampling switch, and improves the linearity of the sampling switch output voltage by changing the substrate connection to the source method, specifically by connecting a PMOS transistor in parallel at the MSW transistor.

4. The high-precision and high-linearity analog-to-digital converter with low power consumption and small layout according to claim 3, characterized in that: The circuit architecture design of the sampling switch: Utilize the arrangement design architecture of the transistors in the circuit, specifically adopt the design of a bidirectional element.

5. A high-precision and high-linearity analog-to-digital converter with low power consumption and small layout area according to claim 1, characterized in that: The digital-to-analog conversion module includes: a first voltage division unit and a second voltage division unit connected to the first voltage division unit; the first voltage division unit includes: a first switch sub-unit, a first impedance sub-unit, and a second switch sub-unit connected in sequence; the second voltage division unit includes: a second impedance sub-unit and a third switch sub-unit connected to the second impedance sub-unit; Wherein, one end of the first impedance sub-unit is connected to the external reference analog signal, and the other end of the first impedance sub-unit is grounded; Control the first switch sub-unit and the second switch sub-unit through the first target control signal to perform voltage division processing on the reference analog signal to obtain a first intermediate voltage and a second intermediate voltage; One end of the second impedance sub-unit is connected to the first intermediate voltage, and the other end of the second impedance sub-unit is connected to the second intermediate voltage; the third switching sub-unit is controlled by the second target control signal to perform voltage division on the difference between the first intermediate voltage and the second intermediate voltage to obtain the target analog signal.

6. The high-precision and high-linearity analog-to-digital converter with low power consumption and small layout according to claim 5, characterized in that: The first impedance sub-unit includes: two resistors connected in series in sequence; M ​ The second impedance sub-unit includes: two resistors connected in series in sequence; where M and N are both integers greater than or equal to 1, and M + N is an integer greater than or equal to 10. N ​ 7. A high-precision and high-linearity analog-to-digital converter with low power consumption and small layout area according to claim 6, characterized in that: The first switching sub-unit includes: 2 M first control switches, each of the first control switches is respectively and sequentially connected to a series node between two adjacent resistors of the first impedance sub-unit; The second switching subunit includes: 2 M second control switches, and each of the second control switches is respectively and sequentially connected to a series node between two adjacent resistors of the first impedance subunit; Wherein, there is a stagger of one series node between the first control switch and the second control switch.

8. A high-precision and high-linearity analog-to-digital converter with low power consumption and small layout area according to claim 7, characterized in that: The third switch sub-unit includes: 2 N third control switches, each of the third control switches is sequentially connected to a series node between two adjacent resistors of the second impedance sub-unit.

9. The high-precision and high-linearity analog-to-digital converter with low power consumption and small layout area according to claim 1, characterized in that: The comparison unit (6) includes: a current adder, a pre-amplifier and a dynamic latch which are connected in sequence.

10. A high-precision and high-linearity analog-to-digital converter with low power consumption and small layout area according to claim 1, characterized in that: The analog-to-digital converter further includes a buffer module (7) for buffering and adjusting the target analog signal.

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