Array substrate and manufacturing method thereof, and display panel

Abstract

The present invention provides an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes at least one low-temperature polysilicon thin-film transistor (LTPS) and at least one oxide thin-film transistor (OTT). The LTPS includes an active layer and a first gate electrode, while the oxide thin-film transistor includes an oxide semiconductor layer, a second source electrode, and a second drain electrode. The first gate electrode, the second source electrode, and the second drain electrode are provided in the same layer, while the active layer and the oxide semiconductor layer are provided in different layers. The present invention simplifies the manufacturing process by using the same photomask to manufacture the gate electrode of the LTPS OT and the source electrode and drain electrode of the oxide thin-film transistor.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, and a display panel. Background Art

[0002] Actively driven self-luminous displays such as OLED, Micro LED, and Mini LED generally require more than two thin-film transistors for their driving substrates to control the display state of a single pixel, such as the common 2T1C circuit or 3T1C circuit. On the other hand, with the rapid development of 5G and the Internet of Things (LOT), the application scenarios of mobile terminals have become more diversified. For display panels, reducing the display refresh frequency under non-essential high refresh frequency conditions can effectively reduce display power consumption. The current mainstream high-resolution self-luminous displays are mainly low-temperature polycrystalline silicon thin-film transistors, which are characterized by high mobility and high leakage current. The high leakage current keeps the driving power consumption high. In the pixel circuit, if the transistor that controls the capacitor point is replaced with a transistor with low current characteristics, and the transistor that drives the pixel light emission remains a high-mobility transistor, the refresh frequency of the pixel can be reduced without flickering. Reducing the refresh frequency can effectively reduce the driving power consumption.

[0003] However, the existing hybrid pixel structure of low-temperature polysilicon and oxide thin-film transistors requires a large number of photomasks and complex processes. To save on photomasks, some existing technologies manufacture both thin-film transistors in the same process, placing the low-temperature polysilicon active layer and the oxide semiconductor layer on the same layer. This can cause the high temperature of the laser annealing process during the manufacturing process to affect the electrical characteristics of one of the thin-film transistors. In particular, the oxide semiconductor layer in the oxide thin-film transistor is sensitive to the external environment. Under the influence of factors such as temperature and light, additional carriers will be induced inside and migrate under the action of the electric field, which will change the performance of the device. The most important parameter shift is the threshold voltage.

[0004] Therefore, it is necessary to provide a solution to solve the above problems. Summary of the Invention

[0005] The present invention provides an array substrate and a manufacturing method thereof, and a display panel, which can solve the technical problem of complex manufacturing process of an array substrate with a mixed structure of low-temperature polysilicon and oxide thin film transistors in the prior art.

[0006] To solve the above problems, the present invention provides the following technical solutions:

[0007] An embodiment of the present invention provides an array substrate, comprising at least one low-temperature polysilicon thin film transistor and at least one oxide thin film transistor;

[0008] The low-temperature polysilicon thin film transistor includes an active layer and a first gate electrode, and the oxide thin film transistor includes an oxide semiconductor layer, a second source electrode, and a second drain electrode;

[0009] The first gate electrode, the second source electrode, and the second drain electrode are arranged in the same layer, and the active layer and the oxide semiconductor layer are arranged in different layers.

[0010] Optionally, in some embodiments of the present invention, the array substrate further includes a base, and the low-temperature polysilicon thin film transistor and the oxide thin film transistor are both disposed on the base;

[0011] The first gate is located on a side of the active layer away from the substrate, and the second source and the second drain are located on a side of the oxide semiconductor layer close to the substrate.

[0012] Optionally, in some embodiments of the present invention, the low-temperature polysilicon thin film transistor further includes a first source electrode and a first drain electrode located on a side of the active layer close to the substrate, the active layer being electrically connected to the first source electrode through a first via hole, and the active layer being electrically connected to the first drain electrode through a second via hole;

[0013] The oxide thin film transistor further includes a second gate located on a side of the oxide semiconductor layer away from the substrate. The oxide semiconductor layer is electrically connected to the second source through a third via hole, and the oxide semiconductor layer is electrically connected to the second drain through a fourth via hole.

[0014] Optionally, in some embodiments of the present invention, the orthographic projection of the second source electrode on the substrate overlaps with the orthographic projection of the first drain electrode on the substrate, and the orthographic projection of the second source electrode on the substrate is spaced apart from the orthographic projection of the first gate electrode on the substrate.

[0015] Optionally, in some embodiments of the present invention, the second source is located between the first gate and the second drain, the orthographic projection of the oxide semiconductor layer on the substrate overlaps with the orthographic projection of the active layer on the substrate, and the orthographic projection of the oxide semiconductor layer on the substrate is spaced from the orthographic projection of the first source on the substrate.

[0016] Optionally, in some embodiments of the present invention, the oxide semiconductor layer includes a channel region corresponding to the second gate and a conductor region located on both sides of the channel region, the orthographic projection of the conductor region on the substrate covers the orthographic projection of the first gate on the substrate, wherein a capacitor is formed between the conductor region and the first gate.

[0017] An embodiment of the present invention further provides a display panel, comprising the array substrate described above.

[0018] The present invention also provides a method for manufacturing an array substrate, comprising the following steps:

[0019] providing a substrate;

[0020] Fabricating at least one low-temperature polysilicon thin film transistor and at least one oxide thin film transistor on the substrate, wherein the low-temperature polysilicon thin film transistor includes an active layer and a first gate electrode, and the oxide thin film transistor includes an oxide semiconductor layer, a second source electrode, and a second drain electrode;

[0021] The active layer and the oxide semiconductor layer are arranged in different layers, and the first gate, the second source and the second drain are made by using the same photomask.

[0022] Optionally, in some embodiments of the present invention, the step of fabricating at least one low-temperature polysilicon thin film transistor and at least one oxide thin film transistor on the substrate includes:

[0023] forming a first metal layer and a first insulating layer in sequence on the substrate, wherein the first metal layer includes a first source electrode and a first drain electrode spaced apart from each other, and a first via hole exposing the first source electrode and a second via hole exposing the first drain electrode are formed on the first insulating layer;

[0024] An active layer, a second insulating layer, and a second metal layer are sequentially formed on the first insulating layer, wherein the active layer includes a first channel region and first conductor regions located on both sides of the first channel region, the first conductor region is electrically connected to the first source electrode through the first via hole, and the first conductor region is electrically connected to the first drain electrode through the second via hole, and the second metal layer includes a first gate electrode, a second source electrode, and a second drain electrode spaced apart from each other, and the first gate electrode corresponds to the first channel region;

[0025] forming a third insulating layer, an oxide semiconductor layer, a fourth insulating layer, and a second gate electrode in sequence on the second metal layer, wherein a third via hole exposing the second source electrode and a fourth via hole exposing the second drain electrode are formed on the third insulating layer, the oxide semiconductor layer includes a second channel region and second conductor regions located on both sides of the second channel region, the second conductor region is electrically connected to the second source electrode through the third via hole, the second conductor region is electrically connected to the second drain electrode through the fourth via hole, and the second gate electrode corresponds to the second channel region;

[0026] The first source, the first drain, the active layer and the first gate constitute a low-temperature polysilicon thin film transistor, and the second source, the second drain, the oxide semiconductor layer and the second gate constitute an oxide thin film transistor.

[0027] Optionally, in some embodiments of the present invention, the orthographic projection of the second source electrode on the substrate overlaps with the orthographic projection of the first drain electrode on the substrate;

[0028] Wherein, after forming the active layer on the first insulating layer and before forming the second insulating layer and the second metal layer, the manufacturing method further includes the following steps:

[0029] An ion doping treatment is performed on the region of the active layer to be conductive to form the first conductive region.

[0030] The beneficial effects of the present invention are as follows: the array substrate and its manufacturing method, and the display panel provided by the present invention use the same mask to manufacture the gate of the low-temperature polysilicon thin film transistor and the source and drain of the oxide thin film transistor, thereby achieving partial sharing of film layers and simplifying the manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 is a structural diagram of an array substrate provided in Embodiment 1 of the present invention;

[0033] Figure 2 is a structural diagram of an array substrate provided in a second embodiment of the present invention;

[0034] Figure 3 is a structural diagram of an array substrate provided in a third embodiment of the present invention;

[0035] Figure 4 is a flow chart of a method for manufacturing an array substrate provided in Embodiment 1 of the present invention;

[0036] Figures 5A-5I Schematic diagram of the manufacturing process of the array substrate provided in the first embodiment of the present invention. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0038] See also Figure 1-Figure 3 The present invention provides an array substrate comprising at least one low-temperature polysilicon thin-film transistor (T1) and at least one oxide thin-film transistor (T2). The low-temperature polysilicon thin-film transistor (T1) comprises an active layer 15 and a first gate electrode 17, and the oxide thin-film transistor (T2) comprises an oxide semiconductor layer 21, a second source electrode 18, and a second drain electrode 19. The first gate electrode 17, the second source electrode 18, and the second drain electrode 19 are disposed in the same layer, and the active layer 15 and the oxide semiconductor layer 21 are disposed in different layers.

[0039] In the embodiment of the present invention, the first gate 17 of the low-temperature polysilicon thin-film transistor T1 and the second source 18 and the second drain 19 of the oxide thin-film transistor T2 are arranged in the same layer. During the manufacturing process, only one photomask process is needed to simultaneously form the first gate 17 of the low-temperature polysilicon thin-film transistor T1 and the second source 18 and the second drain 19 of the oxide thin-film transistor T2. Compared with the traditional structure in which the low-temperature polysilicon thin-film transistor and the oxide thin-film transistor are manufactured separately, the embodiment of the present invention can save at least one photomask process and simplify the process.

[0040] The array substrate of the present invention is described in detail below with reference to specific embodiments, and is specifically explained as follows.

[0041] See also Figure 1 , Figure 1 : is a schematic structural diagram of an array substrate provided in Embodiment 1 of the present invention. The array substrate includes a substrate 11 and at least one low-temperature polycrystalline silicon thin-film transistor T1 and at least one oxide thin-film transistor T2 disposed on the substrate 11. The substrate 11 can be either a rigid substrate or a flexible substrate, which is not limited here. The array substrate also includes an inorganic stacked layer 110 disposed on the substrate 11, with at least one low-temperature polycrystalline silicon thin-film transistor T1 and at least one oxide thin-film transistor T2 located in the inorganic stacked layer 110.

[0042] The inorganic stacked layer 110 includes a first insulating layer 14 , a second insulating layer 16 , a third insulating layer 20 , a fourth insulating layer 22 and a fifth insulating layer 24 stacked from bottom to top, but the present invention is not limited thereto.

[0043] As an embodiment, the first insulating layer 14 may be a buffer layer, the second insulating layer 16 may be a first gate insulating layer, the third insulating layer 20 may be an interlayer insulating layer, the fourth insulating layer 22 may be a second gate insulating layer, and the fifth insulating layer 24 may be a passivation layer.

[0044] In this embodiment, both the low-temperature polysilicon thin-film transistor T1 and the oxide thin-film transistor T2 have a top-gate structure. The low-temperature polysilicon thin-film transistor T1 further includes a first source electrode 12 and a first drain electrode 13 located on a side of the active layer 15 close to the substrate 11. The oxide thin-film transistor T2 further includes a second gate electrode 23 located on a side of the oxide semiconductor layer 21 away from the substrate 11.

[0045] Specifically, the first source electrode 12 and the first drain electrode 13 are disposed on the substrate 11 with an interval therebetween. The first insulating layer 14 is disposed on the first source electrode 12, the first drain electrode 13, and the substrate 11. The active layer 15 is disposed on the first insulating layer 14. The active layer 15 is electrically connected to the first source electrode 12 via a first via hole penetrating the first insulating layer 14. The active layer 15 is electrically connected to the first drain electrode 13 via a second via hole penetrating the first insulating layer 14. The active layer 15 includes a first channel region 152 and first conductor regions 151 located on both sides of the first channel region 152. The second insulating layer 16 is disposed on the active layer 15 and the first insulating layer 14. The first gate 17, the second source 18, and the second drain 19 are disposed on the same layer and spaced apart from each other on the second insulating layer 16. The second insulating layer 16 includes insulating layer patterns corresponding to the first gate 17, the second source 18, and the second drain 19, respectively. The first gate 17, the second source 18, and the second drain 19 form a stacked structure with the corresponding insulating layer patterns. The third insulating layer 20 is entirely disposed on the first gate 17, the second source 18, and the second drain 19. The oxide semiconductor layer 21 is disposed on the third insulating layer 20 and is electrically connected to the second source 18 via a third via extending through the third insulating layer 20. The oxide semiconductor layer 21 is electrically connected to the second drain 19 via a fourth via extending through the third insulating layer 20. The oxide semiconductor layer 21 includes a second channel region 211 and second conductor regions 212 located on either side of the second channel region 211. The fourth insulating layer 22 and the second gate electrode 23 are stacked on the oxide semiconductor layer 21 corresponding to the second channel region 211. The fifth insulating layer 24 is entirely disposed on the second gate electrode 23.

[0046] In this embodiment, since the oxide semiconductor layer 21 is located on a film layer above the active layer 15, on the one hand, it can prevent the dopant ions from entering the oxide semiconductor layer 21 when the active layer 15 is doped, thereby reducing the electrical stability of the oxide thin film transistor T2. On the other hand, it can prevent the amorphous silicon of the active layer 15 from affecting the crystallinity of the oxide semiconductor layer 21 when it is converted into polycrystalline silicon through a laser annealing process. Therefore, the embodiment of the present invention can achieve the goal of simplifying the process while taking into account the electrical stability of the device. In addition, the oxide thin film transistor T2 adopts the form of contacting the bottom of the oxide semiconductor layer 21 with the top of the second source 18 and the second drain 19, which saves the process of making an interlayer insulating layer (ILD) on the oxide semiconductor layer in the traditional structure. Since the interlayer insulating layer is generally made by CVD process, the high temperature of the CVD process will affect the crystallinity of the oxide semiconductor. However, the thin film transistor of the present invention adopts this structural design, which can further improve the electrical stability of the device. Furthermore, in this embodiment, the oxide semiconductor layer 21 is located above the third insulating layer (ie, the interlayer insulating layer) 20 , so the high temperature of the CVD process of the third insulating layer will not affect the stability of the device.

[0047] It is understandable that in other embodiments, other conventional film layers, such as a light shielding layer, etc., may be included between the substrate 11 and the first source electrode 12 and the first drain electrode 13, which is not limited here.

[0048] Furthermore, the array substrate further includes a pixel electrode 25, which is disposed on the fifth insulating layer 24 and electrically connected to the first source electrode 12 of the low-temperature polysilicon thin-film transistor T1 via a fifth via hole extending through the fifth insulating layer 24 and the third insulating layer 20. The low-temperature polysilicon thin-film transistor T1 can function as a driving thin-film transistor, having high mobility, which can reduce driving voltage and achieve high refresh rates and high resolutions. The oxide thin-film transistor T2 can function as a switching thin-film transistor, having low leakage current, which can enable the display panel to maintain good display quality at low frame rates and reduce power consumption.

[0049] See also Figure 2 , Figure 2It is a structural schematic diagram of the array substrate provided in the second embodiment of the present invention. The array substrate includes a substrate 11 and at least one low-temperature polycrystalline silicon thin film transistor T1 and at least one oxide thin film transistor T2 arranged on the substrate 11. The array substrate also includes an inorganic stacking layer 110 arranged on the substrate 11, and at least one low-temperature polycrystalline silicon thin film transistor T1 and at least one oxide thin film transistor T2 are located in the inorganic stacking layer 110. Among them, the structural composition of the low-temperature polycrystalline silicon thin film transistor T1, the oxide thin film transistor T2 and the inorganic stacking layer 110 is the same as that in the above-mentioned embodiment one. Please refer to the description in the above-mentioned embodiment one for details, and no further details will be given here. The difference between this embodiment and the above-mentioned embodiment one is that the low-temperature polycrystalline silicon thin film transistor T1 and the oxide thin film transistor T2 in the array substrate of this embodiment partially overlap in the direction perpendicular to the array substrate, thereby reducing the space occupied by the thin film transistor and increasing the pixel aperture ratio.

[0050] Specifically, the orthographic projection of the second source electrode 18 of the oxide thin film transistor T2 on the substrate 11 overlaps with the orthographic projection of the first drain electrode 13 of the low-temperature polysilicon thin film transistor T1 on the substrate 11 .

[0051] Furthermore, the orthographic projection of the second source electrode 18 on the substrate 11 is spaced apart from the orthographic projection of the first gate electrode 17 on the substrate 11. In addition, since the second source electrode 18 is separated from the active layer 15 of the low-temperature poly-silicon thin-film transistor T1 by the second insulating layer 16, this design does not affect the performance of the low-temperature poly-silicon thin-film transistor T1 and the oxide thin-film transistor T2.

[0052] Furthermore, in one embodiment, the orthographic projection of the oxide semiconductor layer 21 of the oxide thin film transistor T2 on the substrate 11 overlaps with the orthographic projection of the active layer 15 on the substrate 11 and is spaced apart from the orthographic projection of the first gate 17 on the substrate 11.

[0053] The orthographic projection of the second source electrode 18 on the substrate 11 partially overlaps or completely overlaps with the orthographic projection of the first drain electrode 13 on the substrate 11. A direction parallel to the array substrate is a first direction, and a direction perpendicular to the array substrate is a second direction. Since the low-temperature polysilicon thin-film transistor T1 and the oxide thin-film transistor T2 overlap in the second direction, the spatial proportion of the low-temperature polysilicon thin-film transistor T1 and the oxide thin-film transistor T2 in the first direction can be reduced, thereby providing more space for the pixel opening and increasing the aperture ratio. Therefore, this embodiment can achieve the effect of increasing the pixel aperture ratio while simplifying the manufacturing process and improving the electrical stability of the device.

[0054] See also Figure 3 , Figure 3 is a schematic diagram of the structure of an array substrate provided in Embodiment 3 of the present invention. The array substrate of this embodiment includes a substrate 11 and an inorganic stacked layer 110 disposed on the substrate 11, and further includes at least one low-temperature polycrystalline silicon thin-film transistor T1 and at least one oxide thin-film transistor T2 disposed in the inorganic stacked layer 110. The structural composition of the low-temperature polycrystalline silicon thin-film transistor T1, the oxide thin-film transistor T2, and the inorganic stacked layer 110 is the same as that of the above-mentioned Embodiments 1 and 2. For details, please refer to the description of the above-mentioned Embodiments 1 and 2, and will not be repeated here.

[0055] The difference between this embodiment and the above-mentioned embodiment 2 is that: the orthographic projection of the oxide semiconductor layer 21 of the oxide thin film transistor T2 of this embodiment on the substrate 11 overlaps with the orthographic projection of the first gate 17 of the low-temperature polycrystalline silicon thin film transistor T1 on the substrate 11, and the orthographic projection of the oxide semiconductor layer 21 on the substrate 11 is spaced from the orthographic projection of the first source 12 of the low-temperature polycrystalline silicon thin film transistor T1 on the substrate 11.

[0056] The orthographic projection of the first gate 17 on the substrate 11 falls within the range of the orthographic projection of the oxide semiconductor layer 21 on the substrate 11. Specifically, the oxide semiconductor layer 21 includes a second channel region 211 corresponding to the second gate 23 and second conductor regions 212 located on both sides of the second channel region 211. The orthographic projection of the second conductor region 212 on the substrate 11 covers the orthographic projection of the first gate 17 on the substrate 11. A capacitor is formed between the second conductor region 212 and the first gate 17.

[0057] In addition to the advantages of the array substrates in the first and second embodiments, the array substrate of this embodiment further reduces a separate capacitor manufacturing process by extending the second conductor region 212 of the oxide semiconductor layer 21 and forming a capacitor with the first gate 17. In addition, the capacitor formed by the second conductor region 212 and the first gate 17 does not require additional space, which is beneficial for increasing the aperture ratio of the pixel.

[0058] An embodiment of the present invention further provides a display panel, comprising the array substrate described above, wherein the display panel can be selected from, but not limited to, an LCD display panel, an OLED display panel, a Mini-LED display panel, or a Micro-LED display panel.

[0059] The present invention also provides a method for manufacturing an array substrate. Figure 4 and Figures 5A-5I , the production method comprises the following steps:

[0060] Step 1: providing a substrate 11.

[0061] The substrate 11 may be a glass substrate or a flexible substrate.

[0062] Step 2: Fabricate at least one low-temperature polycrystalline silicon thin film transistor T1 and at least one oxide thin film transistor T2 on the substrate 11, wherein the low-temperature polycrystalline silicon thin film transistor T1 includes an active layer 15 and a first gate electrode 17, and the oxide thin film transistor T2 includes an oxide semiconductor layer 21, a second source electrode 18, and a second drain electrode 19; wherein the active layer 15 and the oxide semiconductor layer 21 are arranged in different layers, and the first gate electrode 17, the second source electrode 18, and the second drain electrode 19 are fabricated using the same photomask.

[0063] Specifically, the step of manufacturing at least one low-temperature polysilicon thin film transistor T1 and at least one oxide thin film transistor T2 on the substrate 11 in step 2 includes:

[0064] Step S1, such as Figures 5A-5B As shown, a first metal layer (12, 13) and a first insulating layer 14 are sequentially formed on the substrate 11, the first metal layer (12, 13) includes a first source 12 and a first drain 13 spaced apart from each other, and a first via 100 exposing the first source 12 and a second via 200 exposing the first drain 13 are formed on the first insulating layer 14.

[0065] Specifically, a first metal film is formed on the substrate 11, and a patterned first source electrode 12 and a first drain electrode 13 are formed by a first photomask process. A first insulating layer 14 is formed entirely on the first source electrode 12 and the first drain electrode 13, and a first via hole 100 and a second via hole 200 are formed on the first insulating layer 14 through the second photomask process.

[0066] The first metal layers (12, 13) may be single layers of Mo, Al, or Ti; or may be stacked layers of Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, or Mo / Cu / ITO. The first metal layers (12, 13) may be fabricated by physical vapor sputtering deposition, and the first source electrode 12 and the first drain electrode 13 may be formed by an etching process.

[0067] Step S2, such as Figures 5C-5D As shown, an active layer 15, a second insulating layer 16 and a second metal layer (17, 18, 19) are sequentially formed on the first insulating layer 14, the active layer 15 includes a first channel region 152 and first conductor regions 151 located on both sides of the first channel region 152, the first conductor region 151 is electrically connected to the first source 12 through the first via 100, and the first conductor region 151 is electrically connected to the first drain 13 through the second via 200, the second metal layer (17, 18, 19) includes a first gate 17, a second source 18 and a second drain 19 spaced apart, and the first gate 17 corresponds to the first channel region 152.

[0068] Specifically, an amorphous silicon film is formed on the first insulating layer 14, a patterned amorphous silicon pattern is formed through a third photomask process, and an active layer 15 made of polycrystalline silicon is obtained through a laser annealing crystallization method. After the active layer 15 is formed, a second insulating film and a second metal film are continuously deposited on the active layer 15, and the second insulating film and the second metal film are patterned through a fourth photomask process to form a stacked second metal layer (17, 18, 19) and a second insulating pattern 16'. Thereafter, using the first gate 17 and the second insulating pattern 16' corresponding to the first gate 17 as masks, the portion of the active layer 15 not covered by the second insulating pattern 16' is doped to form the first conductor region 151. Specifically, phosphorus ions can be doped to form N-type heavy doping or N-light doping, or boron ions can be doped to form P-type heavy doping to produce an NMOS or PMOS transistor.

[0069] Among them, the material of the second metal layer (17, 18, 19) can be a single film layer such as Mo, Al or Ti; it can also be a stacked structure such as Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO or Mo / Cu / ITO.

[0070] Step S3, such as Figures 5E-5GAs shown, a third insulating layer 20, an oxide semiconductor layer 21, a fourth insulating layer 22 and a second gate 23 are sequentially formed on the second metal layer (17, 18, 19), and a third via 300 exposing the second source 18 and a fourth via 400 exposing the second drain 19 are formed on the third insulating layer 20. The oxide semiconductor layer 21 includes a second channel region 211 and second conductor regions 212 located on both sides of the second channel region 211. The second conductor region 212 is electrically connected to the second source 18 through the third via 300, and the second conductor region 212 is electrically connected to the second drain 19 through the fourth via 400. The second gate 23 corresponds to the second channel region 211.

[0071] Specifically, a third insulating layer 20 is formed as a whole layer on the second metal layer (17, 18, 19), and the third via 300 and the fourth via 400 penetrating the third insulating layer 20 are formed by a fifth photomask process. An oxide semiconductor film is formed on the third insulating layer 20, and the oxide semiconductor layer 21 is formed by a sixth photomask process. A fourth insulating film and a third metal film are continuously deposited on the oxide semiconductor layer 21, and the fourth insulating film and the third metal film are patterned by a seventh photomask process to form a stacked second gate 23 and a fourth insulating pattern 22'. Thereafter, using the second gate 23 and the fourth insulating pattern 22' as masks, the portion of the oxide semiconductor layer 21 not covered by the fourth insulating pattern 22' is subjected to a conductorization process to form the second conductor region 212.

[0072] The first source 12 , the first drain 13 , the active layer 15 and the first gate 17 constitute a low-temperature polysilicon thin film transistor T1 , and the second source 18 , the second drain 19 , the oxide semiconductor layer 21 and the second gate 23 constitute an oxide thin film transistor T2 .

[0073] The material of the second gate 23 is the same as that of the first gate 17. The material of the oxide semiconductor layer 21 is a metal oxide material with low leakage current, such as IGZO, IGTO, IGZO, IGO, IZO, AIZO or ATZO.

[0074] After the above step 2 is completed, the method for manufacturing the array substrate further includes the following steps:

[0075] Step three, such as Figures 5H-5I As shown, a fifth insulating layer 24 and a pixel electrode 25 are sequentially formed on the second gate 23 , and the pixel electrode 25 is electrically connected to the low-temperature polysilicon thin film transistor T1 through a fifth via hole 500 penetrating the fifth insulating layer 24 and the third insulating layer 20 .

[0076] The fifth via hole 500 is formed by an eighth photomask process, and the pixel electrode 25 is formed by a ninth photomask process.

[0077] The first insulating layer 14, the third insulating layer 20, and the fifth insulating layer 24 may be made of SiOx or SiNx, or may be a stack of SiOx / SiNx / SiOx or Al2O3 / SiNx / SiOx. The second insulating layer 16 and the fourth insulating layer 22 may be made of SiOx or a stack of SiOx / SiNx.

[0078] So far, this embodiment completes the manufacture of the array substrate through nine photomask processes.

[0079] In this embodiment, because the first gate electrode 17 of the low-temperature polysilicon thin-film transistor T1 and the second source electrode 18 and the second drain electrode 19 of the oxide thin-film transistor T2 are fabricated using the same photomask, one photomask process is eliminated, simplifying the manufacturing process. Furthermore, the low-temperature polysilicon thin-film transistor T1 and the oxide thin-film transistor T2 can share the second insulating layer 16 and the third insulating layer 20 as insulating layers, reducing the number of film layers on the array substrate and further simplifying the manufacturing process.

[0080] In this embodiment, the active layer 15 and the oxide semiconductor layer 21 are arranged in separate layers, which has the following advantages: First, it prevents dopant ions from entering the oxide semiconductor layer 21 during the doping treatment of the active layer 15. If a large number of dopant ions enter the oxide semiconductor layer 21, the oxide semiconductor layer 21 will exhibit a conductive effect, reducing the electrical stability of the oxide thin-film transistor T2. Second, it also prevents the amorphous silicon in the active layer 15 from affecting the crystallinity of the oxide semiconductor layer 21 when it is converted to polycrystalline silicon through a laser annealing process. Therefore, the embodiment of the present invention can achieve both simplified manufacturing processes and device electrical stability. In addition, the oxide thin-film transistor T2 adopts a structure in which the bottom of the oxide semiconductor layer 21 contacts the top of the second source electrode 18 and the second drain electrode 19, eliminating the need for forming an interlayer insulating layer (ILD) on the oxide semiconductor layer in traditional structures. Since the interlayer insulating layer is generally formed using a CVD process, the high temperature of the CVD process can affect the crystallinity of the oxide semiconductor. However, the thin-film transistor of the present invention adopts this structural design, which helps improve the electrical stability of the device. Furthermore, in this embodiment, the oxide semiconductor layer 21 is located above the third insulating layer (ie, the interlayer insulating layer) 20 , so the high temperature of the CVD process will not affect the stability of the device.

[0081] Combine Figure 2 and Figure 3 The manufacturing method of the array substrate provided in the second and third embodiments of the present invention is similar to the manufacturing method of the array substrate of the first embodiment. Please refer to the above description for details. The difference is that: since the orthographic projection of the second source electrode 18 of the array substrate in the second and third embodiments overlaps with the orthographic projection of the first drain electrode 13 on the substrate 11, after the active layer 15 is formed on the first insulating layer 14 and before the second insulating layer 16 and the second metal layer (17, 18, 19) are formed, the manufacturing method further includes the following steps:

[0082] An ion doping process is performed on the region of the active layer 15 to be conductive, so as to form the first conductive region 151 .

[0083] That is, when manufacturing the array substrates in the second and third embodiments, the active layer 15 may be firstly conductively formed, and then the second insulating layer 16 and the second metal layer ( 17 , 18 , 19 ) may be formed on the active layer 15 .

[0084] In summary, the array substrate, its manufacturing method, and display panel provided by the present invention use the same mask to manufacture the gate of the low-temperature polysilicon thin-film transistor and the source and drain of the oxide thin-film transistor, thereby realizing partial sharing of film layers and simplifying the manufacturing process; and the active layer of the low-temperature polysilicon thin-film transistor and the oxide semiconductor layer of the oxide thin-film transistor are arranged in different layers, thereby achieving the goal of simplifying the manufacturing process while taking into account the electrical stability of the device.

[0085] The present invention has been introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. An array substrate, characterized in that: The invention comprises a substrate, at least one low-temperature polysilicon thin film transistor and at least one oxide thin film transistor arranged on the substrate; The low-temperature polysilicon thin film transistor includes an active layer and a first gate electrode, and the oxide thin film transistor includes an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode; The first gate, the second source and the second drain are arranged in the same layer, and the active layer and the oxide semiconductor layer are arranged in different layers. The oxide semiconductor layer includes a channel region corresponding to the second gate and a conductor region located on both sides of the channel region. The orthographic projection of the conductor region on the substrate covers the orthographic projection of the first gate on the substrate. A capacitor is formed between the conductor region and the first gate.

2. The array substrate according to claim 1, wherein: The first gate is located on a side of the active layer away from the substrate, and the second source and the second drain are located on a side of the oxide semiconductor layer close to the substrate.

3. The array substrate according to claim 2, wherein: The low-temperature polysilicon thin film transistor further includes a first source electrode and a first drain electrode located on a side of the active layer close to the substrate, the active layer being electrically connected to the first source electrode through a first via hole, and the active layer being electrically connected to the first drain electrode through a second via hole; The oxide thin film transistor further includes a second gate located on a side of the oxide semiconductor layer away from the substrate. The oxide semiconductor layer is electrically connected to the second source through a third via hole, and the oxide semiconductor layer is electrically connected to the second drain through a fourth via hole.

4. The array substrate according to claim 3, wherein: The orthographic projection of the second source electrode on the substrate overlaps with the orthographic projection of the first drain electrode on the substrate, and the orthographic projection of the second source electrode on the substrate is spaced apart from the orthographic projection of the first gate electrode on the substrate.

5. The array substrate according to claim 4, wherein: The second source is located between the first gate and the second drain, the orthographic projection of the oxide semiconductor layer on the substrate overlaps with the orthographic projection of the active layer on the substrate, and the orthographic projection of the oxide semiconductor layer on the substrate is spaced from the orthographic projection of the first source on the substrate.

6. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 5.

7. A method for manufacturing an array substrate, characterized in that: The following steps are involved: providing a substrate; Fabricating at least one low-temperature polysilicon thin film transistor and at least one oxide thin film transistor on the substrate, wherein the low-temperature polysilicon thin film transistor includes an active layer and a first gate electrode, and the oxide thin film transistor includes an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode; In which, the active layer and the oxide semiconductor layer are arranged in different layers, the first gate, the second source and the second drain are made using the same mask, the oxide semiconductor layer includes a channel region corresponding to the second gate and a conductor region located on both sides of the channel region, the orthographic projection of the conductor region on the substrate covers the orthographic projection of the first gate on the substrate, wherein a capacitor is formed between the conductor region and the first gate.

8. The method for manufacturing an array substrate according to claim 7, wherein: The steps of fabricating at least one low-temperature polysilicon thin film transistor and at least one oxide thin film transistor on the substrate include: forming a first metal layer and a first insulating layer in sequence on the substrate, wherein the first metal layer includes a first source electrode and a first drain electrode spaced apart from each other, and a first via hole exposing the first source electrode and a second via hole exposing the first drain electrode are formed on the first insulating layer; An active layer, a second insulating layer, and a second metal layer are sequentially formed on the first insulating layer, wherein the active layer includes a first channel region and first conductor regions located on both sides of the first channel region, the first conductor region is electrically connected to the first source electrode through the first via hole, and the first conductor region is electrically connected to the first drain electrode through the second via hole, and the second metal layer includes a first gate electrode, a second source electrode, and a second drain electrode spaced apart from each other, and the first gate electrode corresponds to the first channel region; forming a third insulating layer, an oxide semiconductor layer, a fourth insulating layer, and a second gate electrode in sequence on the second metal layer, wherein a third via hole exposing the second source electrode and a fourth via hole exposing the second drain electrode are formed on the third insulating layer, the oxide semiconductor layer includes a second channel region and second conductor regions located on both sides of the second channel region, the second conductor region is electrically connected to the second source electrode through the third via hole, the second conductor region is electrically connected to the second drain electrode through the fourth via hole, and the second gate electrode corresponds to the second channel region; The first source, the first drain, the active layer and the first gate constitute a low-temperature polysilicon thin film transistor, and the second source, the second drain, the oxide semiconductor layer and the second gate constitute an oxide thin film transistor.

9. The method for manufacturing an array substrate according to claim 8, wherein: The orthographic projection of the second source electrode on the substrate overlaps with the orthographic projection of the first drain electrode on the substrate; Wherein, after forming the active layer on the first insulating layer and before forming the second insulating layer and the second metal layer, the manufacturing method further includes the following steps: An ion doping treatment is performed on the region of the active layer to be conductive to form the first conductive region.

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