A low-power power-on reset circuit

Abstract

The present invention discloses a low-power power-on reset circuit, which includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a resistance adjustment module, a capacitance adjustment module, an inverter and a buffer. The drain of the first PMOS transistor, the drain of the first NMOS transistor, the gate of the first NMOS transistor, the gate of the second PMOS transistor, the gate of the second NMOS transistor and the gate of the third NMOS transistor are connected. The drain of the second PMOS transistor, the gate of the third PMOS transistor and one end of the resistance adjustment module are connected. The other end of the resistance adjustment module and the drain of the second NMOS transistor are connected. The drain of the third PMOS transistor, the drain of the third NMOS transistor and the input end of the inverter are connected. The output end of the inverter, the other end of the capacitance adjustment module and the input end of the buffer are connected. The advantages are that the circuit structure is simple, the chip area occupied is small, the power consumption is low, and at the same time, a reset signal can be generated under a short power-on reset delay and also under a long power-on reset delay.

Description

Technical Field

[0001] The present invention relates to a power-on reset circuit, and more particularly to a low-power power-on reset circuit. Background Art

[0002] With the progress of microelectronics technology and the improvement of integration, the complexity of existing information processing chips is increasing day by day. Various analog functional units and digital logic units are integrated on the chip. The digital logic units often provide calibration for the analog functional units to improve the performance of the chip, and the final calibration data will be stored in units such as EEPROM or OTP. During the power-on process of the chip, there are intermediate states inside, especially in the power-on process of circuit units such as oscillators and clocks, a pulse reset signal needs to be provided by the reset circuit.

[0003] A power-on reset circuit is proposed in a Chinese patent with the publication number CN101753119B. Its voltage division part includes at least two NMOS transistors connected in series between the power supply terminal and the ground, and the voltage detection part includes an NMOS transistor and a PMOS transistor. The voltage division part of this power-on reset circuit uses at least two NMOS transistors connected in series to replace the existing voltage dividing resistors, with a simple circuit structure, a smaller chip area occupied, a reduced working current, and lower power consumption. However, since this power-on reset circuit uses the voltage division of at least two series-connected NMOS transistors to detect the power-on signal, a reset signal is quickly generated after the power supply VCC is powered on and reaches the threshold voltage of the NMOS transistor. Generally, the power-on reset delay is at the μs level, making it difficult to meet the application scenarios with longer reset delays.

[0004] A power-on reset circuit with fast charge and discharge and controllable reset time is proposed in a Chinese patent with the publication number CN107733407B. This power-on reset circuit charges a capacitor with a current to generate a voltage, compares this voltage with a reference voltage, and a comparator generates a level jump signal (i.e., the power-on detection threshold), and a reset signal is generated from this jump signal. Thus, the power-on reset delay of this power-on reset circuit is controllable, and a reset signal can be generated both under a shorter power-on reset delay and under a longer power-on reset delay. However, this power-on reset circuit relies on an on-chip reference circuit to generate the reference voltage and requires an active comparator circuit to compare the power-on detection threshold, so the power consumption is large, and the circuit structure is relatively complex, occupying a larger chip area. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a low-power power-on reset circuit that has a simple circuit structure, occupies a smaller chip area, has lower power consumption, and can generate a reset signal both under a shorter power-on reset delay and under a longer power-on reset delay.

[0006] The technical solution adopted by the present invention to solve the above technical problems is as follows: A low-power power-on reset circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a resistance adjustment module, a capacitance adjustment module, an inverter, and a buffer. The resistance value of the resistance adjustment module can be adjusted, and the capacitance value of the capacitance adjustment module can be adjusted. The gate of the first PMOS transistor, the source of the first NMOS transistor, the source of the second NMOS transistor, the source of the third NMOS transistor, and one end of the capacitance adjustment module are all grounded. The sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are connected, and the connection end is the power supply terminal of the low-power power-on reset circuit. The power supply terminal of the low-power power-on reset circuit is used to connect to the power supply voltage VCC. The drain of the first PMOS transistor, the drain of the first NMOS transistor, the gate of the first NMOS transistor, the gate of the second PMOS transistor, the gate of the second NMOS transistor, and the gate of the third NMOS transistor are connected. The drain of the second PMOS transistor, the gate of the third PMOS transistor, and one end of the resistance adjustment module are connected. The other end of the resistance adjustment module and the drain of the second NMOS transistor are connected. The drain of the third PMOS transistor, the drain of the third NMOS transistor, and the input terminal of the inverter are connected. The output terminal of the inverter, the other end of the capacitance adjustment module, and the input terminal of the buffer are connected. The output terminal of the buffer is the output terminal of the low-power power-on reset circuit, and the output terminal of the low-power power-on reset circuit is used to output a reset signal.

[0007] The resistance adjustment module includes n resistors and n first switches, where n is an integer greater than or equal to 2. One ends of the n resistors are connected, and the connection end serves as one end of the resistance adjustment module. The other end of the jth resistor is connected to one end of the jth first switch, and the other ends of the n first switches are connected, and the connection end serves as the other end of the resistance adjustment module, where j = 1, 2,..., n.

[0008] The n resistors are all implemented by high-poly resistors.

[0009] The capacitance adjustment module includes m capacitors and m second switches, where m is an integer greater than or equal to 2. One ends of the m capacitors are connected, and the connection end serves as one end of the capacitance adjustment module. The other end of the kth capacitor is connected to one end of the kth second switch, and the other ends of the m second switches are connected, and the connection end serves as the other end of the capacitance adjustment module, where k = 1, 2,..., m.

[0010] Compared with the prior art, the advantages of the present invention are as follows: A low-power power-on reset circuit is constituted by a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a resistance adjustment module, a capacitance adjustment module, an inverter and a buffer. The resistance value of the resistance adjustment module can be adjusted, and the capacitance value of the capacitance adjustment module can be adjusted. The gate of the first PMOS transistor, the source of the first NMOS transistor, the source of the second NMOS transistor, the source of the third NMOS transistor and one end of the capacitance adjustment module are all grounded. The sources of the first PMOS transistor, the second PMOS transistor and the third PMOS transistor are connected, and the connection end is the power supply terminal of the low-power power-on reset circuit. The power supply terminal of the low-power power-on reset circuit is used to connect to the power supply voltage VCC. The drain of the first PMOS transistor, the drain of the first NMOS transistor, the gate of the first NMOS transistor, the gate of the second PMOS transistor, the gate of the second NMOS transistor and the gate of the third NMOS transistor are connected. The drain of the second PMOS transistor, the gate of the third PMOS transistor and one end of the resistance adjustment module are connected. The other end of the resistance adjustment module and the drain of the second NMOS transistor are connected. The drain of the third PMOS transistor, the drain of the third NMOS transistor and the input terminal of the inverter are connected. The output terminal of the inverter, the other end of the capacitance adjustment module and the input terminal of the buffer are connected. The output terminal of the buffer is the output terminal of the low-power power-on reset circuit. The output terminal of the low-power power-on reset circuit is used to output a reset signal. When the power supply terminal of the low-power power-on reset circuit is connected to the power supply voltage VCC, since the gate terminal of the first PMOS transistor is grounded, when the power supply voltage VCC rises to a certain value, the first PMOS transistor starts to conduct. At this time, there is current flowing through the first NMOS transistor, and the drain voltage and gate voltage of the first NMOS transistor rise slowly. At the same time, the gate voltage of the second NMOS transistor also rises slowly. Before the gate voltage of the second NMOS transistor reaches its threshold voltage, the second NMOS transistor is in the off state. At this time, one end of the resistance adjustment module and the gate voltage of the third PMOS transistor are at a low level, and the gate voltage of the third PMOS transistor is lower than its threshold voltage. Before the gate voltage of the third PMOS transistor rises to its threshold voltage, the third PMOS transistor is not turned on, but the drain voltage of the third PMOS transistor rises with the power supply voltage VCC until the gate voltages of the first NMOS transistor, the second NMOS transistor and the third NMOS transistor rise to equal the threshold voltage of the gate of the second PMOS transistor. The branch formed by the second PMOS transistor, the resistance adjustment module and the second NMOS transistor conducts, and the voltage at one end of the resistance adjustment module rises rapidly and approaches the power supply voltage VCC. At this time, the third PMOS transistor is turned off, and the voltage connected to the input terminal of the inverter is instantaneously pulled down from rising with the power supply voltage VCC. At this time, the signal output from the output terminal of the inverter is pulled up from a low level to a high level, and a reset signal is generated at the output terminal of the inverter. This reset signal is delayed by the capacitance adjustment module and then enters the buffer and is output at the output terminal of the buffer.The present invention controls the power-on detection threshold by adjusting the resistance value of the resistance adjustment module, and controls the reset delay time by adjusting the capacitance value of the capacitance adjustment module. It is simple and reliable. It can generate a reset signal with a short power-on reset delay and also generate a reset signal with a long power-on reset delay. The overall circuit structure is simple, occupies a small chip area, does not require the integration of a high-precision reference source and a comparator, and saves the power consumption of the chip. Description of the Drawings

[0011] Figure 1 is the circuit diagram of the low-power power-on reset circuit of the present invention;

[0012] Figure 2 is the waveform diagram of the internal key nodes of the low-power power-on reset circuit of the present invention;

[0013] Figure 3 is the circuit diagram of the resistance adjustment module of the low-power power-on reset circuit of the present invention;

[0014] Figure 4 is the circuit diagram of the capacitance adjustment module of the low-power power-on reset circuit of the present invention. Detailed Embodiments

[0015] The present invention will be further described in detail below in conjunction with the embodiments of the drawings.

[0016] Embodiment: As Figure 1As shown, a low-power power-on reset circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a resistance adjustment module, a capacitance adjustment module, an inverter U1, and a buffer U2. The resistance value of the resistance adjustment module can be adjusted, and the capacitance value of the capacitance adjustment module can be adjusted. The gate of the first PMOS transistor P1, the source of the first NMOS transistor N1, the source of the second NMOS transistor N2, the source of the third NMOS transistor N3, and one end of the capacitance adjustment module are all grounded. The sources of the first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3 are connected, and the connection end is the power supply terminal of the low-power power-on reset circuit. The power supply terminal of the low-power power-on reset circuit is used to connect to the power supply voltage VCC. The drain of the first PMOS transistor P1, the drain of the first NMOS transistor N1, the gate of the first NMOS transistor N1, the gate of the second PMOS transistor P2, the gate of the second NMOS transistor N2, and the gate of the third NMOS transistor N3 are connected. The drain of the second PMOS transistor P2, the gate of the third PMOS transistor P3, and one end of the resistance adjustment module are connected. The other end of the resistance adjustment module is connected to the drain of the second NMOS transistor N2. The drain of the third PMOS transistor P3, the drain of the third NMOS transistor N3, and the input terminal of the inverter U1 are connected. The output terminal of the inverter U1, the other end of the capacitance adjustment module, and the input terminal of the buffer U2 are connected. The output terminal of the buffer U2 is the output terminal of the low-power power-on reset circuit. The output terminal of the low-power power-on reset circuit is used to output a reset signal.

[0017] The working principle of the low-power power-on reset circuit of the present invention is as follows: When the power supply terminal of the low-power power-on reset circuit is connected to the power supply voltage VCC, since the gate terminal of the first PMOS transistor P1 is grounded, when the power supply voltage VCC rises to a certain value, the first PMOS transistor P1 starts to conduct. At this time, there is a current flowing through the first NMOS transistor N1, and the drain voltage and gate voltage of the first NMOS transistor N1 rise slowly. At the same time, the gate voltage of the second NMOS transistor N2 also rises slowly. Before the gate voltage of the second NMOS transistor N2 reaches its threshold voltage, the second NMOS transistor N2 is in the off state. At this time, one end of the resistor adjustment module and the gate voltage of the third PMOS transistor P3 are at a low level, and the gate voltage of the third PMOS transistor P3 is lower than its threshold voltage. Before the gate voltage of the third PMOS transistor P3 rises to its threshold voltage, the third PMOS transistor P3 is not turned on, but the drain voltage of the third PMOS transistor P3 rises with the power supply voltage VCC. Until the gate voltages of the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3 rise to be equal to the gate voltage threshold of the second PMOS transistor P2, the branch formed by the second PMOS transistor P2, the resistor adjustment module, and the second NMOS transistor N2 conducts, and the voltage at one end of the resistor adjustment module rises rapidly and approaches the power supply voltage VCC. At this time, the third PMOS transistor P3 is turned off, and the voltage applied to the input terminal of the inverter U1 is instantaneously pulled low from rising with the power supply voltage VCC. At this time, the signal output from the output terminal of the inverter U1 is pulled high from a low level, and a reset signal is generated at the output terminal of the inverter U1. This reset signal is delayed by the capacitor adjustment module and then enters the buffer U2 and is output from the output terminal of the buffer U2. The present invention controls the power-on detection threshold through the resistor adjustment module and controls the reset delay time through the capacitor adjustment module, which is simple and reliable.

[0018] The waveform diagram of the internal key nodes of the low-power power-on reset circuit of the present invention is as Figure 2 shown, Figure 2 In the figure, a represents the connection node of the drain of the first PMOS transistor P1, the gate of the first NMOS transistor N1, the drain of the first NMOS transistor N1, the gate of the second NMOS transistor N2, the gate of the third NMOS transistor N3, and the gate of the second PMOS transistor P2; b represents the connection node of the drain of the second PMOS transistor P2, the gate of the third PMOS transistor P3, and one end of the resistor adjustment module; c represents the connection node of the drain of the third PMOS transistor P3, the drain of the third NMOS transistor N3, and the input terminal of the inverter; d represents the connection node of the output terminal of the inverter U1, the other end of the capacitor adjustment module, and the input terminal of the buffer U2. Analyze Figure 2It can be known that: the voltage at point a changes synchronously with the power-on process of the power supply voltage VCC. The voltage at point b starts to rise to a certain value and then is pulled down until the voltage rises again after the second PMOS transistor P2 is turned on. The rising detection threshold of the voltage at point c is controlled by the resistance adjustment module. When it rises to the required power-on detection threshold, it is pulled down to start the reset delay to generate a reset signal at node d. After being delayed and controlled by the capacitance adjustment module, the reset signal is buffered by buffer U2 and then output. From Figure 2 It can be seen that the present invention generates the expected reset signal.

[0019] As Figure 3 shown, in this embodiment, the resistance adjustment module includes n resistors R1-Rn and n first switches S1-Sn, where n is an integer greater than or equal to 2. One ends of the n resistors R1-Rn are connected and the connection end is used as one end of the resistance adjustment module. The other end of the jth resistor Rj is connected to one end of the jth first switch Sj. The other ends of the n first switches S1-Sn are connected and the connection end is used as the other end of the resistance adjustment module, where j = 1, 2,..., n. When all n first switches S1-Sn in the resistance adjustment module are closed, the resistance of the resistance adjustment module is the smallest, and the resistance value of the resistance adjustment module becomes smaller as the number of closed n first switches S1-Sn increases.

[0020] In this embodiment, all n resistors R1-Rn are implemented by high-poly resistors.

[0021] As Figure 4 shown, in this embodiment, the capacitance adjustment module includes m capacitors C1-Cm and m second switches S'1-S'm, where m is an integer greater than or equal to 2. One ends of the m capacitors C1-Cm are connected and the connection end is used as one end of the capacitance adjustment module. The other end of the kth capacitor Cj is connected to one end of the kth second switch S'k. The other ends of the m second switches S'1-S'm are connected and the connection end is used as the other end of the capacitance adjustment module, where k = 1, 2,..., m. When all m second switches S'1-S'm in the capacitance adjustment module are closed, the capacitance of the resistance adjustment module is the largest, and the capacitance value of the capacitance adjustment module becomes larger as the number of closed m second switches S'1-S'm increases.

Claims

1. A low-power power-on reset circuit, characterized in that It includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a resistance adjustment module, a capacitance adjustment module, an inverter, and a buffer. The resistance value of the resistance adjustment module can be adjusted, and the capacitance value of the capacitance adjustment module can be adjusted. The gate of the first PMOS transistor, the source of the first NMOS transistor, the source of the second NMOS transistor, the source of the third NMOS transistor, and one end of the capacitance adjustment module are all grounded. The sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are connected, and the connection end is the power supply terminal of the low-power power-on reset circuit. The power supply terminal of the low-power power-on reset circuit is used to connect to the power supply voltage VCC. The drain of the first PMOS transistor, the drain of the first NMOS transistor, the gate of the first NMOS transistor, the gate of the second PMOS transistor, the gate of the second NMOS transistor, and the gate of the third NMOS transistor are connected. The drain of the second PMOS transistor, the gate of the third PMOS transistor, and one end of the resistance adjustment module are connected. The other end of the resistance adjustment module is connected to the drain of the second NMOS transistor. The drain of the third PMOS transistor, the drain of the third NMOS transistor, and the input terminal of the inverter are connected. The output terminal of the inverter, the other end of the capacitance adjustment module, and the input terminal of the buffer are connected. The output terminal of the buffer is the output terminal of the low-power power-on reset circuit, and the output terminal of the low-power power-on reset circuit is used to output a reset signal.

2. The low-power power-on reset circuit according to claim 1, characterized in that The resistance adjustment module includes n resistors and n first switches, where n is an integer greater than or equal to 2. One ends of the n resistors are connected, and the connection end serves as one end of the resistance adjustment module. The other end of the jth resistor is connected to one end of the jth first switch. The other ends of the n first switches are connected, and the connection end serves as the other end of the resistance adjustment module, where j = 1, 2,..., n.

3. The low-power power-on reset circuit according to claim 2, characterized in that The n resistors are all implemented using high-poly resistors.

4. The low-power power-on reset circuit according to claim 1, wherein The capacitance adjustment module includes m capacitors and m second switches, where m is an integer greater than or equal to 2. One ends of the m capacitors are connected, and the connection end serves as one end of the capacitance adjustment module. The other end of the kth capacitor is connected to one end of the kth second switch. The other ends of the m second switches are connected, and the connection end serves as the other end of the capacitance adjustment module, where k = 1, 2,..., m.

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