Method of manufacturing a semiconductor integrated device

Abstract

The present invention provides a manufacturing method of a semiconductor integrated device, which is applied to the field of semiconductor technology. Specifically, during the process of forming the gate oxide of the MOS device in the region by removing the thick oxide in the low-voltage device region, a thin oxide layer is simultaneously formed on the surface in the SGT device, thereby compensating for the damage to the gate oxide of the SGT device caused by the error during the etching process when forming the gate polysilicon of the SGT device, and further avoiding the problem of leakage in the SGT device, that is, improving the performance of the device. Moreover, the present invention provides a method for simultaneously producing SGT discrete devices and BCD power IC devices on the same chip, thereby avoiding the problem of relatively large parasitic Rs and Rc between the two devices caused by separately forming the two devices step by step and then bonding and connecting them in the prior art, and also improving the performance matching degree between the SGT device and the BCD device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a manufacturing method of a semiconductor integrated device. Background Art

[0002] Power integrated ICs are widely used in fields such as power management, motor drive, automotive electronics, and industrial control. BCD refers to a process technology that integrates high-voltage power devices such as Bipolar, CMOS, and DMOS, as well as various resistors, capacitors, and diodes on the same chip. It has the characteristics of low cost, easy packaging, easy design, and a simpler peripheral chip, and has rapidly developed into the mainstream technology in the field of power ICs. The Bipolar bipolar transistor in the BCD technology has high analog accuracy and is mainly used in analog circuits. CMOS has high integration and is mainly used in logic circuits. DMOS has high power (high voltage) characteristics and is commonly used as a switch.

[0003] In the prior art, BCD devices often integrate high-voltage devices and low-voltage devices. For example, the high-voltage devices can be LDMOS devices, high-voltage JFET devices, etc., and the low-voltage devices can be low-voltage MOS devices, etc. The discrete-gate or shield-gate MOSFET is an improved type of UMOS device, which has a faster switching speed and lower switching loss compared to UMOS. According to the structure of the poly, it can be divided into up-down (UD SGT) and left-right (LR SGT). Among them, the SGT device utilizes the charge balance principle to appropriately increase the doping concentration of the epitaxial layer to reduce the on-resistance; and uses the shield gate to reduce Cgd / Ciss and improve the Dv / dt capability.

[0004] Currently, the SGT discrete devices and BCD devices of PowerIC (power IC) on the market are generally produced separately and then combined and packaged together to form a module. Therefore, in high-end application fields, there are the following problems with the module formed by the above method: 1. The SGT discrete device and the BCD Power IC device are connected by bonding wires, which will result in relatively large parasitic Rs and Rc; 2. The SGT discrete device and the BCD PowerIC device are produced asynchronously, so the performance matching degree between them is not high. Summary of the Invention

[0005] The purpose of the present invention is to provide a manufacturing method of a semiconductor integrated device, so as to propose a new manufacturing method for integrating SGT devices and BCD devices on the same chip, and at the same time solve the problem that the gate oxide of the SGT device will be over-etched during the process of etching to form gate polysilicon, resulting in low reliability of the device gate oxide.

[0006] To solve the above technical problems, the present invention provides a manufacturing method for a semiconductor integrated device. Specifically, the manufacturing method may at least include the following steps:

[0007] Provide a semiconductor substrate, the semiconductor substrate includes an SGT device region, a low-voltage device region, and a high-voltage device region arranged side by side in sequence. The low-voltage device region includes a PMOS region and an NMOS region, and the high-voltage device region includes an NLDMOS region and a PLDMOS region. A plurality of trench isolation structures for isolating each device structure in the SGT device region, the low-voltage device region, and the high-voltage device region are formed on the semiconductor substrate, and the top surface of the trench isolation structure is higher than the top surface of the semiconductor substrate;

[0008] Form a gate trench, a breakdown voltage trench, and a first oxide layer, a source polysilicon, an isolation layer, a second oxide layer, and a gate polysilicon filled in the gate trench in the semiconductor substrate corresponding to the SGT device region. The source polysilicon also fills the breakdown voltage trench. The gate polysilicon covers the surface of the isolation layer and at least fills the remaining gate trench, and also extends to cover the source polysilicon in the breakdown voltage trench and the surfaces of the semiconductor substrates corresponding to the low-voltage device region and the high-voltage device region. The second oxide layer also extends to cover the surface of the semiconductor substrate between adjacent trench isolation structures;

[0009] Etch back the gate polysilicon until the remaining gate polysilicon in the breakdown voltage trench and the gate trench is flush with the surface of the remaining second oxide layer after the etch back;

[0010] Form a third oxide layer on the surface of the semiconductor substrate. The third oxide layer covers the surface of the remaining second oxide layer and extends to cover the surface of the semiconductor substrate corresponding to the region between two adjacent trench isolation structures in the low-voltage device region.

[0011] Furthermore, during the process of etching back the gate polysilicon, a part of the thickness of the second oxide layer will also be etched back, thereby causing loss of the gate oxide layer of the SGT device.

[0012] Furthermore, after forming the gate trench and the breakdown voltage trench, the manufacturing method may further include:

[0013] Perform a first ion implantation process on the semiconductor substrates corresponding to the PMOS region, the NMOS region, the NLDMOS region, and the PLDMOS region to form at least three P-type deep trenches in the low-voltage device region and the high-voltage device region;

[0014] Perform a second ion implantation process on the semiconductor substrate corresponding to the P-type deep well to form a plurality of high-voltage N wells in the high-voltage device region and a plurality of low-voltage N wells in the low-voltage device region.

[0015] Further, the steps of forming the first oxide layer, source polysilicon, isolation layer, second oxide layer, and gate polysilicon in the gate trench may include:

[0016] Form a first oxide layer on the inner walls of the breakdown voltage trench and the gate trench, and after forming the first oxide layer, fill the breakdown voltage trench and the gate trench with source polysilicon so that the top surface of the filled source polysilicon is flush with the upper surface of the semiconductor substrate;

[0017] Mask the surface of the semiconductor substrate corresponding to the breakdown voltage trench, and back-etch the source polysilicon and the first oxide layer in the gate trench to form the shielding gate and the thick oxide layer of the SGT device structure in the gate trench. Then, form an isolation layer on the top surface of the source polysilicon and the first oxide layer after back-etching, and a second oxide layer covering the surface of the isolation layer and the inner walls of the remaining gate trench, wherein the second oxide layer also extends to cover the surface of the remaining exposed semiconductor substrate.

[0018] Further, the surface of the remaining exposed semiconductor substrate covered by the extension of the second oxide layer may include: the surface of the semiconductor substrate corresponding to the region between two adjacent trench isolation structures in the low-voltage device region.

[0019] Further, after back-etching the gate polysilicon and before forming the third oxide layer, the manufacturing method may further include:

[0020] Form a photoresist layer that masks the semiconductor substrate corresponding to the SGT device region and the high-voltage device region and exposes the semiconductor substrate corresponding to the low-voltage device region, and use the photoresist layer as a mask to etch and remove the second oxide layer formed in the low-voltage device region;

[0021] Form a third oxide layer on the surface of the semiconductor substrate exposed between two adjacent trench isolation structures in the low-voltage device region where the second oxide layer has been removed.

[0022] Further, the process of forming the third oxide layer may include: a thermal oxidation process.

[0023] Further, the steps of forming the trench isolation structure may include:

[0024] Form a plurality of shallow trenches in the semiconductor substrate, and fill the shallow trenches to form the trench isolation structure for isolating the SGT device region, the low-voltage device region, the high-voltage device region, and each MOS transistor included in the low-voltage device region and the high-voltage device region.

[0025] Further, after forming the third oxide layer, the manufacturing method may further include:

[0026] Form a gate material layer, the gate material layer covering the surface of the entire semiconductor substrate, and etch the gate material layer to form corresponding gate structures in the low-voltage device region and the high-voltage device region.

[0027] Further, the materials of the isolation layer, the first oxide layer, the second oxide layer, and the third oxide layer may include silicon dioxide.

[0028] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0029] In a manufacturing method of a semiconductor integrated device provided by the present invention, during the process of forming the gate oxide of the MOS device in the region by removing the thick oxide in the low-voltage device region, a thin oxide layer is simultaneously formed on the surface of the SGT device, thereby compensating for the damage of the gate oxide of the SGT device caused by the error during the etching process when forming the gate polysilicon of the SGT device, and further avoiding the problem of leakage of the SGT device, that is, improving the performance of the device.

[0030] Moreover, the present invention provides a method for synchronously producing SGT discrete devices and BCD power IC devices on the same chip, thereby avoiding the problem of relatively large parasitic Rs and Rc between the two caused by separately forming the devices step by step and then bonding and connecting the two in the prior art, and at the same time improving the performance matching degree of the SGT device and the BCD device. Description of the Drawings

[0031] Figure 1 It is a schematic flow chart of a manufacturing method of a semiconductor integrated device in an embodiment of the present invention;

[0032] Figures 2a to 2d It is a schematic structural diagram of a manufacturing method of a semiconductor integrated device in an embodiment of the present invention during its preparation process.

[0033] Among them, the reference numerals are as follows:

[0034] 100 - semiconductor substrate; 110 - epitaxial layer;

[0035] A - SGT device region; B - high-voltage device region;

[0036] C - Low - voltage device area; 101 - Trench isolation structure;

[0037] DPW - P - type deep well; LVNW - Low - voltage N - well;

[0038] HVNW - High - voltage N - well; 102 - Gate trench;

[0039] 103 - Breakdown voltage trench; 120 - First oxide layer;

[0040] 130 - Source polysilicon; 140 - Isolation layer;

[0041] 150 - Second oxide layer; 160 - Gate polysilicon;

[0042] 170 - Photoresist layer; 180 - Third oxide layer. Detailed implementation mode

[0043] As described in the background art, high - voltage devices and low - voltage devices are often integrated in BCD devices. For example, high - voltage devices can be LDMOS devices, high - voltage JFET devices, etc., and low - voltage devices can be low - voltage MOS devices, etc. The discrete - gate or shield - gate MOSFET is an improved UMOS device, which has a faster switching speed and lower switching loss compared to UMOS. According to the structure of the poly, it can be divided into up - down (UD SGT) and left - right (LR SGT). Among them, the SGT device utilizes the charge - balance principle to reduce the on - resistance by appropriately increasing the doping concentration of the epitaxial layer; and uses the shield - gate to reduce Cgd / Ciss and improve the Dv / dt capability.

[0044] Currently, SGT discrete devices and BCD devices of Power IC (Power Integrated Circuit) on the market are generally produced separately and then packaged together to form a module. Therefore, in high - end application fields, there are the following problems with the module formed by the above method: 1. The SGT discrete device and the BCD's Power IC device are connected by bonding wires, which will result in relatively large parasitic Rs and Rc; 2. The SGT discrete device and the BCD's Power IC device are produced asynchronously, so the performance matching degree between them is not high.

[0045] For this reason, the present invention provides a manufacturing method of a semiconductor integrated device to propose a new manufacturing method for integrating SGT devices and BCD devices on the same chip, and at the same time can solve the problem that the gate oxide of the SGT device will be over - etched during the process of etching to form the gate polysilicon, resulting in low reliability of the device gate oxide.

[0046] Refer to Figure 1 as shown Figure 1Schematic flow chart of the manufacturing method of the semiconductor integrated device provided in the embodiments of the present invention; wherein, the manufacturing method of the semiconductor integrated device may include the following steps:

[0047] Step S100: Provide a semiconductor substrate, the semiconductor substrate includes an SGT device area, a low-voltage device area and a high-voltage device area arranged side by side in sequence, the low-voltage device area includes a PMOS area and an NMOS area, the high-voltage device area includes an NLDMOS area and a PLDMOS area, a plurality of trench isolation structures for isolating each device structure in the SGT device area, the low-voltage device area and the high-voltage device area are formed on the semiconductor substrate, and the top surface of the trench isolation structure is higher than the top surface of the semiconductor substrate;

[0048] Step S200: Form a gate trench, a breakdown voltage trench and a first oxide layer, a source polysilicon, an isolation layer, a second oxide layer and a gate polysilicon filled in the gate trench in the semiconductor substrate corresponding to the SGT device area, wherein the source polysilicon also fills the breakdown voltage trench, the gate polysilicon covers the surface of the isolation layer and at least fills the remaining gate trench, and also extends to cover the source polysilicon in the breakdown voltage trench and the surfaces of the semiconductor substrates corresponding to the low-voltage device area and the high-voltage device area, and the second oxide layer also extends to cover the surface of the semiconductor substrate between adjacent trench isolation structures;

[0049] Step S300: Etch back the gate polysilicon until the remaining gate polysilicon in the breakdown voltage trench and the gate trench is flush with the surface of the remaining second oxide layer after the etch back;

[0050] Step S400: Form a third oxide layer on the surface of the semiconductor substrate, the third oxide layer covers the surface of the remaining second oxide layer and extends to cover the surface of the semiconductor substrate corresponding to the area between two adjacent trench isolation structures in the low-voltage device area.

[0051] That is, in a method for manufacturing a semiconductor integrated device provided by the present invention, during the process of removing the thick oxide in the low-voltage device region and forming the gate oxide of the MOS device in this region, a thin oxide layer is simultaneously formed on the surface in the SGT device, thereby compensating for the damage to the gate oxide of the SGT device caused by the error during the etching process when forming the gate polysilicon of the SGT device, and further avoiding the problem of leakage in the SGT device, that is, improving the performance of the device. Moreover, the present invention provides a method for synchronously producing SGT discrete devices and BCD power IC devices on the same chip, thereby avoiding the problem of relatively large parasitic Rs and Rc between the two caused by separately forming the two devices step by step and then bonding and connecting them in the prior art, and at the same time improving the performance matching degree between the SGT device and the BCD device.

[0052] The following further elaborates on the method for manufacturing a semiconductor integrated device proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention. Many specific details are set forth in the following description in order to provide a thorough understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, so the present invention is not limited by the specific embodiments disclosed below.

[0053] As shown in this application and the claims, unless the context clearly indicates an exception, words such as "a", "an", "one", and / or "the" are not specifically singular and may also include plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of the clearly identified steps and elements, and these steps and elements do not constitute an exclusive list, and the method or device may also include other steps or elements. When elaborating on the embodiments of the present invention, for the convenience of explanation, the cross-sectional views showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0054] Figures 2a to 2d It is a schematic structural diagram in the preparation process of the method for manufacturing a semiconductor integrated device in an embodiment of the present invention.

[0055] In step S100, specifically refer to Figure 2aAs shown, a semiconductor substrate 100 is provided. The semiconductor substrate includes an SGT device region A, a low-voltage device region C, and a high-voltage device region B arranged side by side in sequence. Among them, the low-voltage device region C may include one or more PMOS regions and NMOS regions. That is, the low-voltage device region C is a device region containing multiple CMOS transistors, and the operating voltage of the CMOS transistors in this device region can be 5V; the high-voltage device region B may include one or more NLDMOS regions and PLDMOS regions. That is, the high-voltage device region B is a device region containing multiple LDMOS transistors. Further, a plurality of trench isolation structures 101 for isolating each device structure in the SGT device region A, the low-voltage device region C, and the high-voltage device region B may be formed on the semiconductor substrate 100, and the top surface of the trench isolation structure 101 is higher than the top surface of the semiconductor substrate.

[0056] In this embodiment, first, a semiconductor substrate needs to be provided, such as Figure 2a the semiconductor substrate 100 shown. The semiconductor substrate 100 may be any suitable substrate well-known in the art. For example, it may be at least one of the materials mentioned below: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, and also includes multilayer structures composed of these semiconductors, etc. Or it may also be a double-sided polished silicon wafer (Double Side Polished Wafers, DSP), or a ceramic substrate such as alumina, a quartz or glass substrate, etc. Exemplarily, the semiconductor substrate 100 in this embodiment is, for example, a silicon wafer.

[0057] After that, for the N-type doped silicon substrate 100, an N-type doped epitaxial layer (Nepi) 110 may be formed on the surface of the N-type silicon substrate 100 by combining an epitaxial process and a doping process. Further, after forming the N-type doped epitaxial layer (Nepi) 110, the semiconductor substrate 100 may be subjected to multiple ion implantation steps to form multiple P-type deep wells and N-type wells in the N-type doped epitaxial layer (Nepi) 110. The specific formation steps may be referred to as follows:

[0058] Step S101, perform a first ion implantation process on the semiconductor substrate 100 corresponding to the PMOS region, NMOS region, NLDMOS region, and PLDMOS region to form at least three P-type deep wells DPW in the low-voltage device region C and the high-voltage device region B;

[0059] Step S102: Perform a second ion implantation process on the semiconductor substrate 100 corresponding to the P-type deep well DPW to form a plurality of high-voltage N wells HVNW in the high-voltage device region B and a plurality of low-voltage N wells LVNW in the low-voltage device region C.

[0060] In this embodiment, as can be seen from the above steps S101 and S102, the MOS transistors in the high-voltage device region B and the low-voltage device region C are distinguished by being formed in different N-type wells. This is prior art and will not be described in detail in this invention.

[0061] Furthermore, after forming the N well LVNW in the above step S102, the present invention can also use an etching process to form a plurality of shallow trenches in the semiconductor substrate 100, and then fill each shallow trench with silicon dioxide to form the trench isolation structure 101 that isolates the SGT device region A, the low-voltage device region C, the high-voltage device region B, and each MOS transistor included in the low-voltage device region C and the high-voltage device region B.

[0062] In step S200, continue to refer to Figure 2a As shown, a gate trench 102, a pressure-resistant trench 103, and a first oxide layer 120, a source polysilicon 130, an isolation layer 140, a second oxide layer 150, and a gate polysilicon 160 filled in the gate trench 102 are formed in the semiconductor substrate 100 corresponding to the SGT device region A. Among them, the source polysilicon 130 also fills the pressure-resistant trench 103, the gate polysilicon 160 covers the surface of the isolation layer 140 and at least fills the remaining gate trench 102, and also extends to cover the source polysilicon 130 in the pressure-resistant trench 103 and the surfaces of the semiconductor substrates 100 corresponding to the low-voltage device region C and the high-voltage device region B. The second oxide layer 150 also extends to cover the surface of the semiconductor substrate 100 between adjacent trench isolation structures 101.

[0063] In this embodiment, before the above step S102, a hard mask layer (not shown) may be formed on the surface of the semiconductor substrate 100, and the hard mask layer covers the surfaces of the semiconductor substrate 100 corresponding to the entire low-voltage device region B and the high-voltage device region C, while exposing multiple places in the SGT device region A. Then, in the case of using this hard mask layer as a mask, multiple gate trenches 102 and a breakdown voltage trench 103 may be formed in the SGT device region A. The gate trenches 102 are used to form the SGT devices with an upper and lower structure in the SGT device region A, and the breakdown voltage trench 103 is used to form a breakdown voltage device serving as a field stop region in the SGT device region A to improve the breakdown voltage performance of the SGT device. The hard mask layer may be silicon dioxide, silicon nitride, or an ONO stacked structure composed of oxide-nitride-oxide. Exemplarily, in the embodiment of the present invention, the hard mask layer may be an ONO stacked structure.

[0064] Further, after forming multiple gate trenches 102 and a breakdown voltage trench 103 in the SGT device region A, a thick oxide layer with a certain thickness, that is, the first oxide layer 120, may be formed on the bottom and side walls of the gate trenches 102 and the breakdown voltage trench 103 by using a deposition process. Then, source polysilicon 130 is filled in the gate trenches 102 and the breakdown voltage trench 103 so that the top surface of the filling material in the filled gate trenches 102 and the breakdown voltage trench 103 is flush with the top surface of the semiconductor substrate 100. After that, a photoresist layer (not shown) covering the surfaces of the semiconductor substrate 100 corresponding to the breakdown voltage trench 103, the low-voltage device region C, and the high-voltage device region B is formed, and by using an etching process, the first oxide layer 120 and the source polysilicon 130 formed in the region corresponding to the gate trenches 102 in the SGT device region A that are not covered (exposed) by the photoresist layer are etched back to form an etched first oxide layer 120 and source polysilicon 130 with a flush surface within a partial height at the bottom of the shown gate process 102. After that, an isolation layer 140 made of silicon dioxide may be formed on the surface of the etched first oxide layer 120 and source polysilicon 130 with a flush surface (inside the gate trench 102), and the photoresist layer is removed. Then, a second oxide layer 150 is formed covering the side walls of the gate trench 102 with the isolation layer 140 as the bottom and extending to cover the surface of the other semiconductor substrate, that is, the surface of the semiconductor substrate 100 corresponding to the region between two adjacent trench isolation structures 101 in the low-voltage device region C. After that, gate polysilicon 160 is formed covering the surface of the isolation layer 140 and at least filling the remaining gate trenches 102, and also extending to cover the source polysilicon 130 in the breakdown voltage trench 103 and the surfaces of the semiconductor substrate 100 corresponding to the low-voltage device region B and the high-voltage device region C. Specifically, as Figure 2aAs shown. After the deposition process of the gate polysilicon 160, chemical mechanical polishing (CMP) process can be used to polish a part of its thickness.

[0065] It should be noted that in the embodiments of the present invention, all identifiers identifying the same film layer, no matter how they change, are identified by only one identifier. The purpose of this approach is to clearly identify each film layer and effectively distinguish it from other film layers. However, in other embodiments, it can also use different states of the same identifier. For example, the states of the same film layer after different semiconductor process flows can be identified in the ways such as 120, 120', 120", etc. The present invention does not make specific limitations on this.

[0066] In step S300, specifically referring to Figure 2b As shown, back-etch the gate polysilicon 160 until the remaining gate polysilicon 160 in the withstand voltage groove 103 and the gate trench 102 is flush with the surface of the remaining second oxide layer 150 after the back-etching.

[0067] In this embodiment, the inventor of the present invention found that during the process of back-etching the gate polysilicon 160, a part of the thickness of the second oxide layer 150 will also be back-etched, thus causing loss of the gate oxide layer (i.e., the second oxide layer 150) of the SGT device, as shown in Figure 2b the circled part D in. Therefore, this will cause problems such as leakage and low performance to the integrated SGT device formed. Based on this, the inventor of the present invention proposes that during the process of forming the gate oxide (i.e., the third oxide layer 180 formed in the subsequent steps) of the MOS device in the region by removing the thick oxide (i.e., the second oxide layer 150 covering this region) in the low-voltage device region C, a thin oxide layer is simultaneously formed on the surface in the SGT device, so as to compensate for the damage of the gate oxide of the SGT device caused by the error during the etching process of forming the gate polysilicon of the SGT device, and thus avoid the problem of leakage of the SGT device, that is, improve the performance of the device.

[0068] Moreover, through the above steps, it can be seen that in the embodiments of the present invention, a method for synchronously producing SGT discrete devices and BCD power IC devices on the same chip is proposed, thus avoiding the problem of relatively large parasitic Rs and Rc between the two caused by separately forming the devices step by step and then bonding and connecting them in the prior art, and at the same time providing the performance matching degree between the SGT device and the BCD device.

[0069] In step S400, specifically referring to Figure 2c and Figure 2dAs shown, a third oxide layer 180 is formed on the surface of the semiconductor substrate 100. The third oxide layer 180 covers the surface of the remaining second oxide layer 150 and extends to cover the surface of the semiconductor substrate 100 corresponding to the region between two adjacent trench isolation structures 101 in the low-voltage device region C.

[0070] In this embodiment, specifically, first, as Figure 2c shown, a photoresist layer 170 is formed on the structure formed in the above step S300. The photoresist layer 170 exposes the semiconductor substrate 100 corresponding to the low-voltage device region C. Then, an etching process for removing the second oxide layer 150 in this region is performed. For example, it can be a dry etching process, a wet etching process, or a mixed process of the two. After that, the photoresist layer 170 is removed, and the third oxide layer 180 is formed. Specifically, the process can be described by the following steps:

[0071] Step S401, specifically as Figure 2c shown, a photoresist layer 170 that shields the semiconductor substrate 100 corresponding to the SGT device region A and the high-voltage device region B and exposes the semiconductor substrate 100 corresponding to the low-voltage device region C is formed. Using the photoresist layer 170 as a mask, the second oxide layer 150 formed in the low-voltage device region C is etched and removed;

[0072] Step S402, a third oxide layer 180 is formed on the surface of the semiconductor substrate 100 exposed between two adjacent trench isolation structures 101 in the low-voltage device region C from which the second oxide layer 150 has been removed. Among them, the photoresist layer 170 needs to be removed first in this process, and the process for forming the third oxide layer 180 can include a thermal oxidation process. In other embodiments, it can also be a deposition process. Since the third oxide layer 180 formed in the present invention not only covers the surface of the semiconductor substrate 100 between two adjacent trench isolation structures 101 in the low-voltage device region C and thus serves as the gate oxide of the MOS transistor device to be formed in this region, but also the third oxide layer 180 will be covered in the SGT device region A during this step process, thereby compensating for the damage to the gate oxide of the SGT device caused by the error during the etching process when forming the gate polysilicon 160 of the SGT device, and thus avoiding the problem of leakage of the SGT device. That is, the performance of the device is improved, achieving the object of the present invention.

[0073] Furthermore, in the embodiment of the present invention, after the third oxide layer 180 is formed, the manufacturing method may further include the following steps:

[0074] Step S403: Form a gate material layer (not shown). The gate material layer (not shown) covers the entire surface of the semiconductor substrate 100, and the gate material layer is etched to form corresponding gate structures in the low-voltage device region C and the high-voltage device region B.

[0075] In the embodiment of the present invention, the formation process in this step is the prior art, so the present invention will not elaborate on it specifically. Exemplarily, in the embodiment of the present invention, the materials of the isolation layer, the first oxide layer, the second oxide layer, and the third oxide layer may all include silicon dioxide.

[0076] In summary, in the manufacturing method of a semiconductor integrated device provided by the present invention, during the process of forming the gate oxide of the MOS device in the region by removing the thick oxide in the low-voltage device region, a thin oxide layer is simultaneously formed on the surface of the SGT device, thereby compensating for the damage to the gate oxide of the SGT device caused by the error during the etching process of forming the gate polysilicon of the SGT device, and further avoiding the problem of leakage of the SGT device, that is, improving the performance of the device. Moreover, the present invention provides a method for synchronously producing SGT isolation devices and BCD power IC devices on the same chip, thereby avoiding the problem of relatively large parasitic Rs and Rc between the two caused by separately forming the two devices step by step and then bonding them together in the prior art, and at the same time improving the performance matching degree of the SGT device and the BCD device.

[0077] It should be noted that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the disclosed technical content, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

[0078] It should also be understood that unless specifically stated or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish each component, element, step, etc. in the specification, rather than to represent the logical relationship or sequential relationship between each component, element, step, etc.

[0079] It should also be recognized that the terminology described herein is only used to describe specific embodiments and is not intended to limit the scope of the present invention. It must be noted that the singular forms "a" and "an" used herein and in the appended claims include plural referents unless the context clearly dictates otherwise. For example, the recitation of "a step" or "a device" means the recitation of one or more steps or devices and may include sub-steps and sub-devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" definition unless the context clearly dictates otherwise. In addition, the implementation of the methods and / or devices in the embodiments of the present invention may include performing the selected tasks manually, automatically, or in combination.

Claims

1. A method for manufacturing a semiconductor integrated device, characterized in that: At least the following steps are included: A semiconductor substrate is provided, comprising an SGT device region, a low-voltage device region, and a high-voltage device region arranged in sequence, wherein the low-voltage device region comprises a PMOS region and an NMOS region, and the high-voltage device region comprises an NLDMOS region and a PLDMOS region. A plurality of trench isolation structures for isolating device structures in the SGT device region, the low-voltage device region, and the high-voltage device region are formed on the semiconductor substrate, and top surfaces of the trench isolation structures are higher than a top surface of the semiconductor substrate. A gate trench, a voltage-withstanding trench, and a first oxide layer, a source polysilicon, an isolation layer, a second oxide layer, and a gate polysilicon filled in the gate trench are formed in the semiconductor substrate corresponding to the SGT device region, wherein the source polysilicon also fills the voltage-withstanding trench, the gate polysilicon covers the surface of the isolation layer and at least fills the remaining gate trench, and further extends to cover the source polysilicon in the voltage-withstanding trench and the surface of the semiconductor substrate corresponding to the low-voltage device region and the high-voltage device region, and the second oxide layer further extends to cover the surface of the semiconductor substrate between adjacent trench isolation structures; Etching back the gate polysilicon until the remaining gate polysilicon in the voltage-withstand groove and the gate trench is flush with the surface of the second oxide layer remaining after the back etching; removing the first oxide layer located in the low-voltage device area; A third oxide layer is formed on the surface of the semiconductor substrate, the third oxide layer covers the surface of the remaining second oxide layer and extends to cover the surface of the semiconductor substrate corresponding to two adjacent trench isolation structures in the low-voltage device area.

2. The method for manufacturing a semiconductor integrated device according to claim 1, wherein: During the process of etching back the gate polysilicon, a portion of the second oxide layer will also be etched back, thereby causing loss of the gate oxide layer of the SGT device.

3. The method for manufacturing a semiconductor integrated device according to claim 1, wherein: After forming the gate trench and the voltage-withstand trench, the manufacturing method further includes: Performing a first ion implantation process on the semiconductor substrate corresponding to the PMOS region, the NMOS region, the NLDMOS region, and the PLDMOS region to form at least three P-type deep wells in the low-voltage device region and the high-voltage device region; A second ion implantation process is performed on the semiconductor substrate corresponding to the P-type deep well to form a plurality of high-voltage N-wells in the high-voltage device region and a plurality of low-voltage N-wells in the low-voltage device region.

4. The method for manufacturing a semiconductor integrated device according to claim 3, wherein: The step of forming the first oxide layer, source polysilicon, an isolation layer, a second oxide layer and gate polysilicon in the gate trench comprises: forming a first oxide layer on inner walls of the voltage-withstand groove and the gate trench, and after forming the first oxide layer, filling the voltage-withstand groove and the gate trench with source polysilicon so that a top surface of the filled source polysilicon is flush with an upper surface of the semiconductor substrate; The surface of the semiconductor substrate corresponding to the voltage-resistant groove is masked, and the source polysilicon and the first oxide layer in the gate trench are etched back to form a shield gate and a thick oxide layer of the SGT device area in the gate trench, and then an isolation layer is formed on the top surface of the source polysilicon and the first oxide layer after the back etching, and a second oxide layer covering the surface of the isolation layer and the inner wall of the remaining gate trench, wherein the second oxide layer also extends to cover the surface of the remaining exposed semiconductor substrate.

5. The method for manufacturing a semiconductor integrated device according to claim 4, wherein: The remaining exposed semiconductor substrate surface covered by the second oxide layer includes: a surface of the semiconductor substrate corresponding to two adjacent trench isolation structures in the low-voltage device region.

6. The method for manufacturing a semiconductor integrated device according to claim 5, wherein: After etching back the gate polysilicon and before forming the third oxide layer, the manufacturing method further includes: forming a photoresist layer that shields the semiconductor substrate corresponding to the SGT device region and the high-voltage device region and exposes the semiconductor substrate corresponding to the low-voltage device region, and using the photoresist layer as a mask to etch away the second oxide layer formed in the low-voltage device region; A third oxide layer is formed on the surface of the semiconductor substrate exposed between two adjacent trench isolation structures in the low-voltage device area from which the second oxide layer has been removed.

7. The method for manufacturing a semiconductor integrated device according to claim 6, wherein: The process of forming the third oxide layer includes a thermal oxidation process.

8. The method for manufacturing a semiconductor integrated device according to claim 1, wherein: The steps of forming the trench isolation structure include: A plurality of shallow trenches are formed in the semiconductor substrate and filled to form the trench isolation structure for isolating the SGT device area, the low voltage device area, the high voltage device area and the MOS transistors contained in the low voltage device area and the high voltage device area.

9. The method for manufacturing a semiconductor integrated device according to claim 1, wherein: After forming the third oxide layer, the manufacturing method further includes: A gate material layer is formed, the gate material layer covering the entire surface of the semiconductor substrate, and the gate material layer is etched to form corresponding gate structures in the low-voltage device area and the high-voltage device area.

10. The method for manufacturing a semiconductor integrated device according to claim 1, wherein: The isolation layer, the first oxide layer, the second oxide layer and the third oxide layer are made of silicon dioxide.

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