Pixel sensor array

Abstract

A polysilicon well is formed at a cross-crossing portion between a plurality of pixel sensors in the pixel sensor array. In addition, a portion of the underlying oxide layer between the polysilicon well and a semiconductor layer of the pixel sensor array is thinner than others. The polysilicon well and the thinner oxide layer may reduce the likelihood and / or extent of lateral etching occurring during etching the semiconductor layer to form a recess that accommodates the BDTI structure of the pixel sensor array. Furthermore, the bottom of the BDTI structure is surrounded by a polysilicon well such that a bias voltage can be applied to the BDTI structure via the polysilicon well, while passivating damage that may occur in the semiconductor layer around the bottom of the BDTI structure.

Description

Technical Field

[0001] The utility model relates to a pixel sensor array. Background Art

[0002] A complementary metal oxide semiconductor (CMOS) image sensor (CIS) may include multiple pixel sensors. A CIS pixel sensor may include a transfer gate transistor (TGT), which may include a photodiode configured to convert incident light photons into a photocurrent composed of electrons, and a transfer gate configured to control the flow of the photocurrent between the photodiode and a drain region. The drain region may be configured to receive the photocurrent so that it can be measured and / or transmitted to other regions of the CIS. Utility Model Content

[0003] The utility model provides a pixel sensor array, comprising a plurality of pixel sensors. The pixel sensor array includes a backside deep trench isolation structure laterally surrounding the plurality of pixel sensors, wherein the backside deep trench isolation structure completely extends through a semiconductor layer between a front side and a back side of the semiconductor layer of the pixel sensor array, and wherein a portion of the backside deep trench isolation structure extends into a first polysilicon well below the semiconductor layer and / or is surrounded by the first polysilicon well.

[0004] The present invention provides a method for forming a pixel sensor array, comprising forming a plurality of polysilicon wells above the front side of a semiconductor layer of the pixel sensor array. The method comprises forming an oxide layer on the front side of the semiconductor layer and on the plurality of polysilicon wells. The method comprises forming a plurality of spacers around the sidewalls of the plurality of polysilicon wells. The method comprises forming a contact structure etch stop layer above the oxide layer and above the plurality of spacers. The method comprises forming a plurality of trenches through the semiconductor layer and extending into the plurality of polysilicon wells, wherein the plurality of trenches extend from the back side of the semiconductor layer to the front side of the semiconductor layer. The method comprises forming backside deep trench isolation structures in the plurality of trenches.

[0005] The utility model provides a pixel sensor array, comprising a plurality of pixel sensors. The pixel sensor array includes a backside deep trench isolation structure extending completely through a semiconductor layer between a front side and a back side of the semiconductor layer of the pixel sensor array, wherein a bottom portion of the backside deep trench isolation structure extends into one or more dielectric liners below the semiconductor layer or is surrounded by the one or more dielectric liners, and wherein an annular polysilicon well is disposed around the bottom portion of the backside deep trench isolation structure in the one or more dielectric liners.

[0006] Based on the above, polysilicon wells are formed at the intersections between the plurality of pixel sensors in the pixel sensor array. Furthermore, the thickness of the underlying oxide layer between the polysilicon well and the semiconductor layer of the pixel sensor array can be thinner than its thickness elsewhere. The polysilicon well and the thinner oxide layer can reduce the probability and / or extent of lateral etching that occurs during etching of the semiconductor layer to form the recessed backside deep trench isolation structure that accommodates the pixel sensor array. Furthermore, the bottom of the backside deep trench isolation structure extends into the polysilicon well, allowing a bias voltage to be applied to the backside deep trench isolation structure through the polysilicon well to passivate damage that may occur to the portion of the semiconductor layer around the bottom of the backside deep trench isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of an exemplary pixel sensor described herein.

[0008] Figure 2A and Figure 2B is a schematic diagram of an example implementation of a pixel sensor array described herein.

[0009] Figures 3A to 3G is a schematic diagram of an example implementation of a pixel sensor array described herein.

[0010] Figure 4 is a schematic diagram of an example implementation of a pixel sensor array described herein.

[0011] Figures 5A to 5J is a schematic diagram of an example embodiment of a method for forming an example embodiment of a pixel sensor array described herein.

[0012] Figure 6A and Figure 6B is a schematic diagram of an example implementation of a pixel sensor array described herein.

[0013] Figures 7A to 7G is a schematic diagram of an example embodiment of a method for forming an example embodiment of a pixel sensor array described herein.

[0014] Figure 8A and Figure 8B is a schematic diagram of an example implementation of a pixel sensor array described herein.

[0015] Figures 9A to 9G is a schematic diagram of an example embodiment of a method for forming an example embodiment of a pixel sensor array described herein.

[0016] 10A to 10C is a schematic diagram of an example implementation of a pixel sensor array described herein.

[0017] Figures 11A to 11C is a schematic diagram of an example implementation of a pixel sensor array described herein.

[0018] 12A to 12C is a schematic diagram of an example implementation of a pixel sensor array described herein.

[0019] Figure 13 is a flow chart of an exemplary method for forming a pixel sensor array as described herein. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for implementing the different features of the provided objects. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. Such repetition is for the purpose of brevity and clarity and does not itself represent a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0022] Generally speaking, pixel sensors in a pixel sensor array are separated from each other by trench isolation structures. For example, a backside deep trench isolation (BDTI) structure can electrically and / or optically isolate pixel sensors in a pixel sensor array from each other. The BDTI structure can include a network of trenches arranged around the pixel sensors, consisting of staggered trenches. Some regions of the BDTI structure (referred to as non-staggered portions) can surround one or two pixel sensors in the sensor array or extend between two pixel sensors. Other regions of the BDTI structure (referred to as staggered portions) can be located at the intersections between the corners of three or more pixel sensors in the pixel sensor array.

[0023] Due to the larger critical dimension (CD) between the photodiode regions, the etch rate for etching the recesses in the cross-staggered portion of the BDTI structure is generally greater than the etch rate for etching the recesses in the non-cross-staggered portion of the BDTI structure. This can be attributed to the larger diagonal spacing between the photodiode regions in the cross-staggered portion than the lateral spacing between the photodiode regions in the non-cross-staggered portion. The larger feature size in the cross-staggered portion results in greater trench depth loading. In some examples, a plasma etch can be performed to form the recesses, wherein ions in a plasma are used to bombard the target material to etch the recesses. Due to the larger feature size in the cross-staggered portion, radicals in the plasma can more easily enter the sidewalls and bottom of the recesses in the cross-staggered portion, resulting in lateral etching when etching through the semiconductor layer and / or through the underlying oxide layer.

[0024] This lateral etching can damage the crystal structure of the photodiode region of the pixel sensor, thereby increasing dark current in the photodiode region. Dark current can be current in the photodiode region caused by factors other than incident light. For example, damage to the crystal structure of the photodiode region can be a factor that causes dark current. The generation of dark current may increase noise and cause other defects in images and / or video captured based on the photocurrent generated by the photodiode region. For example, dark current can abnormally increase the photocurrent generated by the photodiode region, which can degrade low-light performance and / or cause some pixels in the image or video to appear as white pixels (while pixels) or hot pixels (hot pixels).

[0025] In some embodiments described herein, polysilicon wells are formed at intersections between multiple pixel sensors in a pixel sensor array. Furthermore, the underlying oxide layer is thinner between the polysilicon well and the semiconductor layer of the pixel sensor array than in other portions. The polysilicon well and the thinner oxide layer reduce the likelihood and / or extent of lateral etching during the etching of the semiconductor layer to form the recessed BDTI structure housing the pixel sensor array. Furthermore, the semiconducting properties of the polysilicon well enable a bias voltage to be applied to the BDTI structure through the polysilicon well.

[0026] Compared to another pixel sensor array that does not include the polysilicon well, the pixel sensor array of the disclosed embodiments can reduce dark current in the photodiode region due to less and / or lower levels of lateral etching at the cross-intersection. Furthermore, applying a bias voltage to the BDTI structure through the polysilicon well can passivate potential damage to the photodiode region by increasing the hole density in the portion of the semiconductor layer surrounding the BDTI structure (compared to when no bias voltage is applied), thereby further reducing dark current in the pixel sensor array. Furthermore, the polysilicon well provides a larger process window for etching the recess that accommodates the BDTI structure, which reduces the process complexity of forming the BDTI structure.

[0027] Figure 1 FIG1 is a schematic diagram of an exemplary pixel sensor 100 described herein. Pixel sensor 100 may include a frontside pixel sensor (e.g., a pixel sensor configured to receive photons of incident light from the front side of the sensor die), a backside pixel sensor (e.g., a pixel sensor configured to receive photons of incident light from the back side of the sensor die), and / or another type of pixel sensor. Pixel sensor 100 may be electrically connected to a power supply voltage (Vdd) 102 and an electrical ground 104.

[0028] The pixel sensor 100 includes a sensing region 106 that can be configured to sense and / or concentrate incident light (e.g., light directed toward the pixel sensor 100). The pixel sensor 100 also includes a control circuitry region 108. The control circuitry region 108 is electrically connected to the sensing region 106 and configured to receive a photocurrent 110 generated by the sensing region. Furthermore, the control circuitry region 108 is configured to transmit the photocurrent 110 from the sensing region 106 to downstream circuitry, such as an amplifier or an analog-to-digital (AD) converter.

[0029] Sensing region 106 includes a photodiode 112. Photodiode 112 absorbs and collects photons of incident light and generates a photocurrent 110 based on the absorbed photons. The magnitude of photocurrent 110 depends on the amount of light collected by photodiode 112. Therefore, photons collected by photodiode 112 generate an accumulation of charge, which represents the intensity or brightness of the incident light. For example, a greater amount of charge represents a greater intensity or brightness of the incident light, while a smaller amount of charge represents a lower intensity or brightness of the incident light.

[0030] The photodiode 112 is electrically connected to the source of a transmission gate 114 in the control circuitry area 108. The transmission gate 114 is configured to control the transmission of the photocurrent 110 from the photodiode 112. Based on the selective switching of the gate of the transmission gate 114, the photocurrent 110 is provided from the source of the transmission gate 114 to the drain of the transmission gate 114. The transmission voltage (V tx ) 116 is applied to the transfer gate 114 to selectively switch the gate of the transfer gate 114. In some embodiments, the transfer voltage 116 applied to the transfer gate 114 causes a channel to form between the source and drain of the transfer gate 114, which allows the photocurrent 110 to be transmitted from the source to the drain along this conductive channel. In some embodiments, removing the transfer voltage 116 from the transfer gate 114 (or in the absence of the transfer voltage 116) eliminates the conductive channel, preventing the photocurrent 110 from flowing from the source to the drain.

[0031] The control circuit system area 108 further includes a reset gate 118. The reset gate 118 is electrically connected to the power supply voltage 102. rst ) 120 to control the reset gate 118. The transfer gate 114 and the reset gate 118 can be electrically coupled to a floating diffusion node 122. The reset voltage 120 can be applied to the reset gate 118 to pull the drain of the transfer gate 114 to a high voltage (e.g., to the power supply voltage 102) before turning on the transfer gate 114 to transfer the photocurrent 110 from the photodiode 112 to the floating diffusion node 122, thereby resetting the floating diffusion node 122 (e.g., by extracting any residual charge from the floating diffusion node 122).

[0032] Photocurrent 110 can be used to apply a floating diffusion voltage (Vfd) to a source follower gate 124 of control circuitry area 108. This allows photocurrent 110 to be observed without removing photocurrent 110 or discharging photocurrent 110 from floating diffusion node 122. Reset gate 118 can instead be used to remove photocurrent 110 or discharge photocurrent 110 from floating diffusion node 122.

[0033] Source-follower gate 124 acts as a high impedance amplifier for pixel sensor 100. It provides voltage-to-current conversion for the floating diffusion voltage. The output of source-follower gate 124 is electrically connected to column select gate 126, which is configured to control the path of photocurrent 110 to external circuitry. Column select gate 126 is controlled by selectively applying a select voltage (Vdi) 128 to its gate. This allows photocurrent 110 to flow to output 130 of pixel sensor 100.

[0034] As mentioned above, Figure 1 This is provided as an example only. Other examples may differ from the reference Figure 1 Examples described.

[0035] Figure 2A and Figure 2B is a schematic diagram of an example implementation 200 of a pixel sensor array 202 as described herein. Figure 2A A top view of the pixel sensor array 202 is shown, and Figure 2B A schematic perspective view of pixel sensor array 202 is shown. In some embodiments, pixel sensor array 202 may be included in image sensor 204. Image sensor 204 may include a CMOS image sensor (CIS), a back-illuminated CIS, a front-illuminated CIS, or another type of image sensor.

[0036] like Figure 2A As shown, the pixel sensor array 202 may include a plurality of pixel sensors 100. Figure 2A As further shown, the pixel sensors 100 can be arranged in a grid. In some embodiments, the pixel sensors 100 are square (e.g., Figure 2A In some embodiments, the pixel sensor 100 includes other shapes, such as a rectangle, a circle, an octagon, a diamond, and / or other shapes.

[0037] The pixel sensors 100 may be configured to sense and / or collect incident light (e.g., light directed toward the pixel sensor array 202). For example, the pixel sensors 100 may absorb and collect photons of the incident light in a photodiode. The photons collected in the photodiode may generate a charge representing the intensity or brightness of the incident light (e.g., a larger amount of charge may correspond to incident light of higher intensity or brightness, while a smaller amount of charge may correspond to incident light of lower intensity or brightness). In some embodiments, at least a subgroup of the pixel sensors 100 may be configured to sense incident light in the visible light band. In some embodiments, at least a subgroup of the pixel sensors 100 may be configured to sense incident light in the infrared light band or the near-infrared light band.

[0038] In some embodiments, the dimensions (e.g., width or radius) of pixel sensor 100 range from approximately 0.5 μm to approximately 2 μm. In some embodiments, the dimensions (e.g., width or radius) of pixel sensor 100 are less than approximately 1 μm. In these examples, pixel sensor 100 may be referred to as a sub-micron pixel sensor. Sub-micron pixel sensors may reduce the pixel sensor pitch (e.g., the distance between adjacent pixel sensors) in pixel sensor array 202, thereby increasing the pixel sensor density in pixel sensor array 202 (and thereby improving the performance of pixel sensor array 202).

[0039] The pixel sensors 100 can be electrically and optically isolated from each other via the BDTI structure 206 in the pixel sensor array 202. The BDTI structure 206 can include a plurality of interconnected and staggered trenches filled with one or more materials, such as dielectric materials (e.g., oxygen-containing materials, high-k dielectric materials), polysilicon materials, and / or other types of materials. Figure 2A As shown, the trenches of the BDTI structure 206 may be disposed around the edges of the pixel sensor 100 such that the BDTI structure 206 surrounds the pixel sensor 100 (and the photodiode and drain region included therein).

[0040] like Figure 2B As shown, the portion of BDTI structure 206 located between one or two pixel sensors 100 may be referred to as a non-interleaved portion 208 of BDTI structure 206. The portion of BDTI structure 206 interleaved between corners of three or more pixel sensors 100 may be referred to as an interleaved portion 210 of BDTI structure 206.

[0041] The BDTI structure 206 can extend into (and be included in) the substrate in which the pixel sensor 100 is formed to surround the photodiodes and other structures of the pixel sensor 100 in the substrate. As described above, the pixel sensor array 202 can be included in a BSICIS. In these examples, the BDTI structure 206 can be formed from the backside of the substrate of the pixel sensor array 202.

[0042] Figure 2A and Figure 2BReference section AA is further illustrated for use in one or more of the schematic diagrams herein. Section AA is a cross-section through the plurality of pixel sensors 100 of pixel sensor array 202. This cross-section extends through one or more non-cross-interleaved portions 208 and one or more cross-interleaved portions 210 of BDTI structure 206. Schematic diagrams of this cross-section are depicted in the following figures. In some of the figures, reference numbers may be omitted for some components or features described herein to avoid obscuring other components or features and to facilitate depiction of the other components or features.

[0043] As mentioned above, Figure 2A and Figure 2B This is provided as an example only. Other examples may differ from the reference Figure 2A and Figure 2B Examples described.

[0044] Figures 3A to 3G FIG. 3 is a schematic diagram of an example implementation 300 of the pixel sensor array 202 described herein. Figure 3A As shown in the perspective diagram of FIG, pixel sensor array 202 includes polysilicon wells 302 that conform to the grid shape of BDTI structure 206. Polysilicon wells 302 are configured to reduce or minimize etching damage that may be caused to pixel sensor array 202 during the formation of BDTI structure 206. As another and / or alternative purpose, polysilicon wells 302 are used to apply a bias voltage around BDTI structure 206 to increase the hole density around BDTI structure 206, thereby electrically passivating etching damage that may be caused to pixel sensor array 202 during the formation of BDTI structure 206.

[0045] like Figure 3A As further shown, dielectric spacers 304 may be disposed on and / or around the sidewalls of the polysilicon well 302. The dielectric spacers 304 may include one or more dielectric materials, such as silicon oxide (SiOx, such as silicon dioxide), silicon nitride (SixNy), silicon carbide (SiCx), hafnium oxide (HfOx), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide, and / or other dielectric materials.

[0046] like Figure 3AAs further shown, a contact etch stop layer (CESL) 306 may be disposed above the polysilicon well 302 and the dielectric spacer 304. For simplicity, the CESL 306 is Figure 3A CESL 306 may include one or more dielectric materials, such as silicon oxide (SiOx, e.g., silicon dioxide), silicon nitride (SixNy), silicon carbide (SiCx), hafnium oxide (HfOx), silicon oxynitride (SiON), tetraethylorthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide, and / or other dielectric materials.

[0047] like Figure 3A As further shown, in the example embodiment 300 of the pixel sensor array 202, a polysilicon well 302, a dielectric spacer 304, and a CESL 306 are included in the non-cross-staggered portion 208 and the cross-staggered portion 210 of the BDTI structure 206. The polysilicon well 302, the dielectric spacer 304, and the CESL 306 can be formed on the front side of the substrate of the pixel sensor array 202.

[0048] like Figure 3B As shown in another perspective diagram of pixel sensor array 202, electrode 308 may extend from and be coupled to polysilicon well 302. Electrode 308 is used to apply a bias voltage to polysilicon well 302 to increase the hole density around BDTI structure 206 and electrically passivate etching damage that may be caused to pixel sensor array 202 during the formation of BDTI structure 206. The bias voltage may be provided by a voltage source provided via a back-end-of-line (BEOL) region of an image sensor including pixel sensor array 202.

[0049] Figure 3C A cross-sectional schematic diagram of an example implementation 300 of pixel sensor array 202 is depicted. Figure 3C The cross-sectional diagram in the figure is along Figure 2A and Figure 2B As shown in the section AA in Figure 3CAs shown, pixel sensors 100 of pixel sensor array 202 may be formed in and / or on semiconductor layer 310, where semiconductor layer 310 may be a substrate of pixel sensor array 202. Semiconductor layer 310 may include a silicon substrate, a substrate composed of a silicon-containing material, a III-V semiconductor material substrate (e.g., a gallium arsenide (GaAs) substrate), a germanium substrate, a silicon-germanium substrate, or other types of semiconductor substrates.

[0050] Pixel sensor 100 may include a photodiode 112 and a floating diffusion junction 122 within a semiconductor layer 310 between BDTI structures 206. Photodiode 122 may include multiple regions of semiconductor layer 310 doped with various ion types to form a PN junction or a PIN junction (e.g., a junction between a P-type portion, an intrinsic (undoped) portion, and an N-type portion). For example, semiconductor layer 310 may be doped with N-type dopants to form one or more N-type regions of photodiode 112, and semiconductor layer 310 may be doped with P-type dopants to form a P-type region of photodiode 112. Photodiode 112 may be configured to absorb photons of incident light (e.g., visible light or near-infrared light). Based on the absorbed photons, photodiode 112 accumulates charge (referred to as photocurrent 110) due to the photoelectric effect. The photons may bombard photodiode 112, causing electrons and holes to be emitted into photodiode 112, resulting in the generation of photocurrent 110.

[0051] Floating diffusion node 122 may include a heavily doped N-type region (N+ doped region) of semiconductor layer 310. In some embodiments, a drain extension region is included in semiconductor layer 310 adjacent to floating diffusion node 122. The drain extension region may include a lightly doped N-type region that facilitates transfer of photocurrent 110 from photodiode 112 to floating diffusion node 122.

[0052] Pixel sensor 100 may include a transfer gate 114 on the front side of semiconductor layer 310. Transfer gate 114 may be configured to selectively control photocurrent transmission from photodiode 112 of pixel sensor 100 to floating diffusion node 122 of pixel sensor 100 by controlling the conductivity of semiconductor layer 310 between photodiode 112 and floating diffusion node 122.

[0053] like Figure 3CAs further shown, the BDTI structure 206 can extend through the semiconductor layer 310. Specifically, the BDTI structure 206 can extend completely through the semiconductor layer 310 from the front side of the semiconductor layer 310 to the back side of the semiconductor layer 310. Accordingly, the BDTI structure 206 can be referred to as a full BDTI (f-BDTI) structure. The BDTI structure 206 can be formed from the back side of the semiconductor layer 310 during backside processing of the pixel sensor array 202. The back side of the semiconductor layer 310 can be the side of the semiconductor layer 310 opposite the front side where the transfer gate 114 is located.

[0054] The BDTI structure 206 may include an extension of the dielectric material 312 between the dielectric material 312 and the semiconductor layer 310 and a dielectric liner 314. The dielectric liner 314 may be disposed on the sidewalls and bottom surface of the BDTI structure 206 and may be formed as an antireflective coating (ARC) and / or further improve electrical and / or optical isolation of the pixel sensor 100. In some embodiments, the dielectric material 312 includes silicon oxide (SiOx, such as silicon dioxide), silicon nitride (SixNy), silicon carbide (SiCx), hafnium oxide (HfOx), silicon oxynitride (SiON), tetraethylorthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide, and / or other dielectric materials. In some embodiments, the dielectric liner 314 may include a high-k dielectric material, such as silicon nitride (SixNy), hafnium oxide (HfOx), and / or other high-k dielectric materials.

[0055] like Figure 3C As further shown, the BDTI structure 206 may extend or protrude from the front side of the semiconductor layer 310 and into the polysilicon well 302. The polysilicon well 302 provides a buffer zone for over-etching when forming the recess to accommodate the BDTI structure 206. The polysilicon well 302 (or the combination of the polysilicon well 302 and the CESL 306) can increase the process margin for over-etching because the polysilicon well 302 (or the combination of the polysilicon well 302 and the CESL 306) can tolerate a larger amount of over-etching than using the CESL 306 alone, which increases the likelihood that the recess for accommodating the BDTI structure 206 will completely penetrate the semiconductor layer 310.

[0056] As shown in the enlarged view of the non-cross-interleaved portion 208 of the BDTI structure 206 Figure 3E and an enlarged view of the cross-interlaced portion 210 Figure 3F As shown, the etch depth of the recess accommodating the BDTI structure 206 may be greater in the cross-staggered portion 210 than in the non-cross-staggered portion 208. As described above, this may be attributed to the greater etch load in the cross-staggered portion 210 than in the non-cross-staggered portion 208. Accordingly, the distance 316 between the bottom of the BDTI structure 206 and the bottom of the polysilicon well 302 in the non-cross-staggered portion 208 may be greater than the distance 318 between the bottom of the BDTI structure 206 and the bottom of the polysilicon well 302 in the cross-staggered portion 210.

[0057] The thickness of the polysilicon well 302 is about to about To allow for over-etching in the non-cross-interlaced portion 208 and the cross-interlaced portion 210. Furthermore, if the thickness of the polysilicon well 302 is less than about This may cause self-aligned implant tuning and device failure in the pixel sensor array 202. In addition, if the thickness of the polysilicon well 302 is greater than about However, other thicknesses of the polysilicon well 302 (at about to about Thickness ranges outside the range of ) are still within the scope of the present disclosure.

[0058] like Figure 3C As further shown, dielectric spacers 304 may be located on the sidewalls of the polysilicon well 302. CESL 306 may cover the dielectric spacers 304 and be located above the top surface of the polysilicon well 302 (or, in another perspective, below the bottom surface of the polysilicon well 302). In some embodiments, the thickness of CESL 306 below the polysilicon well 302 is about 1000 Å. to about If the thickness of CESL 306 is less than about The CESL 306 cannot provide sufficient etching barrier when forming the contact structure of the floating diffusion node 122. In other words, if the thickness of the CESL 306 is at least about This can provide sufficient etching barrier when forming the contact structure of the floating diffusion node 122. In addition, if the thickness of the CESL 306 exceeds about Under-etching may occur when forming the contact structure of the floating diffusion node 122. In other words, if the thickness of the CESL 306 is about or thinner, the possibility of under-etching is reduced. However, other thicknesses of CESL306 (at about to about Thickness ranges outside the range of ) are still within the scope of the present disclosure.

[0059] like Figure 3C As further shown, additional dielectric layers may be disposed over the front side of the semiconductor layer 310 in the non-cross-interleaved portions 208 and the cross-interleaved portions 210. For example, an oxide layer 320 may be disposed between the semiconductor layer 310 and the CESL 306. Furthermore, the oxide layer 320 may be disposed between the semiconductor layer 310 and the polysilicon well 302. In some embodiments, the oxide layer 320 may be located between the polysilicon well 302 and the dielectric spacer 304 and / or between the bottom of the polysilicon well 302 and the CESL 306. The oxide layer 320 may include an oxygen-containing material, such as hafnium oxide (HfOx), silicon oxynitride (SiON), and / or other oxygen-containing dielectric materials.

[0060] The thickness of the portion of the oxide layer 320 between the semiconductor layer 310 and the polysilicon well 302 can be thinner than the thickness of other portions of the oxide layer 320. In other words, the oxide layer 320 can have a thinner portion between the semiconductor layer 310 and the polysilicon well 302 to reduce lateral etching in the oxide layer 320 (and associated damage to the oxide layer 310) when overetching occurs during formation of the recess to accommodate the BDTI structure 206. Since the etch selectivity between the polysilicon well 302 and the semiconductor layer 310 is smaller than the etch selectivity between the semiconductor layer 310 and the oxide layer 320, the polysilicon well 302 can facilitate faster overetching, thereby further reducing lateral etching (and associated damage to the oxide layer 310). In particular, if the oxide layer 320 has a greater thickness in the recess used to etch the BDTI structure 206, the lower etch rate of the oxide layer 320 can result in a greater amount of lateral etching of the oxide layer 320. The polysilicon well 302 can help reduce the thickness of the oxide layer 320 in the recess used to etch the BDTI structure 206 while still providing a sufficient over-etch buffer without the need for an additional mask layer, thereby reducing lateral etching in the oxide layer 320. Thus, the provision of the polysilicon well 302 and the thinner thickness of the oxide layer 320 formed between the polysilicon well 302 and the semiconductor layer 310 can allow the pixel sensors 100 of the pixel sensor array 202 to have lower dark current.

[0061] To further reduce the dark current of the pixel sensors 100 of the pixel sensor array 202, a bias voltage 322 can be applied to the polysilicon well 302 (e.g., applied to the polysilicon well 302 via the electrode 308). Applying the bias voltage 322 can cause a region 324 of higher hole density to form around the bottom of the BDTI structure 206 in the semiconductor layer 310. This region 324 can passivate damage in the semiconductor layer 310 caused by the lateral etched region 326 in the BDTI structure 206.

[0062] In some embodiments, another oxide layer 328 (eg, a remote plasma oxide (RPO) layer) may be disposed between the dielectric spacer 304 and the CESL 306 and / or between the oxide layer 320 and the CESL 306 .

[0063] like Figure 3C As further shown, a buffer layer 330 may be disposed on the back side of the semiconductor layer 310. The buffer layer 330 may include silicon oxide (SiOx, such as silicon dioxide), silicon nitride (SixNy), silicon carbide (SiCx), hafnium oxide (HfOx), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide, and / or other dielectric materials.

[0064] The metal grid 332 may be embedded in the buffer layer 330. The metal grid 322 may be configured to confine light in the pixel, which results in reduced optical crosstalk between the pixel sensors 100. The metal grid 322 may be substantially conformal to the grid shape of the BDTI structure 206 and may include a bonding layer 334 and a metal layer 336, such as Figure 3G The next layer 334 may include titanium nitride (TiN) and / or other suitable materials. The metal layer 336 may include tungsten and / or other suitable metal materials.

[0065] Color filters 338 may be disposed on buffer layer 330 (either above or directly on buffer layer 330). In some embodiments, color filters 338 include visible light color filters configured to filter out visible light of a specific wavelength or wavelength range (e.g., red, blue, or green). In some embodiments, at least a subset of color filters 338 include near infrared (NIR) filters (e.g., NIR bandpass filters) configured to allow wavelengths associated with the NIR to pass through color filters 338 while blocking light in other wavelengths. In some embodiments, at least a subset of color filters 338 include NIR cut filters configured to block NIR light from passing through color filters 338. In some embodiments, one or more pixel sensors 100 may omit color filters 338, thereby allowing light of all wavelengths to pass through and enter the associated photodiode 112. In such examples, the pixel sensor(s) 100 may be configured as white light pixel sensors.

[0066] Microlens 340 may be disposed on color filter 338 (either above or directly on color filter 338). Microlens 340 may include microlenses for pixel sensor 100 configured to focus incident light onto photodiode 112 and / or reduce optical crosstalk between pixel sensors 100.

[0067] Figure 3D FIG. 2 shows a top view of the pixel sensor 100 in the pixel sensor array 202. Figure 3D As shown, the BDTI structure 206 can be disposed along the perimeter of the pixel sensor 100. An electrode 308 can be coupled to the BDTI structure 206 to allow a bias voltage 322 to be applied to the BDTI structure 206. The photodiode 112 and the floating diffusion node 122 can be disposed in the semiconductor layer 310 around the BDTI structure 206. The transfer gate 114 can be disposed between the photodiode 112 and the floating diffusion node 122. The floating diffusion node 122 can be electrically coupled to the reset gate 118 and the source-follower gate 124. The source-follower gate 124 can be electrically coupled to the column select gate 126.

[0068] In this manner, the pixel sensor array 202 includes a plurality of pixel sensors 100 and a BDTI structure 206 surrounding the plurality of pixel sensors 100. The BDTI structure 206 extends completely through the semiconductor layer 310 of the pixel sensor array 202 between the front side of the semiconductor layer 310 and the back side of the semiconductor layer 310. A portion of the BDTI structure 206 extends into the polysilicon well 302 below the semiconductor layer 310 and / or is surrounded by the polysilicon well 302. In some embodiments, the portion of the BDTI structure 206 may be a non-interlaced portion 208 of the BDTI structure 206 between two pixel sensors 100 in the plurality of pixel sensors 100 and an interlaced portion 210 of the BDTI structure 206 between corners of at least three pixel sensors 100 in the plurality of pixel sensors 100, and may extend into the polysilicon well 302 below the semiconductor layer 310. A distance 316 between the bottom of the polysilicon well 302 and the bottom of the non-cross-staggered portion 208 of the BDTI structure 206 can be greater than a distance 318 between the bottom of the polysilicon well 302 and the cross-staggered portion 210 of the BDTI structure 206. The polysilicon well 302 can be configured to be electrically biased to increase the hole density around the portion of the BDTI structure 206.

[0069] As mentioned above, Figures 3A to 3D This is provided as an example only. Other examples may differ from the reference Figures 3A to 3D Examples described.

[0070] Figure 4 is a schematic diagram of an example implementation 400 of the pixel sensor array 202 described herein. Figure 4 A cross-sectional schematic diagram of an example implementation 400 of pixel sensor array 202 is depicted. Figure 4 The cross-sectional view shown is along Figure 2A and Figure 2B The pixel sensor array 202 is shown in section AA.

[0071] The pixel sensor array 202 in the exemplary embodiment 400 includes a similar combination and configuration of film layers and structures as the pixel sensor array 202 in the exemplary embodiment 300 shown in FIG3 . However, in the pixel sensor array 202 of the exemplary embodiment 400 , the metal grid 332 is omitted, and instead a composite metal grid 402 is disposed above the buffer layer 330 . The composite metal grid 402 includes staggered rows and columns that conform substantially to the grid shape of the BDTI structure 206 . The composite metal grid 402 may include a film layer stack comprising a dielectric portion 404 , a metal portion 406 , and another dielectric portion 408 . A liner 410 may be disposed on the composite metal grid 402 .

[0072] The dielectric portions 404 and 408 may each include silicon oxide (SiOx, such as silicon dioxide), silicon nitride (SixNy), silicon carbide (SiCx), hafnium oxide (HfOx), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide, and / or other dielectric materials. The metal portion 406 may include a composition similar to that of the metal grid 332. The liner 410 may include silicon oxide (SiOx, such as silicon dioxide), silicon nitride (SixNy), silicon carbide (SiCx), hafnium oxide (HfOx), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide, and / or other dielectric materials. Figure 4 As further shown, the color filters 338 may be recessed into the composite metal mesh 402 and may be located between adjacent rows of the composite metal mesh 402 .

[0073] As mentioned above, Figure 4 This is provided as an example only. Other examples may differ from the reference Figure 4 Examples described.

[0074] Figures 5A to 5J is a schematic diagram of an example embodiment 500 of a method for forming the example embodiment 300 of the pixel sensor array 202 described herein. Figures 5A to 5J Along Figure 2A and Figure 2B The pixel sensor array 202 is shown in section AA, which illustrates a cross-sectional view of an exemplary embodiment 500. In some embodiments, one or more semiconductor processing equipment may be used to perform the reference Figures 5A to 5J The one or more processing operations described are as follows: the semiconductor processing equipment is, for example, a deposition equipment, an exposure equipment, a development equipment, an etching equipment, a planarization equipment, a plating equipment and / or an ion implantation equipment.

[0075] Please refer to Figure 5A, an example embodiment 500 of a method of forming the example embodiment 300 of the pixel sensor array 202 can be performed on a semiconductor layer 310. The semiconductor layer 310 can be provided from a semiconductor wafer or other type of semiconductor workpiece.

[0076] like Figure 5B As shown, multiple regions of the semiconductor layer 310 are doped to form one or more photodiodes 112 of the pixel sensor 100. Ion implantation equipment may be used to dope the semiconductor layer 310 to form one or more N-type regions and / or one or more P-type regions of the photodiode 112. The ion implantation equipment may be used to implant P+ ions into the semiconductor layer 310 to form the P-type regions, and / or N+ ions may be implanted into the semiconductor layer 310 to form the N-type regions.

[0077] like Figure 5B As further shown, one or more regions of semiconductor layer 310 may be doped to form one or more floating diffusion nodes 122 of pixel sensor 100. In some embodiments, ion implantation equipment may be used to implant N+ ions into semiconductor layer 310 to form floating diffusion nodes 122.

[0078] like Figure 5C As shown, an oxide layer 320 may be formed on (directly on and / or above) semiconductor layer 310. Furthermore, a polysilicon well 302 may be formed on (directly on and / or above) oxide layer 320. One or more transfer gates 114 may be formed on (directly on and / or above) oxide layer 320. Oxide layer 320 may serve as a gate oxide or gate dielectric layer for transfer gates 114. In some embodiments, polysilicon well 302 and transfer gates 114 are formed in the same set of one or more deposition operations. In some embodiments, polysilicon well 302 and transfer gates 114 are formed in different deposition operations.

[0079] The oxide layer 320 may be deposited using a deposition apparatus in a physical vapor deposition (PVD) operation, an atomic layer deposition (ALD) operation, a chemical vapor deposition (CVD) operation, an epitaxial operation, an oxidation operation, or other types of deposition operations. In some embodiments, after depositing the oxide layer 320, a planarization apparatus may be used to planarize the oxide layer 320. The polysilicon well 302 and the transfer gate 114 may be deposited using a deposition apparatus in an epitaxial operation and / or other types of deposition operations.

[0080] like Figure 5DAs shown, an oxide layer 328 may be formed on (directly on and / or above) the oxide layer 320, on (directly on and / or above) the sidewalls of the polysilicon well 302, on (directly on and / or above) the sidewalls of the polysilicon well 302, on (directly on and / or above) the top surface of the polysilicon well 302, on (directly on and / or above) the top surface of the polysilicon well 302, on (directly on and / or above) the sidewalls of the transfer gate 114, and / or on (directly on and / or above) the top surface of the transfer gate 114. The oxide layer 328 may increase the thickness of the oxide layer 320 in portions not covered by the polysilicon well 302 or the transfer gate 114. Accordingly, the thickness of oxide layer 320 below transfer gate 114 and / or polysilicon well 302 may be less than the thickness between polysilicon wells 302 and / or between transfer gates 114. Deposition equipment may be used to deposit oxide layer 328 in a PVD operation, an ALD operation, a CVD operation, an oxidation operation, a PRO operation, or other types of deposition operations.

[0081] like Figure 5D As further shown, dielectric spacers 304 can be formed on the sidewalls of the polysilicon well 302 and the sidewalls of the transfer gate 114. The dielectric spacers 304 can be deposited using a deposition tool in a PVD operation, an ALD operation, a CVD operation, an oxidation operation, a PRO operation, or other types of deposition operations. In some embodiments, a conformal layer of dielectric material is deposited, and then an etching tool is used to remove portions of the dielectric layer, such that the remaining portions of the dielectric layer form the dielectric spacers 304. Accordingly, based on the etching operation, the dielectric spacers 304 can have a rounded outer surface.

[0082] like Figure 5E As shown, a CESL 306 can be formed on (directly on and / or over) the dielectric spacer 304, the polysilicon well 302, and / or the transfer gate 114. The CESL 306 can be deposited using a deposition tool in a PVD operation, an ALD operation, a CVD operation, an oxidation operation, a PRO operation, or other types of deposition operations.

[0083] like Figure 5F As shown, the semiconductor layer 310 may be flipped over and backside processing may be performed on the pixel sensor array 202 .

[0084] like Figure 5GAs shown, a recess 502 can be formed from the back side of the semiconductor layer 310 completely through the semiconductor layer 310 to the front side of the semiconductor layer 310. Overetching can be performed to extend the recess 502 into the polysilicon well 302 on the front side of the semiconductor layer 310. An etching device can be used to etch the semiconductor layer 310 and the polysilicon well 302. Furthermore, forming the recess 502 can include etching through the oxide layer 320 between the semiconductor layer 310 and the polysilicon well 302. Because the oxide layer has a smaller thickness between the semiconductor layer 310 and the polysilicon well 302 and the provision of the polysilicon well 302, the oxide layer 320 can be subjected to less lateral etching. The etch depth of the polysilicon well 302 in the cross-interleaved portion 210 can be greater than the etch depth in the non-cross-interleaved portion 208.

[0085] In some embodiments, the recess 502 is patterned using a pattern of a photoresist layer. In such embodiments, a deposition apparatus may be used to form the photoresist layer on the backside surface of the semiconductor layer 310. An exposure apparatus may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development apparatus may be used to develop and remove portions of the photoresist layer to reveal the pattern. An etching apparatus may be used to etch the semiconductor layer 310, the oxide layer 320, and the polysilicon well 302 based on the pattern to form the recess 502. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a photoresist removal apparatus may be used to remove the remaining portions of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or other techniques). Alternatively, the pattern of the photoresist layer may be transferred to a hard mask layer used to form the recess 502.

[0086] like Figure 5H As shown, a dielectric liner 314 can be formed on the sidewalls and bottom surface of the recess 502. The dielectric liner 314 can be conformally deposited using a deposition apparatus in a PVD operation, an ALD operation, a CVD operation, an oxidation operation, a PRO operation, or other type of deposition operation. The dielectric liner 314 can further be deposited on the backside surface of the semiconductor layer 310. In some embodiments, the dielectric liner 314 is subsequently removed from the backside surface of the semiconductor layer 310. In some embodiments, the dielectric liner 314 remains on the backside surface of the semiconductor layer 310 (e.g., to serve as an anti-reflective layer).

[0087] like Figure 5I As shown, the recess 502 on the dielectric liner 314 may be filled with a dielectric material 312 (eg, an oxygen-containing dielectric material, a high-k dielectric material) to form a BDTI structure 206 in the recess 502 . The BDTI structure 206 may extend into the polysilicon well 302 .

[0088] like Figure 5IAs further shown, dielectric material 312 may be deposited on the backside surface of semiconductor layer 310 to form buffer layer 330. Furthermore, metal grid 332 may be formed in buffer layer 330. For example, a first portion of buffer layer 330 may be deposited; recesses may be etched in the first portion of buffer layer 330; and metal grid 332 may be formed in these recesses. Subsequently, the remainder of buffer layer 330 may be deposited over the first portion of buffer layer 330 and metal grid 332.

[0089] A deposition apparatus may be used to deposit dielectric material 312 within the recess in a PVD operation, an ALD operation, a CVD operation, an oxidation operation, a PRO operation, or other type of deposition operation to form BDTI structure 206. A deposition apparatus may be used to deposit buffer layer 330 in a PVD operation, an ALD operation, a CVD operation, an oxidation operation, a PRO operation, or other type of deposition operation. In some embodiments, a planarization apparatus may be used to planarize buffer layer 330 after deposition. A deposition apparatus and / or a plating apparatus may be used to deposit metal grid 332 in a PVD operation, an ALD operation, a CVD operation, an oxidation operation, a PRO operation, or other type of deposition operation. In some embodiments, a seed layer is deposited first, and then metal grid 332 is deposited on the seed layer. In some embodiments, a planarization apparatus may be used to planarize metal grid 332 after deposition.

[0090] like Figure 5J As further shown, color filters 338 and microlenses 340 may be formed on the buffer layer 330 (directly on and / or above the buffer layer 330 ).

[0091] As mentioned above, Figures 5A to 5J This is provided as an example only. Other examples may differ from the reference Figures 5A to 5J Examples described.

[0092] Figure 6A and Figure 6B FIG. 6 is a schematic diagram of an example implementation 600 of the pixel sensor array 202 described herein. Figure 6A A cross-sectional schematic diagram of an example implementation 600 of pixel sensor array 202 is depicted. Figure 6A The cross-sectional view is along Figure 2A and Figure 2B 1 and 2. It is shown in cross section AA of the pixel sensor array 202 in FIG.

[0093] like Figure 6AAs shown, the pixel sensor array 202 in the exemplary embodiment 600 includes a combination and configuration of film layers and structures similar to the pixel sensor array 202 in the exemplary embodiment 300. However, in the exemplary embodiment 600 of the pixel sensor array 202, the bottom portion of the dielectric liner 314 of the BDTI structure 206 is omitted, as shown in the enlarged view. Figure 6B As shown. Furthermore, the BDTI structure 206 includes a polysilicon material 602 instead of the dielectric material 312. The polysilicon material 602 (e.g., a polysilicon trench structure) is in direct contact with the polysilicon well 302. This allows the BDTI structure 206 to be fully electrically biased, further passivating any damage that may occur to the semiconductor layer 310 during the formation of the BDTI structure 206. The BDTI structure 206 can be electrically biased via the polysilicon well 302. For example, a bias voltage 322 can be applied to the BDTI structure 206 via the polysilicon well 302 to electrically bias the BDTI structure 206. This can further reduce the dark current of the pixel sensor 100.

[0094] In some embodiments, dielectric liner 314 comprises a high-k dielectric material, which may have a higher hole density than oxygen-containing dielectric materials. This enhances the negative bias of polysilicon material 602 and reduces the interface capacitance of BDTI structure 206. In some embodiments, dielectric liner 314 comprises an oxygen-containing dielectric material, which may provide better optical performance (e.g., reduced light tunneling) than high-k dielectric materials because it can be formed at a greater thickness than a high-k dielectric material liner.

[0095] As mentioned above, Figure 6A and Figure 6B This is provided as an example only. Other examples may differ from the reference Figure 6A and Figure 6B Examples described.

[0096] Figures 7A to 7G FIG. 7 is a diagram illustrating an example embodiment 700 of a method for forming an example embodiment 600 of a pixel sensor array 202 as described herein. Figures 7A to 7G Along Figure 2A and Figure 2B The pixel sensor array 202 is shown in section AA, which illustrates a cross-sectional view of an exemplary embodiment 700. In some embodiments, one or more semiconductor processing equipment may be used to perform a reference Figures 7A to 7G The one or more processing operations described are as follows: the semiconductor processing equipment is, for example, a deposition equipment, an exposure equipment, a development equipment, an etching equipment, a planarization equipment, a plating equipment and / or an ion implantation equipment.

[0097] like Figure 7A As shown, you can refer to Figures 5A to 5E The illustrated front-side semiconductor processing operations are for the pixel sensor array 202. The semiconductor layer 310 may be flipped over and back-side processing may be performed on the pixel sensor array 202.

[0098] like Figure 7B As shown, a recess 702 can be formed from the back side of the semiconductor layer 310 completely through the semiconductor layer 310 to the front side of the semiconductor layer 310. Overetching can be performed to extend the recess 702 into the polysilicon well 302 on the front side of the semiconductor layer 310. An etching device can be used to etch the semiconductor layer 310 and the polysilicon well 302. Furthermore, forming the recess 702 can include etching through the oxide layer 320 between the semiconductor layer 310 and the polysilicon well 302. Because the oxide layer has a smaller thickness between the semiconductor layer 310 and the polysilicon well 302 and the provision of the polysilicon well 302, the oxide layer 320 can be subjected to less lateral etching. The etch depth of the polysilicon well 302 in the cross-interleaved portion 210 can be greater than the etch depth in the non-cross-interleaved portion 208.

[0099] In some embodiments, the recess 702 is patterned using a pattern of a photoresist layer. In such embodiments, a deposition apparatus may be used to form the photoresist layer on the backside surface of the semiconductor layer 310. An exposure apparatus may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development apparatus may be used to develop and remove portions of the photoresist layer to reveal the pattern. An etching apparatus may be used to etch the semiconductor layer 310, the oxide layer 320, and the polysilicon well 302 based on the pattern to form the recess 702. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a photoresist removal apparatus may be used to remove the remaining portions of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or other techniques). Alternatively, the pattern of the photoresist layer may be transferred to a hard mask layer used to form the recess 702.

[0100] like Figure 7C As shown, a dielectric liner 314 can be formed on the sidewalls and bottom surface of the recess 702. The dielectric liner 314 can be conformally deposited using a deposition apparatus in a PVD operation, an ALD operation, a CVD operation, an oxidation operation, a PRO operation, or other type of deposition operation. The dielectric liner 314 can further be deposited on the backside surface of the semiconductor layer 310. The thickness of the dielectric liner 314 formed on the backside surface of the semiconductor layer 310 can be greater than the thickness of the dielectric liner 314 formed on the bottom surface of the recess 702. This allows the dielectric liner 314 to protect the backside surface of the semiconductor layer 310 from etching damage when etching through the portion of the dielectric liner 314 located on the bottom surface of the recess 702 to expose the polysilicon well 302 through the recess 702.

[0101] like Figure 7D As shown, an etch-back operation can be performed to remove portions of the dielectric liner 314 from the bottom surface 704 of the recess 702, thereby exposing the polysilicon well 302 through the recess 702. As described above, the thickness of the dielectric liner 314 formed on the backside surface of the semiconductor layer 310 can be greater than the thickness of the dielectric liner 314 formed on the bottom surface 704 of the recess 702. This allows the dielectric liner 314 on the bottom surface 704 of the recess 702 to be completely removed before the dielectric liner 314 on the backside surface of the semiconductor layer 310 is completely etched. Accordingly, when etching through the dielectric liner 314 on the bottom surface 704 of the recess 702 to expose the polysilicon well 302 through the recess 702, the backside surface of the semiconductor layer 310 can be protected from etching damage by the dielectric liner 314. In some embodiments, an etching device can be used to perform dry etching to achieve the etch-back operation. For example, the etch-back operation may include a highly directional plasma etch performed to remove material of the dielectric liner 314 from the bottom surface 704 of the recess 702 while minimizing the removal of material of the dielectric liner 314 from the sidewalls of the recess 702. However, other techniques may also be used to remove material of the dielectric liner 314 from the bottom surface 704 of the recess 702.

[0102] like Figure 7E As shown, the recess 702 on the dielectric liner 314 can be filled with polysilicon material 602 to form the BDTI structure 206 in the recess 702. The polysilicon material 602 can extend into the polysilicon well 302 and can contact the polysilicon well 302 from above by etching through the bottom surface 704 of the recess 702 to form an opening. The polysilicon material 602 can be deposited using a deposition tool in an epitaxial operation and / or other types of deposition operations.

[0103] like Figure 7F As further shown, the polysilicon material 602 on the backside surface of the semiconductor layer 310 may be removed during a planarization operation. The planarization operation may be performed using a planarization tool, such as a chemical mechanical planarization (CMP) operation.

[0104] like Figure 7G As shown, a dielectric material may be deposited on the backside surface of semiconductor layer 310 to form a buffer layer 330. Furthermore, a metal grid 332 may be formed in buffer layer 330. For example, a first portion of buffer layer 330 may be deposited; recesses may be etched in the first portion of buffer layer 330; and metal grid 332 may be formed in these recesses. Subsequently, the remaining portion of buffer layer 330 may be deposited on the first portion of buffer layer 330 and metal grid 332.

[0105] The buffer layer 330 may be deposited using a deposition apparatus in a PVD operation, an ALD operation, a CVD operation, an oxidation operation, a PRO operation, or other type of deposition operation. In some embodiments, a planarization apparatus may be used to planarize the buffer layer 330 after deposition. The metal grid 332 may be deposited using a deposition apparatus and / or a plating apparatus in a PVD operation, an ALD operation, a CVD operation, an oxidation operation, a PRO operation, or other type of deposition operation. In some embodiments, a seed layer is deposited first, and then the metal grid 332 is deposited on the seed layer. In some embodiments, a planarization apparatus may be used to planarize the metal grid 332 after deposition. Color filters 338 and microlenses 340 may be formed on the buffer layer 330 (directly on and / or above the buffer layer 330).

[0106] As mentioned above, Figures 7A to 7G This is provided as an example only. Other examples may differ from the reference Figures 7A to 7G Examples described.

[0107] Figure 8A and Figure 8B is a schematic diagram of an example implementation 800 of the pixel sensor array 202 described herein. Figure 8A A cross-sectional schematic diagram of an example implementation 800 of pixel sensor array 202 is depicted. Figure 8A The cross-sectional view is along Figure 2A and Figure 2B 1 and 2. It is shown in cross section AA of the pixel sensor array 202 in FIG.

[0108] like Figure 8A As shown, the pixel sensor array 202 in the exemplary embodiment 800 includes a combination and configuration of film layers and structures similar to the pixel sensor array 202 in the exemplary embodiment 600. However, in the exemplary embodiment 800 of the pixel sensor array 202, the BDTI structure 206 includes multiple liner layers, including the dielectric liner 314 and the dielectric liner 802, as shown in the enlarged view. Figure 8B As shown, dielectric liner 314 may be disposed between dielectric liner 802 and semiconductor layer 310. Dielectric liner 802 may be disposed between polysilicon material 602 and dielectric liner 314. Dielectric liner 314 may comprise a high-k dielectric material, while dielectric liner 802 may comprise an oxygen-containing dielectric material. The combination of the high-k dielectric liner and the oxygen-containing dielectric liner enables BDTI structure 206 to have improved optical performance (e.g., by reducing light tunneling through the oxygen-containing dielectric liner) and enhanced damage passivation (e.g., by increasing negative bias voltage due to the high hole density in the high-k dielectric liner).

[0109] As mentioned above, Figure 8A and Figure 8BThis is provided as an example only. Other examples may differ from the reference Figure 8A and Figure 8B Examples described.

[0110] Figures 9A to 9G is a schematic diagram of an example embodiment 900 of a method for forming an example embodiment 800 of the pixel sensor array 202 described herein. Figures 9A to 9G Along Figure 2A and Figure 2B The pixel sensor array 202 is shown in section AA, which illustrates a cross-sectional view of the exemplary embodiment 900. In some embodiments, one or more semiconductor processing equipment may be used to perform the reference Figures 9A to 9G The one or more processing operations described are as follows: the semiconductor processing equipment is, for example, a deposition equipment, an exposure equipment, a development equipment, an etching equipment, a planarization equipment, a plating equipment and / or an ion implantation equipment.

[0111] like Figure 9A As shown, you can refer to Figures 5A to 5E The illustrated front-side semiconductor processing operations are for the pixel sensor array 202. The semiconductor layer 310 may be flipped over and back-side processing may be performed on the pixel sensor array 202.

[0112] like Figure 9B As shown, a recess 902 can be formed from the back side of the semiconductor layer 310 completely through the semiconductor layer 310 to the front side of the semiconductor layer 310. Overetching can be performed to extend the recess 902 into the polysilicon well 302 on the front side of the semiconductor layer 310. An etching device can be used to etch the semiconductor layer 310 and the polysilicon well 302. Furthermore, forming the recess 902 can include etching through the oxide layer 320 between the semiconductor layer 310 and the polysilicon well 302. Because the oxide layer has a smaller thickness between the semiconductor layer 310 and the polysilicon well 302 and the presence of the polysilicon well 302, the oxide layer 320 can be subjected to less lateral etching. The etch depth of the polysilicon well 302 in the cross-interleaved portion 210 can be greater than the etch depth in the non-cross-interleaved portion 208.

[0113] In some embodiments, the recess 902 is patterned using a pattern of a photoresist layer. In such embodiments, a deposition apparatus may be used to form the photoresist layer on the backside surface of the semiconductor layer 310. An exposure apparatus may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development apparatus may be used to develop and remove portions of the photoresist layer to reveal the pattern. An etching apparatus may be used to etch the semiconductor layer 310, the oxide layer 320, and the polysilicon well 302 based on the pattern to form the recess 902. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a photoresist removal apparatus may be used to remove the remaining portions of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or other techniques). Alternatively, the pattern of the photoresist layer may be transferred to a hard mask layer used to form the recess 902.

[0114] like Figure 9C As shown, dielectric liner 314 and dielectric liner 802 may be formed on the sidewalls and bottom surface of recess 902. For example, dielectric liner 314 may be formed directly on the sidewalls and bottom surface of recess 902, while dielectric liner 802 may be formed on the bottom surface and sidewalls of dielectric liner 314. Deposition equipment may be used to conformally deposit dielectric liner 314 in a PVD operation, ALD operation, CVD operation, oxidation operation, PRO operation, or other type of deposition operation. Deposition equipment may be used to conformally deposit dielectric liner 802 in a PVD operation, ALD operation, CVD operation, oxidation operation, PRO operation, or other type of deposition operation. Dielectric liner 314 and dielectric liner 802 may further be deposited on the backside surface of semiconductor layer 310. The total thickness of dielectric liner 314 and 802 formed on the backside surface of semiconductor layer 310 may be greater than the thickness of dielectric liner 314 and 802 formed on the bottom surface of recess 902. This allows the dielectric liner 314 , 802 to protect the backside surface of the semiconductor layer 310 from being damaged by etching when etching through the portion of the dielectric liner 314 , 802 located on the bottom surface of the recess 902 to expose the polysilicon well 302 through the recess 902 .

[0115] like Figure 9DAs shown, an etch-back operation can be performed to remove portions of the dielectric liner 314, 802 from the bottom surface 904 of the recess 902, thereby exposing the polysilicon well 302 through the recess 902. As described above, the total thickness of the dielectric liner 314, 802 formed on the backside surface of the semiconductor layer 310 can be greater than the total thickness of the dielectric liner 314, 802 formed on the bottom surface 904 of the recess 902. This allows the dielectric liner 314, 802 on the bottom surface 904 of the recess 902 to be completely removed before the dielectric liner 314, 802 on the backside surface of the semiconductor layer 310 is completely etched. Accordingly, when etching through the dielectric liner 314, 802 on the bottom surface 904 of the recess 902 to expose the polysilicon well 302 through the recess 902, the backside surface of the semiconductor layer 310 can be protected from etching damage by the dielectric liner 314, 802. In some embodiments, an etching apparatus can be used to perform dry etching to implement an etch-back operation. For example, the etch-back operation can include a highly directional plasma etch performed to remove material of the dielectric liner 314, 802 from the bottom surface 904 of the recess 902 while minimizing the removal of material of the dielectric liner 314, 802 from the sidewalls of the recess 902. However, other techniques can also be used to remove material of the dielectric liner 314, 802 from the bottom surface 904 of the recess 902.

[0116] like Figure 9E As shown, the recess 902 on the dielectric liner 314, 802 can be filled with polysilicon material 602 to form the BDTI structure 206 in the recess 902. The polysilicon material 602 can extend into the polysilicon well 302 and can contact the polysilicon well 302 from above by etching through the bottom surface 904 of the recess 902 to form an opening. The polysilicon material 602 can be deposited using a deposition device in an epitaxial operation and / or other types of deposition operations.

[0117] like Figure 9F As further shown, the polysilicon material 602 on the backside surface of the semiconductor layer 310 may be removed during a planarization operation. The planarization operation may be performed using a planarization tool, such as a chemical mechanical planarization (CMP) operation.

[0118] like Figure 9G As shown, a dielectric material may be deposited on the backside surface of semiconductor layer 310 to form a buffer layer 330. Furthermore, a metal grid 332 may be formed in buffer layer 330. For example, a first portion of buffer layer 330 may be deposited; recesses may be etched in the first portion of buffer layer 330; and metal grid 332 may be formed in these recesses. Subsequently, the remaining portion of buffer layer 330 may be deposited on the first portion of buffer layer 330 and metal grid 332.

[0119] The buffer layer 330 may be deposited using a deposition apparatus in a PVD operation, an ALD operation, a CVD operation, an oxidation operation, a PRO operation, or other type of deposition operation. In some embodiments, a planarization apparatus may be used to planarize the buffer layer 330 after deposition. The metal grid 332 may be deposited using a deposition apparatus and / or a plating apparatus in a PVD operation, an ALD operation, a CVD operation, an oxidation operation, a PRO operation, or other type of deposition operation. In some embodiments, a seed layer is deposited first, and then the metal grid 332 is deposited on the seed layer. In some embodiments, a planarization apparatus may be used to planarize the metal grid 332 after deposition. Color filters 338 and microlenses 340 may be formed on the buffer layer 330 (directly on and / or above the buffer layer 330).

[0120] As mentioned above, Figures 9A to 9G This is provided as an example only. Other examples may differ from the reference Figures 9A to 9G Examples described.

[0121] 10A to 10C is a schematic diagram of an example implementation 1000 of the pixel sensor array 202 described herein. Figure 10A A perspective diagram of an example implementation 1000 of the pixel sensor array 202 is depicted. Figure 10B A cross-sectional schematic diagram of an example implementation 1000 of a pixel sensor array 202 is depicted. Figure 10B The cross-sectional diagram in the figure is along Figure 2A and Figure 2B The pixel sensor 202 is shown drawn in section AA.

[0122] like Figure 10A and Figure 10B As shown, the pixel sensor array 202 in the exemplary embodiment 1000 includes a combination and configuration of layers and structures similar to the pixel sensor array 202 in the exemplary embodiment 300. However, in the exemplary embodiment 1000 of the pixel sensor array 202, the polysilicon wells 302 and the dielectric spacers 304 are omitted from the non-cross-interleaved portions 208 of the BDTI structure. Instead, the polysilicon wells 302 and the associated dielectric spacers 304 are only included in the cross-interleaved portions 210, as shown in the enlarged view. Figure 10CAs shown, CESL 306 can still be disposed over both the non-cross-staggered portion 208 and the cross-staggered portion 210. This can reduce the density of polysilicon wells in pixel sensor array 202, which can allow for denser polysilicon components to be formed in pixel sensor array 202 (due to less polysilicon-to-polysilicon confinement in pixel sensor array 202). Furthermore, because the non-cross-staggered portion 208 is subject to less lateral etching than the cross-staggered portion 210 (due to a lower etch rate for the non-cross-staggered portion 208 than for the cross-staggered portion 210), the polysilicon well 302 can be omitted from the non-cross-staggered portion 208. In other words, the non-cross-staggered portion 208 may be less susceptible to etching damage from the semiconductor layer 310 than the cross-staggered portion 210. Therefore, the polysilicon well 302 can be included only in the cross-staggered portion 210.

[0123] Thus, the pixel sensor array 202 includes a plurality of pixel sensors 100 and a BDTI structure 206 surrounding the plurality of pixel sensors 100. The BDTI structure 206 extends between the front side and the back side of the semiconductor layer 310 and completely penetrates the semiconductor layer 310. The BDTI structure 206 extends into the polysilicon well 302 and / or is surrounded by the polysilicon well 302 at the cross-interleaved portion 210 of the BDTI structure 206 below the semiconductor layer 310, but does not extend into the polysilicon well 302 and / or be surrounded by the polysilicon well 302 at the non-cross-interleaved portion 208 of the BDTI structure 206. Between two pixel sensors 100 of the plurality of pixel sensors 100, the non-cross-interleaved portion 208 of the BDTI structure 206 may extend into a portion of the CESL 306.

[0124] As mentioned above, Figure 10A and Figure 10B This is provided as an example only. Other examples may differ from the reference Figure 10A and Figure 10B Examples described.

[0125] Figures 11A to 11C is a schematic diagram of an example implementation 1100 of the pixel sensor array 202 described herein. Figure 11A A perspective schematic diagram of an example implementation 1100 of the pixel sensor array 202 is depicted. Figure 11B A cross-sectional schematic diagram of an example implementation 1100 of pixel sensor array 202 is depicted. Figure 11B The cross-sectional diagram in the figure is along Figure 2A and Figure 2B The pixel sensor 202 is shown drawn in section AA.

[0126] like Figure 11A and Figure 11BAs shown, the pixel sensor array 202 in the exemplary embodiment 1100 includes a combination and configuration of film layers and structures similar to the pixel sensor array 202 in the exemplary embodiment 1000. However, in the exemplary embodiment 1100 of the pixel sensor array 202, an additional spacer material is disposed above (or below) the polysilicon well 302 in the cross-interleaved portion 210, so that the hard mask layer 1102 is disposed above (or below) the polysilicon well 302 in the cross-interleaved portion 210, as shown in the enlarged view. Figure 11C The hard mask layer 1102 may be located between the oxide layer 320 and the oxide layer 328 .

[0127] The hard mask layer 1102 above (or below) the polysilicon well 302 in the cross-interleaved portion 210 can further improve the etching margin for etching the recess for accommodating the BDTI structure 206, thereby further reducing the possibility of defects in the pixel sensor array 202 and / or reducing the complexity of the process for forming the pixel sensor array 202. In some embodiments, the total thickness of the hard mask layer 1102 and the CESL 306 can be about 1000 nm. to about If the total thickness of the hard shield layer 1102 and the CESL 306 is less than about The etching margin for etching the recess to accommodate the BDTI structure 206 may be reduced and / or etching damage may be caused to the semiconductor layer 310. If the combined thickness of the hard mask layer 1102 and the CESL 306 is at least about If the combined thickness of the hard mask layer 1102 and the CESL 306 is greater than about Under-etching may occur when forming the contact structure of the floating diffusion node 122 and / or the transmission gate 114. If the combined thickness of the hard mask layer 1102 and the CESL 306 does not exceed approximately However, the total thickness of the hard mask layer 1102 and the CESL 306 (at about to about Thickness ranges outside the range of ) are still within the scope of the present disclosure.

[0128] Thus, the pixel sensor array 202 includes a plurality of pixel sensors 100 and a BDTI structure 206 surrounding the plurality of pixel sensors 100. The BDTI structure 206 extends between the front and back sides of a semiconductor layer 310 and completely penetrates the semiconductor layer 310. A portion of the BDTI structure 206 extends into the polysilicon well 302 below the semiconductor layer 310 and / or is surrounded by the polysilicon well 302. In some embodiments, the portion of the BDTI structure 206 may be a non-interleaved portion 208 of the BDTI structure located between two pixel sensors 100 in the plurality of pixel sensors 100. Alternatively, the interleaved portion 210 of the BDTI structure 206 located between corners of at least three pixel sensors 100 in the plurality of pixel sensors 100 may extend into another polysilicon well 302 below the semiconductor layer 310. The non-interleaved portion 208 of the BDTI structure 206 located between two pixel sensors 100 in the plurality of pixel sensors 100 may extend into a portion of the CESL 306. The hard mask layer 1102 is disposed below the bottom surface of the polysilicon well 302 .

[0129] Thus, the pixel sensor array 202 includes a plurality of pixel sensors 100 and a BDTI structure 206 surrounding the plurality of pixel sensors 100. The BDTI structure 206 extends between the front side and the back side of the semiconductor layer 310 and completely penetrates the semiconductor layer 310. The BDTI structure 206 extends into the polysilicon well 302 and / or is surrounded by the polysilicon well 302 at the cross-interleaved portion 210 of the BDTI structure 206 below the semiconductor layer 310, but does not extend into the polysilicon well 302 and / or be surrounded by the polysilicon well 302 at the non-cross-interleaved portion 208 of the BDTI structure 206. Between two pixel sensors 100 of the plurality of pixel sensors 100, the non-cross-interleaved portion 208 of the BDTI structure 206 may extend into a portion of the CESL 306.

[0130] As mentioned above, Figure 11A and Figure 11B This is provided as an example only. Other examples may differ from the reference Figure 11A and Figure 11B Examples described.

[0131] 12A to 12C is a schematic diagram of an example implementation 1200 of the pixel sensor array 202 described herein. Figure 12A A perspective diagram of an example implementation 1200 of the pixel sensor array 202 is depicted. Figure 12B A cross-sectional schematic diagram of an example implementation 1200 of pixel sensor array 202 is depicted. Figure 12B The cross-sectional diagram in the figure is along Figure 2A and Figure 2BThe pixel sensor 202 is shown drawn in section AA.

[0132] like Figure 12A and Figure 12B As shown, the pixel sensor array 202 in the exemplary embodiment 1200 includes a combination and configuration of film layers and structures similar to the pixel sensor array 202 in the exemplary embodiment 1100. However, in the exemplary embodiment 1200 of the pixel sensor array 202, the annular polysilicon well 302 may be disposed in the cross-interleaved portion 210 of the BDTI structure 206, as shown in the enlarged view. Figure 12C The BDTI structure 206 may extend through the aperture or opening in the annular polysilicon well 302. The annular polysilicon well 302 may be enclosed by an oxide layer 320. A dielectric spacer 304 and the oxide layer 320 may be disposed between the BDTI structure 206 and the annular polysilicon well 302.

[0133] The hard mask layer 1102 above (or below) the annular polysilicon well 302 in the cross-interleaved portion 210 can further increase the over-etch window for etching the recess that accommodates the BDTI structure 206, thereby further reducing the chance of defects in the pixel sensor array 202 and / or reducing the complexity of the process for forming the pixel sensor array 202.

[0134] As mentioned above, Figure 12A and Figure 12B This is provided as an example only. Other examples may differ from the reference Figure 12A and Figure 12B Examples described.

[0135] Figure 13 1300 is a flow chart of an exemplary method 1300 for forming a pixel sensor array as described herein. In some embodiments, one or more semiconductor process equipment is used to perform Figure 13 One or more process operations are shown.

[0136] like Figure 13 As shown, method 1300 may include forming a plurality of polysilicon wells over a front side of a semiconductor layer of a pixel sensor array (operation 1310). As an example, a plurality of polysilicon wells 302 may be formed over a front side of a semiconductor layer 310 of pixel sensor array 202 using one or more semiconductor processing tools as described herein.

[0137] like Figure 13 As further shown, method 1300 may include forming an oxide layer on the front side of the semiconductor layer and the polysilicon well (operation 1320). As an example, one or more semiconductor processing tools as described herein may be used to form oxide layer 320 on the front side of semiconductor layer 310 and polysilicon well 302.

[0138] like Figure 13 As further shown, method 1300 may include forming spacers around the sidewalls of the polysilicon (operation 1330). As an example, one or more semiconductor processing tools, as described herein, may be used to form spacers (e.g., dielectric spacers 304) around the sidewalls of the polysilicon well 302.

[0139] like Figure 13 As further shown, the method 1300 may include forming a CESL over the oxide layer and the spacers (operation 1340). As an example, the CESL 306 may be formed over the oxide layer 320 and the spacers using one or more semiconductor processing tools as described herein.

[0140] like Figure 13 As further shown, method 1300 may include forming a plurality of recesses extending through the semiconductor layer and into the polysilicon well (operation 1350). By way of example, as described herein, one or more semiconductor processing tools may be used to form a plurality of recesses (e.g., recesses 502, 702, 902) extending through the semiconductor layer 310 and into the polysilicon well 302. In some embodiments, the plurality of recesses extend from a back side of the semiconductor layer 310 to a front side of the semiconductor layer 310. Alternatively, the polysilicon well 302 comprises an annular polysilicon well 302, and the recesses are formed as apertures extending through the annular polysilicon well 302 (e.g., located at an inner edge of the annular polysilicon well 302).

[0141] like Figure 13 As further shown, method 1300 may include forming a BDTI structure in the plurality of recesses (operation 1360). As an example, one or more semiconductor processing tools may be used to form the BDTI structure 206 in the plurality of recesses, as described herein.

[0142] Method 1300 may include additional embodiments, such as any one or any combination of the embodiments described below and / or in connection with one or more other methods described elsewhere herein.

[0143] In the first embodiment, forming the oxide layer 320 includes forming the oxide layer 320 to have a greater thickness on the front side of the semiconductor layer 310 than on the polysilicon well 302 .

[0144] In a second embodiment (or a combination of the first and second embodiments), the method 1300 includes forming the hard mask layer 1102 over the top surface of the polysilicon well 302 , and forming the CESL 306 includes forming the CESL 306 over the hard mask layer 1102 .

[0145] In the third embodiment (or a combination of one or both of the first and second embodiments), forming the BDTI structure 206 includes forming one or more dielectric liners (e.g., dielectric liners 314, 802) on the sidewalls and bottom surface of a recess of the plurality of recesses, and filling the recess with an oxygen-containing material (e.g., dielectric material 312) over the one or more dielectric liners.

[0146] In the fourth embodiment (or a combination of one or more of the first to third embodiments), forming the BDTI structure 206 includes: forming a dielectric liner (e.g., dielectric liner 314, 802) on the sidewalls and bottom surface of a recess among the plurality of recesses; removing the dielectric liner from the bottom surface of the recess to expose a polysilicon well 302 among the plurality of polysilicon wells 302 through the bottom surface of the recess; and filling the plurality of recesses with polysilicon material 602, wherein the polysilicon material is formed directly on the polysilicon well 302 at the bottom surface of the recess.

[0147] In a fifth embodiment (or a combination of one or more of the first to fourth embodiments), forming the dielectric liner further includes forming the dielectric liner on the back side of the semiconductor layer 310 such that a first thickness of the dielectric liner on the back side of the semiconductor layer 310 is greater than a second thickness at the bottom of the recess, and removing a portion of the dielectric liner from the bottom of the recess causes the dielectric liner to be removed from the back side of the semiconductor layer 310.

[0148] In the sixth embodiment (or a combination of one or more of the first to fifth embodiments), forming the BDTI structure 206 includes forming a multi-layer dielectric liner (e.g., dielectric liner 314, 802) on the sidewalls and bottom surface of a recess among the plurality of recesses; removing the multi-layer dielectric liner from the bottom surface of the recess to expose a polysilicon well 302 among the plurality of polysilicon wells 302 through the bottom surface of the recess; and filling the recesses with polysilicon material 602, wherein the polysilicon material 602 is formed directly on the polysilicon well 302 at the bottom surface of the recess.

[0149] although Figure 13 Example operations of method 1300 are shown. In some embodiments, method 1300 may include additional operations, fewer operations, different operations, or operations that are different from those of method 1300. Figure 13 The operations are shown in a different order. Additionally (or alternatively), two or more operations in method 1300 may be performed in parallel.

[0150] In summary, polysilicon wells are formed at the intersections between the plurality of pixel sensors in a pixel sensor array. Furthermore, the thickness of the underlying oxide layer between the polysilicon well and the semiconductor layer of the pixel sensor array can be thinner than its thickness elsewhere. The polysilicon well and the thinner oxide layer can reduce the likelihood and / or extent of lateral etching during the etching of the semiconductor layer to form the recessed BDTI structure that houses the pixel sensor array. Furthermore, the bottom of the BDTI structure extends into the polysilicon well, allowing a bias voltage to be applied to the BDTI structure through the polysilicon well to passivate any damage that may occur to the portion of the semiconductor layer surrounding the bottom of the BDTI structure.

[0151] As described in more detail above, some embodiments herein provide a pixel sensor array comprising a plurality of pixel sensors, the pixel sensor array including a backside deep trench isolation structure laterally surrounding the plurality of pixel sensors, wherein the backside deep trench isolation structure extends completely through a semiconductor layer between a front side and a back side of the semiconductor layer of the pixel sensor array, and wherein a portion of the backside deep trench isolation structure extends into a first polysilicon well below the semiconductor layer and / or is surrounded by the first polysilicon well.

[0152] In some embodiments, the portion of the backside deep trench isolation structure is a non-cross-interleaved portion of the backside deep trench isolation structure between two pixel sensors in the plurality of pixel sensors, and the second polysilicon well below the semiconductor layer surrounds the cross-interleaved portion of the backside deep trench isolation structure at corners of at least three pixel sensors in the plurality of pixel sensors. In some embodiments, a first distance between a bottom of the first polysilicon well and a bottom of the non-cross-interleaved portion of the backside deep trench isolation structure is greater than a second distance between a bottom of the second polysilicon well and a bottom of the cross-interleaved portion of the backside deep trench isolation structure. In some embodiments, the first polysilicon well is configured to be electrically biased to increase a hole density around the portion of the backside deep trench isolation structure. In some embodiments, the portion of the backside deep trench isolation structure is a cross-staggered portion of the backside deep trench isolation structure at a corner of at least three pixel sensors in the plurality of pixel sensors, wherein a dielectric spacer is disposed around a sidewall of the first polysilicon well, wherein a contact structure etch stop layer is disposed around the dielectric spacer and below a bottom surface of the first polysilicon well, and a portion of the contact structure etch stop layer surrounds a non-cross-staggered portion of the backside deep trench isolation structure located between two pixel sensors in the plurality of pixel sensors. In some embodiments, the portion of the backside deep trench isolation structure is a cross-staggered portion of the backside deep trench isolation structure at a corner of at least three pixel sensors in the plurality of pixel sensors, wherein a dielectric spacer is disposed around a sidewall of the first polysilicon well, wherein a hard mask layer is disposed below a bottom surface of the first polysilicon well, wherein a contact structure etch stop layer is disposed below and around the dielectric spacer and the hard mask layer, and a portion of the contact structure etch stop layer surrounds a non-cross-staggered portion of the backside deep trench isolation structure located between two pixel sensors in the plurality of pixel sensors. In some embodiments, the backside deep trench isolation structure comprises: a polysilicon trench structure disposed in a staggered grid around the plurality of pixel sensors; and one or more dielectric liners positioned between the polysilicon trench structure and the semiconductor layer, wherein the portion of the backside deep trench isolation structure is electrically coupled to the first polysilicon well. In some embodiments, the portion of the backside deep trench isolation structure is configured to be electrically biased via the first polysilicon well to increase a hole density around the portion of the backside deep trench isolation structure. In some embodiments, the one or more dielectric liners comprise at least one of: an oxygen-containing dielectric liner or a high-k dielectric liner.

[0153] As described in more detail above, some embodiments herein provide a method for forming a pixel sensor array, comprising forming a plurality of polysilicon wells above a front side of a semiconductor layer of the pixel sensor array. The method comprises forming an oxide layer on the front side of the semiconductor layer and above the plurality of polysilicon wells. The method comprises forming a plurality of spacers around sidewalls of the plurality of polysilicon wells. The method comprises forming a contact structure etch stop layer above the oxide layer and above the plurality of spacers. The method comprises forming a plurality of trenches through the semiconductor layer and extending into the plurality of polysilicon wells, wherein the plurality of trenches extend from a back side of the semiconductor layer to the front side of the semiconductor layer. The method comprises forming backside deep trench isolation structures in the plurality of trenches.

[0154] In some embodiments, forming the oxide layer includes forming the oxide layer such that a thickness of the oxide layer on the first side of the semiconductor layer is greater than a thickness of the oxide layer on the multiple polysilicon wells. In some embodiments, the method for forming a pixel sensor array further includes forming multiple hard mask layers above the top surfaces of the multiple polysilicon wells, wherein forming the contact structure etch stop layer includes forming the contact structure etch stop layer above the multiple hard mask layers. In some embodiments, forming the backside deep trench isolation structure includes forming one or more dielectric liners on the sidewalls and bottom surface of a trench among the multiple trenches; and filling the trench with an oxygen-containing material above the one or more dielectric liners. In some embodiments, forming the backside deep trench isolation structure includes: forming a dielectric liner on the sidewalls and bottom surface of a trench among the plurality of trenches; removing a portion of the dielectric liner from the bottom surface of the trench to expose a polysilicon well among the plurality of polysilicon wells through the bottom surface of the trench; and filling the trench with a polysilicon material, wherein the polysilicon material is formed directly on the polysilicon well at the bottom surface of the trench. In some embodiments, forming the dielectric liner also includes: forming the dielectric liner on the second side of the semiconductor layer such that a first thickness of the dielectric liner on the second side of the semiconductor layer is greater than a second thickness of the dielectric liner on the bottom surface of the trench, wherein removing the portion of the dielectric liner from the bottom surface of the trench results in removal of the dielectric liner from the second side of the semiconductor layer. In some embodiments, forming the backside deep trench isolation structure includes: forming a multi-layer dielectric liner on the sidewalls and bottom surface of a trench among the multiple trenches; removing a portion of the multi-layer dielectric liner from the bottom surface of the trench to expose a polysilicon well among the multiple polysilicon wells through the bottom surface of the trench; and filling the trench with a polysilicon material, wherein the polysilicon material is formed directly on the polysilicon well at the bottom surface of the trench.

[0155] As described in greater detail above, some embodiments herein provide a pixel sensor array comprising a plurality of pixel sensors, the pixel sensor array including a backside deep trench isolation structure extending completely through a semiconductor layer between a front side and a back side of the semiconductor layer of the pixel sensor array, wherein a bottom portion of the backside deep trench isolation structure extends into or is surrounded by one or more dielectric liners beneath the semiconductor layer, and wherein an annular polysilicon well is disposed around the bottom portion of the backside deep trench isolation structure in the one or more dielectric liners.

[0156] In some embodiments, the one or more dielectric liners include an oxide layer positioned between the annular polysilicon well and the backside deep trench isolation structure. In some embodiments, the one or more dielectric liners include a silicon nitride spacer layer positioned between the annular polysilicon well and the backside deep trench isolation structure. In some embodiments, the one or more dielectric liners include a contact structure etch stop layer positioned below and around the annular polysilicon well, and the contact structure etch stop layer is positioned between the annular polysilicon well and another annular polysilicon well surrounding another bottom portion of the backside deep trench isolation structure.

[0157] The term "meets a threshold value" in this article may mean, depending on the context, that a certain value is greater than the threshold value, greater than or equal to the threshold value, less than the threshold value, less than or equal to the threshold value, equal to the threshold value, not equal to the threshold value, etc.

[0158] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications to the present invention without departing from the spirit and scope of the present invention.

Claims

1. A pixel sensor array, characterized in that: include: Multiple pixel sensors; as well as a backside deep trench isolation structure surrounding the plurality of pixel sensors at least in a lateral direction, wherein the backside deep trench isolation structure extends completely through the semiconductor layer between the front side and the back side of the semiconductor layer of the pixel sensor array, and A first polysilicon well below the semiconductor layer surrounds a portion of the backside deep trench isolation structure.

2. The pixel sensor array according to claim 1, wherein: The portion of the backside deep trench isolation structure is a non-cross-interleaved portion of the backside deep trench isolation structure between two pixel sensors in the plurality of pixel sensors, and A second polysilicon well under the semiconductor layer surrounds a cross-staggered portion of the backside deep trench isolation structure at corners of at least three pixel sensors among the plurality of pixel sensors.

3. The pixel sensor array according to claim 2, wherein: A first distance between a bottom of the first polysilicon well and a bottom of the non-cross-staggered portion of the backside deep trench isolation structure is greater than a second distance between a bottom of the second polysilicon well and a bottom of the cross-staggered portion of the backside deep trench isolation structure.

4. The pixel sensor array according to claim 1, wherein: The portion of the backside deep trench isolation structure is a cross-staggered portion of the backside deep trench isolation structure at corners of at least three pixel sensors among the plurality of pixel sensors, A dielectric spacer is disposed around the sidewall of the first polysilicon well. A contact structure etch stop layer is disposed around the dielectric spacer and below the bottom surface of the first polysilicon well, and A portion of the contact structure etch stop layer surrounds a non-intersecting portion of the backside deep trench isolation structure located between two pixel sensors of the plurality of pixel sensors.

5. The pixel sensor array according to claim 1, wherein: The portion of the backside deep trench isolation structure is a cross-staggered portion of the backside deep trench isolation structure at corners of at least three pixel sensors among the plurality of pixel sensors, A dielectric spacer is disposed around the sidewall of the first polysilicon well. The hard shield layer is disposed below the bottom surface of the first polysilicon well. A contact structure etch stop layer is disposed below and around the dielectric spacer and the hard shield layer, and A portion of the contact structure etch stop layer surrounds a non-intersecting portion of the backside deep trench isolation structure located between two pixel sensors of the plurality of pixel sensors.

6. The pixel sensor array according to claim 1, wherein: The backside deep trench isolation structure includes: a polysilicon trench structure disposed in a staggered grid around the plurality of pixel sensors; and One or more dielectric liner layers are located between the polysilicon trench structure and the semiconductor layer, The portion of the backside deep trench isolation structure is electrically coupled to the first polysilicon well.

7. A pixel sensor array, characterized in that: include: Multiple pixel sensors; as well as a backside deep trench isolation structure extending completely through the semiconductor layer between the front side and the back side of the semiconductor layer of the pixel sensor array, wherein one or more dielectric liners below the semiconductor layer surround the bottom portion of the backside deep trench isolation structure, and An annular polysilicon well is disposed around the bottom portion of the backside deep trench isolation structure in the one or more dielectric liners.

8. The pixel sensor array according to claim 7, wherein: The one or more dielectric liners include an oxide layer between the annular polysilicon well and the backside deep trench isolation structure.

9. The pixel sensor array according to claim 7, wherein: The one or more dielectric liners include a silicon nitride spacer layer between the annular polysilicon well and the backside deep trench isolation structure.

10. The pixel sensor array according to claim 7, wherein: wherein the one or more dielectric liner layers include a contact structure etch stop layer disposed below and around the annular polysilicon well, and The contact structure etch stop layer is disposed between the annular polysilicon well and another annular polysilicon well surrounding another bottom portion of the backside deep trench isolation structure.

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