Apparatus including structures comprising contact vias and conductive lines and related methods

Abstract

The present application relates to apparatuses including structures comprising contact vias and conductive lines and related methods. The apparatuses include a structure comprising an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material including a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also includes a liner material adjacent to the metal line. An uppermost surface of the conductive material of the metal line outside of the contact has a width that is relatively smaller than a width of an uppermost surface of the conductive material of the contact.

Description

[0001] Divisional application information

[0002] This application is a divisional application of the invention patent application filed on August 13, 2020, with application number "202010810979.4" and titled "Apparatus and Related Methods Including Structures with Contact Through Holes and Conductive Wires".

[0003] Priority requirements

[0004] This application claims the benefit of U.S. Patent Application Serial No. 16 / 542,507, filed August 16, 2019, entitled “Apparatus Comprising Structures Including Contact Vias and Conductive Lines, Related Methods, and Memory Devices.” Technical Field

[0005] The embodiments disclosed herein relate to microelectronic devices and the manufacture of microelectronic devices. More specifically, embodiments of this disclosure relate to devices and related methods, memory devices, and electronic systems that include structures comprising metal wires, wherein the width of the metal wires is narrower at the uppermost surface of the metal wires outside the contact than at the uppermost surface of the contact. Background Technology

[0006] A persistent goal of the semiconductor industry has been to increase the memory density of memory devices (e.g., the number of memory cells per memory die), such as non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is by utilizing vertical memory array (also known as "3D memory array") architectures. Utilizing narrower metal lines is another way to increase memory density in such memory devices and associated logic devices (e.g., control logic components) by reducing the area occupied by the metal lines.

[0007] With advancements in 3D memory device technology, interconnect structures can be fabricated to minimize signal latency and optimize packing density. Such memory devices may comprise one or more memory arrays overlaid on complementary metal-oxide-semiconductor (CMOS) regions, such as under-array CMOS (CUA) regions. The reliability and performance of integrated circuits can be affected by the quality of their interconnect structures. As the size of such devices decreases, advanced and diverse metallization materials have been used to accommodate higher packing densities. One such metallization approach is a dual-damascene structure formed through a dual-damascene process. The dual-damascene process is a sequential mask / etch process used to form a two-level structure, for example, a contact via electrically connected to metal lines intersecting with contact vias.

[0008] Compared to a single damascene process, contact vias and trenches (e.g., wire trenches) can be filled simultaneously with a low-resistivity metal material in one or more stages (e.g., steps). Therefore, the dual damascene process has the advantages of simplifying the process and reducing manufacturing costs compared to a single damascene process.

[0009] To form a memory device using conventional dual damascene technology, metal material is deposited in a smaller opening of a metal wire trench. However, the increasing use of higher depth-to-width ratios for contact vias places greater demands on methods for forming memory devices that include metal wires and contact vias, such as in structures with metal wires in the trench, where the trench is narrower at its upper edge compared to the upper edge of the contact via. Summary of the Invention

[0010] According to embodiments of this disclosure, an apparatus includes a structure comprising an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material including metal wires and contacts. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also includes a lining material adjacent to the metal wires. The width of the uppermost surface of the conductive material on the metal wires outside the contacts is relatively smaller than the width of the uppermost surface of the conductive material on the contacts.

[0011] According to embodiments of this disclosure, a method for forming a device is disclosed. The method includes forming a trench in an upper insulating material overlying a lower insulating material, and forming contact vias in both the upper and lower insulating materials. The contact vias partially intersect the trench and extend from an upper surface of the upper insulating material to an upper surface of a conductive element below the contact via. The width of the upper edge of the contact via is greater than the width of the upper edge of the trench. The method further includes forming a conductive material in the contact vias, forming a lining material within the trench, and forming conductive material within the trench.

[0012] Furthermore, according to embodiments of this disclosure, a method for forming a device is also disclosed. The method includes forming contact vias in a first insulating material and a second insulating material to expose a conductive element underlying the first insulating material, and forming a trench in the second insulating material. The upper edge of the trench is narrower than the upper edge of the contact via. The method further includes forming a first portion of conductive material within the contact via, forming a lining material within the trench, and forming a second portion of conductive material within the trench.

[0013] According to an additional embodiment of this disclosure, a memory device includes a first insulating material adjacent to a metal pad, a second insulating material adjacent to the first insulating material, and a structure including a conductive material comprising metal wires extending through the second insulating material and contacts extending through both the first and second insulating materials. The metal wires intersect the contacts. The depth-to-width ratio of the contacts is between about 3:1 and about 12:1. The memory device also includes a lining material adjacent to the metal wires. The conductive material is in direct contact with each of the first insulating material, the second insulating material, and the metal pad. Attached Figure Description

[0014] Figures 1A to 1H A simplified partial cross-sectional view is provided to illustrate the various stages of forming a microelectronic device according to embodiments of the present disclosure, wherein... Figure 1D The simplified cross-sectional views of embodiments A, B, and C are along... Figure 1C The cross-section line 1D-1D of the plan view is used for cutting;

[0015] Figures 2A to 2H A simplified partial cross-sectional view is provided to illustrate various stages of forming a microelectronic device according to an additional embodiment of the present disclosure, wherein... Figure 2D The simplified cross-sectional views of embodiments A, B, and C are along... Figure 2C The cross-sectional line of the plan view is taken from 2D-2D.

[0016] Figure 3 This is a schematic block diagram illustrating one or more memory devices included in a microelectronic device according to embodiments of the present disclosure; and

[0017] Figure 4 This is a schematic block diagram of an electronic system according to an embodiment of the present disclosure. Detailed Implementation

[0018] Disclosed are microelectronic devices (e.g., apparatuses) comprising structures including contact vias and conductive (e.g., metallic) wires. In some embodiments, the structure of the microelectronic device includes an upper insulating material overlying a lower insulating material. Conductive elements (e.g., metal pads) may be located beneath the lower insulating material. The conductive material comprises metallic wires (e.g., within trenches) of the upper insulating material and contacts (e.g., within contact vias) extending through each of the upper and lower insulating materials. The conductive material may extend from an upper surface of the upper insulating material to the surface of the conductive element. The microelectronic device may also include a lining material adjacent to (e.g., beneath and / or laterally adjacent to) the metallic wires (e.g., within trenches). The width of the conductive material on the uppermost surface of the metallic wires outside the contacts may be relatively small compared to the width of the conductive material on the uppermost surface of the contacts. The structure may be formed using a so-called "trench-first" method, wherein trenches are formed in the upper insulating material, followed by contact vias formed in each of the upper and lower insulating materials. Alternatively, a so-called "through-hole first" method can be used to form the structure, in which contact through-holes are formed in each of the upper and lower insulating materials, followed by the formation of trenches in the upper insulating material.

[0019] The following description provides specific details, such as material composition and processing conditions, to provide a sufficient description of embodiments of this disclosure. However, those skilled in the art will understand that embodiments of this disclosure can be practiced without these specific details. In fact, embodiments of this disclosure can be practiced in conjunction with conventional semiconductor manufacturing techniques used in the semiconductor industry. Furthermore, the description provided below does not form a complete process flow for manufacturing microelectronic devices (e.g., memory devices). The structures described below do not form a complete microelectronic device. Only those processing stages (e.g., actions) and structures necessary for understanding embodiments of this disclosure are described in detail below. Additional stages for forming a complete microelectronic device can be performed using conventional manufacturing techniques.

[0020] The materials described herein can be formed using conventional techniques including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, or physical vapor deposition (PVD). Alternatively, the material can be grown. Depending on the specific material to be formed, the technique used for depositing or growing the material can be selected by one of ordinary skill in the art. Unless the context otherwise indicates, material removal can be achieved by any suitable technique including, but not limited to, etching, planarization (e.g., chemical-mechanical planarization), or other known methods.

[0021] The drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. Variations in the shapes depicted in the drawings should be expected, for example, due to manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas illustrated, but rather include shape deviations, for example, due to manufacturing processes. For instance, an area illustrated or described as box-shaped may have rough and / or non-linear characteristics, and an area illustrated or described as circular may include some rough and / or linear characteristics. Furthermore, acute angles illustrated may be rounded, and vice versa. Therefore, the areas illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the areas and do not limit the scope of the claims of the invention. The drawings are not necessarily drawn to scale. Additionally, common elements between figures may retain the same reference numerals.

[0022] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” are intended to include the plural forms as well.

[0023] As used herein, “and / or” includes any and all combinations of one or more of the associated listed items.

[0024] As used herein, “about” or “approximately” when referring to a value for a particular parameter includes, as understood by one of ordinary skill in the art, a value within acceptable tolerances of the particular parameter and the degree of variation in the value. For example, “about” or “approximately” when referring to a reference value may include additional values ​​that are in the range of 90.0% to 110.0% of the value, such as 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0025] As used herein, spatial relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “back,” “left,” and “right” may be used for descriptive purposes to illustrate the relationship of one element or feature to another as shown in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of material in addition to those depicted in the figures. For example, if the material in the figures is inverted, an element described as “below,” “under,” “below,” or “on the bottom” of another element or feature would be oriented “above” or “on the top” of said other element or feature. Thus, the term “below” may cover both above and below orientations depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptors used herein may be interpreted accordingly.

[0026] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is generally parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is generally perpendicular to the principal plane of the structure. The principal plane of the structure is defined by structural surfaces that have a relatively large area compared to the other surfaces of the structure.

[0027] As used herein, the term “configured” refers to the size, shape, material composition, orientation, and arrangement of one or more of the structures and devices that facilitate the operation of one or more of the structures and devices in a predetermined manner.

[0028] As used herein, referring to an element as "on" or "above" another element means and includes that the element is directly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to) the other element, below the other element, or in direct contact with the other element. This also includes the element being indirectly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to) the other element, below the other element, or near the other element, with other elements present therein. In contrast, when an element is referred to as "directly on" or "immediately adjacent to" another element, there is no intervening element.

[0029] As used herein, the term “critical size” refers to the size of the smallest geometric feature (e.g., the width of an interconnect, contact, trench, etc.).

[0030] As used herein, the term “microelectronic device” includes, but is not limited to, memory devices, and other devices (e.g., semiconductor devices), such as logic devices, processor devices, or radio frequency (RF) devices, which may or may not have memory. Furthermore, microelectronic devices may have memory in addition to other functions, such as a so-called “system-on-a-chip” (SoC) that includes a processor and memory, or a microelectronic device that includes logic and memory.

[0031] As used herein, the term "generally" in reference to a given parameter, property, or condition means and includes the degree to which a given parameter, property, or condition conforms to variance (e.g., within acceptable tolerances) as would be understood by one of ordinary skill in the art. By way of example, depending on the specific parameter, property, or condition that is generally satisfied, it may satisfy at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0032] As used herein, the term "substrate" means and includes materials (e.g., substrates) on which additional materials are formed. A substrate can be a semiconductor substrate, a base semiconductor material on a support structure, a metal electrode, or a semiconductor substrate having one or more materials, layers, structures, or regions formed thereon. Materials on a semiconductor substrate can include, but are not limited to, semiconducting materials, insulating materials, conductive materials, etc. A substrate can be a conventional silicon substrate or other bulk substrate including layers of semiconducting materials. As used herein, the term "bulk substrate" means and includes not only silicon wafers but also silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") and silicon-on-glass ("SOG") substrates, silicon epitaxial layers on a base semiconductor, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. Substrates can be doped or undoped.

[0033] Figures 1A to 1H Various method stages of a method for forming a microelectronic device comprising a structure according to some embodiments of the present disclosure are described. The method is a so-called "trench-first" structure formation method. For simplicity, the formation of two structures is described, but those skilled in the art will understand that the method may involve forming multiple microelectronic devices (e.g., more than one device, an array of devices) comprising such structures. For ease of description... Figures 1A to 1H ,like Figures 1A to 1E The first direction shown in 1G can be defined as the X direction. For example... Figure 1F and 1H The second direction, which is laterally (e.g., perpendicularly) to the first direction, of the metal wire extension direction shown can be defined as the Y direction. Figures 1A to 1HThe direction shown (e.g., vertical) that is laterally (e.g., perpendicular) to each of the first and second directions can be defined as the Z direction. Figures 2A to 2H As shown, similar directions can be defined, as discussed in more detail below.

[0034] refer to Figure 1A The partially fabricated microelectronic device 100 includes a substrate insulating material 102 adjacent to a substrate (not shown) (e.g., above the substrate), conductive elements 104 (e.g., conductive pads, metal pads), a barrier material 106 formed adjacent to the substrate insulating material 102 (e.g., above the substrate insulating material), and a first insulating material 108 (e.g., interlayer insulating material) formed adjacent to the barrier material 106 (e.g., above the barrier material). The microelectronic device 100 also includes an etch-stopping material 110 formed adjacent to the first insulating material 108 (e.g., above the first insulating material), and a second insulating material 112 (e.g., another interlayer insulating material) formed adjacent to the etch-stopping material 110 (e.g., above the etch-stopping material).

[0035] The conductive element 104 can be formed using conventional techniques and can be at least partially embedded within the substrate insulating material 102 and / or the barrier material 106. For example, the conductive material can be formed over the substrate insulating material 102 and patterned using conventional photolithography to form the conductive element 104. For example, a photoresist material (not shown) can be formed over the conductive material and patterned using conventional techniques, wherein the pattern in the photoresist material is then transferred to the conductive material. The conductive element 104 can be formed, for example, using a dry etching process. In some embodiments, at least a portion of the barrier material 106 can be formed above the upper surface of the conductive element 104 (e.g., covering the upper surface). In other embodiments, the portion of the barrier material 106 covering the conductive element 104 is removed to expose the upper surface of the conductive element 104 such that the upper surface of the conductive element 104 is substantially coplanar with the upper surface of the barrier material 106.

[0036] The conductive element 104 (e.g., a conductive material) may be formed of a metal, a metal alloy, a metal-containing material, a conductively doped semiconductor material, or a combination thereof. The conductive element 104 may include, but is not limited to, aluminum, copper, gold, iridium, iridium oxide, molybdenum, molybdenum nitride, nickel, platinum, ruthenium, ruthenium oxide, titanium ruthenium nitride, silver, tantalum, tantalum nitride, tantalum silicide, titanium, titanium nitride, titanium silicide, aluminum titanium nitride, silicon titanium nitride, tungsten, tungsten nitride, tungsten silicide, their alloys, combinations thereof, or conductively doped silicon.

[0037] Each of the substrate insulating material 102, barrier material 106, first insulating material 108, etch-stopping material 110, and second insulating material 112 may be formed of one or more dielectric materials. The dielectric materials may be formed over the respective underlying materials using conventional techniques. For example, the dielectric materials may be formed by spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, or physical vapor deposition (PVD). In some embodiments, each of the first insulating material 108, etch-stopping material 110, and second insulating material 112 may be formed in a single deposition stage of a dual-damascene process.

[0038] The dielectric material may include, but is not limited to, silicon oxide or silicon nitride. For example, at least one (or more) of the substrate insulating material 102, the first insulating material 108, or the second insulating material 112 may be formed of silicon oxide. The first insulating material 108 and the second insulating material 112 are separated from each other by an etch-stopping material 110. The substrate insulating material 102, the first insulating material 108, and the second insulating material 112 may be formed to a thickness sufficient to electrically isolate the conductive materials from each other. Furthermore, each of the first insulating material 108 and the second insulating material 112 may be formed to a thickness (e.g., depth) sufficient to accommodate the conductive material formed therein, as discussed in more detail below. In some embodiments, the first insulating material 108 may be formed to a thickness of about 1 μm to about 10 μm, for example, about 1 μm to about 5 μm, or about 5 μm to about 10 μm, and the second insulating material 112 may be formed to a thickness of about 1 μm to about 30 μm, for example, about 1 μm to about 15 μm, or about 15 μm to about 30 μm.

[0039] Furthermore, each of the barrier material 106 and the etch-stop material 110 may also be formed of a dielectric material comprising, but not limited to, silicon oxide or silicon nitride. For example, at least one (e.g., both) of the barrier material 106 or the etch-stop material 110 may be formed of silicon nitride. The dielectric materials of the barrier material 106 and the etch-stop material 110 may be selectively etchable relative to the substrate insulating material 102, the first insulating material 108, and the second insulating material 112. Each of the dielectric materials of the barrier material 106 and the etch-stop material 110 may be different from the materials of the substrate insulating material 102, the first insulating material 108, and the second insulating material 112, and may react with etchants different from the three insulating materials. In some embodiments, the barrier material 106 and the etch-stop material 110 may be formed of the same dielectric material (e.g., silicon nitride). In other embodiments, the dielectric materials of the barrier material 106 and the etch-stop material 110 may be different from each other.

[0040] like Figure 1AAs shown, portions of the second insulating material 112 are selectively removed to form trenches 114 corresponding to the locations of the metal lines where the second-level interconnects will ultimately be formed. An etch-stop material 110 substantially prevents the trenches 114 from extending through the first insulating material 108. The thickness of the second insulating material 112 substantially corresponds to the depth of the trenches 114. The trenches 114 are at least partially defined by the sidewalls of the second insulating material 112 and can be formed using conventional photolithography techniques. For example, a photoresist material (not shown) can be formed over the second insulating material 112 and patterned using conventional techniques, wherein the pattern in the photoresist material is then transferred to the second insulating material 112. The trenches 114 can be formed, for example, using a dry etching process.

[0041] like Figure 1B As shown, additional portions of the second insulating material 112, the etch-stop material 110, and the underlying portion of the first insulating material 108 are selectively removed to expose corresponding portions of the conductive element 104 and form a via 116 (e.g., an opening). The conductive element 104 prevents the via 116 from extending through to the substrate insulating material 102. The combined thickness of the first insulating material 108, the etch-stop material 110, and the second insulating material 112 substantially corresponds to the depth of the via 116. In some embodiments, the depth of the via 116 within the first insulating material 108 is relatively large compared to the depth of the trench 114 within the second insulating material 112. The via 116 is defined by the sidewalls of the second insulating material 112, the etch-stop material 110, and the first insulating material 108 and can be formed using conventional photolithography techniques. For example, the trench 114 can be used, for instance, during the etching process to mask the underlying material. Specifically, one or more dry etching processes can be used to form the via 116. The same etchant used to remove the etch-stopping material 110 or a different etchant can be used to remove portions of the first insulating material 108 and the second insulating material 112. In embodiments where a portion of the barrier material 106 is formed adjacent to the conductive element 104, portions of the barrier material 106 are also selectively removed to expose corresponding portions of the conductive element 104.

[0042] like Figure 1B As shown, the trench 114 may be defined by the sidewalls of the second insulating material 112. Furthermore, the upper edge of the trench 114 is relatively narrower than the upper edge of the through-hole 116. In other words, the critical dimension (e.g., the width W1 extending in the X direction) measured from the top of the trench 114 outside the through-hole 116 (e.g., the side-connected through-hole) may be relatively smaller than the critical dimension (e.g., the width W2 extending in the X direction) measured from the top of the through-hole 116.

[0043] In some embodiments, each of the trenches 114 and vias 116 may have a wedge-shaped profile, wherein the upper portion of each individual trench 114 and individual via 116 has a larger critical dimension (e.g., width) than its lower portion. In such embodiments, the trench 114 may have a top critical dimension (e.g., width) of about 20 nm to about 100 nm, about 30 nm to about 100 nm, or about 30 nm to about 90 nm, and a bottom critical dimension of about 20 nm to about 90 nm, about 30 nm to about 90 nm, or about 30 nm to about 85 nm. Furthermore, the trench 114 may have a uniform trench depth. The width of the via 116 at its top may be relatively larger than the width of the trench 114 at its top, and the via may have a top critical dimension of about 30 nm to about 120 nm, for example, about 30 nm to about 110 nm, or about 30 nm to about 100 nm, and a bottom critical dimension of about 20 nm to about 100 nm, about 30 nm to about 100 nm, or about 30 nm to about 95 nm. By means of non-limiting examples, the depth-to-width ratio (depth:width) of the via 116 (e.g., extending from the top surface of the second insulating material 112 to the top surface of the conductive element 104) may be between about 3:1 and about 30:1, for example, between about 3:1 and about 12:1, between about 3:1 and about 10:1, or between about 3:1 and about 5:1. In other embodiments, at least some of the trenches 114 and / or through holes 116 may have different profiles, such as right-angled (e.g., rectangular) profiles, disc-shaped profiles, or any other three-dimensional recessed shapes.

[0044] like Figure 1C and Figure 1D As shown in the combination, one or more conductive materials (e.g., low-resistivity metallic materials) are formed in one or more stages within the openings of portions of the via 116 and / or trench 114 to form contacts 120 (e.g., via plugs) within the via 116 and / or trench 114. The conductive material of the contacts 120 may be a low-resistivity metallic material including, but not limited to, tungsten or tungsten nitride. Alternatively, the contacts 120 may be formed of any other low-resistivity metallic material, such as aluminum, copper, molybdenum, noble metals, near-noble metals, or alloys thereof.

[0045] Lining material 118 may be formed within the through-hole 116 and / or groove 114 as a portion adjacent to (e.g., above) the contact 120. In some embodiments, lining material 118 may be present along portions of the sidewalls of the first insulating material 108 and / or the second insulating material 112, without being adjacent to (e.g., above) the central portion of the contact 120. Alternatively, lining material 118 may cover the contact 120 without being present along the sidewalls of either the first insulating material 108 or the second insulating material 112. In yet another embodiment, lining material 118 may cover (e.g., substantially completely cover) the contact 120 and be present along substantially the entire exposed portion of the exposed sidewalls of the first insulating material 108 and / or the second insulating material 112, such as... Figure 1D As shown in the cross-sectional view. Those skilled in the art will appreciate that embodiments of this disclosure may also include any combination of lining materials 118 present along portions of the sidewalls and / or the bottom portions of the openings. The lining material 118 may be formed of a metal nitride material comprising, but not limited to, metal silicon nitride or metal boron nitride.

[0046] Furthermore, the placement of the lining material 118 may depend on the extent (e.g., size, position, etc.) of the contacts 120 within the opening. Specifically, the size (e.g., thickness, depth, etc.) of the contacts 120 may vary, such as Figure 1C and 1D As shown in embodiments A, B, and C, wherein Figure 1D The cross-sectional views of embodiments A, B, and C are along... Figure 1C The planar view is cut by a 1D-1D section line. For example, the upper surface of contact 120 can be substantially aligned with the upper surface of the etch stop material 110, such as... Figure 1D As shown in the cross-sectional view of Embodiment A. In this embodiment, the lining material 118 may be present only in the upper portion of the through-hole 116 (e.g., along the sidewall of the second insulating material 112), while the lower portion of the through-hole 116 (e.g., the sidewall of the first insulating material 108) may be partially or alternatively completely devoid of (e.g., lacking, absent, etc.) the lining material 118. In other words, the lining material 118 may be formed only above the upper surface of the etch-stop material 110. Additionally, the lining material 118 may be present in the portion of the trench 114 outside the opening (e.g., in the trench 114 of the side-connected through-hole 116), such that the lining material 118 is continuous along the metal line, as... Figure 1C As shown in the plan view of embodiment A.

[0047] In other embodiments, the upper surface of contact 120 may be lower than the etch stop material 110 (e.g., recessed relative to the etch stop material), such as... Figure 1DAs shown in the cross-sectional view of Embodiment B. In other words, portions of the lining material 118 may also be located within at least some of the upper portions of the through-hole 116. In such embodiments, the lining material 118 may be formed within the upper portion of the through-hole 116 (e.g., along the sidewall of the second insulating material 112) and within the lower portion of the through-hole 116 (e.g., along the sidewall of the first insulating material 108). Additionally, the lining material 118 may be present within the portion of the groove 114 outside the through-hole 116 (e.g., within the groove 114 adjacent to the through-hole 116), such that the lining material 118 is continuous along the metal wire, as... Figure 1C As shown in the plan view of embodiment B.

[0048] In other embodiments, the upper surface of the contact 120 may be substantially aligned with the upper surface of the second insulating material 112, such as... Figure 1D As shown in the cross-sectional view of Embodiment C. In other words, each of the portions of the through-hole 116 and the trench 114 covering the through-hole 116 may be completely free of lining material 118. In such embodiments, the lining material 118 may be present only in the portion of the trench 114 outside the through-hole 116 (e.g., the bottom portion and / or sidewalls), and not at all surrounding the conductive material within the through-hole 116, such as... Figure 1C As shown in the plan view of Embodiment C. Furthermore, the sidewalls of the first insulating material 108 and / or the second insulating material 112 within the through-hole 116 may be partially or entirely devoid of (e.g., lacking, absent, etc.) lining material 118. In other words, lining material 118 may be present only within a portion of the side-connected through-hole 116 of the trench 114, such that a portion of lining material 118 is discontinuous along the metal line 122.

[0049] Furthermore, a significant portion (e.g., more than half) of the surface area of ​​the sidewalls of the second insulating material 112 may be substantially free of (e.g., completely free of) the lining material 118. By way of a non-limiting example, between about 25% and about 50%, for example, between about 25% and about 35%, of the surface area of ​​the sidewalls of the second insulating material 112 may be completely free of the lining material 118. In other words, only between about 50% and about 75%, for example, between about 50% and about 65%, of the surface area of ​​the second insulating material 112 may contain the lining material 118. In some embodiments, the size (e.g., thickness, depth, etc.) of the lining material 118 may depend at least in part on the relative sizes of the vias 116 and the trenches 114. In other embodiments, the size of the lining material 118 may be independent of the relative sizes of the vias 116 and the trenches 114. Furthermore, in some embodiments, the microelectronic device 100 may be formed using a dual-damascene process without being limited by the depth-to-width ratio of the vias 116. For example, the liner material 118 can be formed independently of the depth-to-width ratio of the via 116. In other embodiments, the formation of the liner material 118 may depend at least in part on the specific depth-to-width ratio of the via 116. Thus, the microelectronic device 100 can be formed using a dual damascene process without being limited by the relative critical dimensions (e.g., width) of the via 116 and the trench 114, and without being limited by the depth-to-width ratio of the via 116.

[0050] like Figure 1E As shown, in one or more stages, one or more additional portions of conductive material (e.g., a low-resistivity metallic material) are formed within the openings of via 116 and trench 114 to form a contact 120 within via 116 and a metal wire 122 within trench 114. The additional portions of conductive material (e.g., of the contact 120 and metal wire 122) may also be a low-resistivity metallic material comprising, but not limited to, tungsten or tungsten nitride. Alternatively, the additional portions of conductive material may be formed of any other low-resistivity metallic material, such as aluminum, copper, molybdenum, noble metals, near-noble metals, or alloys thereof. The conductive materials in each of via 116 and trench 114 may be the same or different.

[0051] In some embodiments, the via 116 and trench 114 may be filled with conductive material simultaneously in a single stage. In other words, conductive material may be deposited in a single deposition stage to substantially fill the via 116 and trench 114. For example, a dual damascene process may be employed, comprising a single stage (e.g., a cycle) of insulating film deposition, two stages of photoresist patterning and etching (e.g., for the via 116 and trench 114), and a single stage of CMP processing. In other embodiments, the via 116 and trench 114 may be filled with conductive material substantially in two deposition stages. In such embodiments, selective metal deposition in the via 116, as referenced above, may be used. Figure 1C and 1D In more detail, a lining material 118 is then formed within portions of trench 114 (e.g., the bottom portion and / or sidewalls) and through-hole 116 to form portions of the contact 120. Subsequently, additional portions of the contact 120 and / or metal lines 122 can be formed in another (e.g., a subsequent) deposition stage using, for example, conventional deposition techniques. In other words, a first insulating material 108 and a second insulating material 112 can be formed in a single deposition process, followed by the deposition of a conductive material. Subsequently, the upper portion of the conductive material above the upper surface of the second insulating material 112 can be removed (e.g., by CMP treatment) without removing the upper portion of the conductive material above the upper surface of the first insulating material 108 before forming the second insulating material 112. In contrast to a dual damascene process, a single damascene process generally requires two stages of film deposition, two stages of photoresist patterning and etching processes, and two stages of CMP treatment. Before forming the metal line 122 within the trench 114, the exposed surface of the contact 120 can be cleaned with a selective etchant, for example, to provide a rough (e.g., textured) surface on the exposed surface to allow (e.g., promote) the growth of metal material (e.g., lining material 118) thereon, without requiring a two-stage CMP process.

[0052] Contacts 120 and metal wires 122 can be formed, for example, using chemical vapor deposition (CVD) or physical vapor deposition (PVD). Alternatively or additionally, conventional techniques can be used to form contacts 120 and / or metal wires 122 using selective CVD deposition. Such selective deposition processes can be used to reduce (e.g., prevent) the conductive material from becoming "pinched" at the interface between contacts 120 and metal wires 122, and can be used to reduce voids, gaps, etc., within or near the conductive material. Furthermore, lining material 118 can be grown in situ within trenches 114 and / or vias 116. For example, lining material 118 can be formed during the epitaxial "bottom-up" growth of CVD metal within trenches 114 and / or vias 116 by selective CVD deposition, for example, using such conductive material of contacts 120 as a reactant, while at least a portion of the conductive material is exposed. Specifically, this conductive material can be conductive to supply electrons required for the decomposition of the metal precursor gas and the deposition of the resulting metal material. Therefore, forming a lining material 118 within the trench 114 and / or through-hole 116 can reduce the potential occurrence of voids, gaps, etc. between adjacent areas of the conductive material during the double-insertion process and improve the metal-to-metal contact therebetween, while not allowing (e.g., promoting) the conductive material to accumulate along the sidewalls of the second insulating material 112, for example, within openings having a smaller critical size and / or a high depth-to-width ratio.

[0053] like Figure 1EAs shown, portions of each of the etch-stop material 110 and the first insulating material 108 underlying the second insulating material 112 may be laterally recessed relative to the liner material 118, such that the area under the etch-stop material 110 and the first insulating material 108 is cut into the second insulating material 112 and / or the liner material 118. In other words, portions of the second insulating material 112 and / or the liner material 118 may extend further into the upper portion of the through-hole 116 relative to the sidewalls of the etch-stop material 110 and / or the first insulating material 108. Furthermore, portions of the second insulating material 112 and / or the liner material 118 may provide sidewalls for at least a portion of the upper portion of the through-hole 116, such that the uppermost surface of the metal line 122 outside the contact (e.g., the side contact point) is relatively narrower than the uppermost surface of the contact 120. In other words, the critical dimension (e.g., width W3 extending in the X direction) measured from the uppermost surface of the metal wire 122 outside the contact 120 can be relatively small compared to the critical dimension (e.g., width W4 extending in the X direction). By means of a non-limiting example, the width of the uppermost surface of each of the metal wires 122 outside the contact 120 is between about 15% and about 95% of the width of the uppermost surface of the contact 120, for example, between about 25% and about 85%, or between about 35% and about 75%. In other words, for example, the width of the uppermost surface of each of the metal wires 122 outside the contact 120 is between about 5 nm and about 10 nm smaller than the width of the uppermost surface of the contact 120. Specifically, the lining material 118 may be positioned and configured to reduce the formation of voids in the via 116 near the sidewalls of the etch-stop material 110 and / or the sidewalls of the first insulating material 108 (e.g., in the undercut region of the portion of the second insulating material 112 and / or the lining material 118) when the conductive material is formed in the via 116 and the trench 114.

[0054] In contrast, conventional dual-damascene processes create a conventional structure where the top of the trench is wider than the top of the contact via. For example, the top width of the contact via in a conventional structure may be between approximately 45% and approximately 85% of the width of the trench top. A wider trench allows direct visibility of the contact via, where the top of the contact via is relatively narrower than the top of the trench in such conventional structures. However, using a dual-damascene process in the microelectronic device 100 that includes forming a trench 114 with a top relatively narrower than the top of the via 116 increases the likelihood of voids, gaps, etc., appearing in the conductive material, and specifically at the interface between the contact 120 and the metal wire 122. Therefore, the lining material 118, as disclosed herein, can be positioned and configured to reduce (e.g., prevent) the occurrence of such voids, gaps, etc., to allow sufficient metal-to-metal contact between the contact 120 and the metal wire 122 at their interface. Furthermore, the lining material 118 can be positioned and configured to enhance the insulating properties of selected areas (e.g., adjacent to the metal wire 122). Those skilled in the art will understand that embodiments of this disclosure can also be used to form conventional structures where the top of the trench is wider than the top of the contact via.

[0055] Furthermore, in some embodiments, one or more of the openings may be lined with additional material (e.g., seed material, diffusion barrier material, etc.) to ensure proper electrical connection between the contact 120 and the metal wire 122. In other embodiments, each of the openings including the through-hole 116 and the trench 114 may be completely free of seed material and diffusion barrier material. In other words, the conductive material of the metal wire 122 may be in direct contact (e.g., direct physical contact) with the second insulating material 112 and each of the contacts 120. Additionally, the contacts 120 may be in direct contact (e.g., direct physical contact) with the second insulating material 112, the first insulating material 108, and the conductive element 104.

[0056] Figure 1F In order to be in Figure 1E The diagram shows a cross-sectional view of the microelectronic device 100 at the formation stage along the Y direction. Figure 1F As shown, when viewed from the Y direction, a portion of the metal wire 122 within the through-hole 116 may be formed to extend substantially between the sidewalls of the second insulating material 112 at this formation stage (e.g., fully extended).

[0057] like Figure 1GAs shown, the formation of contacts 120 and metal wires 122 results in the formation of a conductive structure 126 coupling one of the metal wires 122 to the contacts 120 within one or more vias 116. In other words, the combined structure including contacts 120 and metal wires 122 is formed together using a dual damascene process to form the conductive structure 126, the process comprising selectively depositing a conductive material comprising a metal nitride material (e.g., liner material 118), the metal nitride material being grown in situ in the bottom of at least one of the conductive materials (e.g., contacts 120) under at least a portion of the conductive material.

[0058] Figure 1H In order to be in Figure 1G The diagram shows a cross-sectional view of the microelectronic device 100 at the formation stage along the Y direction. The trench 114 is located at the through-hole 116 ( Figure 1B The external portion (e.g., a side-mounted via) may be formed over the etch-stop material 110 and may be formed by the second insulating material 112. Figure 1G The remaining portions (shown) are separated from each other to form the metal wire 122 therein. An opening (not shown) can be formed in the second insulating material 112 using conventional techniques, for example, a dry etching process. The metal wire 122 can then be formed within such an opening using conventional techniques. As discussed above, the metal wire 122 can be formed of a low-resistivity metallic material similar to the material of the contact 120 (e.g., tungsten or tungsten nitride). Alternatively, the metal wire 122 can be formed of any other low-resistivity metallic material, such as aluminum, copper, molybdenum, or alloys thereof. The metal wire 122 can be connected to the contact 120 (e.g., electrically connected), as from... Figure 1H Viewed in the Y direction. Subsequently, a chemical mechanical planarization (CMP) process can be performed to remove the conductive material portion extending above the upper surface of the second insulating material 112, leaving this conductive material in the trenches 114 and through-holes 116. Figure 1BThe desired portion within the structure 126. In this way, the second insulating material 112 can serve as an etch stop layer during the CMP stage. A portion of the side-mounted via 116 of the metal line 122 can connect the conductive material of the individual conductive structures 126, including portions of the metal line 122 and contact 120 within the via 116, and the conductive element 104, to other conductive structures within the microelectronic device 100. The planarized surface of the microelectronic device 100 allows for subsequent metallization to establish a multi-level interconnect structure. Subsequent process stages not described herein can be performed using conventional techniques to complete the formation of the microelectronic device 100 and microelectronic devices containing such structures. Therefore, the microelectronic device 100 can be fabricated using a dual damascene process, which includes a single-stage (e.g., cyclic) insulating film deposition, two-stage photoresist patterning and etching processes (e.g., for via 116 and trench 114), one or two stages of conductive material deposition, and a single-stage CMP process. In comparison, a single tiling process generally requires two stages of insulating material film deposition, two stages of photoresist patterning and etching, and two stages of CMP treatment.

[0059] Therefore, a method for forming a device is disclosed. The method includes forming a trench in an upper insulating material overlying a lower insulating material, and forming contact vias in both the upper and lower insulating materials. The contact vias partially intersect the trench and extend from the upper surface of the upper insulating material to the upper surface of a conductive element below the contact via. The width of the upper edge of the contact via is greater than the width of the upper edge of the trench. The method also includes forming a conductive material in the contact vias, forming a lining material within the trench, and forming a conductive material within the trench.

[0060] Figures 2A to 2H This section describes various method stages of a method for forming a microelectronic device structure including a dual-damascene structure according to additional embodiments of the present disclosure. The method is a so-called "via-first" method for forming a dual-damascene structure.

[0061] refer to Figure 2AThe partially fabricated microelectronic device 100' includes a substrate insulating material 102 adjacent to a substrate (not shown) (e.g., above the substrate), a conductive element 104, a barrier material 106 formed adjacent to the substrate insulating material 102 (e.g., above the substrate insulating material), and a first insulating material 108 formed adjacent to the barrier material 106 (e.g., above the barrier material). The microelectronic device 100' also includes an optional etch-stopping material 110 formed adjacent to the first insulating material 108 (e.g., above the first insulating material), and a second insulating material 112 formed adjacent to the optional etch-stopping material 110 (e.g., above the etch-stopping material). Many portions of the microelectronic device 100', such as the conductive material of the conductive element 104 and the dielectric materials of the substrate insulating material 102, barrier material 106, first insulating material 108, optional etch-stopping material 110, and second insulating material 112, and their dimensions, may be consistent with... Figures 1A to 1H The components included in the embodiments of the microelectronic device 100 are the same. Furthermore, such conductive and dielectric materials are formed (e.g., deposited) using the same processes used in the previous embodiments. As in the previous embodiments, a first insulating material 108 is formed adjacent to a barrier material 106 (e.g., above the barrier material), which in turn is formed adjacent to a substrate insulating material 102 (e.g., above the substrate insulating material). Additionally, an optional etch-stop material 110 (if present) is formed adjacent to the first insulating material 108 (e.g., above the first insulating material), and a second insulating material 112 is formed above the etch-stop material. Thereafter, a via 116 may be formed in each of the second insulating material 112, the optional etch-stop material 110, and the first insulating material 108. As in the previous embodiment, the via 116 is defined by a second insulating material 112, an optional etch-stopping material 110 (if present), and the sidewalls of a first insulating material 108, and can be formed by conventional photolithography using photoresist materials followed by a dry etching process, for example, as referenced above. Figure 1B To elaborate further.

[0062] like Figure 2B As shown, additional portions of the second insulating material 112 are selectively removed to form a trench 114, and then a conductive material is formed in the trench to create metal lines 122 for the second-level interconnect. In such embodiments, the trench 114 may be formed after the via 116 is formed. The trench 114 is at least partially defined by the sidewalls of the second insulating material 112 and can be formed by conventional photolithography using photoresist materials, followed by a dry etching process, such as as referenced above. Figure 1A To elaborate further. As in the previous embodiment, the upper edge of the groove 114 is relatively narrower than the upper edge of the through hole 116.

[0063] like Figure 2C and Figure 2D As shown in the combination, one or more conductive materials (e.g., low resistivity metallic materials) are formed in one or more stages within a portion of the opening of the through-hole 116 to form a contact 120 (e.g., a through-hole plug) within the through-hole 116 and a metal wire 122 within the trench 114. A lining material 118 may be formed within portions of the through-hole 116 and / or the trench 114 as a portion adjacent to the contact 120 (e.g., above the portion). The placement of the lining material 118 may depend on the extent (e.g., size, position, etc.) of the contact 120 within the opening, as referenced above. Figure 1C and 1D To elaborate further. Specifically, the size of contact 120 (e.g., thickness, depth, etc.) can vary, such as... Figure 2C and 2D As shown in embodiments A, B, and C, wherein Figure 2D The cross-sectional views of embodiments A, B, and C are along... Figure 2C The 2D-2D section line of the plan view is taken.

[0064] like Figure 2E As shown, in one or more stages, one or more additional portions of a conductive material (e.g., a low-resistivity metallic material) are formed within the openings of the via 116 and the trench 114 to form a contact 120 within the via 116 and a metal wire 122 within the trench 114. For example, the via 116 and the trench 114 may be filled substantially simultaneously with such conductive material, or alternatively, the via and the trench may be filled with conductive material in two deposition stages of the dual damascene process, as referenced above. Figure 1E To elaborate further. Additional portions of the conductive material of contact 120 and metal wire 122 may be low-resistivity metallic materials comprising, but not limited to, tungsten or tungsten nitride. Furthermore, the conductive material may be formed using a CVD or PVD deposition process, and / or using a liner material 118, for example, a selective CVD deposition process in-situ grown within trench 114 and / or via 116. For example, the liner material 118 may be formed during the epitaxial “bottom-up” growth of CVD metal within trench 114 and / or via 116 by a selective CVD deposition process, for example, using the conductive material of contact 120 as a reactant. Therefore, forming the liner material 118 within trench 114 and / or via 116 can reduce the potential occurrence of voids, gaps, etc., between adjacent areas of the conductive material during the dual-damascene process and improve metal-to-metal contact therebetween, without allowing (e.g., promoting) the accumulation of conductive material along the sidewalls of the second insulating material 112, for example, within openings having smaller critical dimensions and / or high depth-to-width ratios. Furthermore, the location and size of the material may be substantially similar (e.g., identical) to those locations and sizes discussed in the previous embodiments.

[0065] Figure 2F In order to be in Figure 2E The diagram shows a cross-sectional view of the microelectronic device 100' at the formation stage along the Y direction. Figure 2F As shown, when viewed from the Y direction, a portion of the metal wire 122 within the through-hole 116 may be formed to extend substantially between the sidewalls of the second insulating material 112 at this formation stage (e.g., fully extended).

[0066] like Figure 2G As shown, the formation of the contact 120 and the metal wire 122 results in the formation of a conductive structure 126 comprising the contact 120 (e.g., a through-hole plug) and the metal wire 122, as referenced above. Figure 1G To be discussed in more detail. Thus, the combined structure of contact 120 and metal wire 122 is used together to form conductive structure 126 using a dual damascene process, which includes selectively depositing a conductive material comprising a metal nitride material (e.g., lining material 118), which can be in-situ grown using the conductive material (e.g., contact 120), for example, in the bottom of at least one of the openings (e.g., trench 114).

[0067] Figure 2H In order to be in Figure 2G The diagram shows a cross-sectional view of the microelectronic device 100′ at the formation stage along the Y direction. As in the previous embodiment, the trench 114 is located in the through-hole 116 ( Figure 2B The external portion (e.g., a side-mounted via) may be formed adjacent to the etch-stop material 110 and may be made of a second insulating material 112. Figure 2G The remaining portions (shown in the diagram) are separated from each other to form metal lines 122 therein. Subsequently, a chemical mechanical planarization (CMP) process can be performed to provide a planarized surface for subsequent metallization to establish a multi-level interconnect structure and for subsequent process stages to complete the formation of the microelectronic device 100'.

[0068] Therefore, a method for forming a device is disclosed. The method includes forming a contact via in a first insulating material and a second insulating material to expose a conductive element underlying the first insulating material, and forming a trench in the second insulating material. The upper edge of the trench is narrower than the upper edge of the contact via. The method further includes forming a first portion of conductive material within the contact via, forming a lining material within the trench, and forming a second portion of conductive material within the trench.

[0069] Figures 2A to 2H The resulting structure of the microelectronic device 100' can be substantially similar to (e.g., identical to) that of... Figures 1A to 1HThe structure of the microelectronic device 100. Therefore, whether using a "trench-first" or "via-first" approach integrated into a dual damascene process, a microelectronic device (e.g., a device) incorporating a dual damascene structure can be fabricated without being limited by the relative critical dimensions of the contact vias and trenches, and without requiring a single damascene process. This structure includes a metal line outside the contact with a relatively narrow upper surface compared to the upper surface of the contact. Furthermore, a lining material 118 can be formed during the epitaxial "bottom-up" growth of the CVD metal within the trenches 114 and / or vias 116 via a selective CVD deposition process, for example, to reduce (e.g., prevent) the appearance of voids, so as to allow sufficient metal-to-metal contact between conductive materials containing contact vias with a high depth-to-width ratio. The dual damascene process and the resulting structure disclosed herein may include sequential (e.g., two-stage) mask / etching processes for forming a two-level structure, such as contact vias intersecting two side-mounted trenches, the upper edges of which are relatively narrower than the upper edges of the contact vias. Therefore, the dual damascene process improves upon the single damascene process by allowing trenches and contact vias to be filled before planarization, thus eliminating processing stages and avoiding unnecessary waste of conductive material.

[0070] Therefore, an apparatus is disclosed. The apparatus includes a structure comprising an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material including metal wires and contacts. The conductive material extends from the upper surface of the upper insulating material to the upper surface of the conductive element. The structure also includes a lining material adjacent to the metal wire. The width of the uppermost surface of the conductive material on the metal wire outside the contacts is relatively smaller than the width of the uppermost surface of the conductive material on the contacts.

[0071] Microelectronic devices 100, 100' according to embodiments of the present disclosure can be used in memory devices 300 comprising one or more memory arrays 302 containing memory cells. Figure 3The functional block diagram schematically illustrates a memory device 300 (e.g., a DRAM device, a 3D NAND flash memory device). The memory device 300 includes a memory array 302 comprising memory cells of one or more microelectronic devices 100, 100', and a control logic component 304. The control logic component 304 is configured to operatively interact with the memory array 302 to read, write, or refresh any or all memory cells within the memory array 302. For example, the memory device 300 may include a memory array 302 that may include complementary metal-oxide-semiconductor (CMOS) regions, such as an under-array CMOS (CUA) region 306 underlying the memory array 302. The memory array 302 may include memory cells connected to access lines (e.g., word lines) and data lines (e.g., bit lines). Furthermore, the CUA region 306 may be underlying the memory array 302 and include its support circuitry. The support circuitry may support one or more additional arrays of memory cells present in a stacked configuration. For example, the memory device 300, which includes a memory array 302 with memory cells, may be two-dimensional (2D) to display a single layer (e.g., a single level, a single hierarchy) of memory cells, or it may be three-dimensional (3D) to display multiple layers (e.g., multiple levels, multiple hierarchy) of memory cells. In a stacked configuration, the CUA area 306 may facilitate access to one or more memory cells in each array. For example, the CUA area 306 may facilitate data transfer between memory cells coupled to channels of memory array 302, memory cells coupled to channels of additional memory array 302 (which are coupled to memory array 302), and the controller.

[0072] Therefore, the memory device includes a first insulating material adjacent to a metal pad, a second insulating material adjacent to the first insulating material, and a structure including a conductive material comprising metal wires extending through the second insulating material and contacts extending through both the first and second insulating materials. The metal wires intersect the contacts. The depth-to-width ratio of the contacts is between approximately 3:1 and approximately 12:1. The memory device also includes a lining material adjacent to the metal wires. The conductive material is in direct contact with each of the first insulating material, the second insulating material, and the metal pad.

[0073] Microelectronic devices incorporating device structures (e.g., microelectronic devices 100, 100') according to embodiments of the present disclosure can be used in embodiments of the electronic systems of the present disclosure. For example, Figure 4 This is a block diagram of an illustrative electronic system 400 according to embodiments of the present disclosure. Electronic system 400 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, etc. or Tablet computers with Wi-Fi or cellular networks, e-book readers, navigation devices, etc. Electronic system 400 includes at least one memory device 420. Memory device 420 may include embodiments of microelectronic devices (e.g., microelectronic devices 100, 100') previously described herein. Electronic system 400 may further include at least one electronic signal processor device 410 (often referred to as a "microprocessor"). Electronic signal processor device 410 may optionally include embodiments of microelectronic devices (e.g., microelectronic devices 100, 100') previously described herein. Electronic system 400 may further include one or more input devices 430 for users to input information into electronic system 400, such as a mouse or other pointing device, keyboard, touchpad, buttons, or control panel. Electronic system 400 may further include one or more output devices 440 for outputting information to users (e.g., visual or audio output), such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 430 and the output device 440 may include a single touchscreen device, which can be used to input information to the electronic system 400 and output visual information to the user. The input device 430 and the output device 440 may be electrically communicated with one or more of the memory device 420 and the electronic signal processor device 410.

[0074] Therefore, an electronic system is disclosed, comprising a processor device operatively coupled to input and output devices, and a memory device operatively coupled to the processor device. The memory device includes memory cells, at least one of which includes a structure comprising an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material including metal wires and contacts. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also includes a lining material adjacent to the metal wires. The width of the uppermost surface of the conductive material on the metal wires outside the contacts is relatively smaller than the width of the uppermost surface of the conductive material on the contacts.

[0075] The embodiments of this disclosure may be further characterized in the manner described below, but not limited to the manner described below.

[0076] Example 1: An apparatus comprising: a structure including: an upper insulating material adjacent to a lower insulating material; a conductive element resting on the lower insulating material; a conductive material including a metal wire and contacts, the conductive material extending from the upper surface of the upper insulating material to the upper surface of the conductive element; and a lining material adjacent to the metal wire, wherein the width of the uppermost surface of the conductive material of the metal wire outside the contacts is relatively smaller than the width of the uppermost surface of the conductive material of the contacts.

[0077] Example 2: The device according to Example 1, wherein the conductive material of the contact is in direct contact with each of the lower insulating material and conductive elements, such that the opening including the metal wire and the contact is substantially completely free of seed material and diffusion barrier material.

[0078] Example 3: The device according to Example 1 or Example 2, wherein the depth-to-width ratio of the contact through-hole of the contact is between about 3:1 and about 12:1.

[0079] Example 4: The device according to any one of Examples 1 to 3, wherein the lining material comprises metal silicon nitride or metal boron nitride and the conductive material comprises tungsten.

[0080] Example 5: The device according to any one of Examples 1 to 4, wherein the lining material is positioned along a portion of the sidewall of each of the upper insulating material and the lower insulating material; and wherein the lining material covers a portion of the conductive material of the contact.

[0081] Example 6: The device according to any one of Examples 1 to 5, wherein the depth of the metal wire corresponds to the thickness of the upper insulating material and the depth of the contact corresponds to the combined thickness of the lower and upper insulating materials, and the depth of the contact is relatively greater than the depth of the metal wire; and wherein the width of the uppermost surface of the metal wire outside the contact is between about 15% and about 95% of the width of the uppermost surface of the contact.

[0082] Example 7: The device according to any one of Examples 1 to 6, wherein the lining material is located in the bottom portion of the groove in the upper insulating material containing the metal wire; and the surface area of ​​the sidewall of the upper insulating material, including the contact through-hole of the contact, between about 25% and about 35% is completely free of lining material.

[0083] Example 8: A method of forming a device, comprising: forming a trench in an upper insulating material covering a lower insulating material; forming a contact through-hole in the upper and lower insulating materials, the contact through-hole partially intersecting the trench and extending from the upper surface of the upper insulating material to the upper surface of a conductive element below the contact through-hole, wherein the width of the upper edge of the contact through-hole is greater than the width of the upper edge of the trench; forming a conductive material in the contact through-hole; forming a lining material in the trench; and forming a conductive material in the trench.

[0084] Example 9: The method according to Example 8 further includes forming an etch stop material between a lower insulating material and an upper insulating material, each of the lower insulating material, the upper insulating material and the etch stop material being formed in a single deposition process, wherein each of the lower insulating material and the upper insulating material includes a first dielectric material and the etch stop material includes a second dielectric material different from the first dielectric material.

[0085] Example 10: The method according to Example 9, wherein the first dielectric material is formed of silicon oxide and the second dielectric material is formed of silicon nitride.

[0086] Example 11: The method according to any one of Examples 8 to 10, wherein forming the lining material includes epitaxially growing the lining material on the upper surface of the conductive material of the contact via.

[0087] Example 12: The method according to any one of Examples 8 to 11, wherein forming a contact via includes forming a contact via having a depth-to-width ratio between about 3:1 and about 12:1.

[0088] Example 13: The method according to any one of Examples 8 to 12, wherein forming conductive material in the contact via and forming conductive material in the trench includes filling each of the trench and the contact via with conductive material, without forming seed material in each of the trench and the contact via.

[0089] Example 14: The method according to any one of Examples 8 to 13, wherein forming a conductive material includes selectively depositing a conductive material adjacent to a conductive element within a contact via; wherein forming a lining material includes subsequently growing a lining material within a trench; and wherein forming a conductive material in a trench includes subsequently depositing a conductive material to fill the remaining portion of the trench.

[0090] Example 15: The method according to any one of Examples 8 to 14 further includes removing the upper surface of the conductive material above the trench, contact via and upper insulating material in a single stage, without removing the upper surface of the conductive material above the lower insulating material before depositing the upper insulating material.

[0091] Example 16: A method of forming a device, comprising: forming a contact via in a first insulating material and a second insulating material to expose a conductive element underlying the first insulating material; forming a trench in the second insulating material, wherein the upper edge of the trench is narrower than the upper edge of the contact via; forming a first portion of conductive material within the contact via; forming a lining material within the trench; and forming a second portion of conductive material within the trench.

[0092] Example 17: The method according to Example 16 further includes forming a first insulating material and a second insulating material in a single deposition process, and subsequently removing the upper portion of the second portion of the conductive material without removing the upper portion of the first portion of the conductive material before forming the second insulating material.

[0093] Example 18: The method according to Example 16 or Example 17 further includes forming the lining material into a size independent of the depth-to-width ratio of the contact via.

[0094] Example 19: The method according to any of Examples 16 to 18, wherein forming the lining material includes growing the lining material from the bottom of the trench without forming the lining material on the sidewall of the second insulating material.

[0095] Example 20: The method according to any one of Examples 16 to 19 further includes forming a lining material in a portion of the side contact point through-hole of the trench, rather than forming a lining material within the contact point through-hole.

[0096] Example 21: A memory device comprising: a first insulating material adjacent to a metal pad; a second insulating material adjacent to the first insulating material; a structure including a conductive material comprising a metal wire extending through the second insulating material and contacts extending through the first and second insulating materials, the metal wire intersecting the contacts, wherein the depth-to-width ratio of the contacts is between about 3:1 and about 12:1; and a lining material adjacent to the metal wire, wherein the conductive material is in direct contact with each of the first insulating material, the second insulating material, and the metal pad.

[0097] Example 22: The memory device according to Example 21, wherein the uppermost surface of the metal wire outside the contact is relatively narrower than the uppermost surface of the contact.

[0098] Example 23: The memory device according to Example 22, wherein the width of the uppermost surface of the metal line outside the contact is between about 5 nm and about 10 nm smaller than the width of the uppermost surface of the contact.

[0099] Example 24: A memory device according to any of Examples 21 to 23, wherein the lining material is positioned adjacent to the bottom portion of the trench including the metal wire, and a surface area of ​​the sidewall of the second insulating material between about 25% and about 35% does not have the lining material.

[0100] Example 25: The memory device according to Example 24, wherein the seed material and the diffusion barrier material are completely absent from each of the trenches including the metal wires and the contact vias including the contacts.

[0101] Example 26: A memory device according to any one of Examples 21 to 25, wherein the conductive material comprises tungsten and the lining material comprises silicon nitride or boron nitride.

[0102] Example 27: A memory device according to any of Examples 21 to 26, further comprising at least one memory array of memory cells and including an array-under-array CMOS (CUA) region under the at least one memory array, wherein metal lines and contacts are connected to the circuitry of the individual memory cells and CUA region of the at least one memory array.

[0103] Example 28: The memory device according to Example 27, wherein at least one memory array is a three-dimensional memory array of a 3D NAND flash memory device, the flash memory device including a CUA region directly beneath the three-dimensional memory array.

[0104] While certain illustrative embodiments have been described with reference to the figures, those skilled in the art will recognize and understand that the embodiments covered by this disclosure are not limited to those explicitly shown and described herein. Rather, various additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments covered by this disclosure (e.g., those claimed herein, including legal equivalents). Furthermore, features of one disclosed embodiment may be combined with features of another disclosed embodiment, and still be covered within the scope of this disclosure.

Claims

1. A device including a microelectronic device structure, the microelectronic device structure comprising: A conductive element, which lies beneath an insulating material; A conductive wire, which is operatively coupled to the conductive element; as well as A contact point intersects the conductive wire and extends from the upper surface of the conductive wire to the upper surface of the conductive element. The contact point is directly adjacent to the insulating material and the conductive element. The outer diameter of the contact point at the height of the upper surface of the conductive wire is larger than the width of the conductive wire outside the contact point. The opening containing the conductive wire and the contact point therein is completely free of seed material and diffusion barrier material.

2. The device of claim 1, further comprising a lining material laterally adjacent to the conductive wire and covering a portion of the contact.

3. The device of claim 2, wherein the lining material comprises a metal nitride material located on the opposite side of the conductive wire.

4. The device of claim 1, further comprising an etch-stopping material covered by the insulating material and an additional insulating material covered by the etch-stopping material, wherein the upper portions of the conductive wire and the contact are laterally adjacent to the additional insulating material.

5. The device of claim 4, wherein a portion of the conductive wire is directly adjacent to the additional insulating material.

6. The device of claim 1, wherein the conductive wire and the contact are made of the same material.

7. A method for forming a microelectronic device, comprising: An insulating material is formed on the conductive element; A contact is formed comprising a first portion of conductive material directly adjacent to the insulating material and the conductive element; as well as A conductive wire is formed that is operatively coupled to the conductive element, the conductive wire intersecting the contact and including a second portion of the conductive material, the contact extending from the upper surface of the conductive wire to the upper surface of the conductive element, the outer diameter of the contact at the height of the upper surface of the conductive wire being larger than the width of the conductive wire outside the contact, and the opening containing the conductive wire and the contact therein being completely free of seed material and diffusion barrier material.

8. The method of claim 7, further comprising forming a trench on the upper portion of the insulating material, covering the lower portion of the insulating material, and then forming a contact through-hole extending completely through the upper and lower portions of the insulating material, the trench containing the conductive wire and the contact through-hole containing the contact.

9. The method of claim 8, wherein forming the insulating material comprises forming the upper portion and the lower portion in a single deposition stage of a dual damascene process.

10. The method of claim 7, further comprising forming a contact opening extending from the upper surface of the insulating material to the upper surface of the conductive element, and then forming a conductive trench in the insulating material.

11. The method of claim 7, further comprising, prior to forming the conductive wire, selectively forming a metal nitride material on the upper surface of the first portion of the conductive material of the contact.

12. The method of claim 7, wherein forming the contact and forming the conductive line comprises forming a conductive structure, the conductive structure comprising a continuous portion of the conductive material.

13. The method of claim 7, wherein forming the contact and forming the conductive wire comprises forming the conductive material in one or more stages after forming the entire insulating material.

14. The method of claim 7, wherein forming the contact comprises removing the upper surface of the first portion of the conductive material of the contact after forming the conductive line, without removing the upper surface of the first portion of the conductive material before forming the conductive line.

15. A memory device comprising: Conductive elements; A conductive wire that extends horizontally along the conductive element; A contact that intersects the conductive wire perpendicularly and extends from the upper surface of the conductive wire to the upper surface of the conductive element, wherein the upper surface of the conductive wire outside the contact is relatively narrower than the upper surface of the contact, and includes an opening in the conductive wire and the contact that is completely free of seed material and diffusion barrier material.

16. The memory device of claim 15, wherein the contacts have a wedge-shaped profile and the upper portion of a single contact has a larger critical dimension than its lower portion.

17. The memory device of claim 15, further comprising at least one memory cell array and an array-below complementary metal-oxide-semiconductor (CMOS) (CUA) region perpendicularly aligned with the at least one memory cell array.

18. The memory device of claim 15, further comprising a lining material comprising silicon nitride or boron nitride, the lining material being adjacent to the conductive line in the region adjacent to the contact.

19. The memory device of claim 18, wherein a portion of the lining material is located between the conductive wire and the contact.

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