Analog-to-Digital Converter and Method of Operating the Same

Abstract

The analog-to-digital converter includes a switching circuit, a first capacitor array, a second capacitor array, and a comparator. The method for operating the analog-to-digital converter includes, during a first sampling period, switching a switching signal to a first level to cause the switching circuit to couple the first capacitor array to a first input terminal of the comparator and a first signal source, and to couple the second capacitor array to a second input terminal of the comparator and a second signal source, and during a second sampling period, switching the switching signal to a second level to cause the switching circuit to couple the first capacitor array to the second input terminal of the comparator and the second signal source, and to couple the second capacitor array to the first input terminal of the comparator and the first signal source. The control logic circuit switches the switching signal between the first level and the second level in a uniform order during a plurality of sampling periods.

Description

Technical Field

[0001] The present invention relates to electronic circuits, and particularly to an analog-to-digital converter and an operation method thereof. Background Art

[0002] An analog-to-digital converter (ADC) is a device used to convert a continuous signal in analog form into a discrete signal in digital form, and is widely used in audio systems, video systems, communication systems, and various digital signal processing systems. A successive approximation register (SAR) analog-to-digital converter is an analog-to-digital converter that uses a capacitor array for analog-to-digital conversion, has the characteristic of low power consumption, and is suitable for mobile devices or portable devices. However, due to the mismatch of capacitors in the capacitor array adopted by the SAR ADC, it will cause non-linear errors of the SAR ADC and reduce the accuracy of the SAR ADC. Summary of the Invention

[0003] An embodiment of the present invention provides an operation method for an analog-to-digital converter. The analog-to-digital converter includes a first capacitor array, a second capacitor array, a switching circuit, a comparator, and a control logic circuit. A first selection circuit is coupled to the first capacitor array, a second selection circuit is coupled to the second capacitor array, the switching circuit is coupled to the first capacitor array and the second capacitor array, the comparator is coupled to the switching circuit, and the control logic circuit is coupled to the switching circuit, the first selection circuit, and the second selection circuit. The comparator includes a first input terminal and a second input terminal. The operation method includes: during a first sampling period, switching the switching signal to a first level, so that the switching circuit couples the first capacitor array to the first input terminal of the comparator and a first signal source, and couples the second capacitor array to the second input terminal of the comparator and a second signal source; and during a second sampling period, switching the switching signal to a second level, so that the switching circuit couples the first capacitor array to the second input terminal of the comparator and the second signal source, and couples the second capacitor array to the first input terminal of the comparator and the first signal source. The control logic circuit switches the switching signal between the first level and the second level according to a uniform order during a plurality of sampling periods, and the first level and the second level are different.

[0004] An embodiment of the present invention provides an analog-to-digital converter, which includes a first capacitor array, a second capacitor array, a comparator, a switching circuit, and a control logic circuit. The comparator includes a first input terminal and a second input terminal. The switching circuit is coupled to the first capacitor array, the second capacitor array, and the comparator, and is configured to couple the first capacitor array to the first input terminal of the comparator and a first signal source and couple the second capacitor array to the second input terminal of the comparator and a second signal source during a first sampling period when the switching signal switches to a first level, and couple the first capacitor array to the second signal source, couple the second capacitor array to the first signal source, couple the first capacitor array to the second input terminal of the comparator, and couple the second capacitor array to the first input terminal of the comparator during a second sampling period when the switching signal switches to a second level. The control logic circuit is coupled to the switching circuit and is configured to switch the switching signal between the first level and the second level in a uniform order during a plurality of sampling periods, and the first level and the second level are different. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. is a circuit schematic diagram of an analog-to-digital converter according to an embodiment of the present invention.

[0006] Figure 1A and Figure 1B respectively represent Figure 1 schematic diagrams of the switching signal at the first level and the second level.

[0007] Figure 2 FIG. is Figure 1 a flowchart of an operation method of the analog-to-digital converter in FIG.

[0008] Figure 3 FIG. is a circuit schematic diagram of another analog-to-digital converter according to an embodiment of the present invention. DETAILED DESCRIPTION

[0009] Figure 1It is a circuit schematic diagram of the analog-to-digital converter 1 in the embodiments of the present invention. The analog-to-digital converter 1 is a 3-bit split capacitor successive approximation register (SAR) analog-to-digital converter, which can convert the differential input voltages Vip and Vin into digital output data Dout according to the successive approximation method (such as the binary search method). The differential input voltages Vip and Vin can be provided by a first signal source and a second signal source respectively. The digital output data Dout can include 3 bits. The analog-to-digital converter 1 can generate a set of digital output data Dout in each operation cycle. Each operation cycle can include a sampling stage (or called an acquisition stage) and a quantization stage (or called a conversion stage). The analog-to-digital converter 1 can sample the differential input voltages Vip and Vin in the sampling stage to generate a pair of sampling signals, and quantize the pair of sampling signals in the quantization stage to generate the digital output data Dout. The quantization stage can include multiple (3) conversions to sequentially generate multiple (3) bits of the digital output data Dout. In multiple sampling stages, the analog-to-digital converter 1 can be reset according to 2 voltage settings, thereby reducing the voltage error caused by capacitive element mismatch, reducing its integral nonlinearity (INL) error and differential nonlinearity (DNL) error, and at the same time providing high-speed analog-to-digital conversion.

[0010] The analog-to-digital converter 1 can include a switching circuit 10, a first capacitor array 141, a first selection circuit 121, a second capacitor array 142, a second selection circuit 122, a comparator 16, and a control logic circuit 18. The switching circuit 10 can be coupled to the first capacitor array 141, the second capacitor array 142, the comparator 16, and the control logic circuit 18. The first selection circuit 121 can be coupled to the first capacitor array 141, and the second selection circuit 122 can be coupled to the second capacitor array 142. The comparator 16 can include a first receiving end coupled to the switching circuit 10, a second receiving end coupled to the switching circuit 10, and an output end coupled to the control logic circuit 18. The control logic circuit 18 is coupled to the first selection circuit 121 and the second selection circuit 122.

[0011] The first capacitor array 141 may include three groups of capacitors. The capacitance values of the three groups of capacitors are different from each other. Each group of capacitors includes a first capacitor and a second capacitor, and the first capacitor and the second capacitor have substantially equal capacitance values. The first group of capacitors of the first capacitor array 141 may include a first capacitor C1pa and a second capacitor C1pb, the second group of capacitors may include a first capacitor C2pa and a second capacitor C2pb, and the third group of capacitors may include a first capacitor C3pa and a second capacitor C3pb. The first group of capacitors, the second group of capacitors, and the third group of capacitors of the first capacitor array 141 may correspond to the most significant bit (MSB) to the least significant bit (LSB) of the digital output data Dout, respectively. The first capacitor C1pa and the second capacitor C1pb may each have a substantially equal capacitance value of 3C, and the first group of capacitors of the first capacitor array 141 may have a capacitance value of 6C; the first capacitor C2pa and the second capacitor C2pb may each have a substantially equal capacitance value of 2C, and the second group of capacitors of the first capacitor array 141 may have a capacitance value of 4C; the first capacitor C3pa and the second capacitor C3pb may each have a substantially equal capacitance value of 1C, and the third group of capacitors of the first capacitor array 141 may have a capacitance value of 2C. The capacitors C1pa, C1pb, C2pa, C2pb, C3pa, C3pb may each include an upper plate and a lower plate. The upper plates of the capacitors C1pa, C1pb, C2pa, C2pb, C3pa, C3pb may be coupled to the switching circuit 10.

[0012] Similarly, the second capacitor array 142 also includes three groups of capacitors with different capacitance values. Each group of capacitors includes a first capacitor and a second capacitor, and the first capacitor and the second capacitor have substantially equal capacitance values. The first group of capacitors in the second capacitor array 142 may include a first capacitor C1na and a second capacitor C1nb, the second group of capacitors may include a first capacitor C2na and a second capacitor C2nb, and the third group of capacitors may include a first capacitor C3na and a second capacitor C3nb. The first group of capacitors, the second group of capacitors, and the third group of capacitors in the second capacitor array 142 may correspond to the most significant bit to the least significant bit of the digital output data Dout, respectively. The first capacitor C1na and the second capacitor C1nb may each have a substantially equal capacitance value of 3C, and the first group of capacitors in the second capacitor array 142 may have a capacitance value of 6C; the first capacitor C2na and the second capacitor C2nb may each have a substantially equal capacitance value of 2C, and the second group of capacitors in the second capacitor array 142 may have a capacitance value of 4C; the first capacitor C3na and the second capacitor C3nb may each have a substantially equal capacitance value of 1C, and the third group of capacitors in the second capacitor array 142 may have a capacitance value of 2C. The capacitors C1na, C1nb, C2na, C2nb, C3na, and C3nb may each include an upper plate and a lower plate. The upper plates of the capacitors C1na, C1nb, C2na, C2nb, C3na, and C3nb may be coupled to the switching circuit 10.

[0013] The first selection circuit 121 may receive a first reference voltage V1 and a second reference voltage V2 to set the three groups of capacitors in the first capacitor array 141, and the second selection circuit 122 may receive the first reference voltage V1 and the second reference voltage V2 to set the three groups of capacitors in the second capacitor array 142. In some embodiments, the first reference voltage V1 may be a supply voltage, such as 1.8V, and the second reference voltage V2 may be a ground voltage, such as 0V. In other embodiments, the first reference voltage V1 may be a ground voltage and the second reference voltage V2 may be a supply voltage. The first selection circuit 121 may be coupled to the lower plates of the capacitors C1pa, C1pb, C2pa, C2pb, C3pa, and C3pb. The second selection circuit 122 may be coupled to the lower plates of the capacitors C1na, C1nb, C2na, C2nb, C3na, and C3nb.

[0014] The first selection circuit 121 and the second selection circuit 122 can be implemented by one or more multiplexers and / or switches, but are not limited thereto. One or more multiplexers and / or switches of the first selection circuit 121 can receive selection signals from the control logic circuit 18 to respectively select one from the first reference voltage V1 and the second reference voltage V2 and output it to the capacitors C1pa, C1pb, C2pa, C2pb, C3pa, C3pb. One or more multiplexers and / or switches of the second selection circuit 122 can receive selection signals from the control logic circuit 18 to respectively select one from the first reference voltage V1 and the second reference voltage V2 and output it to the capacitors C1na, C1nb, C2na, C2nb, C3na, C3nb.

[0015] The switching circuit 10 may include switches SW11 to SW18. The switch SW11 may include a first terminal coupled to the first signal source and a second terminal coupled to the first capacitor array 141. The switch SW12 may include a first terminal coupled to the second signal source and a second terminal coupled to the first capacitor array 141. The switch SW13 may include a first terminal coupled to the first signal source and a second terminal coupled to the second capacitor array 142. The switch SW14 may include a first terminal coupled to the second signal source and a second terminal coupled to the second capacitor array 142. The switch SW15 may include a first terminal coupled to the first capacitor array 141 and a second terminal coupled to the first input terminal of the comparator 16. The switch SW16 may include a first terminal coupled to the second capacitor array 142 and a second terminal coupled to the first input terminal of the comparator 16. The switch SW17 may include a first terminal coupled to the first capacitor array 141 and a second terminal coupled to the second input terminal of the comparator 16. The switch SW18 may include a first terminal coupled to the second capacitor array 142 and a second terminal coupled to the second input terminal of the comparator 16.

[0016] During the sampling phase, the switching circuit 10 may turn on two of the switches SW11 to SW14 according to the switching signal Sswp and turn off the other two, and turn on two of the switches SW15 to SW18 according to the switching signal Sswp and turn off the other two, so that the first capacitor array 141 and the second capacitor array 142 can respectively sample the differential input voltages Vip, Vin, and the first input terminal and the second input terminal of the comparator 16 respectively receive the voltages Vp, Vn.

[0017] During the sampling period, the first selection circuit 121 and the second selection circuit 122 may output voltages to the capacitors C1pa, C1pb, C2pa, C2pb, C3pa, C3pb and the capacitors C1na, C1nb, C2na, C2nb, Cna, C3nb according to the first voltage setting or the second voltage setting. Tables 1 and 2 respectively show the first voltage setting and the second voltage setting:

[0018] Table 1

[0019] Capacitor C1pa C1pb C2pa C2pb C3pa C3pb Lower plate voltage V1 V2 V1 V2 V1 V2 Capacitor C1na C1nb C2na C2nb C3na C3nb Lower plate voltage V1 V2 V1 V2 V1 V2

[0020] Table 2

[0021] Capacitor C1pa C1pb C2pa C2pb C3pa C3pb Lower plate voltage V2 V1 V2 V1 V2 V1 Capacitor C1na C1nb C2na C2nb C3na C3nb Lower plate voltage V2 V1 V2 V1 V2 V1

[0022] The control logic circuit 18 can switch the switching signal Sswp between a first level and a second level according to a uniform order during multiple sampling periods, and the first level and the second level are different. In some embodiments, the first level may be a first reference voltage V1, and the second level may be a second reference voltage V2. The uniform order may be an alternating order, a random order, or other specific orders. When the uniform order is an alternating order, the control logic circuit 18 can alternately switch the switching signal Sswp between the first level and the second level. When the uniform order is a random order, the control logic circuit 18 can randomly switch the switching signal Sswp, and the probabilities of the switching signal Sswp switching to the first level and the second level are substantially the same. The switches SW11 to SW18 can be turned off or on according to the switching signal Sswp. Other specific orders may be orders that are not purely alternating or not purely random. For example, other specific orders may be an order in which the switching signal Sswp is at the first level during N sampling periods, and the switching signal Sswp is at the second level during the subsequent N sampling periods. In some other embodiments, the operation of the current data can be determined by the information of the previous sampling, whether the switching signal Sswp is at the first level or the second level.

[0023] In some embodiments, when sampling is performed and the switching signal Sswp is at the first level, the switching circuit 10 can turn on the switches SW11 and SW14 according to the switching signal Sswp, and turn off the switches SW12 and SW13, turn on the switches SW15 and SW18 according to the switching signal Sswp, and turn off the switches SW16 and SW17, so that the first capacitor array 141 samples the input voltage Vip from the first signal source and the second capacitor array 142 samples the input voltage Vin from the second signal source, and the first input terminal of the comparator 16 receives the voltage Vp and the second input terminal of the comparator 16 receives the voltage Vn; when sampling is performed and the switching signal Sswp is at the second level, the switching circuit 10 can turn on the switches SW12 and SW13 according to the switching signal Sswp, and turn off the switches SW11 and SW14, turn on the switches SW16 and SW17 according to the switching signal Sswp, and turn off the switches SW15 and SW18, so that the first capacitor array 141 samples the input voltage Vin from the second signal source and the second capacitor array 142 samples the input voltage Vip from the first signal source, and the first input terminal of the comparator 16 receives the voltage Vp and the second input terminal of the comparator 16 receives the voltage Vn.

[0024] In some embodiments, switches SW15 to SW18 can be replaced by a multiplexer coupled to the output of comparator 16, or integrated into the control logic circuit 18 in the form of a multiplexer / logic gate, so as to, when the switching signal Sswp is at the first level, respectively enable the first capacitor array 141 and the second capacitor array 142 to sample Vip from the first signal source and Vin from the second signal source, and output voltages Vp and Vn to the first input terminal and the second input terminal of comparator 16; and so as to, when the switching signal Sswp is at the second level, respectively enable the second capacitor array 142 and the first capacitor array 141 to sample Vip from the first signal source and Vin from the second signal source, and output voltages Vp and Vn to the first input terminal and the second input terminal of comparator 16.

[0025] In other embodiments, when sampling and the switching signal Sswp is at the first level, the switching circuit 10 can turn on switches SW12 and SW13 according to the switching signal Sswp, and turn off switches SW11 and SW14, turn on switches SW16 and SW17 according to the switching signal Sswp, and turn off switches SW15 and SW18, so that the first capacitor array 141 samples the input voltage Vin from the second signal source and the second capacitor array 142 samples the input voltage Vip from the first signal source, and the first input terminal of comparator 16 receives voltage Vp and the second input terminal of comparator 16 receives voltage Vn; when sampling and the switching signal Sswp is at the second level, the switching circuit 10 can turn on switches SW11 and SW14 according to the switching signal Sswp, and turn off switches SW12 and SW13, turn on switches SW15 and SW18 according to the switching signal Sswp, and turn off switches SW16 and SW17, so that the first capacitor array 141 samples the input voltage Vip from the first signal source and the second capacitor array 142 samples the input voltage Vin from the second signal source, and the first input terminal of comparator 16 receives voltage Vp and the second input terminal of comparator 16 receives voltage Vn.

[0026] In some embodiments, switches SW11 to SW18 in the switching circuit 10 may also be replaced by an input multiplexer and an output multiplexer. During a first sampling period, when the switching signal Sswp switches to a first level, the input multiplexer couples the first capacitor array 141 to the first signal source and couples the second capacitor array 142 to the second signal source, and the output multiplexer couples the first capacitor array 141 to the first input terminal of the comparator 16 and couples the second capacitor array 142 to the second input terminal of the comparator 16. During a second sampling period, when the switching signal Sswp switches to a second level, the input multiplexer couples the first capacitor array 141 to the second signal source and couples the second capacitor array 142 to the first signal source, and the output multiplexer couples the first capacitor array 141 to the second input terminal of the comparator 16 and couples the second capacitor array 142 to the first input terminal of the comparator 16. The control manner of the switching signal Sswp can be found in the foregoing paragraphs and will not be elaborated herein.

[0027] In the quantization phase, the analog-to-digital converter 1 can perform 3 conversions for 3 bits of the digital output data Dout. The comparator 16 can compare the voltages Vp and Vn to generate 3 comparison results. The control logic circuit 18 can store each comparison result as the bit value of 1 bit of the digital output data Dout, and output selection signals to the first selection circuit 121 and the second selection circuit 122 according to each comparison result to update the voltages Vp and Vn. The comparison result can be binary "0" or binary "1". For example, when performing the conversion of the most significant bit, if the switches that are turned on by the swap signal Sswp to make the swap circuit 10 conductive are switches SW11, SW14, SW15, SW18, and if the voltage Vp is greater than the voltage Vn, the comparator 16 can generate binary "1" as the comparison result. The control logic circuit 18 can store binary "1" as the most significant bit, set the first selection circuit 121 to output a ground voltage to the lower plates of the capacitors C1pa and C1pb to pull down the voltage Vp, and set the second selection circuit 122 to output a supply voltage to the lower plates of the capacitors C1na and C1nb to raise the voltage Vn. The updated voltage Vp will be lower than the previous voltage Vp, and the updated voltage Vn will be higher than the previous voltage Vn. If the voltage Vp is less than the voltage Vn, the comparator 16 can generate binary "0" as the comparison result. The control logic circuit 18 can store binary "0" as the most significant bit, set the first selection circuit 121 to output a supply voltage to the lower plates of the capacitors C1pa and C1pb to raise the voltage Vp, and set the second selection circuit 122 to output a ground voltage to the lower plates of the capacitors C1na and C1nb to pull down the voltage Vn. The updated voltage Vp will be higher than the previous voltage Vp, and the updated voltage Vn will be lower than the previous voltage Vn. The analog-to-digital converter 1 can sequentially compare and update the voltages Vp and Vn to generate 3 bit values of 3 bits of the digital output data Dout, and output the digital output data Dout for subsequent use.

[0028] When the swap signal Sswp toggles, the control logic circuit 18 also needs to swap the selection signals of the first selection circuit 121 and the second selection circuit 122. Figure 1A and Figure 1B are schematic diagrams showing the swap signal Sswp at the first level and the second level respectively. As Figure 1A shown, if the swap signal Sswp is at the first level, the switches SW11, SW14, SW15, SW18 are conductive, and the switches SW12, SW13, SW16, SW17 are non-conductive. The control logic circuit 18 can output the selection signal Ssel1 to the first selection circuit 121 and output the selection signal Ssel2 to the second selection circuit 122. As Figure 1BAs shown, if the switching signal Sswp is at the second level, switches SW12, SW13, SW16, and SW17 are turned on, and switches SW11, SW14, SW15, and SW18 are turned off. The control logic circuit 18 can output the selection signal Ssel2 to the first selection circuit 121 and output the selection signal Ssel1 to the second selection circuit 122.

[0029] Figure 2 It is a flowchart of the operation method 200 of the analog-to-digital converter 1. The operation method 200 includes steps S202 and S204 for connecting the first capacitor array 141 and the second capacitor array 142 using two connection settings during multiple sampling periods. Any reasonable technical changes or step adjustments fall within the scope disclosed by the present invention. Steps S202 and S204 are as follows:

[0030] Step S202: During the first sampling period, switch the switching signal Sswp to the first level so that the switching circuit 10 couples the first capacitor array 141 to the first input terminal of the comparator 16 and the first signal source, and couples the second capacitor array 142 to the second input terminal of the comparator 16 and the second signal source;

[0031] Step S204: During the second sampling period, switch the switching signal Sswp to the second level so that the switching circuit 10 couples the first capacitor array 141 to the second input terminal of the comparator 16 and the second signal source, and couples the second capacitor array 142 to the first input terminal of the comparator 16 and the first signal source.

[0032] In step S202, during the first sampling period, when the switching signal Sswp is switched to the first level, switch SW11 is turned on to couple the first capacitor array 141 to the first signal source, switch SW14 is turned on to couple the second capacitor array 142 to the second signal source, switch SW15 is turned on to couple the first capacitor array 141 to the first input terminal of the comparator 16, switch SW18 is turned on to couple the second capacitor array 142 to the second input terminal of the comparator 16, and switches SW12, SW13, SW16, and SW12 are turned off. In step S204, during the second sampling period, when the switching signal Sswp is switched to the second level, switch SW12 is turned on to couple the first capacitor array 141 to the second signal source, switch SW13 is turned on to couple the second capacitor array 142 to the first signal source, switch SW17 is turned on to couple the first capacitor array 141 to the second input terminal of the comparator 16, switch SW16 is turned on to couple the second capacitor array 142 to the first input terminal of the comparator 16, and switches SW11, SW14, SW15, and SW18 are turned off.

[0033] Figure 3It is a circuit schematic diagram of another analog-to-digital converter 3 in an embodiment of the present invention. The analog-to-digital converter 3 can be a monotonic switching / set-and-down switching successive approximation register analog-to-digital converter. The difference between the analog-to-digital converter 3 and the analog-to-digital converter 1 is that the analog-to-digital converter 3 uses the first capacitor array 341 and the second capacitor array 342 to replace the first capacitor array 141 and the second capacitor array 142 of the analog-to-digital converter 1 respectively, and uses the first selection circuit 321 and the second selection circuit 322 to replace the first selection circuit 121 and the second selection circuit 122 of the analog-to-digital converter 1 respectively. The following explains the differences of the analog-to-digital converter 3. The first capacitor array 341 includes capacitors C1p, C2p, C3p and C4p, and the second capacitor array 342 includes capacitors C1n, C2n, C3n and C4n. The first selection circuit 321 may include one or more multiplexers and / or switches for respectively outputting a supply voltage or a ground voltage to the capacitors C1p, C2p, C3p and C4p, and the second selection circuit 322 may include one or more multiplexers and / or switches for respectively outputting a supply voltage or a ground voltage to the capacitors C1n, C2n, C3n and C4n. During the sampling period, the first selection circuit 321 and the second selection circuit 322 may reset the first selection circuit 321 and the second selection circuit 322 according to the voltage settings shown in Table 3, output the supply voltage VR to the lower plates of the capacitors C1p, C2p, C3p and C4p, and output the supply voltage VR to the lower plates of C1n, C2n, C3n and C4n.

[0034] Table 3

[0035] Capacitor C1p C2p C3p C4p Lower plate voltage VR VR VR VR Capacitor C1n C2n C3n C4n Lower plate voltage VR VR VR VR

[0036] During conversion, when converting the most significant bit, if the voltage Vp is greater than the voltage Vn, the comparator 16 may generate a binary "1" as the comparison result. The control logic circuit 18 may store the binary "1" as the most significant bit. The first selection circuit 321 may output a ground voltage to the lower plate of the capacitor C1p to update the voltage Vp, and the second selection circuit 322 may maintain the output supply voltage VR to the lower plate of the capacitor C1n to maintain the voltage Vn. The updated voltage Vp will be lower than the previous voltage Vp, and the voltage Vn remains unchanged. If the voltage Vp is less than the voltage Vn, the comparator 16 may generate a binary "0" as the comparison result. The control logic circuit 18 may store the binary "0" as the most significant bit. The first selection circuit 321 may maintain the output supply voltage VR to the lower plate of the capacitor C1p to maintain the voltage Vp, and the second selection circuit 322 may output a ground voltage to the lower plate of the capacitor C1n to update the voltage Vn. The updated voltage Vn will be lower than the previous voltage Vn, and the voltage Vp remains unchanged. The analog-to-digital converter 1 may sequentially compare and update the voltages Vp and Vn to generate digital output data Dout.

[0037] The digital converter 3 may also use the method 200 to uniformly switch the switching signal Sswp between the first level and the second level during multiple sampling periods.

[0038] Since the analog-to-digital converters 1, 3 and the operation method 200 uniformly switch the switching signal Sswp between the first level and the second level during multiple sampling periods, the output-input curve (transfer curve) of the entire analog-to-digital converter will equivalently switch between two configurations, so that the average non-linear error will cancel out positive and negative effects at most digital code positions, reducing the differential linear error and integral linear error caused by capacitor mismatch. In some embodiments, if the capacitor arrays 141 and 142 are in a ten-bit binary weighted configuration, when each unit capacitance value has a random drift with a standard deviation of two percent, when used with the analog-to-digital converter 1 and the method 200, the maximum differential non-linear error will be reduced from about 0.37 LSB to 0.3 LSB; and in the statistical chart of the differential linear digital output codes, the error of the digital codes with obvious peaks in the differential linear error (such as the digital codes at 1 / 4, 1 / 8, 1 / 16, 1 / 32... of the full scale range of the entire ADC) can be reduced by an average of 0.05 LSB.

[0039] The present invention is not limited to the 3-bit SAR ADC adopted in the embodiments, and those of ordinary skill in the art can also apply Method 200 to SAR ADCs of other sizes according to the spirit of the present invention. The analog-to-digital converters 1, 3 and the operation method 200 switch the switching signal Sswp evenly between the first level and the second level during multiple sampling periods, reducing the differential non-linearity error and the integral non-linearity error generated by the capacitance mismatch between the same group of capacitors or different groups of capacitors, and greatly improving the linearity of the SAR ADC.

[0040] The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the protection scope of the present invention.

[0041] Description of reference numerals:

[0042] 1, 3: Analog-to-digital converter

[0043] 10: Switching circuit

[0044] 121, 321: First selection circuit

[0045] 122, 322: Second selection circuit

[0046] 141, 341: First capacitor array

[0047] 142, 342: Second capacitor array

[0048] 16: Comparator

[0049] 18: Control logic circuit

[0050] 200: Method

[0051] S202, S204: Steps

[0052] C1pa, C1pb, C2pa, C2pb, C3pa, C3pb, C1na, C1nb, C2na, C2nb, C3na, C3nb, C1p, C2p, C3p, C4p, C1n, C2n, C3n, C4n: Capacitors

[0053] Dout: Digital output data

[0054] SW11 to SW18: Switches

[0055] Sswp: Switching signal

[0056] V1: First reference voltage

[0057] V2: Second reference voltage

[0058] Vip, Vin: Differential input voltage

[0059] Vp, Vn: Voltage

Claims

1. A method for operating an analog-to-digital converter, the analog-to-digital converter comprising a first capacitor array, a second capacitor array, a switching circuit, a comparator, and a control logic circuit, the switching circuit being coupled to the first capacitor array and the second capacitor array, the comparator being coupled to the switching circuit, the control logic circuit being coupled to the switching circuit, the comparator comprising a first input terminal and a second input terminal, the method comprising: During a first sampling period, the switching signal is switched to a first level to cause the switching circuit to couple the first capacitor array to the first input terminal of the comparator and a first signal source, and to couple the second capacitor array to the second input terminal of the comparator and a second signal source; and During a second sampling period, switching the switching signal to a second level to cause the switching circuit to couple the first capacitor array to the second input terminal of the comparator and the second signal source, and to couple the second capacitor array to the first input terminal of the comparator and the first signal source; wherein the control logic circuit switches the switching signal between the first level and the second level in a uniform order during a plurality of sampling periods, and the first level and the second level are different.

2. The method for operating according to claim 1, wherein the analog-to-digital converter further comprises a first selection circuit and a second selection circuit, each group of capacitors in the first capacitor array comprising a first capacitor and a second capacitor having substantially equal capacitance values, each group of capacitors in the second capacitor array comprising a first capacitor and a second capacitor having substantially equal capacitance values, the method further comprising, during the first sampling period and the second sampling period, the first selection circuit outputting a first reference voltage to the first capacitor of each group of capacitors in the first capacitor array and outputting a second reference voltage to the second capacitor of each group of capacitors in the first capacitor array, and the second selection circuit outputting the first reference voltage to the first capacitor of each group of capacitors in the second capacitor array and outputting the second reference voltage to the second capacitor of each group of capacitors in the second capacitor array.

3. The method for operating according to claim 1, wherein the analog-to-digital converter further comprises a first selection circuit and a second selection circuit, the first capacitor array comprising a plurality of capacitors, the second capacitor array comprising a plurality of capacitors, the method further comprising: During the first sampling period and the second sampling period, the first selection circuit outputs a reference voltage to the capacitors in the first capacitor array, and the second selection circuit outputs the reference voltage to the capacitors in the second capacitor array.

4. The method for operating according to claim 1, wherein the uniform order is an alternating order.

5. The method for operating according to claim 1, wherein the uniform order is a random order.

6. The method for operating according to claim 1, wherein the uniform order is a specific order.

7. An analog-to-digital converter, comprising: A first capacitor array; A second capacitor array; A comparator, comprising a first input terminal and a second input terminal; A switching circuit, coupled to the first capacitor array, the second capacitor array, and the comparator, is configured to couple the first capacitor array to the first input terminal of the comparator and a first signal source, and couple the second capacitor array to the second input terminal of the comparator and a second signal source when a switching signal switches to a first level during a first sampling period, and couple the first capacitor array to the second signal source, couple the second capacitor array to the first signal source, couple the first capacitor array to the second input terminal of the comparator, and couple the second capacitor array to the first input terminal of the comparator when the switching signal switches to a second level during a second sampling period; and A control logic circuit, coupled to the switching circuit, is configured to switch the switching signal between the first level and the second level in a uniform order during a plurality of sampling periods, and the first level and the second level are different.

8. The analog-to-digital converter according to claim 7, wherein: The switching circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch; During the first sampling period, when the switching signal switches to the first level, the first switch couples the first capacitor array to the first signal source, the fourth switch couples the second capacitor array to the second signal source, the fifth switch couples the first capacitor array to the first input terminal of the comparator, and the eighth switch couples the second capacitor array to the second input terminal of the comparator; and During the second sampling period, when the switching signal switches to the second level, the second switch couples the first capacitor array to the second signal source, the third switch couples the second capacitor array to the first signal source, the sixth switch couples the first capacitor array to the second input terminal of the comparator, and the seventh switch couples the second capacitor array to the first input terminal of the comparator.

9. The analog-to-digital converter according to claim 7, wherein: The switching circuit includes an input multiplexer and an output multiplexer; During the first sampling period, when the switching signal switches to the first level, the input multiplexer couples the first capacitor array to the first signal source, and couples the second capacitor array to the second signal source, and the output multiplexer couples the first capacitor array to the first input terminal of the comparator, and couples the second capacitor array to the second input terminal of the comparator; and During the second sampling period, when the switching signal switches to the second level, the input multiplexer couples the first capacitor array to the second signal source and couples the second capacitor array to the first signal source, and the output multiplexer couples the first capacitor array to the second input terminal of the comparator and couples the second capacitor array to the first input terminal of the comparator.

10. The analog-to-digital converter according to claim 7, wherein: The first capacitor array includes N groups of capacitors. Each group of capacitors in the first capacitor array includes a first capacitor and a second capacitor, having substantially equal capacitance values, and N is a positive integer greater than 2; The second capacitor array includes N groups of capacitors. Each group of capacitors in the second capacitor array includes a first capacitor and a second capacitor, having substantially equal capacitance values; and The analog-to-digital converter further includes: A first selection circuit, coupled to the first capacitor array, for outputting a first reference voltage to the first capacitor of each group of capacitors in the first capacitor array and outputting a second reference voltage to the second capacitor of each group of capacitors in the first capacitor array during the sampling period; and A second selection circuit, coupled to the second capacitor array, for outputting the first reference voltage to the second capacitor of each group of capacitors in the second capacitor array and outputting the second reference voltage to the first capacitor of each group of capacitors in the second capacitor array during the sampling period.

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