Analog-to-digital converter and method of operation thereof

Abstract

An operation method of an analog-to-digital converter includes, during a first conversion, a comparator generating a first comparison result, a first selection circuit switching a voltage output to a first capacitor of a set of larger capacitors of a first capacitor array, a second selection circuit switching a voltage output to a second capacitor of the set of larger capacitors of a second capacitor array, and during a second conversion after the first conversion, the comparator generating a second comparison result, the first selection circuit switching back the voltage output to a first capacitor portion of the first capacitor of the set of larger capacitors of the first capacitor array, and the second selection circuit switching back the voltage output to a first capacitor portion of the second capacitor of the set of larger capacitors of the second capacitor array. The first comparison result and the second comparison result are different.

Description

TECHNICAL FIELD

[0001] The present application relates to electronic circuits, and in particular to an analog-to-digital converter and a method of operating the same. BACKGROUND

[0002] Analog-to-digital converters (ADCs) are devices used to convert continuous signals in analog form to discrete signals in digital form, and are widely used in audio systems, video systems, communication systems, and various digital signal processing systems. Successive approximation register (SAR) analog-to-digital converters are a type of analog-to-digital converter that uses a capacitor array for analog-to-digital conversion, and have the characteristics of low power consumption, making them suitable for use in mobile devices or portable devices. However, due to the mismatch of the capacitors in the capacitor array used by the SAR ADC, non-linear errors of the SAR ADC can occur, reducing the accuracy of the SAR ADC. SUMMARY

[0003] Embodiments of the present application provide an operation method of an analog-to-digital converter. The analog-to-digital converter includes a first capacitor array, a first selection circuit, a second capacitor array, a second selection circuit, a comparator, and a control logic circuit. Each set of capacitors in the first capacitor array includes a first capacitor and a second capacitor having substantially equal capacitance values. A first capacitance portion of the first capacitor of a set of larger capacitors of the first capacitor array has a capacitance value substantially equal to a capacitance value of the first capacitor of a set of smaller capacitors of the first capacitor array. A first capacitance portion of the second capacitor of the set of larger capacitors of the first capacitor array has a capacitance value substantially equal to the capacitance value of the first capacitor of the set of smaller capacitors of the first capacitor array. Each set of capacitors in the second capacitor array includes a first capacitor and a second capacitor having substantially equal capacitance values. A first capacitance portion of the first capacitor of a set of larger capacitors of the second capacitor array has a capacitance value substantially equal to a capacitance value of the first capacitor of a set of smaller capacitors of the second capacitor array. A first capacitance portion of the second capacitor of the set of larger capacitors of the second capacitor array has a capacitance value substantially equal to the capacitance value of the first capacitor of the set of smaller capacitors of the second capacitor array. The first selection circuit is coupled to the first capacitor array, the second selection circuit is coupled to the second capacitor array, the comparator includes a first input coupled to the first capacitor array and a second input coupled to the second capacitor array, and the control logic circuit is coupled to the first selection circuit, the second selection circuit, and the comparator. The operation method includes, during a first sampling period, the first selection circuit outputting a first reference voltage to the first capacitor of each set of capacitors in the first capacitor array and outputting a second reference voltage to the second capacitor of each set of capacitors in the first capacitor array, and the second selection circuit outputting the first reference voltage to the first capacitor of each set of capacitors in the second capacitor array and outputting the second reference voltage to the second capacitor of each set of capacitors in the second capacitor array; during a first conversion period, the comparator comparing a voltage at the first input and a voltage at the second input to generate a first comparison result, the first selection circuit outputting the second reference voltage to the first capacitor of the set of larger capacitors of the first capacitor array, and the second selection circuit outputting the first reference voltage to the second capacitor of the set of larger capacitors of the second capacitor array; and during a second conversion period after the first conversion period, the comparator comparing the voltage at the first input and the voltage at the second input to generate a second comparison result, the first selection circuit outputting the first reference voltage to the first capacitance portion of the first capacitor of the set of larger capacitors of the first capacitor array or to the first capacitance portion of the second capacitor of the set of larger capacitors of the first capacitor array, and the second selection circuit outputting the second reference voltage to the first capacitance portion of the first capacitor of the set of larger capacitors of the second capacitor array or to the first capacitance portion of the second capacitor of the set of larger capacitors of the second capacitor array. The first comparison result and the second comparison result are different. BRIEF DESCRIPTION OF DRAWINGS

[0004] Figure 1 is a circuit schematic diagram of an analog-to-digital converter in embodiments of the present application.

[0005] Figure 2 is Figure 1 a flowchart of an operation method of an analog-to-digital converter in DETAILED DESCRIPTION

[0006] Figure 1 is a circuit schematic diagram of an analog-to-digital converter 1 in an embodiment of the present application. The analog-to-digital converter 1 is a 3-bit split capacitor successive approximation register (SAR) analog-to-digital converter, which can convert a differential input voltage Vip, Vin into digital output data Dout according to a successive approximation method, such as binary search method. The differential input voltage Vip, Vin can be provided by a first signal source and a second signal source, respectively. The digital output data Dout can include 3 bits. The analog-to-digital converter 1 can generate a set of digital output data Dout in each operation cycle. Each operation cycle can include a sampling phase (or acquisition phase) and a quantization phase (or conversion phase), in which the analog-to-digital converter 1 can sample the differential input voltage Vip, Vin to generate a pair of sampling signals in the sampling phase, and can quantize the pair of sampling signals to generate the digital output data Dout in the quantization phase. The quantization phase can include multiple (3) conversions to sequentially generate multiple (3) bits of the digital output data Dout. In multiple sampling phases, the analog-to-digital converter 1 can be reset according to two voltage settings, thereby reducing voltage errors due to mismatch of capacitive elements, reducing integral nonlinearity (INL) errors and differential nonlinearity (DNL) errors, and providing high-speed analog-to-digital conversion.

[0007] The analog-to-digital converter 1 can include a switch SW1 and a switch SW2, a first capacitor array 141, a first selection circuit 121, a second capacitor array 142, a second selection circuit 122, a comparator 16, and a control logic circuit 18. The first selection circuit 121 and the switch SW1 are coupled to the first capacitor array 141, and the second selection circuit 122 and the switch SW2 are coupled to the second capacitor array 142. The comparator 16 can include a first receiving end coupled to the first capacitor array 141, a second receiving end coupled to the second capacitor array 142, and an output end coupled to the control logic circuit 18. The control logic circuit 18 is coupled to the first selection circuit 121 and the second selection circuit 122.

[0008] The first capacitor array 141 can include three groups of capacitors, the three groups of capacitors can have all the same, some same or different capacitor values, and can be changed according to design requirements. In some embodiments, the three groups of capacitors have different capacitor values, each group of capacitors includes a first capacitor and a second capacitor, and the first capacitor and the second capacitor have substantially equal capacitor values. The first group of capacitors of the first capacitor array 141 can include a first capacitor C1pa and a second capacitor C1pb, the second group of capacitors can include a first capacitor C2pa and a second capacitor C2pb, and the third group of capacitors can include a first capacitor C3pa and a second capacitor C3pb. The first group of capacitors, the second group of capacitors and the third group of capacitors of the first capacitor array 141 can correspond to the most significant bit (MSB) to the least significant bit (LSB) of the digital output data Dout, respectively. The first capacitor C1pa and the second capacitor C1pb can have substantially equal capacitor values 3C, respectively, and the first group of capacitors of the first capacitor array 141 can have a capacitor value 6C; the first capacitor C2pa and the second capacitor C2pb can have substantially equal capacitor values 2C, respectively, and the second group of capacitors of the first capacitor array 141 can have a capacitor value 4C; the first capacitor C3pa and the second capacitor C3pb can have substantially equal capacitor values 1C, respectively, and the third group of capacitors of the first capacitor array 141 can have a capacitor value 2C. The first capacitor C1pa of the first group of capacitors of the first capacitor array 141 is further divided into a first capacitor portion C1pa1 and a second capacitor portion C1pa2, and the second capacitor C1pb of the first group of capacitors of the first capacitor array 141 is further divided into a first capacitor portion C1pb1 and a second capacitor portion C1pb2. The capacitors C1pa1, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb can each include an upper plate and a lower plate. The upper plates of the capacitors C1pa1, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb can be coupled to the switch SW1 and the first input terminal of the comparator 16.

[0009] Similarly, the second capacitor array 142 also includes three groups of capacitors, each group of capacitors having different capacitance values, each group of capacitors including a first capacitor and a second capacitor having substantially equal capacitance values. The first group of capacitors of the second capacitor array 142 can include a first capacitor Clna and a second capacitor Clnb, the second group of capacitors can include a first capacitor C2na and a second capacitor C2nb, and the third group of capacitors can include a first capacitor C3na and a second capacitor C3nb. The first, second, and third groups of capacitors of the second capacitor array 142 can correspond to the most significant bit to the least significant bit of the digital output data Dout, respectively. The first capacitor Clna and the second capacitor Clnb can have substantially equal capacitance values of 3C, respectively, and the first group of capacitors of the second capacitor array 142 can have a capacitance value of 6C; the first capacitor C2na and the second capacitor C2nb can have substantially equal capacitance values of 2C, respectively, and the second group of capacitors of the second capacitor array 142 can have a capacitance value of 4C; and the first capacitor C3na and the second capacitor C3nb can have substantially equal capacitance values of 1C, respectively, and the third group of capacitors of the second capacitor array 142 can have a capacitance value of 2C. The first capacitor Clna of the first group of capacitors of the second capacitor array 142 can be further divided into a first capacitor portion Clnal and a second capacitor portion Clna2, and the second capacitor Clnb of the first group of capacitors of the second capacitor array 142 can be further divided into a first capacitor portion Clnbl and a second capacitor portion Clnb2. The capacitors Clnal, Clna2, Clnbl, Clnb2, C2na, C2nb, C3na, C3nb can each include an upper plate and a lower plate. The upper plates of the capacitors Clnal, Clna2, Clnbl, Clnb2, C2na, C2nb, C3na, C3nb can be coupled to the switch SW2 and the second input of the comparator 16.

[0010] The first selection circuit 121 can receive a first reference voltage VI and a second reference voltage V2 to set the three groups of capacitors of the first capacitor array 141, and the second selection circuit 122 can receive the first reference voltage VI and the second reference voltage V2 to set the three groups of capacitors of the second capacitor array 142. In some embodiments, the first reference voltage VI can be a supply voltage, such as 1.8V, and the second reference voltage V2 can be a ground voltage, such as 0V. In other embodiments, the first reference voltage VI can be a ground voltage, and the second reference voltage V2 can be a supply voltage. The first selection circuit 121 can be coupled to the lower plates of the capacitors C1pal, C1pa2, C1pbl, C1pb2, C2pa, C2pb, C3pa, C3pb. The second selection circuit 122 can be coupled to the lower plates of the capacitors Clnal, Clna2, Clnbl, Clnb2, C2na, C2nb, C3na, C3nb.

[0011] The first selection circuit 121 and the second selection circuit 122 can be implemented by one or more multiplexers and / or switches, but are not limited thereto. The one or more multiplexers and / or switches of the first selection circuit 121 can receive selection signals from the control logic circuit 18 to select one of the first reference voltage V1 and the second reference voltage V2 to output to the capacitors C1pai, C1pa2, C1pbi, C1pb2, C2pa, C2pb, C3pa, C3pb, respectively. The one or more multiplexers and / or switches of the second selection circuit 122 can receive selection signals from the control logic circuit 18 to select one of the first reference voltage V1 and the second reference voltage V2 to output to the lower plates of the capacitors C1nai, C1na2, C1nbi, C1nb2, C2na, C2nb, C3na, C3nb, respectively. For brevity, the first selection circuit 121 described in the following paragraphs outputs the selected voltage to the lower plate of the capacitors in the first capacitor array 141, and the second selection circuit 122 outputs the selected voltage to the lower plate of the capacitors in the second capacitor array 142.

[0012] During the sampling phase, the switch SW1 and the switch SW2 can be turned on, and the first capacitor array 141 and the second capacitor array 142 can sample the differential input voltage Vip, Vin, respectively. During the sampling, the first selection circuit 121 and the second selection circuit 122 can output the voltage in the first voltage setting or the second voltage setting to the capacitors C1pai, C1pa2, C1pbi, C1pb2, C2pa, C2pb, C3pa, C3pb and the capacitors C1nai, C1na2, C1nbi, C1nb2, C2na, C2nb, C3na, C3nb. Table 1 and Table 2 show the first voltage setting and the second voltage setting, respectively:

[0013] Table 1

[0014] Capacitor C1 pa1 C1 pa2 C1 pb1 C1 pb2 C2 pa C2 pb C3 pa C3 pb Lower plate voltage V1 V1 V2 V2 V1 V2 V1 V2 Capacitor C1 na1 C1 na2 C1 nb1 C1 nb2 C2 na C2 nb C3 na C3 nb Lower plate voltage V1 V1 V2 V2 V1 V2 V1 V2

[0015] Table 2

[0016] Capacitor C1 pa1 C1 pa2 C1 pb1 C1 pb2 C2 pa C2 pb C3 pa C3 pb Lower plate voltage V2 V2 V1 V1 V2 V1 V2 V1 Capacitor C1 na1 C1 na2 C1 nb1 C1 nb2 C2 na C2 nb C3 na C3 nb Lower plate voltage V2 V2 V1 V1 V2 V1 V2 V1

[0017] In some embodiments, the first selection circuit 121 can output a corresponding voltage in the first voltage set to the lower plate of the capacitors C1pai, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb during the sampling period, and the switch SW1 can be turned on to transmit the differential input voltage Vip to the upper plate of the capacitors C1pai, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb, thereby establishing the voltage Vp at the first receiving end of the comparator 16; the second selection circuit 122 can output a corresponding voltage in the first voltage set to the lower plate of the capacitors C1nai, C1na2, C1nb1, C1nb2, C2na, C2nb, C3na, C3nb during the sampling period, and the switch SW2 can be turned on to transmit the differential input voltage Vin to the upper plate of the capacitors C1nai, C1na2, C1nb1, C1nb2, C2na, C2nb, C3na, C3nb, thereby establishing the voltage Vn at the second receiving end of the comparator 16. In other embodiments, the first selection circuit 121 can output a corresponding voltage in the second voltage set to the lower plate of the capacitors C1pai, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb during the sampling period, and the switch SW1 can be turned on to transmit the differential input voltage Vip to the upper plate of the capacitors C1pai, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb, thereby establishing the voltage Vp; the second selection circuit 122 can output a corresponding voltage in the second voltage set to the lower plate of the capacitors C1nai, C1na2, C1nb1, C1nb2, C2na, C2nb, C3na, C3nb, and the switch SW2 can be turned on to transmit the differential input voltage Vin to the upper plate of the capacitors C1nai, C1na2, C1nb1, C1nb2, C2na, C2nb, C3na, C3nb, thereby establishing the voltage Vn.

[0018] In the quantization stage, the analog-to-digital converter 1 can perform 3 conversions for 3 bits of the digital output data Dout, the comparator 16 can compare the voltages Vp and Vn to generate 3 comparison results, the control logic circuit 18 can store each comparison result as a bit value of 1 bit of the digital output data Dout, and set the first selection circuit 121 and the second selection circuit 122 according to each comparison result to update the voltages Vp and Vn. The comparison result can be binary "0" or binary "1". For example, when performing the conversion of the most significant bit, if the voltage Vp is greater than the voltage Vn, the comparator 16 can generate binary "1" as the comparison result, the control logic circuit 18 can store binary "1" as the most significant bit, set the first selection circuit 121 to output the ground voltage to the lower plate of the capacitors C1p a1, C1p a2, C1p b1, C1p b2 to pull down the voltage Vp, and set the second selection circuit 122 to output the supply voltage to the lower plate of the capacitors C1n a1, C1n a2, C1n b1, C1n b2 to pull up the voltage Vn. The updated voltage Vp will be lower than the previous voltage Vp, and the updated voltage Vn will be higher than the previous voltage Vn. If the voltage Vp is less than the voltage Vn, the comparator 16 can generate binary "0" as the comparison result, the control logic circuit 18 can store binary "0" as the most significant bit, set the first selection circuit 121 to output the supply voltage to the lower plate of the capacitors C1p a1, C1p a2, C1p b1, C1p b2 to pull up the voltage Vp, and set the second selection circuit 122 to output the ground voltage to the lower plate of the capacitors C1n a1, C1n a2, C1n b1, C1n b2 to pull down the voltage Vn. The updated voltage Vp will be higher than the previous voltage Vp, and the updated voltage Vn will be lower than the previous voltage Vn. The analog-to-digital converter 1 can sequentially compare and update the voltages Vp and Vn to generate 3 bit values of 3 bits of the digital output data Dout, and output the digital output data Dout for subsequent use.

[0019] Figure 2 is a flowchart of the operation method 200 of the analog-to-digital converter 1. The method 200 includes steps S202 to S206. Step S202 is used to reset the first capacitor array 141 and the second capacitor array 142 during the sampling period. Steps S204 and S206 are used to switch the first capacitor array 141 and the second capacitor array 142 during the conversion period to generate the digital output data Dout. Any reasonable technical changes or step adjustments are within the scope disclosed by the present application. Steps S202 to S206 are as follows:

[0020] Step S202: During the first sampling, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitors of each set of capacitors in the first capacitive array 141 and outputs the second reference voltage V2 to the second capacitors of each set of capacitors in the first capacitive array 141, and the second selection circuit 122 outputs the first reference voltage V1 to the first capacitors of each set of capacitors in the second capacitive array 142 and outputs the second reference voltage V2 to the second capacitors of each set of capacitors in the second capacitive array 142.

[0021] Step S204: During the first conversion, the comparator 16 compares the voltage Vp and the voltage Vn to generate a first comparison result, the first selection circuit 121 outputs the second reference voltage V2 to the first capacitors of the set of larger capacitors in the first capacitive array 141, and the second selection circuit 122 outputs the first reference voltage V1 to the second capacitors of the set of larger capacitors in the second capacitive array 142.

[0022] Step S206: During the second conversion, the comparator 16 compares the voltage Vp and the voltage Vn to generate a second comparison result, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion of the first capacitors of the set of larger capacitors in the first capacitive array 141 or the first capacitor portion of the second capacitors of the set of larger capacitors in the first capacitive array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion of the first capacitors of the set of larger capacitors in the second capacitive array 142 or the first capacitor portion of the second capacitors of the set of larger capacitors in the second capacitive array 142.

[0023] In step S206, the first comparison result and the second comparison result are different. In some embodiments, the first comparison result can show that the voltage Vp is greater than the voltage Vn and the second comparison result can show that the voltage Vp is less than the voltage Vn, and the first reference voltage V1 can be greater than the second reference voltage V2. In other embodiments, the first comparison result can show that the voltage Vp is less than the voltage Vn and the second comparison result can show that the voltage Vp is greater than the voltage Vn, and the first reference voltage V1 can be less than the second reference voltage V2. The steps of the operation method 200 are described below in conjunction with the analog-to-digital converter 1.

[0024] During the first conversion, if the first comparison result shows that the voltage Vp is greater than the voltage Vn, the first selection circuit 121 outputs the second reference voltage V2 to the first capacitor portion C1pa1 and the second capacitor portion C1pa2 of the first capacitor C1pa of the first group of capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the first reference voltage V1 to the first capacitor portion C1nb1 and the second capacitor portion C1nb2 of the second capacitor C1nb of the first group of capacitors of the second capacitor array 142, as shown in Table 3 (step S204):

[0025] Table 3

[0026] Capacitor C1 pa1 C1 pa2 C1 pb1 C1 pb2 C2 pa C2 pb C3 pa C3 pb Lower plate voltage "V2” "V2” V2 V2 V1 V2 V1 V2 Capacitor C1 na1 C1 na2 C1 nb1 C1 nb2 C2 na C2 nb C3 na C3 nb Lower plate voltage V1 V1 "V1” "V1” V1 V2 V1 V2

[0027] During the second conversion, if the second comparison result shows that the voltage Vp is less than the voltage Vn, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pa1 of the first capacitor C1pa of the first group of capacitors of the first capacitor array 141 to reset the first capacitor portion C1pa1 to its reset value (V1), and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nb1 of the second capacitor C1nb of the first group of capacitors of the second capacitor array 142 to reset the first capacitor portion C1nb1 to its reset value (V2), as shown in Table 4 (step S206):

[0028] Table 4

[0029] Capacitor C1 pa1 C1 pa2 C1 pb1 C1 pb2 C2 pa C2 pb C3 pa C3 pb Lower plate voltage "V1” V2 V2 V2 V1 V2 V1 V2 Capacitor C1 na1 C1 na2 C1 nb1 C1 nb2 C2 na C2 nb C3 na C3 nb Lower plate voltage V1 V1 "V2” V1 V1 V2 V1 V2

[0030] In other embodiments, during the second conversion, if the second comparison result shows that the voltage Vp is less than the voltage Vn, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pb1 of the second capacitor C1pb of the first group of capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1na1 of the first capacitor C1na of the first group of capacitors of the second capacitor array 142, as shown in Table 5 (step S206):

[0031] Table 5

[0032] Capacitor C1 pa1 C1 pa2 C1 pb1 C1 pb2 C2 pa C2 pb C3 pa C3 pb Lower plate voltage V2 V2 "V1” V2 V1 V2 V1 V2 Capacitor C1 na1 C1 na2 C1 nb1 C1 nb2 C2 na C2 nb C3 na C3 nb Lower plate voltage "V2” V1 V1 V1 V1 V2 V1 V2

[0033] If the first reference voltage V1 is a ground voltage and the second reference voltage V2 is a supply voltage, during the first conversion, if the first comparison result shows that the voltage Vp is less than the voltage Vn, the first selection circuit 121 outputs the second reference voltage V2 to the first capacitor portion C1pai and the second capacitor portion C1pa2 of the first capacitor C1pa of the first group of capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the first reference voltage V1 to the first capacitor portion C1nbi and the second capacitor portion C1nb2 of the second capacitor C1nb of the first group of capacitors of the second capacitor array 142, as shown in Table 3 (step S204). During the second conversion, if the second comparison result shows that the voltage Vp is greater than the voltage Vn, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pai of the first capacitor C1pa of the first group of capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nbi of the second capacitor C1nb of the first group of capacitors of the second capacitor array 142, as shown in Table 4 (step S206). In other embodiments, during the second conversion, if the second comparison result shows that the voltage Vp is greater than the voltage Vn, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pbi of the second capacitor C1pb of the first group of capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nai of the first capacitor C1na of the first group of capacitors of the second capacitor array 142, as shown in Table 5 (step S206).

[0034] In other embodiments, during the first sampling, the first selection circuit 121 and the second selection circuit 122 reset the first capacitor array 141 and the second capacitor array 142, respectively, using the second voltage setting shown in Table 2 (step S202). If the first reference voltage V1 is a supply voltage and the second reference voltage V2 is a ground voltage, during the first conversion, if the first comparison result shows that the voltage Vp is greater than the voltage Vn, the first selection circuit 121 outputs the second reference voltage V2 to the first capacitor portion C1pbi and the second capacitor portion C1pb2 of the second capacitor C1pb of the first group of capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the first reference voltage V1 to the first capacitor portion C1nai and the second capacitor portion C1na2 of the first capacitor C1na of the first group of capacitors of the second capacitor array 142, as shown in Table 6 (step S204):

[0035] Table 6

[0036] Capacitor C1 pa1 C1 pa2 C1 pb1 C1 pb2 C2 pa C2 pb C3 pa C3 pb Lower plate voltage V2 V2 "V2” "V2” V2 V1 V2 V1 Capacitor C1 na1 C1 na2 C1 nb1 C1 nb2 C2 na C2 nb C3 na C3 nb Lower plate voltage "V1” "V1” V1 V1 V2 V1 V2 V1

[0037] During the second conversion, if the second comparison result shows that the voltage Vp is less than the voltage Vn, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pbl of the second capacitor C1pb of the first set of capacitors of the first capacitor array 141 to reset the first capacitor portion C1pbl to its reset value (V1), and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nal of the first capacitor C1na of the first set of capacitors of the second capacitor array 142 to reset the first capacitor portion C1nal to its reset value (V2), as shown in Table 7 (step S206):

[0038] Table 7

[0039] Capacitor C1 pa1 C1 pa2 C1 pb1 C1 pb2 C2 pa C2 pb C3 pa C3 pb Lower plate voltage V2 V2 "V1” V2 V2 V1 V2 V1 Capacitor C1 na1 C1 na2 C1 nb1 C1 nb2 C2 na C2 nb C3 na C3 nb Lower plate voltage "V2” V1 V1 V1 V2 V1 V2 V1

[0040] In other embodiments, during the second conversion, if the second comparison result shows that the voltage Vp is less than the voltage Vn, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pal of the first capacitor C1pa of the first set of capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nbl of the second capacitor C1nb of the first set of capacitors of the second capacitor array 142, as shown in Table 8 (step S206):

[0041] Table 8

[0042] Capacitor C1 pa1 C1 pa2 C1 pb1 C1 pb2 C2 pa C2 pb C3 pa C3 pb Lower plate voltage "V1” V2 V2 V2 V2 V1 V2 V1 Capacitor C1 na1 C1 na2 C1 nb1 C1 nb2 C2 na C2 nb C3 na C3 nb Lower plate voltage V1 V1 "V2” V1 V2 V1 V2 V1

[0043] If the first reference voltage V1 is the ground voltage and the second reference voltage V2 is the supply voltage, during the first conversion, if the first comparison result shows that the voltage Vp is less than the voltage Vn, the first selection circuit 121 outputs the second reference voltage V2 to the first capacitor portion C1pbl and the second capacitor portion C1pb2 of the second capacitor C1pb of the first capacitor array 141, and the second selection circuit 122 outputs the first reference voltage V1 to the first capacitor portion C1nai and the second capacitor portion C1na2 of the first capacitor C1na of the second capacitor array 142, as shown in Table 6 (step S204). During the second conversion, if the second comparison result shows that the voltage Vp is greater than the voltage Vn, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pai of the first capacitor C1pa of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nai of the first capacitor C1na of the second capacitor array 142, as shown in Table 7 (step S206). In other embodiments, during the second conversion, if the second comparison result shows that the voltage Vp is greater than the voltage Vn, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pai of the first capacitor C1pa of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nbi of the second capacitor C1nb of the second capacitor array 142, as shown in Table 8 (step S206).

[0044] The first sampling period can belong to a first sampling stage, the first conversion period and the second conversion period can belong to a first quantization stage, and the first sampling stage and the first quantization stage can belong to a first operation cycle. After the first operation cycle, the analog-to-digital converter 1 can sequentially generate three comparison results, and output digital output data Dout according to the three comparison results. In a second operation cycle subsequent to the first operation cycle, the analog-to-digital converter 1 can repeat steps S202 to S206 to generate another three comparison results, and output subsequent digital output data Dout according to the other three comparison results.

[0045] The second operation cycle can include a second sampling phase and a second quantization phase. The second sampling phase can include a second sampling period. The second quantization phase can include a third conversion period and a fourth conversion period subsequent to the third conversion period. The third conversion period can correspond to the first conversion period to generate a higher corresponding bit of the digital output data Dout. The fourth conversion period can correspond to the second conversion period to generate a lower corresponding bit of the digital output data Dout. The second conversion period and the fourth conversion period can not be limited to directly succeeding the first conversion period and the third conversion period. In some embodiments, when the analog-to-digital converter 1 performs the third bit conversion, the second capacitor portion of the first capacitor or the second capacitor portion of the second capacitor in the first group of capacitors of the first capacitor array 141 / second capacitor array 142 can also be switched by a similar method, i.e., the capacitors C1pa2, C1pb2, C1na2, C1nb2. In other embodiments, if the number of configurations of the capacitor array is larger (e.g., ten bits), a larger group of capacitors of the first capacitor array 141 / second capacitor array 142 can be divided into multiple capacitor portions, respectively, whose capacitance values are substantially equal to the capacitance value of one or more smaller capacitors. When performing a conversion other than the largest bit, if the comparison result is different from the largest bit result, one of the capacitor portions of the larger group of capacitors can be selected to complete the conversion by combining the method 200.

[0046] In some embodiments, during the second sampling period, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor of each group of capacitors in the first capacitor array 141 and outputs the second reference voltage V2 to the second capacitor of each group of capacitors in the first capacitor array 141. The second selection circuit 122 outputs the first reference voltage V1 to the first capacitor of each group of capacitors in the second capacitor array 142 and outputs the second reference voltage V2 to the second capacitor of each group of capacitors in the second capacitor array 142, as shown in Table 1. During the third conversion period, the comparator 16 compares the voltage at the first input terminal and the voltage at the second input terminal to generate a third comparison result. The first selection circuit 121 outputs the second reference voltage V2 to the first capacitor C1pa of the larger group of capacitors of the first capacitor array 141. The second selection circuit 122 outputs the first reference voltage V1 to the second capacitor C1nb of the larger group of capacitors of the second capacitor array 142, as shown in Table 3. During the fourth conversion period, the comparator 16 compares the voltage at the first input terminal and the voltage at the second input terminal to generate a fourth comparison result. The third comparison result and the fourth comparison result are different.

[0047] If the comparison results generated during the second conversion period and the fourth conversion period are different from the comparison results generated during the first conversion period and the third conversion period, respectively, the analog-to-digital converter 1 can switch the first capacitor array 141 and the second capacitor array 142 using a fixed switching manner during the second conversion period and the fourth conversion period, for example, using one of the table 4, the table 5, the table 7, and the table 8 to switch the first capacitor array 141 and the second capacitor array 142.

[0048] In some embodiments, the analog-to-digital converter 1 can also switch the first capacitor array 141 and the second capacitor array 142 using an alternating switching manner, for example, alternatingly using the table 4 and the table 5 or alternatingly using the table 7 and the table 8 to switch the first capacitor array 141 and the second capacitor array 142.

[0049] In other embodiments, the analog-to-digital converter 1 can also randomly output the voltage settings of the table 4 and the table 5 to the first capacitor array 141 and the second capacitor array 142 according to a uniform random order, or randomly output the voltage settings of the table 7 and the table 8 to the first capacitor array 141 and the second capacitor array 142 according to a uniform random order. A uniform random order is an order in which the probability of outputting the voltage settings of the table 4 and the table 5 is substantially the same, or the probability of outputting the voltage settings of the table 7 and the table 8 is substantially the same.

[0050] In other embodiments, the analog-to-digital converter 1 can also output the voltage settings of the table 4 and the table 5 to the first capacitor array 141 and the second capacitor array 142 according to a uniform specific order, or output the voltage settings of the table 7 and the table 8 to the first capacitor array 141 and the second capacitor array 142 according to a uniform specific order. A uniform specific order can be an order in which the probability of outputting the voltage settings of the table 4 and the table 5 is substantially the same, or the probability of outputting the voltage settings of the table 7 and the table 8 is substantially the same, and the order is neither purely alternating nor purely random. For example, the uniform specific order can be that the voltage settings of the table 4 are output to the first capacitor array 141 and the second capacitor array 142 for N quantization stages, and then the voltage settings of the table 5 are output to the first capacitor array 141 and the second capacitor array 142 for the next N quantization stages. In another example and in other examples, the uniform specific order can be that the voltage settings of the table 4 or the table 5 are output to the first capacitor array 141 and the second capacitor array 142 during a conversion period according to whether the corresponding conversion period of the previous quantization stage requires switching.

[0051] In some embodiments, during the second conversion the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pai of the first capacitor C1pa of the set of larger capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nbi of the second capacitor C1nb of the set of larger capacitors of the second capacitor array 142, as shown in Table 4; during the fourth conversion the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pb i of the second capacitor C1pb of the set of larger capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nai of the first capacitor C1na of the set of larger capacitors of the second capacitor array 142, as shown in Table 5.

[0052] In some embodiments, during the second conversion the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pai of the first capacitor C1pa of the set of larger capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nbi of the second capacitor C1nb of the set of larger capacitors of the second capacitor array 142, as shown in Table 4; during the fourth conversion the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pb i of the second capacitor C1pb of the set of larger capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nai of the first capacitor C1na of the set of larger capacitors of the second capacitor array 142, as shown in Table 5.

[0053] In some embodiments, during the second conversion the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pai of the first capacitor C1pa of the set of larger capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nbi of the second capacitor C1nb of the set of larger capacitors of the second capacitor array 142, as shown in Table 4; during the fourth conversion the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pb i of the second capacitor C1pb of the set of larger capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nai of the first capacitor C1na of the set of larger capacitors of the second capacitor array 142, as shown in Table 5.

[0054] Table 9

[0055] Capacitor C1 pa1 C1 pa2 C1 pb1 C1 pb2 C2 pa C2 pb C3 pa C3 pb Lower plate voltage V2 V2 "V1” V2 V1 V2 V1 V2 Capacitor C1 na1 C1 na2 C1 nb1 C1 nb2 C2 na C2 nb C3 na C3 nb Lower plate voltage V1 V1 "V2” V1 V1 V2 V1 V2

[0056] Table 10

[0057] Capacitor C1 pa1 C1 pa2 C1 pb1 C1 pb2 C2 pa C2 pb C3 pa C3 pb Lower plate voltage "V1” V2 V2 V2 V1 V2 V1 V2 Capacitor C1 na1 C1 na2 C1 nb1 C1 nb2 C2 na C2 nb C3 na C3 nb Lower plate voltage Capacitor C1 pa1 C1 pa2 C1 pb1 C1 pb2 C2 pa C2 pb C3 pa C3 pb Lower plate voltage Capacitor C1 na1 C1 na2 C1 nb1 C1 nb2 C2 na C2 nb C3 na C3 nb Lower plate voltage Capacitor C1 pa1 C1 pa2 C1 pb1 C1 pb2 C2 pa C2 pb C3 pa C3 pb Lower plate voltage Capacitor C1 na1 C1 na2 C1 nb1 C1 nb2 C2 na C2 nb C3 na C3 nb Lower plate voltage "V2” V1 V1 V1 V1 V2 V1 V2

[0058] In other embodiments, during the second conversion, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pa1 of the first capacitor C1pa of the set of larger capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1na1 of the first capacitor C1na of the set of larger capacitors of the second capacitor array 142, as shown in Table 10; during the fourth conversion, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pb1 of the second capacitor C1pb of the set of larger capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nb1 of the second capacitor C1nb of the set of larger capacitors of the second capacitor array 142, as shown in Table 9.

[0059] The method 200 uses the switching back technique to reduce the differential nonlinearity error and the integral nonlinearity error caused by the capacitance mismatch between the different sets of capacitors in the first capacitor array 141 and the second capacitor array 142.

[0060] In some embodiments, if the first capacitor array 141 and the second capacitor array 142 are both configured with 10-bit binary-weighted capacitors, and each set of capacitors has a random drift with a standard deviation of 2% of the capacitance value, when the capacitors of the set of larger capacitors are operated using the method 200 during the second conversion and subsequent conversions, the differential nonlinearity error is reduced from 0.37 LSB to 0.31 LSB, and the integral nonlinearity error is reduced from 0.82 LSB to 0.8 LSB. In other embodiments, when the first capacitor portion of the first capacitor of the set of larger capacitors and the first capacitor portion of the second capacitor of the set of larger capacitors are switched in a uniform random order or an alternating order during the second conversion, the differential nonlinearity error is reduced from 0.37 LSB to 0.21 LSB, and the integral nonlinearity error is reduced from 0.82 LSB to 0.48 LSB.

[0061] The present application is not limited to the 3-bit SAR ADC used in the embodiments, and a person of ordinary skill in the art can apply the method 200 to SAR ADCs of other sizes according to the spirit of the present application. The analog-to-digital converter 1 and the method 200 of operating the analog-to-digital converter 1 use the switching back technique to switch the first capacitor array 141 and the second capacitor array 142, reduce the differential nonlinearity error and the integral nonlinearity error caused by the capacitance mismatch between the same set of capacitors or different sets of capacitors, and greatly improve the linearity of the SAR ADC.

[0062] The above description is only the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application shall fall within the scope of the present application.

[0063] Explanation of reference signs:

[0064] 1: analog-to-digital converter

[0065] 121: first selection circuit

[0066] 122: second selection circuit

[0067] 141: first capacitor array

[0068] 142: second capacitor array

[0069] 16: comparator

[0070] 18: control logic circuit

[0071] 200: method

[0072] S202 to S206: steps

[0073] C1pa, C1pa1, C1pa2, C1pb, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb, C1na, C1na1, C1na2, C1nb, C1nb1, C1nb2, C2na, C2nb, C3na, C3nb: capacitors

[0074] Dout: digital output data

[0075] SW1, SW2: switches

[0076] V1: first reference voltage

[0077] V2: second reference voltage

[0078] Vip, Vin: differential input voltage

[0079] Vp, Vn: voltage

Claims

1. A method of operating an analog-to-digital converter, the analog-to-digital converter comprising a first capacitor array, a first selection circuit, a second capacitor array, a second selection circuit, a comparator, and control logic circuitry, wherein the first capacitor array comprises multiple groups of capacitors, each group of capacitors in the first capacitor array comprising a first capacitor and a second capacitor; the second capacitor array comprises multiple groups of capacitors, each group of capacitors in the second capacitor array comprising a first capacitor and a second capacitor; the first selection circuit is coupled to the first capacitor array; the second selection circuit is coupled to the second capacitor array; the comparator comprises a first input terminal coupled to the first capacitor array and a second input terminal coupled to the second capacitor array; the control logic circuitry is coupled to the first selection circuit, the second selection circuit, and the comparator; the method of operating the comparator comprises: During the first sampling period, the first selection circuit outputs a first reference voltage to the first capacitor of each group of capacitors in the first capacitor array and outputs a second reference voltage to the second capacitor of each group of capacitors in the first capacitor array; the second selection circuit outputs the first reference voltage to the first capacitor of each group of capacitors in the second capacitor array and outputs the second reference voltage to the second capacitor of each group of capacitors in the second capacitor array. During the first conversion, the comparator compares the voltage at the first input terminal and the voltage at the second input terminal to generate a first comparison result. The first selection circuit outputs the second reference voltage to the first capacitor of a group of larger capacitors in the first capacitor array, and the second selection circuit outputs the first reference voltage to the second capacitor of a group of larger capacitors in the second capacitor array. as well as During a second conversion period following the first conversion period, the comparator compares the voltage at the first input terminal and the voltage at the second input terminal to generate a second comparison result. The first selection circuit outputs the first reference voltage to the first capacitor portion of the first capacitor of the group of larger capacitors in the first capacitor array or the first capacitor portion of the second capacitor of the group of larger capacitors in the first capacitor array. The second selection circuit outputs the second reference voltage to the first capacitor portion of the first capacitor of the group of larger capacitors in the second capacitor array or the first capacitor portion of the second capacitor of the group of larger capacitors in the second capacitor array. The first comparison result and the second comparison result are different.

2. The operating method as described in claim 1, wherein: The first comparison result shows that the voltage at the first input terminal of the comparator is greater than the voltage at the second input terminal; The second comparison result shows that the voltage at the first input terminal of the comparator is less than the voltage at the second input terminal; as well as The first reference voltage is greater than the second reference voltage.

3. The operating method as described in claim 1, wherein: The first comparison result shows that the voltage at the first input terminal of the comparator is less than the voltage at the second input terminal; The second comparison result shows that the voltage at the first input terminal of the comparator is greater than the voltage at the second input terminal; as well as The first reference voltage is less than the second reference voltage.

4. The operating method as described in claim 1, wherein: The capacitance value of the first capacitor portion of the first capacitor of the group of larger capacitors in the first capacitor array is substantially equal to the capacitance value of the first capacitor of the group of smaller capacitors in the first capacitor array. The capacitance value of the first capacitor portion of the second capacitor of the group of larger capacitors in the first capacitor array is substantially equal to the capacitance value of the first capacitor of the group of smaller capacitors in the first capacitor array. The capacitance value of the first capacitor portion of the first capacitor of the group of larger capacitors in the second capacitor array is substantially equal to the capacitance value of the first capacitor of the group of smaller capacitors in the second capacitor array. as well as The capacitance value of the first capacitor portion of the second capacitor of the group of larger capacitors in the second capacitor array is substantially equal to the capacitance value of the first capacitor of the group of smaller capacitors in the second capacitor array.

5. The operating method as described in claim 1, further comprising: During the second sampling period, the first selection circuit outputs the first reference voltage to the first capacitor of each group of capacitors in the first capacitor array and outputs the second reference voltage to the second capacitor of each group of capacitors in the first capacitor array; the second selection circuit outputs the first reference voltage to the first capacitor of each group of capacitors in the second capacitor array and outputs the second reference voltage to the second capacitor of each group of capacitors in the second capacitor array. During the third conversion, the comparator compares the voltage at the first input terminal and the voltage at the second input terminal to generate a third comparison result. The first selection circuit outputs the second reference voltage to the first capacitor of the group of larger capacitors in the first capacitor array, and the second selection circuit outputs the first reference voltage to the second capacitor of the group of larger capacitors in the second capacitor array. as well as During the fourth conversion period following the third conversion period, the comparator compares the voltage at the first input terminal and the voltage at the second input terminal to generate a fourth comparison result. If, during the second conversion period, the first selection circuit outputs the first reference voltage to the first capacitor portion of the first capacitor of the group of larger capacitors in the first capacitor array, then the first selection circuit outputs the first reference voltage to the first capacitor portion of the second capacitor of the group of larger capacitors in the first capacitor array. If, during the second conversion period, the second selection circuit outputs the second reference voltage to the first capacitor portion of the second capacitor of the group of larger capacitors in the second capacitor array, then the second selection circuit outputs the second reference voltage to the first capacitor portion of the first capacitor of the group of larger capacitors in the second capacitor array. The third comparison result and the fourth comparison result are different.

6. The operating method as described in claim 1, further comprising: During the second sampling period, the first selection circuit outputs the first reference voltage to the first capacitor of each group of capacitors in the first capacitor array and outputs the second reference voltage to the second capacitor of each group of capacitors in the first capacitor array; the second selection circuit outputs the first reference voltage to the first capacitor of each group of capacitors in the second capacitor array and outputs the second reference voltage to the second capacitor of each group of capacitors in the second capacitor array. During the third conversion, the comparator compares the voltage at the first input terminal and the voltage at the second input terminal to generate a third comparison result. The first selection circuit outputs the second reference voltage to the first capacitor of the group of larger capacitors in the first capacitor array, and the second selection circuit outputs the first reference voltage to the second capacitor of the group of larger capacitors in the second capacitor array. as well as During the fourth conversion period following the third conversion period, the comparator compares the voltage at the first input terminal and the voltage at the second input terminal to generate a fourth comparison result. If, during the second conversion period, the first selection circuit outputs the first reference voltage to the first capacitor portion of the second capacitor of the group of larger capacitors in the first capacitor array, then the first selection circuit outputs the first reference voltage to the first capacitor portion of the first capacitor of the group of larger capacitors in the first capacitor array. If, during the second conversion period, the second selection circuit outputs the second reference voltage to the first capacitor portion of the first capacitor of the group of larger capacitors in the second capacitor array, then the second selection circuit outputs the second reference voltage to the first capacitor portion of the second capacitor of the group of larger capacitors in the second capacitor array. The third comparison result and the fourth comparison result are different.

7. The operating method as described in claim 1, further comprising: During the second sampling period, the first selection circuit outputs the first reference voltage to the first capacitor of each group of capacitors in the first capacitor array and outputs the second reference voltage to the second capacitor of each group of capacitors in the first capacitor array; the second selection circuit outputs the first reference voltage to the first capacitor of each group of capacitors in the second capacitor array and outputs the second reference voltage to the second capacitor of each group of capacitors in the second capacitor array. During the third conversion, the comparator compares the voltage at the first input terminal and the voltage at the second input terminal to generate a third comparison result. The first selection circuit outputs the second reference voltage to the first capacitor of the group of larger capacitors in the first capacitor array, and the second selection circuit outputs the first reference voltage to the second capacitor of the group of larger capacitors in the second capacitor array. as well as During the fourth conversion period following the third conversion period, the comparator compares the voltage at the first input terminal and the voltage at the second input terminal to generate a fourth comparison result. If, during the second conversion period, the first selection circuit outputs the first reference voltage to the first capacitor portion of the second capacitor of the group of larger capacitors in the first capacitor array, then the first selection circuit outputs the first reference voltage to the first capacitor portion of the first capacitor of the group of larger capacitors in the first capacitor array. If, during the second conversion period, the second selection circuit outputs the second reference voltage to the first capacitor portion of the second capacitor of the group of larger capacitors in the second capacitor array, then the second selection circuit outputs the second reference voltage to the first capacitor portion of the first capacitor of the group of larger capacitors in the second capacitor array. The third comparison result and the fourth comparison result are different.

8. The operating method as described in claim 1, further comprising: During the second sampling period, the first selection circuit outputs the first reference voltage to the first capacitor of each group of capacitors in the first capacitor array and outputs the second reference voltage to the second capacitor of each group of capacitors in the first capacitor array; the second selection circuit outputs the first reference voltage to the first capacitor of each group of capacitors in the second capacitor array and outputs the second reference voltage to the second capacitor of each group of capacitors in the second capacitor array. During the third conversion, the comparator compares the voltage at the first input terminal and the voltage at the second input terminal to generate a third comparison result. The first selection circuit outputs the second reference voltage to the first capacitor of the group of larger capacitors in the first capacitor array, and the second selection circuit outputs the first reference voltage to the second capacitor of the group of larger capacitors in the second capacitor array. as well as During the fourth conversion period following the third conversion period, the comparator compares the voltage at the first input terminal and the voltage at the second input terminal to generate a fourth comparison result. If, during the second conversion period, the first selection circuit outputs the first reference voltage to the first capacitor portion of the first capacitor of the group of larger capacitors in the first capacitor array, then the first selection circuit outputs the first reference voltage to the first capacitor portion of the second capacitor of the group of larger capacitors in the first capacitor array. If, during the second conversion period, the second selection circuit outputs the second reference voltage to the first capacitor portion of the first capacitor of the group of larger capacitors in the second capacitor array, then the second selection circuit outputs the second reference voltage to the first capacitor portion of the second capacitor of the group of larger capacitors in the second capacitor array. The third comparison result and the fourth comparison result are different.

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