A method for configuring fault diagnostic logic for a complex electronic system
By representing signal flow and fault relationships using hierarchical directed graphs, generating and deconstructing a fault dictionary, and combining it with syntax rule encoding, the problem of configuring fault diagnosis logic for complex electronic systems is solved, achieving efficient fault diagnosis and location, and improving the combat effectiveness and maintenance efficiency of radar equipment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-09-13
- Publication Date
- 2026-03-17
AI Technical Summary
Existing technologies struggle to efficiently configure fault diagnosis logic for complex electronic systems, especially for radar equipment. The engineering implementation of fault diagnosis logic configuration is difficult, as the order of magnitude of fault diagnosis logic is high, making it difficult to support rapid and accurate fault diagnosis and location.
A hierarchical directed graph is used to represent signal flow and fault relationships, generating a fault dictionary. The fault dictionary is deconstructed through a progressive classification algorithm, and fault modes are encoded by syntax rules to realize the configuration of fault diagnosis logic.
The number of fault diagnosis logic lines for complex electronic systems such as radar has been reduced from tens of thousands to hundreds, improving configuration efficiency, supporting rapid fault diagnosis and isolation, reducing the development cost of health management systems, and enhancing the combat effectiveness of equipment.
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Figure CN115510899B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of radar engineering technology, specifically relating to a radar equipment support technology. Background Technology
[0002] Modernized global combat systems are becoming increasingly complex, requiring seamless coordination among all combat system components to maximize their effectiveness. The loss of combat capability in any component can create a gap or vulnerability in the overall combat system, leading to dramatic shifts in the battlefield situation. This places higher demands on modern weaponry and equipment, requiring not only combat effectiveness but also sustained combat capability. The rapid battlefield recovery capability of weaponry and equipment is particularly crucial, necessitating timely and accurate diagnosis and location of malfunctions.
[0003] Single devices or simple systems tend to use specific algorithms to extract fault characteristics of the object being diagnosed, thereby achieving the purpose of fault diagnosis. Radar equipment generally integrates multiple subsystems such as antenna arrays, power networks, servo drives, hydraulic structures, information processing, and radar control and display, making it a complex electronic system with a high degree of mechanical, electrical, and hydraulic integration. Traditional fault diagnosis algorithms, such as wavelets and integrated empirical mode decomposition (EEMD), are not suitable for radar equipment.
[0004] Currently, radar equipment uses a multi-signal flow diagnostic model to generate a fault dictionary, combined with condition monitoring BIT (Bit-In-Time) fault diagnosis. Due to the large number of devices and the complex signal transmission relationships in radar systems, the fault dictionary matrix representing the correlation between condition monitoring points and fault modes is enormous. Correspondingly, the number of fault diagnosis logic entries can reach tens of thousands or even more, making the engineering implementation of fault diagnosis logic configuration extremely difficult. Summary of the Invention
[0005] In order to solve the problems of complex electronic equipment with many components, complex signal relationships, and difficulty in representing diagnostic logic in the prior art, this invention proposes a fault diagnosis logic configuration application method for complex electronic systems. To achieve the above objectives, this invention adopts the following technical solutions.
[0006] Testable modeling: Using hierarchical directed graphs to represent the relationships between signal flow and faults, defining the correlation between signal transmission and fault mode and state testing, and establishing a multi-signal flow testable model by modeling the upper structure of the product, the fault dependency model of the lower layer of the product, and the testing of each layer of the product, using correlation to characterize the dependency relationship between faults and test points.
[0007] Product upper-level structure modeling includes: establishing product modules and their input and output ports on the model diagram, establishing lower-level structure modules and their ports one by one, establishing the fault modes of the lower-level structure if the lower-level structure has its own fault modes, until all lower-level modules are established, establishing AND gates if the lower-level modules have redundancy, establishing switches if the lower-level modules have multiple working modes, and connecting the lower-level modules, AND gates, and switches.
[0008] Product underlying fault dependency modeling includes: establishing product underlying fault modes, setting signals for mode influence, isolation, and conversion; if there is redundancy in the lower-level module, an AND gate is established; if the lower-level module has multiple operating modes, a switch is established; and the underlying fault modes, AND gates, and switches are connected.
[0009] Product testing at each level includes: first establishing tests for the lower-level module ports and setting test signals, then establishing tests for the product's underlying fault modes and setting test signals.
[0010] Furthermore, the testable model for multi-signal flow includes: a finite set of elements F = {F1, F2, ... F...} n} represents a potential fault source, a set of system-related dependent signals S = {S1, S2, ... S} n A finitely available test set T = {T1, T2, ..., T} k A finite set of test points TP = {TP1, TP2, ..., TP} of size P. h A set of tests T associated with each test point TP, and a set of signals S affected by each component. Ω (F) A subset of signals S that each test can detect Θ (T).
[0011] Assume that the state of the object under test depends on the state of each component unit, and has binary value, either 0 or 1. The normal state means that there is no fault and it can work normally, and the fault state means that it cannot work normally. There is no intermediate state.
[0012] Furthermore, when the tested object malfunctions, the test effectiveness of each test point reachable by the information flow is the same, and the contribution of each test point is 1, which does not decrease as the information flow extends.
[0013] Generate a fault dictionary: Use a hierarchical directed graph to analyze the relationship between fault modes, state tests, and signal transmission, and generate a reciprocity matrix as a fault dictionary. This dictionary describes the mapping relationship between the fault mode library, state test items, and signal flow, provides system diagnostic logic information, and reflects the fuzzy group and redundant test status of the system in test states.
[0014] Deconstructing the Fault Dictionary: The traditional algorithm compares the test results with each row of the fault dictionary to distinguish different fault modes. For highly integrated and complex electronic systems, such as radar equipment, there are many components, numerous test items, a large fault mode library, and complex signal transmission relationships. The corresponding fault dictionary has high dimensionality, low deconstruction efficiency, and is difficult to apply in engineering. This application constructs a discrimination vector, adopts a progressive classification algorithm, sets a fault dictionary matrix, and obtains the equipment diagnostic logic through four binary classifications, thereby improving the efficiency of fault dictionary deconstruction.
[0015] Furthermore, setting the fault dictionary matrix includes: using {F i} represents a set representing the equipment failure mode library, {T j} represents the set of equipment test items, a ij F represents i With T j The relevant relationships are established, and real-time equipment status monitoring messages are pre-processed and integrated using a matrix. The test items are arranged in order to obtain the test result {R}. j}={R1,R2,...R n}
[0016] The first binary classification includes: based on the test results {R} j} and D matrix, if R j =0, then it is determined that the fault mode in the row where the element in the j-th column of matrix D is 1 has not occurred, and {F i} is divided into two subsets, {F A} represents the set of failure modes that have not occurred, {F B} represents the set of possible failure modes.
[0017] The second binary classification includes: establishing a discriminant vector P = {P1, P2, ..., P} n}, which represents the set of possible failure modes {F} B The corresponding row elements are added together to obtain the discrimination vector P. The decision vector P is determined by whether it is a vector consisting entirely of zeros. Then it is determined that there is no generalized fault. Then it is determined that there is a generalized fault, and {F} B} is divided into two subsets, This represents the set of fault modes that did not occur or where false alarms were present. This represents a set of fault modes that are certain to occur, may occur, or have false alarms.
[0018] The third binary classification includes: based on the test results {R j},like Then the test result in column j is determined to be a false alarm. Then it is determined that there is no false alarm, and Divided into two subsets, This represents the set of cases where the fault mode did not occur but false alarms were detected. This represents the set of fault modes that did not occur and had no false alarms.
[0019] The fourth binary classification includes: defining functions. Construct a discriminant vector Q = {Q1, Q2} 2, ...,Q n},in Based on the discriminant vector Q(i), Divided into two subsets, express The set of failure modes that must occur. express The set of possible failure modes.
[0020] Model-based coding: Complex electronic systems have complex equipment compositions and numerous test items. If they are not hierarchically divided according to certain criteria, the model coding will be chaotic, making it impossible to configure subsequent diagnostic logic or causing configuration errors. The device under test and its test items are hierarchically classified and graded, with scientific coding penetrating downwards based on functional division or physical structure. To serve the application of subsequent syntax rules, in complex electronic systems, there may be identical equipment in some local areas. Due to distributed network relationships, such as distributed power supply networks and distributed radio frequency networks, the diagnostic logic may differ. Therefore, during coding, the devices are grouped and clustered according to the local distributed signal transmission relationship, and the regions are independent. Test items and the device under test have a dependency relationship. Test items and device codes are bound according to parent and child nodes, which facilitates the subsequent logic writing.
[0021] Define syntax rules: Logically describe the fault dictionary of complex electronic devices, write the whole machine fault dictionary XML configuration file, and establish the fault mode coding structure and diagnostic logic configuration structure according to the usage parameter definition rules, fault component model coding rules, and test state vector description.
[0022] The parameter definition rules include: replacing repetitive coding in the logic with predefined parameters, which facilitates the coding of fault components and the writing of test item state vectors, reduces the workload of configuration, and simplifies the configuration text.
[0023] The coding rules for faulty components include: filling in the code of the faulty component in the software model and the corresponding fault severity level. The faulty component code is filled in with the model code or represented by a predefined variable. The fault severity level is divided into four levels: failure fault, critical fault, warning fault, and normal, which correspond to the four colors red, orange, yellow, and green in the software model, respectively.
[0024] The test state vector description includes: a set of various factors that affect the diagnosed component; optimized and complete syntax rules to support a single statement representing multiple diagnostic logics and reflecting the correlation between factors, based on actual conditions.
[0025] Furthermore, the syntax rules include: abbreviating multiple variables according to special rules, and operations between variable parameter values including equal to, greater than, less than, not equal to, not greater than, not less than, addition, subtraction, multiplication, division, AND, OR, NOT, XOR, and XNOR.
[0026] Fault Mode Coding Structure
[0027]
[0028] Diagnostic logic configuration structure
[0029]
[0030]
[0031] The beneficial effects of this invention are as follows: It reduces the number of fault diagnosis logic entries for complex electronic systems such as radar from tens of thousands to hundreds, supports logic expansion, improves configuration efficiency, and truly realizes the implementation of fault diagnosis and isolation / location; it uses a multi-signal flow model to build a test prototype for the entire equipment, generating a large fault dictionary; and uses a progressive classification algorithm that constructs discriminant vectors to deconstruct the fault dictionary and obtain the equipment fault diagnosis information contained within it, resulting in high algorithm efficiency; the fault diagnosis logic configuration syntax rules are practical and feasible, realizing the engineering application of fault diagnosis for complex electronic equipment and supporting condition-based maintenance for complex electronic equipment; it describes the impact of faults through equipment test state vector sets, and promptly isolates and locates the current fault location based on equipment BIT monitoring items, providing decision support for equipment testing, training, and combat maintenance activities; it promptly detects faults, grasps the equipment's operating status, reduces detection and maintenance time, facilitates later maintenance, and reduces the development cost of the equipment's health management system; and at appropriate times, it implements targeted support maintenance activities, assesses the current system's task execution capability, and improves the equipment's combat effectiveness. Attached Figure Description
[0032] Figure 1 It is the system modeling process. Figure 2 It is a reflection of the fault dictionary on fuzzy groups and redundancy tests. Figure 3 It is the signal stream of the radar array. Figure 4 It is the definition of the radar array row and column numbers. Figure 5 It refers to the division of radar array components into regions. Detailed Implementation
[0033] Considering the sheer size of the radar system and the inability to fully display all the fault dictionaries and logical relationships, it is not appropriate to use it directly as an example. Instead, we will take a radar system array component as an example and illustrate the implementation steps of the present invention with reference to the accompanying drawings.
[0034] Step 1: Test modeling of the TR component of a radar array
[0035] The modeling process is as follows: Figure 1 As shown, the FMEA of the radar array TR components, the relationship between input and output interfaces, the signal transmission relationship, the associated equipment and test points are analyzed. A multi-signal flow model is used for test modeling, and the modeling results are as follows. Figure 2 As shown.
[0036] The following two points require explanation:
[0037] a) The input / output interface of the array TR module mainly consists of the array power supply network, uplink / downlink optical transmission network, and RF clock network;
[0038] b) The array has 544 TR modules, distributed in 68 high-frequency cells. In each high-frequency cell, 8 modules share a power supply bus ring and a power divider.
[0039] Step 2: Generation of fault dictionary for array TR components
[0040] The approach to generating a dictionary is as follows: Figure 3 As shown, a fault dictionary reflecting the correlation between fault modes and test items of the array TR component is generated using a multi-signal flow model, and is represented as a table matrix as follows:
[0041] A fault dictionary for a radar array TR component
[0042]
[0043] Step 3: Deconstruction of the fault dictionary for array TR components
[0044] Based on the progressive classification algorithm using discriminant vectors, the above fault dictionary is deconstructed to obtain the fault diagnosis logic for the radar array TR component, as shown in the table below:
[0045] TR component transmitter power supply fault diagnosis logic description
[0046]
[0047]
[0048] TR Component Digital 5V Fault Diagnosis Logic Description
[0049]
[0050] TR component negative 5V power supply fault diagnosis logic description
[0051]
[0052] TR component system clock lockout diagnostic logic description
[0053]
[0054] TR Component Fiber Optic Clock Loss Diagnosis Logic Description
[0055]
[0056]
[0057] TR Component RF Front-End Over-Temperature Fault Diagnosis Logic Description
[0058]
[0059] TR component FPGA over-temperature fault diagnosis logic description
[0060] Fault Modes / Test Items FPGA over-temperature test failure FPGA over-temperature fault 1
[0061] TR component leakage fault diagnosis logic description
[0062] Fault Modes / Test Items Component leakage test failure Component leakage fault 1
[0063] Step 4: Perform hierarchical and scientific coding of complex electronic system equipment and condition test items. The equipment is coded in a downward, layered manner, as shown in the table below:
[0064] Equipment hierarchical coding table
[0065]
[0066]
[0067] During coding, test items are bound to parent and child nodes of the device according to their dependencies. The software-defined codes for all test items are shown in the table below:
[0068] Test item code table
[0069] Test Items code Rectifier output test 1030101 Receive power output test 1030201 Clock preamp output test 1010201 Active optical amplifier output test 1020101 RF front-end over-temperature test 101010X0Y0Z01 FPGA over-temperature testing 101010X0Y0Z02 Component leakage test 101010X0Y0Z03 Component communication status test 101010X0Y0Z04 Component system clock lockout test 101010X0Y0Z05 Component fiber clock lock-in test 101010X0Y0Z06 Component transmit power status test 101010X0Y0Z07 Component digital 5V status test 101010X0Y0Z08 Component negative 5V state test 101010X0Y0Z09
[0070] Note: In the table, 0XOYOZ represents the TR component with the serial number Z from left to right in the high-frequency compartment of the Xth row and Yth column.
[0071] Step 5: Configure the fault diagnosis logic according to the defined logical syntax rules.
[0072] Assuming the antenna array's primary subsystem is designated 01 and the TR component's secondary subsystem is also designated 01, the fault modes of the array's TR component are encoded according to the fault mode coding structure, as shown in the table below:
[0073] TR Component Failure Mode Coding Table
[0074]
[0075]
[0076] After providing the equipment, test items, and fault mode codes, the following definitions and explanations are made regarding the XML file syntax rules based on the actual diagnostic logic of the TR component in the embodiment.
[0077] a) The parameter names of the equipment and test items correspond to their codes in the software model and are unique;
[0078] b) Parameter values 0 / 1 / 2 / 3 represent the health status of the device under diagnosis (failure / critical failure / warning failure / normal) and their display color (red / orange / yellow / green) in the software model;
[0079] c) In XML files, the logical relationship of "equal to" is represented by ":", and the parameter name and parameter value are separated by ":".
[0080] d) Predefined variables can be defined, with parameter names such as param1#, param2#, etc.
[0081] e) Defined prevariable parameters can be combined with other values to form new codes. For example, if param1#:10101 is defined, then param1#02 is equivalent to 1010102.
[0082] f) Two numbers separated by a "-" within "[]" support continuous expansion incremented by 1. For example, [01-08] is equivalent to (01,02,03,04,05,06,07,08).
[0083] g) Use ";" as a separator between two sets of parameters.
[0084] h) Parameter names support associativity, for example, param1#[01-03](05,06) is equivalent to param1#0105; param1#0106; param1#0205; param1#0206; param1#0305; param1#0306;
[0085] i) Various logical operations are supported between variable parameter values, with OR logical operations represented by "|" and AND logical operations represented by "^";
[0086] j) Define special function abbreviation rules for the XOR logic operation present in the fault diagnosis logic of high-frequency in-cabin components, for example...
[0087] {param1#[05-08](05,39)}:1 and (param1#0505^param1#0539)|(param1#0605^param1
[0088] #0639)|(param1#0705^param1#0739)|(param1#0805^param1#0839):1 is equivalent.
[0089] Based on the diagnostic logic configuration structure and the above-defined XML file, write the syntax rules, and the component areas are as follows: Figure 5 The following table shows the configuration of the fault diagnosis logic for the transmit power supply of the surface TR component:
[0090] TR component fault diagnosis logic configuration
[0091]
[0092]
[0093] Step 6: Implement fault diagnosis for complex equipment
[0094] The configuration of radar TR component fault diagnosis logic can utilize equipment status test items to achieve fault isolation and location of complex electronic equipment. For a transmission power supply fault of 544 components in an array, only 3 logic lines are needed to complete the configuration of the transmission power supply fault diagnosis logic for the entire array, reducing the workload of software development. As the array size increases and the fault modes increase, the effect of reducing the workload of logic configuration becomes more and more significant.
[0095] The above are embodiments of the present invention and do not limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention are included within the protection scope of the present invention.
Claims
1. A method of applying fault diagnostic logic configuration to a complex electronic system, characterized by, The method comprises the following steps: Testability modeling: the interrelation between signal flow and fault is represented by a hierarchical directed graph, the correlation between signal transmission and fault mode and state test is defined, the dependence between fault and test point is represented by correlation, and a testability model of multiple signal flows is established through product upper structure modeling, product bottom fault dependency modeling and product layer test; Fault dictionary generation: the relationship among fault mode, state test and signal transmission is analyzed by a hierarchical directed graph, a correlation matrix is generated as a fault dictionary, the mapping relationship among fault mode library, state test item and signal flow is described, system diagnosis logic information is provided, and the fuzzy group of system in testability state and redundant test are reflected; Fault dictionary decomposition: a discrimination vector is constructed, a progressive classification algorithm is adopted, a fault dictionary matrix is set, and through four times of binary classification, equipment diagnosis logic is obtained; Modeling coding: the tested equipment and test items thereof are layered and graded, scientific coding is performed downwardly through functional division or physical structure penetration, the test items and equipment coding are bound according to local distributed signal transmission relationship during coding, and the test items and equipment coding are bound according to local distributed signal transmission relationship during coding; Definition of syntax rules: the fault dictionary of complex electronic equipment is logically described, an XML configuration file of whole machine fault dictionary is written, the rule definition, fault part model coding rule and test state vector description are performed according to use parameters, and the fault mode coding structure and diagnosis logic configuration structure are established; The fault dictionary matrix includes: using {F i } represents a set representing the equipment failure mode library, {T j } represents the set of equipment test items, a ij F represents i With T j The relevant relationships are established, and real-time equipment status monitoring messages are pre-processed and integrated using a matrix. The test items are arranged in order to obtain the test result {R}. j }={R1,R 2, ...R n }; The first binary classification of the four binary classifications includes: based on the test result {R j } and D matrix, if R j =0, then it is determined that the fault mode in the row where the element in the j-th column of matrix D is 1 has not occurred, and {F i } is divided into two subsets, {F A } represents the set of failure modes that have not occurred, {F B } represents the set of possible failure modes; The second binary classification includes: establishing a discriminant vector P = {P1, P 2, ...P n}, adding the row elements corresponding to the set of possible failure modes {F B} to obtain the discriminant vector P, and according to whether the vector P is a full zero vector, if , it is determined that there is a generalized fault, if , it is determined that there is a generalized fault, and the set of {F B} is divided into two subsets, , indicating that the failure mode does not occur or there is a false alarm, , indicating that the failure mode must occur, may occur or there is a false alarm; The third binary classification includes: according to the test result {R j}, if the jth column test result is determined as false alarm, if no false alarm is determined, and is divided into two subsets, represents a set of no fault mode occurrence and false alarm, represents a set of no fault mode occurrence and no false alarm; The fourth binary classification comprises defining a function A discriminant vector Q = {Q1, Q2,..., Q n} is constructed, where According to the discriminant vector Q(i), the are divided into two subsets, denote a set in which the failure mode is certain to occur, denote a set in which the failure mode can occur.
2. The method for applying logic configuration for failure diagnosis of a complex electronic system according to claim 1, characterized in that, The product upper structure modeling comprises the following steps: product modules and input and output ports thereof are established on a model graph, lower structure modules of the product and ports thereof are established one by one, if the lower structure has fault modes, the fault modes of the layer are established, until all lower modules are established, if there is redundancy in the lower module, an AND gate is established, if there are multiple working modes in the lower module, a switch is established, and the lower module, AND gate and switch are connected; The product bottom fault dependency modeling comprises the following steps: product bottom fault modes are established, mode influence, blocking and conversion signals are set, if there is redundancy in the lower module, an AND gate is established, if there are multiple working modes in the lower module, a switch is established, and the bottom fault mode, AND gate and switch are connected; The product layer test comprises the following steps: the test of the ports of the product lower module is established first, and then the test of the product bottom fault mode is established.
3. The method for applying logic configuration for fault diagnosis of complex electronic systems according to claim 2, characterized in that, The multi-signal flow testability model includes a set of finite elements F = {F1, F2,... F n} representing potential fault sources, a set of dependent signals S = {S1, S2,... S n} associated with the system, a set of finite available tests T = {T1, T2,... T k}, a set of test points TP = {TP1, TP2,... TP h} of size P, a set of tests T associated with each test point TP, a set of signals S Ω affected by each element F, a set of signals S Θ (T) detectable by each test T.
4. The method for applying fault diagnostic logic configuration of complex electronic systems according to claim 3, characterized in that, Further comprising: The state of the tested object depends on the state of each component unit, has binary nature, is non-0 or 1, the normal state represents no fault and can work normally, the fault state represents that it cannot work normally, and there is no intermediate state.
5. The method for applying fault diagnostic logic configuration of complex electronic systems according to claim 4, characterized in that, Further comprising: When the tested object fails, the test effectiveness of each test point reached by the information flow is the same, the contribution degree of each test point is 1, and does not attenuate with the extension of the information flow.
6. The method for applying fault diagnostic logic configuration for complex electronic systems according to claim 1, characterized in that, The use parameter definition rule comprises: the pre-defined parameters are used to replace the repeated coding in the logic, the configuration workload is reduced, the configuration text is simplified, the fault part coding and test item state vector writing are facilitated, and the configuration workload is reduced. The failure part model coding rule comprises: filling in the code of the failure part in the software model and the corresponding failure severity level, the failure part coding filling in the model code or the pre-defined variable representation, and the failure severity level being divided into four levels of failure failure, critical failure, warning failure and normal, corresponding to four colors of red, orange, yellow and green in the software model; The test state vector description comprises: a variety of factor sets affecting the diagnosed components, supporting a single statement to represent multiple diagnostic logics and reflecting the correlation between the factors, and optimizing the complete syntax rules according to the actual situation.
7. The method for applying fault diagnostic logic configuration of a complex electronic system according to claim 6, characterized in that, The syntax rule comprises: abbreviating multiple variables according to a special rule, and the operation between variable parameter values comprising equal to, greater than, less than, not equal to, not greater than, not less than, addition, subtraction, multiplication, division, and, or, not, exclusive or, and same or.