Display substrate, method for preparing display substrate, and display device

Abstract

The present invention relates to the technical field of display, and discloses a display substrate, a method for preparing the display substrate, and a display device. The display substrate includes: a base substrate, the base substrate including a display area and a non-display area at least partially surrounding the display area, the non-display area including a binding area and a blank area, the binding area being located between the blank area and the display area; a buffer layer located on one side of the base substrate; an insulating layer structure located on a side of the buffer layer away from the base substrate; a plurality of binding pins located in the binding area, the plurality of binding pins being arranged on a side of the insulating layer structure away from the base substrate; a plurality of sub-pixels located in the display area; a plurality of data lines located in the display area and the non-display area, electrically connected to the plurality of sub-pixels and the plurality of binding pins; and a padding structure located in the blank area, disposed between the base substrate and the buffer layer, and configured to reduce a height difference between an edge of the insulating layer structure and the buffer layer, to prevent short circuits that occur when a flexible circuit board is bound to the display substrate.

Description

Technical Field

[0001] The present invention relates to the technical field of display, and in particular to a display substrate, a method for preparing the display substrate, and a display device. Background Art

[0002] The mainstream display devices today are LCD (Liquid Crystal Display) and OLED (Organic Light Emitting Display). Both LCD and OLED are manufactured separately from other circuit integrations. To ensure the normal operation of the display device, various binding connections are involved, the most important of which is the binding connection between the display substrate and the driver chip.

[0003] The display substrate will be connected to the flexible circuit board, but now due to the influence of the display substrate process, there is metal residue at the edge of the display substrate, which causes a short circuit when binding with the flexible circuit board. Summary of the Invention

[0004] The present invention discloses a display substrate, a method for preparing the display substrate, and a display device, which are used to avoid short circuit failure when a flexible circuit board is bound to the display substrate.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] In a first aspect, the present invention provides a display substrate comprising:

[0007] a base substrate, the base substrate comprising a display area and a non-display area at least partially surrounding the display area, the non-display area comprising a binding area and a blank area, the binding area being located between the blank area and the display area;

[0008] a buffer layer located on one side of the substrate;

[0009] an insulating layer structure located on a side of the buffer layer away from the substrate;

[0010] a plurality of binding pins located in the binding area, wherein the plurality of binding pins are arranged on a side of the insulating layer structure away from the substrate;

[0011] A plurality of sub-pixels are located in the display area;

[0012] a plurality of data lines, located in the display area and the non-display area, and electrically connected to the plurality of sub-pixels and the plurality of binding pins;

[0013] The padding structure located in the blank area is disposed between the base substrate and the buffer layer and is configured to reduce a height difference between an edge of the insulating layer structure and the buffer layer.

[0014] A buffer layer is provided on one side of the base substrate, and an insulating layer structure is provided on the side of the buffer layer facing away from the base substrate. Multiple binding pins are provided in the binding area on the side of the functional layer facing away from the base substrate, and a raised structure is provided in the blank area between the base substrate and the buffer layer, thereby reducing the height difference between the edge of the insulating layer structure and the buffer layer. In other words, the height difference is reduced, resulting in a step-like shape between the edge of the insulating layer structure and the buffer layer. Multiple sub-pixels are located in the display area, and multiple data lines are located in the display area and non-display area. The multiple sub-pixels and the multiple binding pins are connected via the multiple data lines. In forming the binding pins, a metal layer is first deposited on the side of the insulating layer structure facing away from the base substrate, and a photoresist is applied to the side of the metal layer facing away from the base substrate. This ensures that the thickness of the photoresist in the blank area is the same as that in other areas. After removing the photoresist, no photoresist remains in the blank area. The metal layer is then patterned to form the binding pins, and no metal layer remains in the blank area. This effectively prevents short circuits during the binding process with the binding pins, which could cause abnormal display of sub-pixels in the display area of ​​the display substrate.

[0015] Optionally, the plurality of binding pins are arranged along a first direction, the binding pins extend along a second direction, and the first direction intersects the second direction;

[0016] An extending direction of the raising structure is parallel to the first direction.

[0017] Optionally, the material of the raising structure is metal.

[0018] Optionally, an orthographic projection of the insulating layer structure on the base substrate does not overlap with an orthographic projection of the padding structure on the base substrate.

[0019] Optionally, along a direction perpendicular to the base substrate, a surface of the insulating layer structure away from the base substrate is higher than a surface of the buffer layer away from the base substrate.

[0020] Optionally, along a direction perpendicular to the base substrate, a height difference between a surface of the insulating layer structure away from the base substrate and a surface of the buffer layer away from the base substrate is less than 0.75 μm.

[0021] Optionally, a reflective layer is further included in the display area, and the reflective layer is arranged between the base substrate and the buffer layer.

[0022] Optionally, the reflective layer and the raised structure are provided on the same layer.

[0023] Optionally, the insulating layer structure includes a gate insulating layer and an interlayer dielectric layer stacked along the substrate toward the buffer layer.

[0024] In a second aspect, the present invention provides a method for preparing a display substrate, comprising:

[0025] Providing a base substrate, the base substrate is divided into a display area and a non-display area, the non-display area includes a binding area and a blank area, and the binding area is located between the blank area and the display area;

[0026] A metal layer is formed on one side of the base substrate, and the metal layer is patterned to form a raised structure located in the blank area;

[0027] forming a buffer layer on a side of the metal layer away from the substrate;

[0028] An insulating layer structure is formed on a side of the buffer layer away from the base substrate.

[0029] Optionally, a conductive layer is formed on a side of the insulating layer structure away from the substrate;

[0030] Photoresist is coated on the side of the conductive layer away from the base substrate, and the photoresist in the blank area is exposed to light to completely remove the photoresist in the blank area.

[0031] In a third aspect, the present invention provides a display device comprising: the display substrate according to any one of the first aspects;

[0032] A flexible circuit board is provided with a plurality of signal pins, wherein the signal pins are connected to the binding pins of the display substrate in a one-to-one correspondence. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of cutting a display motherboard provided by an embodiment of the present invention;

[0034] Figure 2 A schematic structural diagram of a display device provided by an embodiment of the present invention;

[0035] Figure 3 A schematic diagram of the structure of a display substrate provided by an embodiment of the present invention Figure 1 ;

[0036] Figure 4 A schematic diagram of the structure of a display substrate provided by an embodiment of the present invention Figure 2 ;

[0037] Figure 5A schematic structural diagram of a binding area of ​​a display substrate provided by an embodiment of the present invention;

[0038] Figure 6 For the corresponding Figure 4 A schematic cross-sectional view of a sub-pixel in the display area shown;

[0039] Figure 7-10 A schematic diagram of a process for preparing a binding region of a display substrate provided by an embodiment of the present invention;

[0040] Figure 11 Schematic diagram of a binding structure between a binding area of ​​a display substrate and a flexible circuit board provided by an embodiment of the present invention Figure 1 ;

[0041] Figure 12 Schematic diagram of a binding structure between a binding area of ​​a display substrate and a flexible circuit board provided by an embodiment of the present invention Figure 2 ;

[0042] Figure 13 Schematic diagram of a binding structure between a binding area of ​​a display substrate and a flexible circuit board provided by an embodiment of the present invention Figure 3 ;

[0043] Figure 14 A display substrate provided in an embodiment of the present invention is a schematic structural diagram of a liquid crystal display panel. DETAILED DESCRIPTION

[0044] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0045] like Figure 1 As shown, the display substrate 01a is an important part of the display device. The display motherboard 01 can be divided into multiple display substrates 01a. When cutting the display motherboard 01, a laser is usually used to cut along the cutting path to form a single display substrate 01a for subsequent processing. The arrangement of the cutting path depends on the shape of the display substrate to be produced.

[0046] like Figure 2 As shown, after the display substrate 01a is cut, the binding pins 4 of the single display substrate 01a are bound to the flexible circuit board. If there is residual metal near the cutting line, it will cause a short circuit in the flexible circuit board and cause display abnormalities. To avoid the short circuit problem when binding the single display substrate 01a to the flexible circuit board, the following technical solution is adopted.

[0047] Specific references are Figures 2 to 4 As shown, in a first aspect, an embodiment of the present invention provides a display substrate 01a, comprising:

[0048] A base substrate 1, the base substrate 1 is divided into a display area AA and a non-display area BB, the non-display area BB includes a binding area BB1 and a blank area BB2, and the binding area BB1 is located between the blank area BB2 and the display area AA;

[0049] A buffer layer 2 is located on one side of the base substrate 1; an insulating layer structure 3 is located on the side of the buffer layer 2 away from the base substrate 1; a plurality of binding pins 4 are located in the binding area BB1, and the binding pins 4 are arranged on the side of the insulating layer structure 3 away from the base substrate 1; a plurality of sub-pixels 8 are located in the display area AA; a plurality of data lines 9 are located in the display area AA and the non-display area BB, and are electrically connected to the plurality of sub-pixels 8 and the plurality of binding pins 4; a padding structure 5 is located in the blank area BB2, and is arranged between the base substrate 1 and the buffer layer 2, and is configured to reduce the height difference between the edge of the insulating layer structure 3 and the buffer layer 2.

[0050] It should be noted that, combined with Figure 11 As shown, a buffer layer 2 is provided on one side of the base substrate 1, and an insulating layer structure 3 is provided on the side of the buffer layer 2 facing away from the base substrate 1. Multiple binding pins 4 in the binding area BB1 are provided on the side of the functional layer away from the base substrate 1. A padding structure 5 in the blank area BB2 is provided between the base substrate 1 and the buffer layer 2, thereby reducing the height difference between the edge of the insulating layer structure 3 and the buffer layer 2. In other words, the height difference at the S position is reduced, resulting in a stepped shape between the edge of the insulating layer structure 3 and the buffer layer 2. Multiple sub-pixels 8 located in the display area AA and multiple data lines 9 located in the display area AA and the non-display area BB are connected to the multiple sub-pixels 8 and the multiple binding pins 4 via the multiple data lines 9. When forming the binding pin 4, a metal layer 4a is first deposited on the side of the insulating layer structure 3 away from the base substrate 1, and a photoresist 6 is coated on the side of the metal layer 4a away from the base substrate 1, so that the thickness of the photoresist 6 at the blank area BB2 is the same as the thickness in other areas. After the photoresist 6 is removed, no photoresist 6 remains in the blank area BB2. Then, the binding pin 4 formed after patterning the metal layer 4a also has no metal layer residue in the blank area BB2, effectively avoiding short circuit during the binding process with the binding pin 4, which causes abnormal display of the sub-pixel 8 in the display area AA of the display substrate 01a.

[0051] like Figure 2-Figure 5As shown, multiple binding pins 4 are arranged along a first direction, and the binding pins 4 extend along a second direction, with the first direction intersecting the second direction; for example, the first direction is perpendicular to the second direction. A raised structure 5 is located within a raised region 5a, and the extended direction of the raised structure 5 is parallel to the first direction. Because the raised region 5a is raised by the raised structure 5, the height difference between the edge of the insulating layer structure 3 and the buffer layer 2 is effectively reduced, that is, the step difference is reduced, resulting in a step-like shape between the edge of the insulating layer structure 3 and the buffer layer 2. The flexible circuit board is bonded to the display substrate 01a via the binding pins 4. During the formation of the binding pins 4, a metal layer 4a is first deposited on the side of the insulating layer structure 3 facing away from the base substrate 1, and a photoresist 6 is applied to the side of the metal layer 4a facing away from the base substrate 1. This ensures that the thickness of the photoresist 6 at the blank area BB2 is the same as that at other areas. After the photoresist 6 is removed, no photoresist 6 remains in the blank area BB2. The metal layer 4a is then patterned to form the binding pins 4, which also have no metal layer residue in the blank area BB2. That is to say, by disposing a long strip of the padding structure 5 , it can be ensured that the plurality of binding pins 4 arranged along the first direction will not be short-circuited when being bound to the flexible circuit board.

[0052] In some specific embodiments, the material of the raised structure 5 is metal. A metal layer 4a is deposited on the side of the insulating layer structure 3 away from the base substrate 1, and a photoresist 6 is coated on the side of the metal layer 4a away from the base substrate 1. The photoresist 6 is exposed and developed. Due to the presence of the raised structure 5, the thickness of the photoresist 6 at the blank area BB2 is the same as that in other areas. After the photoresist 6 is removed, no photoresist 6 remains in the blank area BB2. At the same time, because the material of the raised structure 5 is metal, the properties of the metal increase the reflection of the photoresist 6 during exposure, further enhancing the ability to remove the photoresist 6 by exposure, and reducing the residual photoresist 6 in the blank area BB2.

[0053] In order to further ensure the exposure and development effects of the photoresist 6 , the orthographic projection of the insulating layer structure 3 on the base substrate 1 does not overlap with the orthographic projection of the padding structure 5 on the base substrate 1 .

[0054] like Figure 6 As shown, taking an OLED as an example, a sub-pixel 8 of each pixel unit in the pixel array of the display area of ​​the display substrate is used to realize light-emitting drive and control. The sub-pixel 8 includes a pixel driving circuit 1120, a first planarization layer 1130, a first transfer electrode 1180, a second planarization layer 1190, and a light-emitting element 1140. A passivation layer 11110 is formed between the pixel driving circuit 1120 and the first planarization layer 1130, and the passivation layer 11110 includes a passivation layer via 11111. A first via 1131 is formed in the first planarization layer 1130 to expose the source electrode 1125 or the drain electrode 1126 (as shown in the figure).

[0055] For example, the sub-pixel further includes a buffer layer 1121 located on the base substrate 1, and the pixel driving circuit 1120 includes an active layer 1122 located on the display area buffer layer 1121. For example, a semiconductor material layer is deposited on the base substrate 1 and then patterned to form the active layer 1122. The active layer 1121 includes a source region 1123 and a drain region 1124. A first gate insulating layer 1128 is located on the side of the active layer 1122 away from the base substrate 1; a gate electrode 11211 is located on the first gate insulating layer 1128 of the display area; a second gate insulating layer 1129 is located on the side of the gate electrode 11211 away from the base substrate 1; a display area interlayer insulating layer 11210 is located on the second gate insulating layer 1129 of the display area; and a source electrode 1125 and a drain electrode 1126 are located on the display area interlayer insulating layer 11210. The display area buffer layer 1121 serves as a transition layer, which can prevent harmful substances in the base substrate from invading the interior of the display substrate and increase the adhesion of the film layer in the display substrate to the base substrate 1 .

[0056] For example, the display area buffer layer 1121 may be made of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The display area interlayer insulating layer 11210, the display area second gate insulating layer 1129, and the display area first gate insulating layer 1128 may be made of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The display area interlayer insulating layer 11210, the display area second gate insulating layer 1129, and the display area first gate insulating layer 1128 may be made of the same or different materials.

[0057] For example, in some examples of the present disclosure, Figure 4 As shown, the pixel driving circuit 1120 may further include a first display metal layer 1127 , and the first display metal layer 1127 includes a source electrode 1125 and a drain electrode 1126 of the thin film transistor in the pixel driving circuit.

[0058] For example, in some examples of the present disclosure, Figure 4 As shown, the second planarization layer 1190 is disposed on the side of the first connecting electrode 1180 away from the base substrate 1 to provide a planarized surface on the side of the first connecting electrode 1180 away from the base substrate 1. In addition, a second via hole 1191 is formed in the second planarization layer 1190.

[0059] For example, a light-emitting element 1140 is formed on the second planarization layer, that is, the light-emitting element 1140 is disposed on the side of the second planarization layer 1190 away from the base substrate. The light-emitting element 1140 includes a first electrode 1141, a light-emitting layer 1142, and a second electrode 1143. The first electrode 1141 of the light-emitting element is electrically connected to the first transfer electrode 1180 through a second via 1191 in the second planarization layer 1140. A pixel-defining layer 1144 is formed on the first electrode 1141. The pixel-defining layer 1144 includes a plurality of openings to define a plurality of pixel units. Each of the plurality of openings exposes a corresponding first electrode 1141. Subsequently, the light-emitting layer 1142 is disposed in the plurality of openings of the pixel-defining layer 1144, and the second electrode 1143 is disposed on the pixel-defining layer 1144 and the light-emitting layer 1142. For example, the second electrode 1143 can be disposed in part or the entire display area, so that it can be formed over the entire surface during the manufacturing process.

[0060] For example, the material of the second planarization layer 1190 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, and the embodiments of the present disclosure are not limited to this.

[0061] For example, the first electrode 1141 may include a reflective layer, and the second electrode 1143 may include a transparent layer or a semi-transparent layer. Thus, the first electrode 1141 can reflect light emitted from the light-emitting layer 1142, with some of the light being emitted into the external environment through the second electrode 1143, thereby improving light extraction efficiency. When the second electrode 1143 includes a semi-transmissive layer, some of the light reflected by the first electrode 1141 is reflected again by the second electrode 1143, thereby forming a resonant structure with the first electrode 1141 and the second electrode 1143, thereby improving light extraction efficiency.

[0062] For example, the material of the first electrode 1141 may include at least one transparent conductive oxide material including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. In addition, the first electrode 1141 may include a metal with high reflectivity as a reflective layer, such as silver (Ag).

[0063] For example, for OLEDs, the light-emitting layer 1142 can include small molecule organic materials or polymer molecule organic materials, and can be fluorescent or phosphorescent, emitting red, green, blue, or white light. Furthermore, the light-emitting layer can further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer, as needed. For QLEDs, the light-emitting layer can include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, and indium arsenide quantum dots, with a particle size of 2-20 nm.

[0064] For example, the second electrode 1143 may include various conductive materials, such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), and the like.

[0065] For example, the material of the pixel defining layer 1144 may include an organic insulating material such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene or phenolic resin, or an inorganic insulating material such as silicon oxide or silicon nitride, which is not limited in the embodiments of the present disclosure.

[0066] In addition, the display substrate also includes a storage capacitor 1160, which may include a first capacitor electrode 1161 and a second capacitor electrode 1162. The first capacitor electrode 1161 is arranged between the first gate insulating layer 1128 of the display area and the second gate insulating layer 1129 of the display area, and the second capacitor electrode 1162 is arranged between the second gate insulating layer 1129 of the display area and the interlayer insulating layer 11210 of the display area. The first capacitor electrode 1161 and the second capacitor electrode 1162 are stacked and at least partially overlap in a direction perpendicular to the base substrate 1. The first capacitor electrode 1161 and the second capacitor electrode 1162 use the second gate insulating layer 1129 of the display area as a dielectric material to form a storage capacitor. Similarly, as described above, in a variation of the above example, the first capacitor electrode and the second capacitor electrode of the storage capacitor 1160 can also be located in other layers, thereby obtaining sub-pixels with different structures.

[0067] In another example, as Figure 4 In a variation of the example shown, the first capacitor electrode of the storage capacitor is still arranged in the same layer as the gate 11211, while the second capacitor electrode of the storage capacitor is arranged in the same layer as the source 1125 and the drain 1126 in the thin film transistor (that is, also located in the first display metal layer 1127), thereby the first capacitor electrode and the second capacitor electrode use the stack of the second gate insulating layer 1129 of the display area and the interlayer insulating layer 11210 of the display area as dielectric materials to form a storage capacitor.

[0068] In yet another example, as Figure 4 In a variation of the example shown, the first capacitor electrode of the storage capacitor is no longer arranged in the same layer as the gate electrode 11211, but is located between the second gate insulation layer 1129 of the display area and the interlayer insulation layer 11210 of the display area, while the second capacitor electrode of the storage capacitor is arranged in the same layer as the source electrode 1125 and the drain electrode 1126 in the thin film transistor (that is, also located in the first display metal layer 1127), thereby the first capacitor electrode and the second capacitor electrode use the display area interlayer insulation layer 11210 as a dielectric material to form a storage capacitor.

[0069] For example, in some examples of the present disclosure, Figure 4 As shown, the display substrate may further include an encapsulation layer 1150 disposed on the light-emitting element 1140. The encapsulation layer 1150 seals the light-emitting element 1140, thereby reducing or preventing degradation of the light-emitting element 1140 caused by moisture and / or oxygen in the environment. The encapsulation layer 1150 may have a single-layer structure or a composite layer structure including a stack of inorganic and organic layers. For example, the encapsulation layer 1150 may include a first inorganic encapsulation layer 1151, a first organic encapsulation layer 1152, and a second inorganic encapsulation layer 1153 disposed in sequence. The encapsulation layer 1150 may extend to the bonding area. In the above example, the encapsulation layer does not cover the contact pads.

[0070] For example, the encapsulation layer may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resins. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, and the like. The organic encapsulation layer may be made of a polymer material containing a desiccant or a polymer material that can block moisture, such as a polymer resin, to planarize the surface of the display substrate and relieve stress on the first and second inorganic encapsulation layers. It may also include a desiccant or other absorbent material to absorb intrusive water, oxygen, and other substances.

[0071] like Figure 5 As shown, in the direction perpendicular to the substrate 1, at the S position, the surface of the insulating layer structure 3 on the side away from the substrate 1 is higher than the surface of the buffer layer 2 on the side away from the substrate 1. In the direction perpendicular to the substrate 1, at the S position, the height difference between the surface of the insulating layer structure 3 on the side away from the substrate 1 and the surface of the buffer layer 2 on the side away from the substrate 1 is less than 0.75 μm. The height difference between the insulating layer structure 3 and the buffer layer 2 at the S position is reduced, so that when the metal layer 4a and the photoresist 6 are deposited on the side of the insulating layer structure 3 away from the substrate 1, the stacking thickness of the photoresist 6 at the S position is reduced. Generally, when there is no padding structure 5, the height difference between the edge of the insulating layer structure 3 and the buffer layer 2 is greater than or equal to 0.75 μm.

[0072] In some specific embodiments, such as Figure 14 As shown, taking LCD as an example, the LCD includes a display substrate and a backlight unit (BLU). For example, since liquid crystal itself does not emit light, the backlight unit provides light source; the display substrate 01a includes a color filter substrate 01a1, a liquid crystal layer 01a2, and an array substrate 01a3. The array substrate 01a3 is provided with a thin film transistor (TFT) to control the deflection of liquid crystal molecules to control the light source of the backlight unit; the color filter layer in the color filter substrate 01a1 realizes the colorization of the light source. The display substrate 01a provided in the embodiment of the present invention also includes a reflective layer 10 located in the display area AA. The reflective layer 10 is located in the array substrate 01a3, that is, it is arranged between the base substrate 1 and the buffer layer 2 in the array substrate 01a3. The reflective layer 10 located in the array substrate 01a3 is arranged on the same layer as the padding structure 5 in the binding area. The provision of the reflective layer can improve the utilization rate of the backlight module light by the display substrate 01a.

[0073] To save manufacturing process, the reflective layer and the raised structure 5 are provided on the same layer. That is, a metal layer is formed on one side of the base substrate 1 and patterned to form the reflective layer in the display area AA and the raised structure 5 in the blank area BB2.

[0074] For example, Figure 11 As shown, a cushioning structure 5 is formed on the base substrate 1 of the non-display area BB of the display substrate, and a buffer layer 2 is formed on the side of the cushioning structure 5 away from the base substrate. The buffer layer 2 in the non-display area BB is prepared in the same layer as the buffer layer 1121 of the display area AA. An insulating layer structure is formed on the side of the buffer layer 2 in the non-display area BB away from the base substrate 1. The insulating layer structure 3 includes a gate insulating layer and an interlayer dielectric layer stacked along the direction of the base substrate 1 pointing to the buffer layer 2. The film layers included in the insulating layer structure 3 are not limited to the film layers listed above. In other examples, the insulating layer structure 3 may include one or more of them, and may also include other film layers. A binding pin 4 is formed on the side of the insulating layer structure 3 away from the base substrate 1. The binding pin 4 is bound to the signal pin 71 of the flexible circuit board to form Figure 11 The structure shown.

[0075] For example, Figure 12As shown, a cushioning structure 5 is formed on the base substrate 1 of the non-display area BB of the display substrate, and a buffer layer 2 is formed on the side of the cushioning structure 5 facing away from the base substrate. The buffer layer 2 in the non-display area BB is prepared in the same layer as the buffer layer 1121 of the display area AA. An insulating layer structure is formed on the side of the buffer layer 2 in the non-display area BB facing away from the base substrate 1. The insulating layer structure 3 includes a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer stacked along the base substrate 1 pointing to the buffer layer 2. The above-mentioned first gate insulating layer, second gate insulating layer, and interlayer insulating layer are prepared in the same layer as the first gate insulating layer 1128, second gate insulating layer 1129, and interlayer insulating layer 11210 of the display area. The film layers included in the insulating layer structure 3 are not limited to the film layers listed above. In other examples, the insulating layer structure 3 may include one or more of them, and may also include other film layers. A binding pin 4 is formed on the side of the insulating layer structure 3 facing away from the base substrate 1. The binding pin 4 is made of a first source-drain layer 41 and a second source-drain layer 42. That is, the first source-drain layer 41 and the second source-drain layer 42 of the binding pin are prepared on the same layer as the first source-drain layer and the second source-drain layer of the display area, and an insulating material layer 45 is patterned between the first source-drain layer 41 and the second source-drain layer 42. For example, the insulating material layer is a flat layer, that is, the flat layer of the non-display area BB is prepared on the same layer as the first flattening layer 1130 of the display area AA. The binding pin 4 is bound to the signal pin 71 of the flexible circuit board to form Figure 12 The structure shown.

[0076] like Figure 13As shown, a padding structure 5 is formed on the base substrate 1 of the non-display area BB of the display substrate, and a buffer layer 2 is formed on the side of the padding structure 5 facing away from the base substrate. The buffer layer 2 in the non-display area BB is prepared on the same layer as the buffer layer 1121 in the display area AA. An insulating layer structure 3 is formed on the side of the buffer layer 2 in the non-display area BB facing away from the base substrate 1. The insulating layer structure 3 in the non-display area BB includes a first gate insulating layer, and the first gate insulating layer in the non-display area BB is prepared on the same layer as the first gate insulating layer 1128 in the display area AA. The film layers included in the insulating layer structure 3 are not limited to the film layers listed above. In other examples, the insulating layer structure 3 may include one or more of them, and may also include other film layers. A binding pin 4 is formed on the side of the insulating layer structure 3 facing away from the base substrate 1. The binding pin 4 is made of a first source and drain layer 41 and a gate layer 44. That is, the first source and drain layer 41 in the binding area is prepared in the same layer as the source and drain in the display area, and the gate layer 44 in the binding area is prepared in the same layer as the gate 11211 in the display area; and an insulating material layer 45 is patterned between the first source and drain layer 41 and the gate layer 44. For example, the insulating material layer is an interlayer insulating layer and a second gate insulating layer, that is, the interlayer insulating layer and the second gate insulating layer of the non-display area BB are prepared in the same layer as the interlayer insulating layer 11210 and the second gate insulating layer 1129 of the display area AA. The binding pin 4 is bound to the signal pin 71 of the flexible circuit board to form Figure 13 The structure shown.

[0077] like Figure 7 In a second aspect, an embodiment of the present invention provides a method for preparing a display substrate 01a, comprising: providing a base substrate 1, wherein the base substrate 1 is divided into a display area AA and a non-display area BB, wherein the non-display area BB includes a binding area BB1 and a blank area BB2, and the binding area BB1 is located between the blank area BB2 and the display area AA;

[0078] A metal layer 4a is formed on one side of the base substrate 1, and the metal layer 4a is patterned to form a raised structure 5 located in the blank area BB2;

[0079] A buffer layer 2 is formed on a side of the metal layer 4 a away from the base substrate 1 ; and an insulating layer structure 3 is formed on a side of the buffer layer 2 away from the base substrate 1 .

[0080] like Figure 8 As shown, a conductive layer is formed on the side of the insulating layer structure 3 away from the substrate 1 ; and a photoresist 6 is coated on the side of the conductive layer away from the substrate 1 .

[0081] like Figure 9 As shown, the photoresist 6 located in the blank area BB2 is exposed to completely remove the photoresist 6 located in the blank area BB2.

[0082] like Figure 10As shown, the metal layer 4a is etched, and then the photoresist 6 is removed, so that the etched metal layer 4a is formed into a binding pin 4, and the binding pin 4 is bound to the signal pin 71 of the flexible circuit board to form Figure 11 The structure shown.

[0083] In a third aspect, an embodiment of the present invention provides a display device, comprising: the display substrate 01a according to any one of the first aspects;

[0084] Continue to refer Figure 9 , flexible circuit board, the flexible circuit board has multiple signal pins 71, and the signal pins 71 are connected to the binding pins 4 of the display substrate 01a in a one-to-one correspondence.

[0085] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the present invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such modifications and variations.

Claims

1. A display substrate, characterized in that: include: a base substrate, the base substrate comprising a display area and a non-display area at least partially surrounding the display area, the non-display area comprising a binding area and a blank area, the binding area being located between the blank area and the display area; a buffer layer located on one side of the substrate; an insulating layer structure located on a side of the buffer layer away from the substrate; a plurality of binding pins located in the binding area, wherein the plurality of binding pins are arranged on a side of the insulating layer structure away from the substrate; A plurality of sub-pixels are located in the display area; a plurality of data lines, located in the display area and the non-display area, and electrically connected to the plurality of sub-pixels and the plurality of binding pins; The padding structure located in the blank area is disposed between the base substrate and the buffer layer and is configured to reduce a height difference between an edge of the insulating layer structure and the buffer layer.

2. The display substrate according to claim 1, wherein: The plurality of binding pins are arranged along a first direction, the binding pins extend along a second direction, and the first direction intersects the second direction; An extending direction of the raising structure is parallel to the first direction.

3. The display substrate according to claim 1, wherein The material of the raising structure is metal.

4. The display substrate according to any one of claims 1 to 3, wherein: The orthographic projection of the insulating layer structure on the base substrate does not overlap with the orthographic projection of the padding structure on the base substrate.

5. The display substrate according to claim 4, wherein: Along a direction perpendicular to the base substrate, a surface of the insulating layer structure away from the base substrate is higher than a surface of the buffer layer away from the base substrate.

6. The display substrate according to claim 5, wherein: Along a direction perpendicular to the base substrate, a height difference between a surface of the insulating layer structure away from the base substrate and a surface of the buffer layer away from the base substrate is less than 0.75 μm.

7. The display substrate according to claim 1, wherein: It also includes a reflective layer located in the display area, and the reflective layer is arranged between the base substrate and the buffer layer.

8. The display substrate according to claim 7, wherein: The reflective layer and the raised structure are arranged on the same layer.

9. The display substrate according to claim 1, wherein: The insulating layer structure includes a gate insulating layer and an interlayer dielectric layer stacked along the substrate toward the buffer layer.

10. A method for preparing a display substrate, characterized in that: include: Providing a base substrate, the base substrate is divided into a display area and a non-display area, the non-display area includes a binding area and a blank area, and the binding area is located between the blank area and the display area; A metal layer is formed on one side of the base substrate, and the metal layer is patterned to form a raised structure located in the blank area; forming a buffer layer on a side of the metal layer away from the substrate; forming an insulating layer structure on a side of the buffer layer away from the substrate; The padding structure is disposed between the base substrate and the buffer layer, and is configured to reduce a height difference between an edge of the insulating layer structure and the buffer layer.

11. The method according to claim 10, characterized in that forming a conductive layer on a side of the insulating layer structure away from the substrate; Photoresist is coated on the side of the conductive layer away from the base substrate, and the photoresist in the blank area is exposed to light to completely remove the photoresist in the blank area.

12. A display device, characterized in that: include: The display substrate according to any one of claims 1 to 9; A flexible circuit board is provided with a plurality of signal pins, wherein the signal pins are connected to the binding pins of the display substrate in a one-to-one correspondence.

Images