A method for preparing an LED chip

Abstract

The present application discloses a method for preparing an LED chip. First, a negative photoresist is spin-coated on the surface of the epitaxial stack away from the substrate. Then, the negative photoresist is first exposed using a first photomask, and then second exposed using a second photomask. After that, the negative photoresist after the two exposures is developed to form a photoresist pattern. Using the negative photoresist with the photoresist pattern as a mask, the epitaxial stack is etched to form isolation channels. The isolation channels penetrate the epitaxial stack until the substrate surface, so as to divide the epitaxial stack into multiple sub-epitaxial stacks and form a mesa. The exposed part of the mesa is the first-type semiconductor layer. One sub-epitaxial stack corresponds to one LED chip. That is, the method for preparing an LED chip provided by the embodiments of the present application can complete mesa etching and deep etching only by spin-coating the negative photoresist once, performing two exposures, and performing one etching. The process is simple and the manufacturing cost is relatively low.

Description

Technical Field

[0001] This application relates to the technical field of light-emitting diodes, and particularly to a method for manufacturing an LED chip. Background Art

[0002] A light-emitting diode (LED) is a semiconductor device that converts electrical energy into light energy. Due to its advantages such as small size, long lifespan, rich colors, and low energy consumption, it is widely used in fields such as lighting, display, and backlighting. Mini LED, as a sub-millimeter light-emitting diode with a size typically ranging from 80μm to 200μm, is a new generation of LED technology that inherits the characteristics of small-pitch LEDs, including high efficiency, high reliability, high brightness, and fast response time, and also has lower power consumption and cost.

[0003] During the manufacturing process of an LED chip, mesa etching (MESA etching) and deep etching (DE etching) need to be performed on the epitaxial wafer. Specifically, taking an epitaxial wafer including a substrate, an N-type GaN layer, an active layer, and a P-type GaN layer as an example, after mesa etching of the epitaxial wafer, the N-type GaN layer is exposed to facilitate the subsequent preparation of the N electrode. After deep etching of the epitaxial wafer, the etching depth reaches the surface of the substrate to achieve device isolation between different LED chips. However, currently, when manufacturing an LED chip, a positive photoresist is usually used as a mask, and the mesa etching is completed using an inductively coupled plasma (ICP) etching process. After mesa etching, a positive photoresist is used as a mask again, and the deep etching is completed using the ICP etching process again. That is, currently, two-step lithography and two ICP etching processes are required to complete mesa etching and deep etching when manufacturing an LED chip, resulting in a complex process and a high manufacturing cost. Summary of the Invention

[0004] To solve the above technical problems, an embodiment of this application provides a method for manufacturing an LED chip to simplify the process steps of mesa etching and deep etching during the manufacturing process of the LED chip and reduce the manufacturing cost.

[0005] To achieve the above objective, an embodiment of this application provides the following technical solution:

[0006] A method for manufacturing an LED chip, comprising:

[0007] Providing a substrate, and forming an epitaxial stack on the substrate, the epitaxial stack including a first-type semiconductor layer, an active layer, and a second-type semiconductor layer arranged in sequence in a direction away from the substrate;

[0008] Spin-coating a negative photoresist on the surface of the epitaxial stack away from the substrate;

[0009] The negative photoresist is subjected to a first exposure using a first photomask, and the first photomask shields the area of the epitaxial stack where isolation channels are to be formed;

[0010] The negative photoresist is subjected to a second exposure using a second photomask, and the second photomask shields the area of the epitaxial stack where isolation channels and mesa are to be formed;

[0011] The negative photoresist after two exposures is developed to form a photoresist pattern;

[0012] Using the negative photoresist with the photoresist pattern as a mask, the epitaxial stack is etched to form the isolation channels. The isolation channels penetrate the epitaxial stack until the substrate surface, separating the epitaxial stack into multiple sub-epitaxial stacks, and mesa are formed in the sub-epitaxial stacks. The mesa exposes a part of the first-type semiconductor layer, and one sub-epitaxial stack corresponds to one LED chip.

[0013] Optionally, in the direction perpendicular to the plane of the substrate, the thickness of the negative photoresist is greater than the thickness of the epitaxial stack;

[0014] The sensitivity of the negative photoresist is E0 mJ / cm 2 , and the exposure dose when the negative photoresist is subjected to the first exposure using the first photomask is E1, where 5.4E0 ≤ E1 ≤ 6.6E0.

[0015] Optionally, the exposure dose when the negative photoresist is subjected to the second exposure using the second photomask is E2, and E2 ≥ 3E0.

[0016] Optionally, before developing the negative photoresist after two exposures, the method further includes:

[0017] Baking the negative photoresist after two exposures;

[0018] After developing the negative photoresist after two exposures, the method further includes:

[0019] Hardening the developed negative photoresist. By baking, developing, and hardening the negative photoresist after two exposures, the surface of the negative photoresist is crosslinked to achieve inversion of the photoresist pattern;

[0020] Performing flood exposure on the hardened negative photoresist to shape the negative photoresist and improve its etching resistance.

[0021] Optionally, the sensitivity of the negative photoresist is E0 mJ / cm 2 , and the exposure dose when performing flood exposure on the hardened negative photoresist is E3, and E3 > E0.

[0022] Optionally, using a negative photoresist with a photoresist pattern as a mask, etching the epitaxial stack includes:

[0023] Using a negative photoresist with a photoresist pattern as a mask, performing a first-step etching on the epitaxial stack to form the isolation channel, where the etching selectivity used in the first-step etching ranges from 0.9 to 1.1, including the end values;

[0024] Using a negative photoresist with a photoresist pattern as a mask, performing a second-step etching on the epitaxial stack to form the mesa, where the etching selectivity used in the second-step etching ranges from 0.6 to 0.9, including the end values.

[0025] Optionally, the method further includes:

[0026] Removing the negative photoresist, and forming a composite transparent conductive layer on the surface of the second-type semiconductor layer in the sub-epitaxial stack facing away from the substrate;

[0027] The formation process of the composite transparent conductive layer includes:

[0028] Forming an ITO layer on the surface of the second-type semiconductor layer in the sub-epitaxial stack facing away from the substrate;

[0029] Forming a nano-gas-sensitive adsorption layer on the surface of the ITO layer facing away from the substrate, where the nano-gas-sensitive adsorption layer has a porous structure, and the ITO layer and the nano-gas-sensitive adsorption layer form the composite transparent conductive layer;

[0030] Performing rapid thermal annealing in an O2 atmosphere to enable the nano-gas-sensitive adsorption layer to adsorb oxygen ions, increasing the oxygen ion concentration on the surface layer of the ITO layer facing away from the substrate, thereby increasing the work function of the ITO layer and forming an ohmic contact between the ITO layer and the second-type semiconductor layer.

[0031] Optionally, the material of the nano-gas-sensitive adsorption layer includes at least one of SnO2, WO3, CuO, ZrO2, Co3O4, Fe2O3, ZnO, SiO2, ZnSnO3, In2O3, CdSnO3, CdFe2O4, and ZnFe2O4.

[0032] Optionally, when performing rapid thermal annealing in an O2 atmosphere, the gas flow rate of O2 ranges from 0.5 sccm to 4 sccm, including the end values; the annealing temperature ranges from 400 °C to 600 °C, including the end values.

[0033] Optionally, the method further includes:

[0034] A first electrode is formed on the tabletop, and a second electrode is formed on the surface of the composite transparent conductive layer facing away from the substrate. Alternatively, the composite transparent conductive layer is etched to form a first through hole penetrating the composite transparent conductive layer, and the second electrode is embedded in the composite transparent conductive layer through the first through hole and electrically connected to the second-type semiconductor layer;

[0035] A reflective layer and an insulating cover layer are sequentially formed on the side of the overall structure composed of the epitaxial stack, the composite transparent conductive layer, the first electrode, and the second electrode facing away from the substrate;

[0036] The reflective layer and the insulating cover layer are etched to form a second through hole and a third through hole penetrating the reflective layer and the insulating cover layer. The second through hole exposes the first electrode, and the third through hole exposes the second electrode;

[0037] A first pad and a second pad are formed. The first pad is electrically connected to the first electrode through the second through hole, and the second pad is electrically connected to the second electrode through the third through hole.

[0038] Compared with the prior art, the above technical solution has the following advantages:

[0039] When preparing an LED chip according to the prior art, two-step photolithography and two ICP etching processes are required to complete mesa etching and deep etching, with a complex process and high manufacturing cost. In the method for preparing an LED chip provided by the embodiment of the present application, first, a negative photoresist is spin-coated on the surface of the epitaxial stack facing away from the substrate, then the negative photoresist is first exposed using a first photomask, and then the negative photoresist is secondarily exposed using a second photomask. After that, the negative photoresist after the two exposures is developed to form a photoresist pattern. Using the negative photoresist with the photoresist pattern as a mask, the epitaxial stack is etched to form isolation channels. The isolation channels penetrate the epitaxial stack until the surface of the substrate, so as to divide the epitaxial stack into multiple sub-epitaxial stacks, and mesas are formed in the sub-epitaxial stacks. The mesas expose a part of the first-type semiconductor layer. One sub-epitaxial stack corresponds to one LED chip. That is, in the method for preparing an LED chip provided by the embodiment of the present application, only one spin-coating of negative glue, two exposures, and one etching are required to complete mesa etching and deep etching, with a simple process and low manufacturing cost. Description of the Drawings

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0041] Figure 1 Schematic flow chart of the method for manufacturing an LED chip provided by an embodiment of the present application;

[0042] Figures 2(a) - 2(i) Schematic diagram of the device structure corresponding to each process step in the method for manufacturing an LED chip provided by an embodiment of the present application;

[0043] Figure 3 Schematic diagram of the first photomask;

[0044] Figure 4 Schematic diagram of the second photomask;

[0045] Figure 5 Schematic diagram of the development after only the first exposure of the negative photoresist in the method for manufacturing an LED chip provided by an embodiment of the present application;

[0046] Figure 6 Schematic diagram of the development after the first exposure and the second exposure of the negative photoresist in the method for manufacturing an LED chip provided by an embodiment of the present application;

[0047] Fig. 7(a) is a topographic diagram of a positive photoresist when deep etching is performed using a positive photoresist as a mask in the prior art;

[0048] Fig. 7(b) is a topographic diagram of the epitaxial stack after deep etching using a positive photoresist as a mask in the prior art;

[0049] Fig. 7(c) is an FIB test diagram of the epitaxial stack after deep etching using a positive photoresist as a mask in the prior art;

[0050] Fig. 8(a) is a topographic diagram of the development after the first exposure with an exposure amount of E1 and the second exposure with an exposure amount of E2 of the negative photoresist in the method for manufacturing an LED chip provided by an embodiment of the present application;

[0051] Fig. 8(b) is a topographic diagram of the epitaxial stack after etching using the negative photoresist shown in Fig. 8(a) as a mask;

[0052] Fig. 8(c) is an FIB test diagram of the epitaxial stack after etching using the negative photoresist shown in Fig. 8(a) as a mask;

[0053] Figure 9 Schematic flow chart of the method for manufacturing an LED chip provided by another embodiment of the present application;

[0054] Figure 10 Schematic diagram of the corresponding relationship between the work function of the ITO layer and the number of oxygen atoms on its surface;

[0055] Figure 11Schematic flow chart of a method for manufacturing an LED chip provided by another embodiment of the present application. Detailed implementation manners

[0056] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0057] In the following description, many specific details are set forth in order to fully understand the present application. However, the present application may be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0058] Secondly, the present application will be described in detail with reference to the schematic diagrams. When describing the embodiments of the present application in detail, for the sake of clarity, the cross-sectional views showing the device structure will be enlarged locally out of the general scale, and the schematic diagrams are only examples and should not limit the protection scope of the present application herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0059] As described in the background art section, currently when manufacturing an LED chip, two-step photolithography and two ICP etching processes are required to complete mesa etching and deep etching, resulting in a complex process and relatively high manufacturing costs.

[0060] In view of this, the embodiments of the present application provide a method for manufacturing an LED chip, as Figure 1 shown, the method includes:

[0061] S100: As shown in Fig. 2(a), provide a substrate 10, and form an epitaxial stack 20 on the substrate 10. The epitaxial stack 20 includes a first-type semiconductor layer 21, an active layer 22, and a second-type semiconductor layer 23 arranged in sequence along the direction away from the substrate 10.

[0062] Optionally, the substrate 10 may be a sapphire substrate, the first-type semiconductor layer 21 may be an N-type GaN layer, and the second-type semiconductor layer 23 may be a P-type GaN layer. However, the present application does not limit the materials of the substrate 10, the first-type semiconductor layer 21, the active layer 22, and the second-type semiconductor layer 23.

[0063] S200: As shown in Fig. 2(b), spin-coat a negative photoresist 30 on the surface of the epitaxial stack 20 away from the substrate 10.

[0064] As we know, under the irradiation of an energy beam (such as a light beam, an electron beam, an ion beam, etc.), the exposed part mainly undergoes a chain-breaking reaction and dissolves in the developer. Such a photoresist is a positive photoresist. As described in the background art section, in the prior art, when preparing an LED chip, a positive photoresist is always used as a mask to perform mesa etching and deep etching on the epitaxial stack.

[0065] In the method for preparing an LED chip provided in the embodiment of the present application, a negative photoresist is spin-coated on the surface of the epitaxial stack 20 facing away from the substrate 10. Contrary to the characteristics of the positive photoresist, in the negative photoresist, the exposed part mainly undergoes a cross-linking reaction and is not easily soluble in the developer.

[0066] In step S200, the viscosity of the negative photoresist 30 can be greater than 250 cP. Step S200 is also called the spin-coating process. In practical applications, after spin-coating, a baking is performed once to remove a large amount of moisture in the negative photoresist.

[0067] S300: Perform a first exposure on the negative photoresist 30 using a first photomask, and the first photomask shields the area of the epitaxial stack 20 where an isolation channel needs to be formed;

[0068] S400: Perform a second exposure on the negative photoresist 30 using a second photomask, and the second photomask shields the area of the epitaxial stack 20 where an isolation channel and a mesa need to be formed;

[0069] S500: Develop the negative photoresist after two exposures to form a photoresist pattern;

[0070] S600: Use the negative photoresist 30 with the photoresist pattern as a mask to etch the epitaxial stack 20 to form an isolation channel 40. As shown in FIG. 2(c), the isolation channel 40 penetrates the epitaxial stack 20 until the surface of the substrate 10 to separate the epitaxial stack 20 into multiple sub-epitaxial stacks, and a mesa 50 is formed in the sub-epitaxial stack. The exposed part of the mesa 50 is the first-type semiconductor layer 21, and one sub-epitaxial stack corresponds to one LED chip.

[0071] It should be noted that the epitaxial stack 20 in FIG. 2(c) is a sub-epitaxial stack corresponding to one LED chip. It can be understood that there are many sub-epitaxial stacks as shown in FIG. 2(c) in a wafer, and the sub-epitaxial stacks are isolated from each other by the isolation channels 40.

[0072] In step S300, the pattern of the first photomask used for the first exposure of the negative photoresist 30 is as Figure 3 shown, Figure 3The white area is the exposed area, and the black area is the non-exposed area. The non-exposed area corresponds to the area in the epitaxial stack 20 where the isolation trench 40 needs to be formed, specifically corresponding to the area where the isolation trench 40 is located in Fig. 2(c). The non-exposed area will be dissolved and removed by the developer during the subsequent development of the negative photoresist.

[0073] In step S400, the pattern of the second photomask used for the second exposure of the negative photoresist 30 is as Figure 4 shown. Figure 4 The white area is the exposed area, and the black area is the non-exposed area. The non-exposed area corresponds to the area in the epitaxial stack 20 where the isolation trench 40 and the mesa 50 need to be formed, specifically corresponding to the areas where the isolation trench 40 and the mesa 50 are located in Fig. 2(c). The non-exposed area will be dissolved and removed by the developer during the subsequent development of the negative photoresist.

[0074] Refer to Figure 3 and Figure 4 , it can be understood that Fig. 2(c) is a cross-sectional view of the device structure corresponding to AA' after etching the epitaxial stack 20, and Fig. 2(d) is a cross-sectional view of the device structure corresponding to BB' after etching the epitaxial stack 20. The following continues to describe with the device structure shown in Fig. 2(c).

[0075] Combined with Figures 2(b) - 2(c) , Figure 3 and Figure 4 it can be seen that the part of the negative photoresist 30 corresponding to the area in the epitaxial stack 20 where the isolation trench 40 needs to be formed is blocked by the photomask during both the first exposure and the second exposure. Therefore, in step 500, after developing the negative photoresist 30 that has been exposed twice, the part of the negative photoresist 30 corresponding to the area in the epitaxial stack 20 where the isolation trench 40 needs to be formed will be dissolved and removed by the developer. Since this part of the negative photoresist has been exposed twice, this part of the negative photoresist is basically completely removed;

[0076] The part of the negative photoresist 30 corresponding to the area in the epitaxial stack 20 where the mesa 50 needs to be formed is not blocked by the photomask during the first exposure and is blocked by the photomask during the second exposure. Therefore, in step S500, after developing the negative photoresist 30 that has been exposed twice, the part of the negative photoresist 30 corresponding to the area in the epitaxial stack 20 where the mesa 50 needs to be formed will be dissolved and removed by the developer. However, since this part of the negative photoresist has only been exposed for the second time, this part of the negative photoresist will retain a certain thickness;

[0077] The portion of the negative photoresist 30 corresponding to other regions in the epitaxial stack 20 except for the isolation trenches 40 and the mesa 50 is not blocked by the photomask during both the first exposure and the second exposure. Therefore, in step S500, after developing the negative photoresist 30 that has been exposed twice, the portion of the negative photoresist 30 corresponding to other regions in the epitaxial stack 20 except for the isolation trenches 40 and the mesa 50 is insoluble in the developer and remains at the original thickness of the negative photoresist.

[0078] To better understand the present application, Figure 5 a schematic diagram of the development after only the first exposure of the negative photoresist 30 is given. From Figure 5 it can be seen that the exposure thickness after only the first exposure and development of the negative photoresist 30 is the first exposure thickness T1. It should be noted that Figure 5 it is only for showing the exposure thickness of the first exposure in the negative photoresist 30. In the method for manufacturing an LED chip provided by the embodiment of the present application, after the first exposure, the negative photoresist 30 is not developed, but developed after two exposures.

[0079] Figure 6 A schematic diagram of the development after the first exposure and the second exposure of the negative photoresist 30 is given. From Figure 6 it can be seen that the exposure thickness after only the second exposure of the negative photoresist 30 is the second exposure thickness T2, and the exposure thickness after the first exposure and the second exposure of the negative photoresist 30 is the third exposure thickness T3. T3>T1 and T3>T2. The third exposure thickness T3 can be the thickness of the negative photoresist 30. Among them, the portion of the negative photoresist 30 with the third exposure thickness T3 corresponds to the isolation trench 40, and the width of this portion corresponds to the line width W of the isolation trench 40 DE , and the portion of the negative photoresist 30 with the second exposure thickness T2 corresponds to the mesa 50, and the width of this portion corresponds to the line width W of the mesa 50 MESA .

[0080] From the above analysis, it can be known that Figure 6 the white region in corresponds to a part of the photoresist pattern in the negative photoresist 30. In step S600, when etching the epitaxial stack 20 with the negative photoresist having the photoresist pattern as a mask, the photoresist pattern is copied into the epitaxial stack 20 to obtain the device structures in FIGS. 2(c) and 2(d).

[0081] It can be seen that when preparing an LED chip according to the prior art, two-step lithography and two ICP etchings are required to complete mesa etching and deep etching, with a complex process and high manufacturing cost. In the method for preparing an LED chip provided by the embodiment of the present application, first, a negative photoresist is spin-coated on the surface of the epitaxial stack away from the substrate, then the negative photoresist is first exposed using a first photomask, and then the negative photoresist is secondarily exposed using a second photomask. After that, the negatively photoresisted film after the two exposures is developed to form a photoresist pattern. Using the negatively photoresisted film with the photoresist pattern as a mask, the epitaxial stack is etched to form isolation channels. The isolation channels penetrate the epitaxial stack until the surface of the substrate, so as to divide the epitaxial stack into multiple sub-epitaxial stacks, and a mesa is formed in the sub-epitaxial stack. The exposed part of the mesa is the first-type semiconductor layer. One sub-epitaxial stack corresponds to one LED chip. That is, the method for preparing an LED chip provided by the embodiment of the present application only requires spin-coating the negative photoresist once, performing two exposures, and completing mesa etching and deep etching through one etching. The process is simple and the manufacturing cost is low.

[0082] It should be noted that in the direction perpendicular to the plane where the substrate 10 is located, the thickness of the negative photoresist 30 needs to be greater than the thickness of the epitaxial stack 20, so that the negative photoresist 30 can be used as a mask plate to etch the epitaxial stack 20. Optionally, the thickness of the epitaxial stack 20 is 6 μm - 7 μm, and the thickness of the negative photoresist 30 can be greater than 8 μm.

[0083] The inventors have found through research that when performing mesa etching and deep etching on the epitaxial stack in the prior art, a positive photoresist is used as a mask. However, as the size of the LED chip shrinks, when using a positive photoresist as a mask, due to the relatively thick mask thickness of the positive photoresist and the large exposure energy on the upper surface, severe diffraction occurs, and the morphology of the photoresist changes severely after high-temperature baking. Fig. 7(a) shows the morphology of the positive photoresist when performing deep etching using a positive photoresist as a mask in the prior art. It can be seen that the light and dark are irregularly distributed in Fig. 7(a), indicating that the morphology of the positive photoresist changes severely. After using the positive photoresist with severely changed morphology as a mask to perform deep etching on the epitaxial stack, as shown in Figs. 7(b) and 7(c), Fig. 7(b) is the morphology of the epitaxial stack after deep etching using a positive photoresist as a mask in the prior art, and Fig. 7(c) is the FIB test pattern of the epitaxial stack after deep etching using a positive photoresist as a mask in the prior art. As can be seen from the parts marked by the dashed boxes in Figs. 7(b) and 7(c), the edge effect of the isolation channels formed by deep etching is obvious, the pattern after etching is severely deformed, the isolation channels present arc-shaped irregular lines, and moreover, there is a risk of misregistration between deep etching and mesa etching, resulting in the risk that the isolation channels and the mesa overlap, affecting the performance and appearance of the LED chip.

[0084] Based on this, the inventors continued their research and found that by controlling the exposure amounts during the first exposure and the second exposure, the etched pattern after etching the epitaxial stack can be regularized.

[0085] Optionally, in an embodiment of the present application, the sensitivity of the negative photoresist is E0 mJ / cm 2 , and the exposure amount during the first exposure of the negative photoresist 30 using the first photomask is E1, where 5.4E0 ≤ E1 ≤ 6.6E0.

[0086] It should be noted that the sensitivity of the photoresist refers to the minimum energy value (or minimum exposure amount) of light with a certain wavelength required to produce a good pattern on a 1-μm-thick photoresist.

[0087] Reference Figure 5 and Figure 6 As shown, the exposure amount E1 during the first exposure of the negative photoresist 30 using the first photomask determines the first exposure thickness T1. Based on the first exposure thickness T1, subsequent second exposure and development of the negative photoresist 30 can form the isolation trench pattern and the mesa pattern. Therefore, it is necessary to control the exposure amount during the first exposure so that the first exposure thickness T1 is less than the thickness T3 of the negative photoresist 30.

[0088] Furthermore, as shown in Figure 6 , the first exposure thickness T1 also affects the aspect ratio of the isolation trench formed subsequently. The larger the first exposure thickness T1, the deeper the depth of the isolation trench formed subsequently and the larger the aspect ratio. Therefore, it is necessary to control the exposure amount during the first exposure to form an isolation trench with an appropriate aspect ratio.

[0089] In this embodiment, the exposure amount E1 during the first exposure of the negative photoresist 30 using the first photomask satisfies 5.4E0 ≤ E1 ≤ 6.6E0, such that the ratio of the first exposure thickness T1 to the thickness T3 of the negative photoresist is 2 / 3 - 4 / 5.

[0090] Based on the above embodiment, in an embodiment of the present application, the exposure amount during the second exposure of the negative photoresist 30 using the second photomask is E2, and E2 ≥ 3E1, so that the negative photoresist after two exposures forms an isolation trench pattern and a mesa pattern after development.

[0091] In this embodiment, the exposure amount E2 during the second exposure of the negative photoresist 30 using the second photomask satisfies E2 ≥ 3E0, such that the ratio of the second exposure thickness T2 to the thickness T3 of the negative photoresist is 1 / 5 - 1 / 3.

[0092] Figure 8(a) shows the topographic map of the negative photoresist 30 after the first exposure with an exposure dose of E1 and the second exposure with an exposure dose of E2 in this embodiment. By comparing Figure 7(a) and Figure 8(a), it can be seen that the light and dark distribution in Figure 8(a) is more regular, indicating that the topography of the negative photoresist 30 after the first exposure with an exposure dose of E1 and the second exposure with an exposure dose of E2 in this embodiment is more regular.

[0093] Figure 8(b) shows the topographic map of the etched epitaxial stack using the negative photoresist shown in Figure 8(a) as a mask, and Figure 8(c) shows the FIB test map of the etched epitaxial stack using the negative photoresist shown in Figure 8(a) as a mask. By comparing Figure 7(b) and Figure 8(b) and comparing Figure 7(c) and Figure 8(c), it can be seen that the photoresist pattern formed after the first exposure with an exposure dose of E1 and the second exposure with an exposure dose of E2 of the negative photoresist 30 in this embodiment is more regular, making the isolation channels and mesa patterns formed after etching the epitaxial stack more regular, and avoiding the overlap of the isolation channels and the mesa caused by the deviation between the deep etching and the mesa etching. Moreover, by comparing Figure 7(b) and Figure 8(b), it can be seen that the size of the isolation channels formed after etching the epitaxial stack in this embodiment is narrower, thereby increasing the effective light-emitting area of the LED chip.

[0094] Based on any of the above embodiments, optionally, in an embodiment of the present application, as Figure 9 shown, before developing the negative photoresist 30 after two exposures, the method further includes:

[0095] S510: Bake the negative photoresist 30 after two exposures;

[0096] After developing the negative photoresist 30 after two exposures, the method further includes:

[0097] S520: Harden the developed negative photoresist 30 to crosslink the surface of the negative photoresist after baking, developing, and hardening the negative photoresist after two exposures, so as to achieve the inversion of the photoresist pattern;

[0098] S530: Perform flood exposure on the hardened negative photoresist 30 to shape the negative photoresist and improve the etching resistance of the negative photoresist.

[0099] Optionally, in an embodiment of the present application, the sensitivity of the negative photoresist is E0 mJ / cm 2 , and the exposure dose during the flood exposure of the hardened negative photoresist 30 is E3, and E3 > E0.

[0100] It should be noted that due to the characteristics of the negative photoresist 30, directly developing the negative photoresist 30 after two exposures will result in a positive trapezoidal pattern that is narrow at the top and wide at the bottom. In step 510, the negative photoresist 30 after two exposures is baked, causing thermal crosslinking on the surface of the negative photoresist, and the photoresist pattern is inverted into an inverted trapezoidal pattern that is wide at the top and narrow at the bottom. In step 500, the baked negative photoresist 30 is developed to form a photoresist pattern. In step 520, the developed negative photoresist 30 is post-baked, which is a re-baking of the developed negative photoresist 30 until the negative photoresist 30 is hardened, thereby adjusting the inclination angle of the inclined surface in the inverted trapezoidal pattern. Refer to Figure 6 as shown in Figure 6 In fact, it is the morphology diagram of the negative photoresist 30 after post-baking. It can be seen that the inclination angle of the inclined surface in the isolation trench pattern is close to 90°, so that the angle of the sidewall of the isolation trench formed after subsequent deep etching is relatively large and close to a vertical sidewall. Specifically, reference can be made to Figure 8(c).

[0101] In the above embodiments, when etching the epitaxial stack using the negative photoresist with the photoresist pattern as a mask, one-step ICP etching can be performed to form the isolation trench 40 and the mesa 50, or multi-step ICP etching can be performed to form the isolation trench 40 and the mesa 50, and finally the isolation trench 40 and the mesa 50 are formed through one-step ICP etching.

[0102] Optionally, in an embodiment of the present application, etching the epitaxial stack using the negative photoresist with the photoresist pattern as a mask includes:

[0103] S610: Using the negative photoresist 30 with the photoresist pattern as a mask, performing the first-step etching on the epitaxial stack 20 to form the isolation trench 40. The etching selectivity used in the first-step etching ranges from 0.9 to 1.1, including the endpoint values.

[0104] S620: Using the negative photoresist 30 with the photoresist pattern as a mask, performing the second-step etching on the epitaxial stack 20 to form the mesa 50. The etching selectivity used in the second-step etching ranges from 0.6 to 0.9, including the endpoint values.

[0105] In step S610, in order to increase the angle of the sidewall of the isolation trench formed after deep etching, a relatively large etching selectivity is used. In step S620, in order to reduce the angle of the sidewall of the mesa formed by mesa etching and make the mesa relatively flat, a relatively small etching selectivity is used.

[0106] Since the radio frequency power of the upper electrode, the radio frequency power of the lower electrode, and the gas flow rate of the etching gas all affect the etching selectivity during ICP etching, the etching selectivity can be controlled by adjusting the radio frequency power of the upper electrode, the radio frequency power of the lower electrode, and the gas flow rate of the etching gas.

[0107] Specifically, in an embodiment of the present application, in step S610, when the first etching is performed on the epitaxial stack 20 with the negative photoresist 30 having a photoresist pattern as a mask, the radio frequency power of the upper electrode (SRF Power) is 400W - 800W, the radio frequency power of the lower electrode (BRF Power) is 150W - 300W, and the etching gas includes Cl2 and BCl3. Among them, the ratio of the gas flow rate n(Cl2) of Cl2 to the gas flow rate n(BCl3) of BCl3 satisfies: n(Cl2):n(BCl3) > 10:1. In this embodiment, by increasing the proportion of the gas flow rate of Cl2 in the etching gas, the angle of the sidewall of the isolation channel formed after deep etching is increased.

[0108] In step S620, when the second etching is performed on the epitaxial stack 20 with the negative photoresist 30 having a photoresist pattern as a mask, the radio frequency power of the upper electrode (SRF Power) is 400W - 800W, the radio frequency power of the lower electrode (BRF Power) is 150W - 300W, and the etching gas includes Cl2, BCl3, and O2. Among them, the ratio of the gas flow rate n(Cl2) of Cl2, the gas flow rate n(BCl3) of BCl3, and the gas flow rate n(O2) of O2 satisfies: n(Cl2):n(BCl3):n(O2) = 10:1:2. In this embodiment, by increasing the proportion of the gas flow rate of O2 in the etching gas, the angle of the sidewall of the mesa formed by mesa etching is reduced, making the mesa relatively flat.

[0109] Based on step S600, it is also necessary to form a transparent conductive layer, usually an ITO layer (In2O3 layer), on the surface of the second-type semiconductor layer 23 in the sub-epitaxial stack facing away from the substrate 10, so that the ITO layer forms an ohmic contact with the second-type semiconductor 23. However, the inventor's research found that when the second-type semiconductor layer 23 is a commonly used P-type GaN layer, due to the work function of P-type GaN being 7.5eV and the work function of pure In2O3 being 5.1eV, the work function difference between the two is relatively large, resulting in a poor ohmic contact between the ITO layer and the P-type GaN layer.

[0110] On this basis, the inventor further found that as Figure 10 shown, the work function of ITO gradually increases with the increase of the surface oxygen atom concentration. Therefore, the work function of the ITO layer can be improved by increasing the surface oxygen content of the ITO layer, so that the ITO layer and the P-type GaN layer form a good ohmic contact under high-temperature annealing.

[0111] Optionally, in an embodiment of the present application, as Figure 11 shown, the method further includes:

[0112] S700: As shown in FIG. 2(e), remove the negative photoresist 30, and form a composite transparent conductive layer 60 on the surface of the second-type semiconductor layer 23 in the sub-epitaxial stack facing away from the substrate 10;

[0113] Referring to FIG. 2(e), the formation process of the composite transparent conductive layer 60 includes:

[0114] S710: Form an ITO layer 61 on the surface of the second-type semiconductor layer 23 in the sub-epitaxial stack facing away from the substrate 10.

[0115] Specifically, the ITO layer is prepared by SPUTTER (magnetron sputtering) or RPD (ion reaction coating) process, and the thickness of the ITO layer can be

[0116] S720: Form a nano-gas-sensitive adsorption layer 62 on the surface of the ITO layer 61 facing away from the substrate 10. The nano-gas-sensitive adsorption layer 62 has a porous structure, and the ITO layer 61 and the nano-gas-sensitive adsorption layer 62 form a composite transparent conductive layer 60.

[0117] Specifically, the nano-gas-sensitive adsorption layer 62 is prepared by PECVD (plasma enhanced chemical vapor deposition) or SPUTTER (magnetron sputtering) process. The thickness of the nano-gas-sensitive adsorption layer 62 can be 60 nm - 800 nm, and the deposition temperature can be 150°C - 400°C.

[0118] Optionally, the material of the nano-gas-sensitive adsorption layer includes at least one of SnO2, WO3, CuO, ZrO2, Co3O4, Fe2O3, ZnO, SiO2, ZnSnO3, In2O3, CdSnO3, CdFe2O4, and ZnFe2O4.

[0119] S730: Perform rapid thermal annealing (RTA) in an O2 atmosphere to enable the nano-gas-sensitive adsorption layer 62 to adsorb oxygen ions, increase the oxygen ion concentration on the surface layer of the ITO layer 61 facing away from the substrate 10, thereby increasing the work function of the ITO layer 61 and forming an ohmic contact between the ITO layer 61 and the second-type semiconductor layer 23.

[0120] In this embodiment, the nano-gas-sensitive adsorption layer 62 adsorbs oxygen ions in an oxygen environment, increasing the oxygen ion concentration on the surface layer of the ITO layer 61 facing away from the substrate 10, thereby increasing the work function of the ITO layer 61, reducing the difference between the work function of the ITO layer 61 and the work function of the second-type semiconductor layer 23, and enabling the ITO layer 61 and the second-type semiconductor layer 23 to form a good ohmic contact after high-temperature rapid annealing.

[0121] Optionally, when performing rapid high-temperature annealing in an O2 atmosphere, the gas flow rate of O2 ranges from 0.5 sccm to 4 sccm, including the end values; the annealing temperature ranges from 400 °C to 600 °C, including the end values, so that a good ohmic contact is formed between the ITO layer 61 and the second-type semiconductor layer 23 after rapid high-temperature annealing.

[0122] Based on the above embodiments, in an embodiment of the present application, as Figure 11 shown, the method further includes:

[0123] S800: As shown in FIG. 2(f), a first electrode 70 is formed on the mesa 50, and a second electrode 80 is formed on the surface of the composite transparent conductive layer 60 facing away from the substrate 10, or, the composite transparent conductive layer 60 is etched to form a first through hole penetrating the composite transparent conductive layer 60, and the second electrode 80 is embedded in the composite transparent conductive layer 60 through the first through hole and electrically connected to the second-type semiconductor layer 23.

[0124] Optionally, the electrode structures of the first electrode 70 and the second electrode 80 are one or a combination of metals such as Cr, Ni, Al, Ti, Pt, Au, etc.

[0125] S900: As shown in FIG. 2(g), a reflective layer 90 and an insulating cover layer 100 are sequentially formed on the side of the overall structure composed of the epitaxial stack 20, the composite transparent conductive layer 60, the first electrode 70, and the second electrode 80 facing away from the substrate 10.

[0126] Optionally, the reflective layer 90 is a DBR reflective layer (Bragg reflective layer), and the DBR reflective layer is a periodic structure composed of two materials with different refractive indices arranged alternately in the ABAB manner. Among them, the high refractive index layer can adopt a Ti3O5 layer, and the low refractive index layer can adopt a SiO2 layer. Specifically, when preparing the Ti3O5 layer in the DBR reflective layer, the following process conditions can be adopted: introducing O2 with a gas flow rate of 40 sccm - 60 sccm, preferably using an ion source power of 600 W - 1000 W, a process vacuum of 2.0E -2 Pa to 9.0E - 2 Pa, a coating temperature of 120 °C - 150 °C, and after evaporating each layer of the Ti3O5 layer, bombarding the surface of each layer of the Ti3O5 layer with oxygen ions to fully oxidize the Ti3O5 layer and reduce the film stress of the Ti3O5 layer. When bombarding the surface of each layer of the Ti3O5 layer with oxygen ions, the O2 gas flow rate is 20 - 30 sccm, and the ion source power is 200 - 400 W. By controlling parameters such as the ion energy, vacuum environment, and O2 gas flow rate of the overlapping layer Ti3O5 layer / SiO2 layer, a high / low refractive index DBR reflective layer is prepared.

[0127] After the DBR reflective layer 90, a SiO2 insulating cover layer 100 can be deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition), and the thickness of the insulating cover layer 100 can be

[0128] S1000: As shown in FIG. 2(h), the reflective layer 90 and the insulating cover layer 100 are etched to form a second through hole and a third through hole penetrating through the reflective layer 90 and the insulating cover layer 100. The second through hole exposes the first electrode 70, and the third through hole exposes the second electrode 80.

[0129] Specifically, etching gases such as CF4 / CHF3 are used to etch the reflective layer 90 and the insulating cover layer 100 to form a second through hole and a third through hole penetrating through the reflective layer 90 and the insulating cover layer 100.

[0130] S1100: As shown in FIG. 2(i), a first pad 110 and a second pad 120 are formed. The first pad 110 is electrically connected to the first electrode 70 through the second through hole, and the second pad 120 is electrically connected to the second electrode 80 through the third through hole.

[0131] Optionally, the metal structures of the first pad 110 and the second pad 120 are one or a combination of metals such as Cr, Ni, Al, Ti, Pt, Au, etc.

[0132] In summary, for the LED chip preparation method provided by the embodiments of the present application, first, a negative photoresist is spin-coated on the surface of the epitaxial stack away from the substrate, then the negative photoresist is first exposed using a first photomask, and then the negative photoresist is second exposed using a second photomask. After that, the negative photoresist after the two exposures is developed to form a photoresist pattern. Using the negative photoresist with the photoresist pattern as a mask, the epitaxial stack is etched to form isolation channels. The isolation channels penetrate through the epitaxial stack until the substrate surface to separate the epitaxial stack into multiple sub-epitaxial stacks, and a mesa is formed in the sub-epitaxial stack. The mesa exposes a part of the first-type semiconductor layer. One sub-epitaxial stack corresponds to one LED chip. That is, for the LED chip preparation method provided by the embodiments of the present application, only one spin-coating of negative glue, two exposures, and one etching are required to complete mesa etching and deep etching. The process is simple and the manufacturing cost is relatively low.

[0133] Furthermore, by reasonably designing the exposure amounts during the first exposure and the second exposure, the patterns of the mesa and the isolation channels are regular, avoiding the overlap of the isolation channels and the mesa caused by the misalignment between the deep etching and the mesa etching. Moreover, the deep etching angle is relatively large, and the size of the formed isolation channels is relatively small, thereby increasing the effective light-emitting area of the LED chip.

[0134] Furthermore, a composite transparent conductive layer including an ITO layer and a nano gas-sensitive adsorption layer is prepared on the epitaxial stack. By adsorbing oxygen ions in an oxygen environment through the nano gas-sensitive adsorption layer, the oxygen ion concentration on the surface layer of the ITO layer facing away from the substrate is increased, thereby increasing the work function of the ITO layer and reducing the difference in work function between the ITO layer and the second-type semiconductor layer in the epitaxial stack, so that a good ohmic contact is formed between the ITO layer and the second-type semiconductor layer after high-temperature rapid annealing.

[0135] In this specification, each part is described in a combined manner of parallelism and progression. The key point of each part is to illustrate the differences from other parts. For the same or similar parts among each part, reference can be made to each other.

[0136] Regarding the above description of the disclosed embodiments, the features recorded in each embodiment in this specification can be replaced or combined with each other, enabling those skilled in the art to implement or use this application. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for preparing an LED chip, characterized in that, Including: Providing a substrate, forming an epitaxial stack on the substrate, the epitaxial stack including a first-type semiconductor layer, an active layer, and a second-type semiconductor layer arranged in sequence in a direction away from the substrate; Spin-coating a negative photoresist on a surface of the epitaxial stack away from the substrate; Performing a first exposure on the negative photoresist using a first photomask, the first photomask covering an area of the epitaxial stack where an isolation channel needs to be formed; Performing a second exposure on the negative photoresist using a second photomask, the second photomask covering an area of the epitaxial stack where an isolation channel and a mesa need to be formed; Developing the negative photoresist after two exposures to form a photoresist pattern; Using the negative photoresist with the photoresist pattern as a mask to etch the epitaxial stack to form the isolation channel, the isolation channel penetrating the epitaxial stack until the substrate surface to divide the epitaxial stack into multiple sub-epitaxial stacks, and forming the mesa in the sub-epitaxial stacks, the mesa exposing a part of the first-type semiconductor layer, and one sub-epitaxial stack corresponding to one LED chip; The method further includes: Removing the negative photoresist and forming a composite transparent conductive layer on a surface of the second-type semiconductor layer in the sub-epitaxial stack away from the substrate; The formation process of the composite transparent conductive layer includes: Forming an ITO layer on a surface of the second-type semiconductor layer in the sub-epitaxial stack away from the substrate; Forming a nano-gas-sensitive adsorption layer on a surface of the ITO layer away from the substrate, the nano-gas-sensitive adsorption layer having a porous structure, and the ITO layer and the nano-gas-sensitive adsorption layer constituting the composite transparent conductive layer; Performing rapid thermal annealing in an O2 atmosphere to enable the nano-gas-sensitive adsorption layer to adsorb oxygen ions, increasing the oxygen ion concentration on a surface layer of the ITO layer away from the substrate, thereby increasing the work function of the ITO layer and enabling the ITO layer and the second-type semiconductor layer to form an ohmic contact.

2. The preparation method according to claim 1, characterized in that, In a direction perpendicular to the plane of the substrate, the thickness of the negative photoresist is greater than the thickness of the epitaxial stack; The sensitivity of the negative photoresist is E0 mJ / cm 2 , and the exposure dose when the negative photoresist is first exposed using the first photomask is E1, where 5.4E0 ≤ E1 ≤ 6.6E0.

3. The preparation method according to claim 2, characterized in that, The exposure dose during the second exposure of the negative photoresist using the second photomask is E2, and E2 ≥ 3E0.

4. The preparation method according to claim 1, characterized in that, Before developing the negative photoresist after two exposures, the method further includes: Baking the negative photoresist after two exposures; After developing the negative photoresist after two exposures, the method further includes: Hardening the developed negative photoresist, so that after baking, developing, and hardening the negative photoresist after two exposures, the surface of the negative photoresist cross-links to achieve inversion of the photoresist pattern; Performing flood exposure on the hardened negative photoresist to shape the negative photoresist and improve the etching resistance of the negative photoresist.

5. The preparation method according to claim 4, characterized in that, The sensitivity of the negative photoresist is E0 mJ / cm 2 , and the exposure dose during flood exposure of the negative photoresist after hard baking is E3, where E3 > E0.

6. The preparation method according to claim 1, characterized in that, Using the negative photoresist with the photoresist pattern as a mask to etch the epitaxial stack includes: Using the negative photoresist with the photoresist pattern as a mask to perform a first-step etching on the epitaxial stack to form the isolation channel, and the etching selectivity used in the first-step etching ranges from 0.9 to 1.1, including the endpoint values; Using a negative photoresist with a photoresist pattern as a mask, perform a second etching on the epitaxial stack to form the mesa. The etching selectivity used in the second etching ranges from 0.6 to 0.9, including the endpoint values.

7. The preparation method according to claim 1, characterized in that, The material of the nano gas-sensitive adsorption layer includes at least one of SnO2, WO3, CuO, ZrO2, Co3O4, Fe2O3, ZnO, SiO2, ZnSnO3, In2O3, CdSnO3, CdFe2O4, and ZnFe2O4.

8. The preparation method according to claim 1, characterized in that, When performing rapid thermal annealing in an O2 atmosphere, the gas flow rate of O2 ranges from 0.5 sccm to 4 sccm, including the endpoint values; the annealing temperature ranges from 400 °C to 600 °C, including the endpoint values.

9. The preparation method according to claim 1, characterized in that, This method further includes: Form a first electrode on the mesa and form a second electrode on the surface of the composite transparent conductive layer facing away from the substrate, or etch the composite transparent conductive layer to form a first through hole penetrating the composite transparent conductive layer, and the second electrode is embedded in the composite transparent conductive layer through the first through hole and electrically connected to the second-type semiconductor layer; Form a reflective layer and an insulating cover layer in sequence on the side of the overall structure composed of the epitaxial stack, the composite transparent conductive layer, the first electrode, and the second electrode facing away from the substrate; Etch the reflective layer and the insulating cover layer to form a second through hole and a third through hole penetrating the reflective layer and the insulating cover layer. The second through hole exposes the first electrode, and the third through hole exposes the second electrode; Form a first pad and a second pad. The first pad is electrically connected to the first electrode through the second through hole, and the second pad is electrically connected to the second electrode through the third through hole.

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