Capacitor structure and method of manufacturing the same

Abstract

A capacitor structure and method of manufacturing the same forms a first layer capacitor assembly including a first alternating layer stack embedded within a first substrate and including at least two first metal electrode layers interleaved with at least one first node dielectric layer and a first metal bonding pad on a first front surface. A second layer capacitor assembly is formed including a second alternating layer stack embedded within a second substrate and including at least two second metal electrode layers interleaved with at least one second node dielectric layer and a second metal bonding pad on a second backside surface. The second metal bonding pad is bonded to the first metal bonding pad such that each of the at least two first metal electrode layers contacts a respective one of the at least two second metal electrode layers. A capacitor having an increased capacitance is provided.

Description

Technical Field

[0001] This disclosure relates to the structure of capacitors and their manufacturing methods. Background Technology

[0002] Capacitors are used in semiconductor wafers for many applications, such as power supply stabilization. However, a considerable amount of device area is often used in the manufacture of such capacitors. Therefore, capacitors that offer high capacitance while having a small device footprint are desirable. Summary of the Invention

[0003] According to various embodiments of the present disclosure, a capacitor structure is provided, the capacitor structure comprising: a first layer capacitor assembly comprising: a first substrate having a first front surface and a first back surface parallel to each other; a first alternating layer stack embedded within the first substrate and including at least two first metal electrode layers interleaved with at least one first node dielectric layer; and a first metal bonding pad located on the first front surface; and a second layer capacitor assembly comprising: a second substrate having a second front surface and a second back surface parallel to each other; a second alternating layer stack embedded within the second substrate and including at least two second metal electrode layers interleaved with at least one second node dielectric layer; and second metal bonding pads located on the second back surface and bonded to the first metal bonding pad; wherein each of the at least two first metal electrode layers contacts a corresponding second metal electrode layer of the at least two second metal electrode layers.

[0004] According to various embodiments of this disclosure, a capacitor structure is provided, the capacitor structure comprising: a first capacitor assembly comprising: a first substrate having a first front surface and a first back surface parallel to each other; and a first alternating layer stack embedded within the first substrate and including at least two first metal electrode layers interleaved with at least one first node dielectric layer, wherein one of the at least two first metal electrode layers includes a lug extending parallel to the first front surface; a second capacitor assembly comprising: a second substrate having a second front surface and a second back surface parallel to each other; and a second alternating layer stack embedded within the second substrate and including at least two second metal electrode layers interleaved with at least one second node dielectric layer; and a contact via structure extending vertically through the second substrate and contacting the top surface of the lug portion of the at least two first metal electrode layers.

[0005] According to various embodiments of this disclosure, a method of manufacturing a capacitor structure includes: forming a first capacitor assembly comprising: a first substrate having a first front surface and a first back surface parallel to each other; a first alternating layer stack embedded within the first substrate and including at least two first metal electrode layers interleaved with at least one first node dielectric layer; and a first metal bonding pad located on the first front surface. Forming a second capacitor assembly comprising: a second substrate having a second front surface and a second back surface parallel to each other; a second alternating layer stack embedded within the second substrate and including at least two second metal electrode layers interleaved with at least one second node dielectric layer; and a second metal bonding pad located on the second back surface. The second metal bonding pad is bonded to the first metal bonding pad. Each of the at least two first metal electrode layers contacts a corresponding second metal electrode layer of the at least two second metal electrode layers. Attached Figure Description

[0006] The features disclosed herein will be best understood from the following detailed description when read in conjunction with the accompanying drawings. Please note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 This is a vertical cross-sectional view of a region of a first exemplary structure after a deep trench has been formed in a first substrate according to an embodiment of the present disclosure;

[0008] Figure 2 This is a vertical cross-sectional view of a region of a first exemplary structure formed after alternating layer stacking according to an embodiment of the present disclosure, the alternating layer stacking including at least two first metal electrode layers interleaved with at least one first node dielectric layer;

[0009] Figure 3 This is a vertical cross-sectional view of a region of a first exemplary structure after the formation of a plurality of pad cavities, a dielectric liner layer and at least one metal filler layer, according to an embodiment of the present disclosure.

[0010] Figure 4 This is a vertical cross-sectional view of a region of a first exemplary structure after a planarization process for forming a first layer capacitor assembly and a plurality of first front metal bonding pads, according to an embodiment of the present disclosure.

[0011] Figure 5 A vertical cross-sectional view of a region of a second-layer capacitor assembly and a plurality of second back-side metal bonding pads according to an embodiment of the present disclosure;

[0012] Figure 6 This is a vertical cross-sectional view of a region of a first exemplary structure after the second substrate has been bonded to the first substrate, according to an embodiment of the present disclosure.

[0013] Figure 7 This is a vertical cross-sectional view of a region of a first exemplary structure after the second substrate has been thinned, according to an embodiment of the present disclosure.

[0014] Figure 8A This is a vertical cross-sectional view of a region of a first exemplary structure after the formation of an interconnect dielectric layer and a plurality of contact via structures, according to an embodiment of the present disclosure.

[0015] Figure 8B For along Figure 8A A horizontal cross-sectional view of a region of the first exemplary structure in the horizontal plane B–B';

[0016] Figure 9 This is a vertical cross-sectional view of a region of an alternative configuration of a first exemplary structure after the formation of a plurality of second front metal bonding pads, according to an alternative embodiment of the present disclosure.

[0017] Figure 10 This is a vertical cross-sectional view of a region of an alternative configuration of a first exemplary structure after the formation of an interconnect dielectric layer and a plurality of contact via structures, according to an alternative embodiment of the present disclosure.

[0018] Figure 11A This is a vertical cross-sectional view of a region of a second exemplary structure after the formation of a plurality of deep grooves and at least one lug recess region according to an embodiment of the present disclosure;

[0019] Figure 11B For along Figure 11A A horizontal cross-sectional view of a region of the second exemplary structure in the horizontal plane B–B';

[0020] Figure 12 This is a vertical cross-sectional view of a second exemplary structure formed after alternating layer stacking according to an embodiment of the present disclosure. The alternating layer stacking includes at least two first metal electrode layers interleaved with at least one first node dielectric layer and a plurality of first front metal bonding pads.

[0021] Figure 13 This is a vertical cross-sectional view of a second exemplary structure after the formation of a second layer capacitor assembly including a second substrate, according to an embodiment of the present disclosure;

[0022] Figure 14 This is a vertical cross-sectional view of a second exemplary structure after the formation of a third layer capacitor assembly including a third substrate, according to an alternative embodiment of the present disclosure.

[0023] Figure 15 This is a vertical cross-sectional view of a second exemplary structure following the formation of an interconnect dielectric layer and a plurality of contact via structures, according to an alternative embodiment of the present disclosure.

[0024] Figure 16 This is a vertical cross-sectional view of an exemplary wafer assembly according to an embodiment of the present disclosure, which also has semiconductor dies containing deep trench capacitors.

[0025] Figure 17 A flowchart illustrating the general processing steps of the method disclosed herein.

[0026] [Symbol Explanation]

[0027] 6,32,106,132,206,232,332: Dielectric lining

[0028] 8:Substrate

[0029] 9: Deep trench

[0030] 9T: Protruding ear recessed area

[0031] 10A, 10B, 20A, 20B: Metal electrode layers

[0032] 15: Node dielectric layer

[0033] 30: First alternating layer stacking

[0034] 32L: Dielectric liner layer

[0035] 32: Dielectric lining

[0036] 33L: Metal filler layer / metal nitride layer

[0037] 33: Metal bonding pad / metal nitride liner

[0038] 34L: Metal filler layer / metal layer

[0039] 34: Metal bonding pad / metal part

[0040] 36,136,236,336: Electrically isolated bonding pad assemblies

[0041] 62: Etching to terminate the dielectric layer

[0042] 70: Interconnect-level dielectric layer

[0043] 80A, 80B: Metal interconnect structure / contact via structure

[0044] 90A, 90B: Metal interconnect structure / metal bonding pad

[0045] 82: Cylindrical dielectric spacer

[0046] 100: First layer capacitor assembly

[0047] 101: Front surface

[0048] 102: Backside surface

[0049] 108:Substrate

[0050] 110A, 110B, 120A, 120B: Metal electrode layers

[0051] 115: Node dielectric layer

[0052] 130: Second alternating layer stacking

[0053] 133: Metal bonding pad / metal nitride liner

[0054] 134: Metal bonding pad / metal part

[0055] 200: Second layer capacitor assembly

[0056] 201: Front surface

[0057] 202: Backside surface

[0058] 208:Substrate

[0059] 210A, 210B, 220A, 220B: Metal electrode layers

[0060] 215: Node dielectric layer

[0061] 230: Third alternating layer stacking

[0062] 233: Metal bonding pad / metal nitride liner

[0063] 234: Metal bonding pad / metal part

[0064] 300: Third-layer capacitor assembly

[0065] 301: Front surface

[0066] 302: Backside surface

[0067] 333: Metal bonding pad / metal nitride liner

[0068] 334: Metal bonding pad / metal part

[0069] 1000: Grain size

[0070] 1500, 2500: Solder balls

[0071] 1710, 1720, 1730: Steps

[0072] 2000: Grain

[0073] 3000: Integrated Fan-Out PoP Package (InFO PoP) Die

[0074] B-B': Horizontal plane Detailed Implementation

[0075] The following disclosure provides numerous different embodiments or instances for implementing the provided signature features. Specific examples of components and configurations will be described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the first feature formed above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0076] Furthermore, for the convenience of describing the relationship between one element or feature as illustrated in the figures and another element or feature, spatially related terms such as "below," "under," "lower," "above," "upper," and similar terms are used herein. Spatially related terms are intended to cover different orientations of elements during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted similarly.

[0077] This disclosure relates to semiconductor devices, and more specifically, to multilayer deep trench capacitors and methods for forming the same. Large-capacitance capacitors are required in the power supply circuitry of semiconductor chips. A capacitor chip including a deep trench capacitor can be attached to a semiconductor chip to provide a large-capacitance capacitor that will be incorporated into the power supply circuitry of the semiconductor chip. Typically, the lateral dimension of the capacitor chip is smaller than the lateral dimension of the semiconductor chip, and therefore, the capacitance of the deep trench capacitor in the capacitor chip is limited. This disclosure provides a multilayer deep trench structure in which multiple capacitor assemblies can be stacked on top of each other to provide a capacitor structure with large capacitance. Various aspects of this disclosure will now be described with reference to the various accompanying drawings.

[0078] refer to Figure 1The illustration shows a first exemplary structure according to an embodiment of the present disclosure, the first exemplary structure comprising a first substrate 8 having a flat top surface. The first substrate 8 may be a semiconductor substrate comprising a semiconductor material and may have a thickness of at least 10 micrometers. The first substrate 8 may have a front surface and a back surface. The front surface of the first substrate 8 is referred to herein as a first front surface 101, and the back surface of the first substrate 8 is referred to herein as a first back surface 102. The first front surface 101 may be perpendicular to the first back surface 102. In one embodiment, the first substrate 8 may comprise a commercially available semiconductor wafer that may be diced into semiconductor dies after a first deep trench is formed. For example, the first substrate 8 may comprise a semiconductor substrate comprising monocrystalline silicon and having a thickness in the range of 500 micrometers to 1,500 micrometers.

[0079] A first deep trench 9 extending vertically into the first substrate 8 can be formed by forming a patterned etch mask layer on the front surface of the first substrate 8. The pattern in the patterned etch mask layer can be transferred to the upper portion of the first substrate 8. Prior to the formation of the patterned etch mask layer, an optional pad dielectric layer (not shown), such as a silicon oxide pad layer, can be formed on the front surface (i.e., the top surface) of the first substrate 8. In an exemplary embodiment, the pad dielectric layer may comprise a silicon oxide layer with a thickness ranging from 20 nm to 100 nm, although thinner or thicker pad dielectric layers may be used.

[0080] The patterned etch mask layer may comprise a silicon nitride layer or a borosilicate glass (BSG) layer with a thickness ranging from 200 nm to 600 nm, although different materials and / or smaller or larger thicknesses may also be used for the optional pad dielectric layer and the patterned etch mask layer. The patterned etch mask layer can be constructed by depositing a blanket etch mask layer, forming a photoresist layer with a photolithography pattern on top of the blanket etch mask layer, and transferring the pattern from the photoresist layer into the blanket etch mask layer using an anisotropic etching process such as reactive ion etching.

[0081] An anisotropic etching process can be performed to transfer a patterned pattern in the etch mask layer onto the upper portion of the first substrate 8 to form a first deep trench 9. For example, a reactive ion etching process using a combination of gases including HBr, NF3, O2, and SF6 can be used to form the first deep trench 9. The depth of the first deep trench 9 can range from 2 micrometers to 20 micrometers (e.g., 3 micrometers to 10 micrometers). The horizontal cross-sectional shape of each first deep trench 9 can have the following shapes: circular, elliptical, rectangular, rounded rectangle, annular with various shapes of inner and outer peripheries, or any two-dimensional shape defining a closed volume. Generally, at least one first deep trench 9 extending downward from the top surface of the first substrate 8 can be formed in the first substrate 8. At least one first deep trench 9 can contain a plurality of first deep trenches 9 with a depth greater than 2 micrometers.

[0082] Generally, at least one first deep trench 9 may be formed extending perpendicularly from the first front surface 101 toward the first back surface 102. In one embodiment, at least one first deep trench 9 may be a plurality of deep trenches 9. The total number of deep trenches 9 may be, for example, in the range of 1 to 1,000,000 (such as 1,000 to 10,000), although smaller or larger numbers may also be used.

[0083] In one embodiment, each of the first deep trenches 9 may extend laterally with a uniform width. The dominant portion of each first deep trench 9 (such as greater than 50% of the entire area) may have a width sufficient to accommodate vertical extensions of all subsequently formed metal electrode layers and at least one first node dielectric layer. For example, the dominant portion of each first deep trench 9 may have a width sufficient to accommodate vertical extensions of at least two first metal electrode layers and at least one first node dielectric layer. In an illustrative example, the dominant portion of each first deep trench 9 may have a width in the range of 40 nm to 4,000 nm (such as 200 nm to 800 nm), although smaller and larger widths may also be used.

[0084] The photoresist layer may be removed prior to the anisotropic etching process forming the first deep trench 9, or may be consumed during the anisotropic etching process forming the first deep trench 9. The patterned etch mask layer and the optional dielectric pad layer may subsequently be removed, for example, by a corresponding isotropic etching process such as a wet etching process.

[0085] refer to Figure 2The dielectric liner 6 may be formed on the solid exposed surface of the first substrate 8, including the top surface of the first substrate 8, and on the sidewalls of the first deep trench 9. The dielectric liner 6 may include a dielectric material that provides electrical isolation between the first deep trench capacitor, which will subsequently be formed, and the first substrate 8. For example, the dielectric liner 6 may include silicon oxide, silicon nitride, silicon oxynitride, and / or a dielectric metal oxide. Other suitable materials within the scope of this disclosure may also be used. In an illustrative example, the dielectric liner 6 may include a silicon oxide layer formed by thermal oxidation of multiple surface portions of the first substrate 8, including silicon. The thickness of the dielectric liner 6 may range from 4 nm to 100 nm, although smaller and larger thicknesses may also be used.

[0086] The first alternating layer stack 30 of the first metal electrode layers (10A, 20A, 10B, 20B) and the node dielectric layer 15 can be formed by a corresponding conformal deposition process. The first alternating layer stack 30 includes at least two first metal electrode layers (10A, 20A, 10B, 20B), which are interleaved with at least one first node dielectric layer 15 and extend continuously above the top surface of the first substrate 8 and into each of at least one first deep trench 9. The first alternating layer stack 30 extends continuously into each first deep trench 9, and a cavity exists in the unfilled volume of each first deep trench 9. Generally, at least two first metal electrode layers (10A, 20A, 10B, 20B) and at least one first node dielectric layer 15 can be deposited by a corresponding conformal deposition process.

[0087] Each of the first metal electrode layers (10A, 20A, 10B, 20B) may include a metallic material, which may comprise a conductive metal nitride, an elemental metal, or an intermetallic alloy, and / or be substantially composed of a conductive metal nitride, an elemental metal, or an intermetallic alloy. In one embodiment, each first metal electrode layer (10A, 20A, 10B, 20B) comprises a conductive metal nitride material, and / or is substantially composed of a conductive metal nitride material, which may be a metal diffusion barrier material. For example, each first metal electrode layer (10A, 20A, 10B, 20B) may include a conductive metal nitride material such as TiN, TaN, or WN, and / or may be substantially composed of such a conductive metal nitride material. Other suitable materials within the intended scope of the disclosure may also be used.

[0088] Using a metal diffusion barrier material for the first metal electrode layers (10A, 20A, 10B, 20B) is advantageous because metal element diffusion through the node dielectric layer 15 and / or through the dielectric liner 6 can lead to a poisoning effect in deep trench capacitors. Each first metal electrode layer (10A, 20A, 10B, 20B) can be formed by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of each first metal electrode layer (10A, 20A, 10B, 20B) can range from 5 nm to 1,000 nm (e.g., 20 nm to 300 nm), although smaller and larger thicknesses are also possible. In one embodiment, each first metal electrode layer (10A, 20A, 10B, 20B) may have the same material composition and the same thickness. In another embodiment, each first metal electrode layer (10A, 20A, 10B, 20B) may have the same material composition but varying thicknesses. In yet another embodiment, each first metal electrode layer (10A, 20A, 10B, 20B) may have different material compositions and the same thickness. In yet another embodiment, each first metal electrode layer (10A, 20A, 10B, 20B) may have different material compositions and different thicknesses.

[0089] Each of the node dielectric layers 15 may include a node dielectric material, which may be a dielectric metal oxide material with a dielectric constant greater than 7.9 (the dielectric constant of silicon nitride), i.e., a "high-k" dielectric metal oxide material, or may include silicon nitride. For example, the node dielectric layer 15 may include dielectric metal oxide materials such as alumina, aluminum silicon oxide, hafnium oxide, hafnium silicon oxide, zirconium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, hafnium titanium oxide, titanium oxide, tantalum oxide, tantalum silicon oxide, lanthanum oxide, lanthanum silicon oxide, strontium titanium oxide (STO), barium titanium oxide (BTO), barium strontium titanium oxide (BSTO), barium zirconium oxide, hafnium lanthanum oxide, alloys or silicates of the foregoing, and / or stacks of the foregoing. In one embodiment, the node dielectric layer 15 may include an amorphous alumina layer, which may be annealed into a polycrystalline alumina material after the contact via structure is formed. Other suitable materials within the scope of the disclosure may also be used.

[0090] Each node dielectric layer 15 can be formed using a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of each node dielectric layer 15 can range from 1 nm to 30 nm (e.g., 3 nm to 15 nm), although smaller and larger thicknesses are also possible. In one embodiment, each node dielectric layer 15 may have the same material composition and the same thickness. In another embodiment, each node dielectric layer 15 may have the same material composition but with varying thicknesses. In yet another embodiment, each node dielectric layer 15 may have different material compositions and the same thickness. In yet another embodiment, each node dielectric layer 15 may have different material compositions and different thicknesses. For example, in one embodiment, a first node dielectric layer 15 may be thinner than a second node dielectric layer 15. The ratio of the thickness of the first metal electrode layer (10A, 20A, 10B, 20B) to the thickness of the first node dielectric layer 15 can be in the range of 3 to 100 (such as 6 to 50 and / or 10 to 30), although smaller and larger ratios may also be used.

[0091] The lower limit of the thickness of each first metal electrode layer (10A, 20A, 10B, 20B) is determined by the resistance of the first metal electrode layer (10A, 20A, 10B, 20B). For example, in an embodiment where the first metal electrode layers (10A, 20A, 10B, 20B) comprise titanium nitride, the lower limit of the thickness of the node dielectric layer 15 may be approximately 3.8 nm. Different dielectric materials of the node dielectric layer 15 can provide different lower limits for the thickness of the node dielectric layer 15. The upper limit of the thickness of each node dielectric layer 15 is determined by the decrease in capacitance in the deep trench capacitor. Generally, the capacitance of the deep trench capacitor is inversely proportional to the thickness of the node dielectric layer 15. Therefore, in the absence of excessive leakage current, it is generally desirable to provide a smaller thickness of the node dielectric layer 15. In the case where the node dielectric layer 15 comprises silicon nitride, it is desirable to limit the thickness of the node dielectric layer 15 to less than 12 nm (such as less than 9 nm and / or less than 6 nm).

[0092] The lower limit of the thickness of each node dielectric layer 15 is determined by the region leakage current density. For example, when the node dielectric layer 15 includes thermally applied silicon nitride, the lower limit of the thickness of the first metal electrode layers (10A, 20A, 10B, 20B) can be approximately 24 nm. Different conductive materials of the first metal electrode layers (10A, 20A, 10B, 20B) can provide different lower limits for the thickness of the first metal electrode layers (10A, 20A, 10B, 20B). The upper limit of the thickness of each first metal electrode layer (10A, 20A, 10B, 20B) is determined by the lateral dimension in the deep trench capacitor. Generally, the greater the thickness of each first metal electrode layer (10A, 20A, 10B, 20B), the larger the lateral dimension of each deep trench capacitor, and therefore, the smaller the total capacitance per unit area. Therefore, in deep trench capacitors where there is no resistivity-limited performance issue, it is generally desirable to provide a low thickness of the first metal electrode layer (10A, 20A, 10B, 20B). In embodiments where the first metal electrode layer (10A, 20A, 10B, 20B) comprises titanium nitride, it is desirable to limit the thickness of the first metal electrode layer (10A, 20A, 10B, 20B) to less than 400 nm (such as less than 200 nm and / or less than 100 nm and / or less than 50 nm).

[0093] In one illustrative example, the node dielectric layer 15 may have a thickness ranging from 4 nm to 8 nm, and the first metal electrode layers (10A, 20A, 10B, 20B) may have a thickness ranging from 48 nm to 200 nm. In these embodiments, the ratio of the thickness of the first metal electrode layers (10A, 20A, 10B, 20B) to the thickness of the first node dielectric layer 15 may be in the range of 6 to 50, although smaller and larger ratios may also be used.

[0094] In one embodiment, at least two first metal electrode layers (10A, 10B, 20A, 20B) comprise at least three first metal electrode layers (10A, 10B, 20A, 20B), and at least one first node dielectric layer 15 comprises at least two first node dielectric layers 15. The total number of first metal electrode layers (10A, 20A, 10B, 20B) may be in the range of 3 to 16 (such as 4 to 8). The total number of node dielectric layers 15 may be one less than the total number of first metal electrode layers (10A, 20A, 10B, 20B).

[0095] Although this disclosure is described using an embodiment of a first alternating layer stack 30 comprising four first metal electrode layers (10A, 20A, 10B, 20B) and three node dielectric layers 15, embodiments in which different numbers of first metal electrode layers (10A, 20A, 10B, 20B) and different numbers of node dielectric layers 15 may be used within the first alternating layer stack 30 are explicitly contemplated herein. Generally, the first alternating layer stack 30 may include at least two first metal electrode layers (10A, 20A, 10B, 20B) interleaved with at least one first node dielectric layer 15, these layers being formed in and over at least one first deep trench 9 formed in the first substrate 8.

[0096] The first metal electrode layers (10A, 20A, 10B, 20B) may be numbered sequentially according to the deposition order. For example, the first metal electrode layers (10A, 10B, 20A, 20B) may include a first primary metal electrode layer 10A, a first secondary metal electrode layer 20A, a second primary metal electrode layer 10B, a second secondary metal electrode layer 20B, etc. The patterned portion of each primary metal electrode layer (10A, 10B) may then be used to form a primary electrode assembly serving as a primary node (i.e., a first node) of a deep trench capacitor, and the patterned portion of each secondary metal electrode layer (20A, 20B) may then be used to form a supplementary electrode assembly serving as a supplementary node (i.e., a second node) of a deep trench capacitor. The total number of first metal electrode layers (10A, 20A, 10B, 20B), the thickness of the first metal electrode layers (10A, 20A, 10B, 20B), and the width of the first deep trench 9 can be selected such that a dominant portion (i.e., greater than 50%) or all of the entire volume of each first deep trench 9 can be filled with the first alternating layer stack 30, rather than completely filling the first deep trench 9. In embodiments where any voids exist in the first deep trench 9, a dielectric filling material layer (not shown) can be deposited to fill or partially fill the remaining voids in the first deep trench 9.

[0097] refer to Figure 3 A photoresist layer (not shown) may be coated over the first exemplary structure and may be photolithographically patterned to form openings in areas not covered by the first deep trench 9. Each opening may have a pad shape and may have lateral dimensions in the range of 500 nm to 100 micrometers (such as 1 micrometer to 30 micrometers), although smaller and larger lateral dimensions may also be used.

[0098] An anisotropic etching process can be performed to transfer the pattern of the openings in the photoresist layer to a horizontal extension of the first alternating layer stack 30 and an upper portion of the first substrate 8. Pad cavities can be formed extending into the upper portion of the first substrate 8. Subsequently, the photoresist layer can be removed, for example, by ashing. The pad cavities can have a rectangular, circular, or rounded rectangular horizontal cross-sectional shape.

[0099] The dielectric liner layer 32L can be conformally deposited in the pad cavities and over the horizontal extension of the first alternating layer stack 30. The dielectric liner layer 32L comprises a dielectric material such as silicon oxide and can have a thickness in the range of 20 nm to 600 nm, although smaller and larger thicknesses are also possible.

[0100] At least one metal filler layer (33L, 34L) may be deposited over the dielectric liner layer 32L. The at least one metal filler layer (33L, 34L) may include a metal nitride layer 33L and a metal layer 34L. The metal nitride layer 33L may include a conductive metal nitride material such as TiN, TaN, and / or WN, and may have a thickness in the range of 5 nm to 100 nm, although different materials and / or smaller or larger thicknesses may also be used for the metal nitride layer. The metal layer 34L may include a low resistivity metal material, which may be an elemental metal (such as Cu) or an intermetallic alloy material that can be bonded to another metal material via metal-to-metal bonding.

[0101] refer to Figure 4A planarization process can be performed to freely remove material portions above a horizontal plane including the first front surface 101. At least one metal filler layer (33L, 34L), dielectric liner layer 32L, and portions of the first alternating layer stack 30 are removed from the first front surface 101 of the first substrate 8. The remaining portions of at least one metal filler layer (33L, 34L), dielectric liner layer 32L, and the first alternating layer stack 30 are embedded within the first substrate 8 and located between the first front surface 101 and the first back surface 102. These remaining portions of the first alternating layer stack 30 include at least one first deep trench capacitor. These remaining portions of the dielectric liner layer 32L include a dielectric liner 32. These remaining portions of the metal nitride layer 33L include a metal nitride liner 33. These remaining portions of the metal layer 34L include a metal portion 34. The thickness of each metal portion 34 can range from 200 nm to 5,000 nm, although smaller and larger thicknesses are also possible. Each successive combination of the dielectric liner 32, the metal nitride liner 33, and the metal portion 34 constitutes an electrically isolated bonding pad assembly 36. Thus, each electrically isolated bonding pad assembly 36 includes a corresponding first metal bonding pad (33, 34) and a corresponding dielectric liner 32. Each successive combination of the metal nitride liner 33 and the metal portion 34 constitutes a metal bonding pad (33, 34). The length-to-width ratio of each metal bonding pad (33, 34) can range from 1 / 4 to 4 (such as 1 / 2 to 2 and / or 0.9 to 1.1 (e.g., 1.0)), although smaller and larger ratios are also possible. The length-to-height ratio of each metal bonding pad (33, 34) can range from 1 / 2h to 30 (such as 1 to 10 and / or 2 to 4), although smaller and larger ratios are also possible.

[0102] Generally, the length and width of each metal bonding pad (33, 34) are limited by the density of the electrically isolated deep trenches. Two sets of metal bonding pads (33, 34) can be used to provide electrical connections to each deep trench capacitor. In an illustrative example, the metal bonding pads (33, 34) may have a horizontal cross-sectional shape of a square or a rounded square (i.e., a shape modified from a square by rounding the four corners), and the wall-to-wall distance of each pair of facing sidewalls (in the case of a square horizontal cross-sectional shape, this distance is the same as the length of the sidewall) may be in the range of 1 micrometer to 20 micrometers. In one embodiment, each metal bonding pad (33, 34) may have a thickness in the range of 1 micrometer to 2 micrometers. Therefore, the length-to-height ratio of each metal bonding pad (33, 34) may be in the range of 1 to 10, although smaller and larger ratios may also be used.

[0103] Generally, each first deep trench capacitor includes at least two first metal electrode layers (10A, 10B, 20A, 20B) interleaved with at least one first node dielectric layer 15. First metal bonding pads (33, 34) may be located above and below the first front surface 101. The combination of material portions located between the first front surface 101 and the first back surface 102 constitutes the first layer capacitor assembly 100. In one embodiment, each layer within the first alternating layer stack 30 is laterally surrounded by, or is laterally surrounded by, any other layer within the first alternating layer stack 30.

[0104] refer to Figure 5 The second-layer capacitor assembly 200 can be provided by performing the same set of processing steps as those used to form the first-layer capacitor assembly 100. In one embodiment, the second-layer capacitor assembly 200 may be a replica of the first-layer capacitor assembly. The second-layer capacitor assembly 200 includes at least one second deep trench capacitor and a plurality of metal bonding pads, which are subsequently bonded to the first metal bonding pads and are referred to herein as second metal bonding pads (133, 134). Each second metal bonding pad (133, 134) may include a metal nitride liner 133 and a metal portion 134.

[0105] Generally, each second deep trench capacitor includes a dielectric liner 106, which may include a dielectric material providing electrical isolation between the subsequently formed first deep trench capacitor and the second substrate 108. For example, the dielectric liner 106 may include silicon oxide, silicon nitride, silicon oxynitride, and / or a dielectric metal oxide. Other suitable materials within the scope of this disclosure may also be used. In an illustrative example, the dielectric liner 106 may include a silicon oxide layer formed by thermal oxidation of multiple surface portions of the second substrate 108, including silicon. The thickness of the dielectric liner 106 may range from 4 nm to 100 nm, although smaller and larger thicknesses may also be used.

[0106] The second deep trench capacitor includes a second alternating layer stack 130 having a dielectric liner 106 and at least two second metal electrode layers (110A, 110B, 120A, 120B) interleaved with at least one second node dielectric layer 115. For example, the second metal electrode layers (110A, 110B, 120A, 120B) may include a first primary metal electrode layer 110A, a first secondary metal electrode layer 120A, a second primary metal electrode layer 110B, a second secondary metal electrode layer 120B, etc. Second metal bonding pads (133, 134) may be located on the top surface and below the second substrate 108. Each electrically isolated bonding pad assembly 136 may include a corresponding second metal bonding pad (133, 134) and a corresponding dielectric liner 132.

[0107] refer to Figure 6 The second capacitor assembly 200 can then be bonded to the first capacitor assembly 100 in an inverted position. Therefore, the horizontal top surface of the second capacitor assembly 200 is referred to herein as the second back surface, and the horizontal bottom surface of the second capacitor assembly 200 is referred to herein as the second front surface. The second front surface and the second back surface are parallel to each other. Generally, at least one second alternating layer stack 130, including at least two second metal electrode layers (110A, 110B, 120A, 120B) interleaved with at least one second node dielectric layer 115, can be formed within the second substrate 108. Second metal bonding pads (133, 134) are located on and below the second back surface. The pattern of the second metal bonding pads (133, 134) can be a mirror image of the pattern of the first metal bonding pads (33, 34). The pattern of the second deep trench capacitor can be a mirror image of the pattern of the first deep trench capacitor. Each second metal electrode layer (110A, 110B, 120A, 120B) contacts the corresponding first metal electrode layer in the first metal electrode layer (10A, 10B, 20A, 20B).

[0108] refer to Figure 7 The back side of the second layer capacitor assembly 200 (i.e., as shown) Figure 7The top side (as shown in the diagram) can be removed, for example, by grinding, polishing, anisotropic etching, isotropic etching, or a combination thereof. For instance, a grinding process can be used to remove the dominant portion of the second substrate 108 covering the uppermost surface of the second alternating layer stack 130, and a chemical mechanical planarization (CMP) process can be performed to simultaneously remove the two-dimensional portions of the second substrate 108 and the second alternating layer stack 130. Each layer within the second alternating layer stack 130 can be solidly exposed after the CMP process. Generally, the second substrate 108 can be thinned such that each layer within the second alternating layer stack 130 is solidly exposed on a thinned side of the second substrate 108, which can be, for example, a thinned side... Figure 7 The top side of the second substrate 108 shown in the figure may be positioned upside down. In one embodiment, the polished surface of the second substrate 108 may include a second front surface 201. The surface of the second substrate 108 that contacts the first front surface 101 of the first substrate 8 includes a second back surface 202. Generally, the planarized surface of the second substrate 108 provided by thinning the second substrate 108 may include one of the second front surface 201 and the second back surface 202.

[0109] The first exemplary structure includes a first capacitor assembly 100 and a second capacitor assembly 200. The first capacitor assembly 100 includes: a first substrate 8 having a first front surface 101 and a first back surface 102 parallel to each other; a first alternating layer stack 30 embedded in the first substrate 8 and including at least two first metal electrode layers (10A, 10B, 20A, 20B) interleaved with at least one first node dielectric layer 15; and first metal bonding pads (33, 34) located on the first front surface 101. The second capacitor assembly 200 includes: a second substrate 108 having a second front surface 201 and a second back surface 202 parallel to each other; a second alternating layer stack 130 embedded in the second substrate 201 and including at least two second metal electrode layers (110A, 110B, 120A, 120B) interleaved with at least one second node dielectric layer 115; and second metal bonding pads (133, 134) located on the second back surface 202 and bonded to the first metal bonding pads (33, 34).

[0110] Each of at least two first metal electrode layers (10A, 10B, 20A, 20B) and at least one first node dielectric layer 15 includes a corresponding vertical extension portion extending from the first front surface 101 toward the first back surface 102. Each of at least two second metal electrode layers (110A, 110B, 120A, 120B) and at least one second node dielectric layer 115 includes a corresponding vertical extension portion extending from the second front surface 201 to the second back surface 202.

[0111] According to one embodiment of the present disclosure, Figure 8A This is a vertical cross-sectional view of a region of a first exemplary structure after the formation of an interconnect dielectric layer and multiple contact via structures. Figure 8B For along Figure 8A The first exemplary structural feature in the horizontal plane B-B' is shown as a horizontal cross-sectional view of a region. Structures not located within the horizontal plane B-B' are shown with dashed lines.

[0112] refer to Figure 8A and Figure 8B An etch-stop dielectric layer 62 may be deposited on the second front surface 201, and at least one interconnect-level dielectric layer 70 may be deposited above the etch-stop dielectric layer 62. Metal interconnect structures (80A, 80B, 90A, 90B) may be formed in at least one interconnect-level dielectric layer 70. The metal interconnect structures (80A, 80B, 90A, 90B) may include a first contact via structure 80A contacting a first subset of the second metal electrode layers (110A, 110B, 120A, 120B), and a second contact via structure 80B contacting a second subset of the second metal electrode layers (110A, 110B, 120A, 120B). Each of the contact via structures (80A, 80B) is electrically connected to a set of corresponding first metal electrode layers in at least two first metal electrode layers (10A, 10B, 20A, 20B) and corresponding second metal electrode layers in at least two second metal electrode layers (110A, 110B, 120A, 120B). The metal interconnect structures (80A, 80B, 90A, 90B) may include metal bonding pads (90A, 90B), which may include a first metal bonding pad 90A electrically connected to the first contact via structure 80A and a second metal bonding pad 90B electrically connected to the second contact via structure 80B.

[0113] refer to Figure 9 An alternative configuration of the first exemplary structure can be achieved by forming an additional metal bonding pad on the front side of the second layer capacitor assembly 200. Figure 7The first exemplary structure is generated. For example, a photoresist layer may be coated over the second front surface 201 of the second capacitor assembly 200 and may be photolithographically patterned to form openings in regions outside the area of ​​the second alternating layer stack 130. A dielectric liner layer and at least one metal material layer may be deposited in the pad cavity and may subsequently be planarized to form electrically isolated bonding pad assemblies 236 on and under the second front surface 201 of the second capacitor assembly 200. Each electrically isolated bonding pad assembly may include a corresponding third metal bonding pad (233, 234) and a corresponding dielectric liner 232. Each third metal bonding pad (233, 234) may include a metal nitride liner 233 and a metal portion 234.

[0114] refer to Figure 10 The third-layer capacitor assembly 300 can be executed with respect to form such as Figure 8A , Figure 8B The processing steps of the second-layer capacitor assembly 200 shown are provided in the same set as those for the third-layer capacitor assembly 300, with the modification being that the third-layer capacitor assembly 300 is attached to... Figure 9 The second layer capacitor assembly 200. In one embodiment, the third layer capacitor assembly 300 may be a replica of the second layer capacitor assembly 200. The third layer capacitor assembly 300 includes at least one third deep trench capacitor and a plurality of metal bonding pads that can be bonded to third metal bonding pads (233, 234) and are referred to herein as fourth metal bonding pads (333, 334). Each fourth metal bonding pad (333, 334) may include a metal nitride liner 333 and a metal portion 334.

[0115] Generally, each third deep trench capacitor includes a dielectric liner 206, which may include a dielectric material providing electrical isolation between the subsequently formed first deep trench capacitor and the third substrate 208. For example, the dielectric liner 206 may include silicon oxide, silicon nitride, silicon oxynitride, and / or a dielectric metal oxide. Other suitable materials within the scope of this disclosure may also be used. In an illustrative example, the dielectric liner 206 may include a silicon oxide layer formed by thermal oxidation of multiple surface portions of the third substrate 208, which includes silicon. The thickness of the dielectric liner 206 may range from 4 nm to 100 nm, although smaller and larger thicknesses may also be used.

[0116] The third deep trench capacitor includes a third alternating layer stack 230 having at least two third metal electrode layers (210A, 210B, 220A, 220B) interleaved with at least one third node dielectric layer 215. For example, the third metal electrode layers (210A, 210B, 220A, 220B) may include a first primary metal electrode layer 210A, a first secondary metal electrode layer 220A, a second primary metal electrode layer 210B, a second secondary metal electrode layer 220B, etc. Fourth metal bonding pads (333, 334) may be located on and above the bottom surface of the third substrate 208. Each electrically isolated bonding pad assembly 336 may include a corresponding fourth metal bonding pad (333, 334) and a corresponding dielectric liner 332.

[0117] The third capacitor assembly 300 may subsequently be bonded to the second capacitor assembly 200. The horizontal top surface of the third capacitor assembly 300, due to its bonding to the second capacitor assembly 200, is referred to herein as the third front surface 301, and the horizontal bottom surface of the third capacitor assembly 300, due to its bonding to the second capacitor assembly 200, is referred herein as the third back surface 302. The third front surface 301 and the third back surface 302 may be parallel to each other. Generally, at least one third alternating layer stack 230, including at least two third metal electrode layers (210A, 210B, 220A, 220B) interleaved with at least one third node dielectric layer 215, may be formed within the third substrate 208.

[0118] Subsequently, Figure 8A and Figure 8BThe processing steps can be performed with necessary modifications to form an etch-stop dielectric layer 62, at least one interconnect-level dielectric layer 70, and metal interconnect structures (80A, 80B, 90A, 90B). The metal interconnect structures (80A, 80B, 90A, 90B) may include a first contact via structure 80A of a first subset of the third metal electrode layers (210A, 210B, 220A, 220B), and a second contact via structure 80B of a second subset of the third metal electrode layers (210A, 210B, 220A, 220B). Each of the contact via structures (80A, 80B) is electrically connected to a set of corresponding first metal electrode layers in at least two first metal electrode layers (10A, 10B, 20A, 20B), corresponding second metal electrode layers in at least two second metal electrode layers (110A, 110B, 120A, 120B), and corresponding third metal electrode layers in at least two third metal electrode layers (210A, 210B, 220A, 220B). The metal interconnect structures (80A, 80B, 90A, 90B) may include metal bonding pads (90A, 90B), which may include a first metal bonding pad 90A electrically connected to the first contact via structure 80A and a second metal bonding pad 90B electrically connected to the second contact via structure 80B.

[0119] According to one embodiment of the present disclosure, Figure 11A This is a vertical cross-sectional view of a region of a second exemplary structure after the formation of multiple deep grooves and at least one lug recessed region. Figure 11B For along Figure 11A A horizontal cross-sectional view of a region of the second exemplary structure in the horizontal plane B–B'. (Reference) Figure 11A and Figure 11B A second exemplary structure according to an embodiment of the present disclosure can be achieved by forming at least one lug-shaped recessed region 9T. Figure 1The first exemplary structure is generated. Each lug recess region 9T is connected to the upper end of the first deep trench 9 and has a thickness less than the total thickness of the subsequent first alternating layer stack (metal electrode layers 10A, 10B, 20A, 20B). In one embodiment, the depth of each lug recess region 9T can be selected such that a horizontal extension of the first node dielectric layer 15 can be formed in a horizontal plane including the first front surface 101. Generally, each lug recess region 9T has a depth less than the sum of the thicknesses of all layers in the subsequent first alternating layer stack and is connected to the upper portion of a corresponding first deep trench in at least one first deep trench 9. For example, the depth of each lug recess region 9T can be in the range of 10 nm to 400 nm (such as 20 nm to 200 nm), although smaller and larger depths are also possible. The lateral extent of each lug recessed region 9T can be similar to the total thickness of the first alternating layer stack (metal electrode layers 10A, 10B, 20A, 20B) that will be formed subsequently.

[0120] refer to Figure 12 It can be executed subsequently. Figures 2 to 4 The processing steps are to form a first layer capacitor assembly 100, which embeds at least one first deep trench capacitor. Generally, each first deep trench capacitor includes at least two first metal electrode layers (10A, 10B, 20A, 20B) interleaved with at least one first node dielectric layer 15. First metal bonding pads (33, 34) may be located on and below the first front surface 101. In one embodiment, each layer within the first alternating layer stack 30 is laterally surrounded by, or is laterally surrounded by, any other layer within the first alternating layer stack 30.

[0121] Due to the presence of at least one lug recessed region in the first deep trench 9 and the lateral extension of the first alternating layer stack 30, the first layer capacitor assembly 100 illustrated in FIG11 can be coupled with... Figure 4 The first layer capacitor assembly 100 is substantially the same. In one embodiment, at least one and / or each of the first metal electrode layers (10A, 10B, 20A, 20B) includes a corresponding lateral extension formed in the lug recess region 9T. Each lateral extension of the first metal electrode layer (10A, 10B, 20A, 20B) is referred to herein as a lug portion.

[0122] In one embodiment, the height of the lug recess region 9T of the first deep trench 9 can be selected such that the horizontal surface of the horizontal extension of the first node dielectric layer 15 is located within a horizontal plane including the first front surface 101. In one embodiment, the lug portion of the first major metal electrode layer 10A can contact the bottom surface of the horizontal extension, and the first node dielectric layer 15 has a solidly exposed horizontal surface. In one embodiment, the lug portion of the second major metal electrode layer 10B can contact the bottom surface of the horizontal extension, and the first node dielectric layer 15 has a solidly exposed horizontal surface. In one embodiment, the lug portion of the first major metal electrode layer 20A can contact the bottom surface of the horizontal extension, and the first node dielectric layer 15 has a solidly exposed horizontal surface. In one embodiment, the lug portion of the second major metal electrode layer 20B can contact the bottom surface of the horizontal extension, and the first node dielectric layer 15 has a solidly exposed horizontal surface. Generally, each of the first metal electrode layers (10A, 10B, 20A, 20B) may have a lug portion that extends laterally horizontally and rests on and contacts a horizontally extending portion of the first node dielectric layer 15 having a solidly exposed surface.

[0123] refer to Figure 13 The second layer capacitor assembly 200 can be formed by performing an action with the capacitor assembly used to form a capacitor assembly. Figure 12The first layer capacitor assembly 100 is formed using the same set of processing steps as the first layer capacitor assembly 100, with the modification being the pattern of the lug recessed region 9T. The second layer capacitor assembly 200 includes at least one second deep trench capacitor. The pattern of the second deep trench capacitor in the second layer capacitor assembly 200 may be the same as the pattern of the first deep trench capacitor in the first layer capacitor assembly 100. Each second deep trench capacitor includes a second alternating layer stack 130 having at least two second metal electrode layers (110A, 110B, 120A, 120B) interleaved with at least one second node dielectric layer 115. For example, the second metal electrode layers (110A, 110B, 120A, 120B) may include a first primary metal electrode layer 110A, a first secondary metal electrode layer 120A, a second primary metal electrode layer 110B, a second secondary metal electrode layer 120B, etc. The second metal bonding pads (133, 134) may be located on the top surface and below the second substrate 108. Each electrically isolated bonding pad assembly 136 may include a corresponding second metal bonding pad (133, 134) and a corresponding dielectric liner 132. In one embodiment, at least one and / or each of the second metal electrode layers (110A, 110B, 120A, 120B) includes a corresponding lateral extension formed in the lug recess region. Each lateral extension of the second metal electrode layers (110A, 110B, 120A, 120B) is referred to herein as a lug portion. The region of the lug portion of the second metal electrode layers (110A, 110B, 120A, 120B) may be laterally offset from the region of the lug portion of the first metal electrode layers (10A, 10B, 20A, 20B), i.e., they do not overlap.

[0124] Electrically isolated bonding pad assemblies 236 may be formed on and below the second front surface 201 of the second capacitor assembly 200. Each electrically isolated bonding pad assembly may include a corresponding third metal bonding pad (233, 234) and a corresponding dielectric liner 232. Each third metal bonding pad (233, 234) may include a metal nitride liner 233 and a metal portion 234.

[0125] refer to Figure 14 , Figure 10 The processing steps can be performed with necessary modifications to form the third layer capacitor assembly 300. In one embodiment, at least one and / or each of the third metal electrode layers (210A, 210B, 220A, 220B) includes a corresponding lateral extension formed in the lug recess region. Each lateral extension of the third metal electrode layer (210A, 210B, 220A, 220B) is referred to herein as a lug portion.

[0126] refer to Figure 15An etch-stop dielectric layer 62 may be deposited on the third front surface 301, and at least one interconnect-level dielectric layer 70 may be deposited above the etch-stop dielectric layer 62. Metal interconnect structures (80A, 80B, 90A, 90B) may be formed in at least one interconnect-level dielectric layer 70. The metal interconnect structures (80A, 80B, 90A, 90B) may include a first contact via structure 80A contacting a first subset of the third metal electrode layers (210A, 210B, 220A, 220B), and a second contact via structure 80B contacting a second subset of the third metal electrode layers (210A, 210B, 220A, 220B). Each of the contact via structures (80A, 80B) is electrically connected to a set of corresponding first metal electrode layers in at least two first metal electrode layers (10A, 10B, 20A, 20B), corresponding second metal electrode layers in at least two second metal electrode layers (110A, 110B, 120A, 120B), and corresponding third metal electrode layers in at least two third metal electrode layers (210A, 210B, 220A, 220B). The metal interconnect structures (80A, 80B, 90A, 90B) may include metal bonding pads (90A, 90B), which may include a first metal bonding pad 90A electrically connected to the first contact via structure 80A and a second metal bonding pad 90B electrically connected to the second contact via structure 80B.

[0127] In one embodiment, a first via cavity may be formed through at least one interconnect-level dielectric layer 70, a third substrate 208, and a second substrate 108 to the top surface of a lug portion of a corresponding first metal electrode layer (10A, 10B, 20A, 20B). In one embodiment, a second via cavity may be formed through at least one interconnect-level dielectric layer 70 and a third substrate 208 to the top surface of a lug portion of a corresponding second metal electrode layer (110A, 110B, 120A, 120B). In one embodiment, a third via cavity may be formed through at least one interconnect-level dielectric layer 70 to the top surface of a lug portion of a corresponding third metal electrode layer (210A, 210B, 220A, 220B). These first, second, and third via cavities may be formed sequentially or simultaneously. The metal electrode layers may serve as etch stop layers during the formation of the various via cavities. A conformal dielectric material layer may be deposited in the via cavities and may be anisotropically etched to form cylindrical dielectric spacers 82. Contact via structures (80A, 80B) may be formed in the remaining volume of the via cavities on the corresponding metal electrode layers.

[0128] refer to Figure 16 The illustration is derived from a non-limiting illustrative application of a semiconductor die with a first exemplary structure. The first semiconductor die 1000 can be executed... Figures 1 to 8B , Figures 1 to 7 , Figure 9 and Figure 10 or Figures 11A to 14 The processing steps are provided as follows. A first semiconductor die 1000 may be attached to the bottom side of a second semiconductor die 2000. For example, the second semiconductor die 2000 may be a system-on-a-chip (SoC) die 2000, which may be bonded to an integrated fan-out package-on-package (InFO PoP) die 3000 via an array of solder balls 2500. The second semiconductor die 2000 may be bonded to another module, such as a printed circuit board (PCB), via another array of solder balls 1500. Deep trench capacitors in semiconductor die 1000 may be used to stabilize the power supply system in the second semiconductor die 2000.

[0129] Referring to all the accompanying drawings and various embodiments according to the present disclosure, a capacitor structure is provided, the capacitor structure comprising: a first layer capacitor assembly 100, the first layer capacitor assembly 100 comprising: a first substrate 8 having a first front surface 101 and a first back surface 102 parallel to each other; a first alternating layer stack 30 embedded within the first substrate 8 and including at least two first metal electrode layers (10A, 10B, 20A, 20B) interleaved with at least one first node dielectric layer 15; and first metal bonding pads (33, 34) located on the first front surface 101; and a second layer capacitor assembly 200 comprising: a second substrate 108 having The substrate has a second front surface 201 and a second back surface 202 that are parallel to each other; a second alternating layer stack 130 embedded within a second substrate 108 and including at least two second metal electrode layers (110A, 110B, 120A, 120B) that are interposed with at least one second node dielectric layer 115; and second metal bonding pads (133, 134) located on the second back surface 202 and bonded to the first metal bonding pads (33, 34); wherein each of the at least two first metal electrode layers (10A, 10B, 20A, 20B) contacts a corresponding second metal electrode layer in the at least two second metal electrode layers (110A, 110B, 120A, 120B).

[0130] In one embodiment, the first front surface 101 contacts the second back surface 202 in a horizontal plane, in which at least two second metal electrode layers (110A, 110B, 120A, 120B) contact at least two first metal electrode layers (10A, 10B, 20A, 20B).

[0131] In one embodiment, each layer within the second alternating layer stack 130 extends continuously from the second front surface 201 to the second back surface 202. In one embodiment, the first alternating layer stack 30 extends from the first front surface 101 into the first substrate 8 and has a first vertical range smaller than the vertical distance between the first front surface 101 and the first back surface 102. In one embodiment, the first vertical range is in the range of 2 micrometers to 20 micrometers; and the vertical distance between the second front surface 201 and the second back surface 202 is in the range of 2 micrometers to 20 micrometers.

[0132] In one embodiment, each of at least two first metal electrode layers (10A, 10B, 20A, 20B) and at least one first node dielectric layer 15 includes a corresponding vertical extension portion extending from the first front surface 101 toward the first back surface 102; and each of at least two second metal electrode layers (110A, 110B, 120A, 120B) and at least one second node dielectric layer 115 includes a corresponding vertical extension portion extending from the second front surface 201 to the second back surface 202.

[0133] In one embodiment, the capacitor structure includes: an interconnect dielectric layer 70 overlying a second substrate 108; and contact via structures (80A, 80B) extending vertically through the interconnect dielectric layer 70 and electrically connected to a corresponding first metal electrode layer in at least two first metal electrode layers (10A, 10B, 20A, 20B) and a corresponding second metal electrode layer in at least two second metal electrode layers (110A, 110B, 120A, 120B).

[0134] In one embodiment, at least two first metal electrode layers (10A, 10B, 20A, 20B) and at least two second metal electrode layers (110A, 110B, 120A, 120B) comprise conductive metal nitrides, elemental metals, or intermetallic alloys; at least one first node dielectric layer 15 and at least one second node dielectric layer 115 comprise dielectric metal oxides or silicon nitride; and the first substrate 8 and the second substrate 108 comprise semiconductor substrates.

[0135] In one embodiment, each layer in the first alternating layer stack 30 is laterally surrounded by, or is laterally surrounded by, any other layer in the first alternating layer stack 30; and each layer in the second alternating layer stack 130 is laterally surrounded by, or is laterally surrounded by, any other layer in the second alternating layer stack 130.

[0136] In one embodiment, at least two first metal electrode layers (10A, 10B, 20A, 20B) comprise at least three first metal electrode layers (10A, 10B, 20A, 20B); at least two second metal electrode layers (110A, 110B, 120A, 120B) comprise at least three second metal electrode layers (110A, 110B, 120A, 120B); at least one first node dielectric layer 15 comprises at least two first node dielectric layers 15; and at least one second node dielectric layer 115 comprises at least two second node dielectric layers 115.

[0137] According to another embodiment of this disclosure, a capacitor structure is provided, comprising: a first capacitor assembly 100, the first capacitor assembly 100 comprising: a first substrate 8 having a first front surface 101 and a first back surface 102 parallel to each other; and a first alternating layer stack 30 embedded within the first substrate 8 and including at least two first metal electrode layers (10A, 10B, 20A, 20B) interleaved with at least one first node dielectric layer 15, wherein one of the at least two first metal electrode layers (10A, 10B, 20A, 20B) includes a tab extending parallel to the first front surface 101; and a second capacitor assembly. 200, the second layer capacitor assembly 200 includes: a second substrate 108 having a second front surface 201 and a second back surface 202 parallel to each other; and a second alternating layer stack 130 embedded within the second substrate 108 and including at least two second metal electrode layers (110A, 110B, 120A, 120B) interleaved with at least one second node dielectric layer 115; and contact via structures (80A, 80B) extending vertically through the second substrate 108 and contacting the top surface of the lug portion of one of the at least two first metal electrode layers (10A, 10B, 20A, 20B).

[0138] In one embodiment, each of at least two first metal electrode layers (10A, 10B, 20A, 20B) contacts a corresponding second metal electrode layer of at least two second metal electrode layers (110A, 110B, 120A, 120B) at the interface where the first front surface 101 contacts the second back surface 202.

[0139] In one embodiment, the capacitor structure includes: first metal bonding pads (33, 34) embedded in a first substrate 8; and second metal bonding pads (133, 134) embedded in a second substrate 108 and bonded to corresponding first metal bonding pads in the first metal bonding pads (33, 34) in a horizontal plane, wherein a first front surface 101 contacts a second back surface 202 located in the horizontal plane.

[0140] Figure 17 This is a flowchart illustrating the general processing steps of a method for manufacturing a semiconductor structure. Refer to step 1710 and... Figures 1 to 4 , Figure 9 and Figures 11A to 12 A first capacitor assembly 100 is formed, comprising: a first substrate 8 having a first front surface 101 and a first back surface 102 parallel to each other; a first alternating layer stack 30 embedded within the first substrate 8 and including at least two first metal electrode layers (10A, 10B, 20A, 20B) interleaved with at least one first node dielectric layer 15; and first metal bonding pads (33, 34) located on the first front surface 101. Refer to step 1720 and... Figure 5 , Figure 9 and Figure 13 A second capacitor assembly 200 can be formed, comprising: a second substrate 108 having a second front surface 201 and a second back surface 202 parallel to each other; a second alternating layer stack 130 embedded within the second substrate 108 and including at least two second metal electrode layers (110A, 110B, 120A, 120B) interleaved with at least one second node dielectric layer 115; and second metal bonding pads (133, 134) located on the second back surface 202. Refer to step 1730 and... Figure 6 , Figure 7 , Figure 9 and Figure 13The second metal bonding pads (133, 134) are bonded to the first metal bonding pads (33, 34). Each of at least two first metal electrode layers (10A, 10B, 20A, 20B) contacts a corresponding second metal electrode layer in at least two second metal electrode layers (110A, 110B, 120A, 120B). In one embodiment, forming the first layer capacitor assembly includes: forming at least one first deep trench extending perpendicularly from the first front surface toward the first back surface; depositing the first alternating layer stack into the at least one first deep trench and above the first front surface; and removing a plurality of portions of the first alternating layer stack from a horizontal plane including the first front surface. In one embodiment, forming the first layer capacitor assembly includes: forming a plurality of pad cavities extending through a plurality of horizontally extending portions of the first alternating layer stack and into an upper portion of the first substrate; depositing at least one metal material into the pad cavities; and removing a plurality of portions of the at least one metal material from the horizontal plane including the first front surface while removing the portions of the first alternating layer stack from the horizontal plane including the first front surface, wherein a plurality of remaining portions of the at least one metal material comprise the first metal bonding pads. In one embodiment, forming the second layer capacitor assembly includes: forming at least one second deep trench into the second substrate, the at least one second deep trench having a depth less than a thickness of the second substrate; depositing the second alternating layer stack into the at least one second deep trench; and removing a plurality of horizontally extending portions of the second alternating layer stack from outside the at least one second deep trench. In one embodiment, forming the second capacitor assembly includes thinning the second substrate such that each layer in the second alternating layer stack is substantially exposed on a thinned side of the second substrate; and a planarized surface of the second substrate provided by thinning the second substrate includes one of the second front surface and the second back surface. In one embodiment, the method further includes: forming a lug recess region in one of the at least one first deep trench, wherein the lug recess region has a depth less than the sum of the thicknesses of all layers in the first alternating layer stack and is coupled to an upper portion of the at least one first deep trench, and the first alternating layer stack is deposited in the lug recess region; and after the second metal bonding pads are bonded to the first metal bonding pads, forming a contact via structure through the second substrate and on a portion of one of the at least two first metal electrode layers in the lug recess region.In one embodiment, the method further includes: forming an interconnect-level dielectric layer over the second capacitor assembly; and forming a plurality of contact via structures through the interconnect-level dielectric layer, wherein each of the contact via structures is electrically connected to a set of a corresponding first metal electrode layer of the at least two first metal electrode layers and a corresponding second metal electrode layer of the at least two second metal electrode layers.

[0141] Various embodiments of this disclosure may be employed to provide a multilayer deep trench structure in which multiple capacitor assemblies (100, 200, 300) are vertically stacked. Although this disclosure is described using embodiments in which two capacitor assemblies (100, 200) or three capacitor assemblies (100, 200, 300) are vertically stacked, embodiments in which four or more capacitor assemblies are vertically stacked are explicitly contemplated herein. Stacking multiple capacitor assemblies can increase the total capacitance of the capacitor structure within a semiconductor die comprising a stack of multiple capacitor assemblies (100, 200, 300), and can be used to provide a capacitor die with high capacitance within a limited area.

[0142] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can readily serve as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A capacitor structure, characterized in that, Include: A first-layer capacitor assembly, comprising: A first substrate having a first front surface and a first back surface that are parallel to each other; A first alternating layer stack is embedded in the first substrate and includes at least two first metal electrode layers that are interleaved with at least one first node dielectric layer; as well as A plurality of first metal bonding pads are located on the first front surface, wherein the first metal bonding pads are laterally spaced from the first alternating layer stack, and the first metal bonding pads have a plurality of top surfaces that are in the same horizontal plane as a top surface of the first alternating layer stack; as well as A second-layer capacitor assembly, comprising: A second substrate having a second front surface and a second back surface that are parallel to each other; A second alternating layer stack is embedded within the second substrate and includes at least two second metal electrode layers that are interleaved with at least one second node dielectric layer; as well as Multiple second metal bonding pads are located on the second back surface and bonded to the first metal bonding pads. Each of the at least two first metal electrode layers contacts a corresponding second metal electrode layer of the at least two second metal electrode layers.

2. The capacitor structure according to claim 1, characterized in that, The first front surface contacts the second back surface in a horizontal plane, and in the same horizontal plane, the at least two second metal electrode layers contact the at least two first metal electrode layers.

3. The capacitor structure according to claim 1, characterized in that, Each layer in the second alternating layer stack extends continuously from the second front surface to the second back surface.

4. The capacitor structure according to claim 3, characterized in that, The first alternating layer stack extends from the first front surface into the first substrate and has a first vertical range smaller than a vertical distance between the first front surface and the first back surface.

5. The capacitor structure according to claim 4, characterized in that... The first vertical range is within the range of 2 micrometers to 20 micrometers; and The vertical distance between the second front surface and the second back surface is in the range of 2 micrometers to 20 micrometers.

6. The capacitor structure according to claim 1, characterized in that, in: Each of the at least two first metal electrode layers and the at least one first node dielectric layer includes a corresponding vertically extending portion extending from the first front surface toward the first back surface; as well as Each of the at least two second metal electrode layers and the at least one second node dielectric layer includes a corresponding vertical extension portion extending from the second front surface to the second back surface.

7. The capacitor structure according to claim 1, characterized in that, Further includes: An interconnect dielectric layer is overlaid on the second substrate; and Multiple contact via structures extend vertically through the interconnect dielectric layer and are electrically connected to a corresponding first metal electrode layer of the at least two first metal electrode layers and a corresponding second metal electrode layer of the at least two second metal electrode layers.

8. The capacitor structure according to claim 1, characterized in that: The at least two first metal electrode layers and the at least two second metal electrode layers comprise a conductive metal nitride, an elemental metal, or an intermetallic alloy; The at least one first node dielectric layer and the at least one second node dielectric layer comprise a dielectric metal oxide or silicon nitride; and The first substrate and the second substrate comprise multiple semiconductor substrates.

9. The capacitor structure according to claim 1, characterized in that: Each layer in the first alternating layer stack is laterally surrounded by, or is laterally surrounded by, any other layer in the first alternating layer stack; as well as Each layer in the second alternating layer stack is laterally surrounded by, or by, any other layer in the second alternating layer stack.

10. The capacitor structure according to claim 1, characterized in that: The at least two first metal electrode layers comprise at least three first metal electrode layers; The at least two second metal electrode layers include at least three second metal electrode layers; The at least one first node dielectric layer comprises at least two first node dielectric layers; as well as The at least one second node dielectric layer comprises at least two second node dielectric layers.

11. A capacitor structure, characterized in that, Include: A first-layer capacitor assembly, comprising: A first substrate having a first front surface and a first back surface that are parallel to each other; and A first alternating layer stack is embedded in the first substrate and includes at least two first metal electrode layers interleaved with at least one first node dielectric layer, wherein one of the at least two first metal electrode layers includes a lug portion extending parallel to the first front surface. A second-layer capacitor assembly, comprising: A second substrate having a second front surface and a second back surface that are parallel to each other; and A second alternating layer stack is embedded within the second substrate and includes at least two second metal electrode layers that are interleaved with at least one second node dielectric layer; as well as A contact via structure extends vertically through the second substrate and contacts the top surface of the lug portion of the first metal electrode layer in the at least two first metal electrode layers; Each of the at least two first metal electrode layers contacts a corresponding second metal electrode layer at an interface where the first front surface contacts the second back surface.

12. The capacitor structure according to claim 11, characterized in that, Further includes: Multiple first metal bonding pads are embedded in the first substrate; and A plurality of second metal bonding pads are embedded in the second substrate and bonded to a corresponding first metal bonding pad in a horizontal plane in which the first front surface contacts the second back surface.

13. A method for manufacturing a capacitor structure, characterized in that, Include: A first-layer capacitor assembly is formed, the first-layer capacitor assembly comprising a first substrate having a first front surface and a first back surface parallel to each other, a first alternating layer stack embedded in the first substrate and including at least two first metal electrode layers intersecting with at least one first node dielectric layer, and a plurality of first metal bonding pads located on the first front surface, the first metal bonding pads being laterally spaced from the first alternating layer stack, and the first metal bonding pads having a plurality of top surfaces located in the same horizontal plane as a top surface of the first alternating layer stack; A second layer capacitor assembly is formed, the second layer capacitor assembly comprising a second substrate having a second front surface and a second back surface parallel to each other, a second alternating layer stack embedded in the second substrate and including at least two second metal electrode layers intersecting with at least one second node dielectric layer, and a plurality of second metal bonding pads located on the second back surface. as well as The second metal bonding pads are bonded to the first metal bonding pads, wherein each of the at least two first metal electrode layers contacts a corresponding second metal electrode layer of the at least two second metal electrode layers.

14. The method according to claim 13, characterized in that, The first layer of capacitor assembly comprises: At least one first deep trench is formed, the at least one first deep trench extending perpendicularly from the first front surface toward the first back surface; The first alternating layer is deposited in the at least one first deep trench and above the first front surface; as well as Multiple portions of the first alternating layer stack are removed from a horizontal plane including the first front surface.

15. The method according to claim 14, characterized in that, The first layer of capacitor assembly comprises: Multiple horizontally extending portions are formed through the first alternating layer stack and into a multiple pad cavity in an upper portion of the first substrate; At least one metallic material is deposited into the cavities of these pads; as well as While removing portions of the first alternating layer stack from the horizontal plane including the first front surface, multiple portions of the at least one metal material are also removed from the horizontal plane including the first front surface, wherein multiple remaining portions of the at least one metal material contain the first metal bonding pads.

16. The method according to claim 13, characterized in that, The second layer capacitor assembly comprises: At least one second deep trench is formed in the second substrate, the at least one second deep trench having a depth less than a thickness of the second substrate; The second alternating layer is deposited into the at least one second deep trench; as well as Multiple horizontal extensions of the second alternating layer stack are removed from outside the at least one second deep trench.

17. The method according to claim 16, characterized in that: Forming the second layer capacitor assembly includes thinning the second substrate such that each layer in the second alternating layer stack is substantially exposed on a thinned side of the second substrate; as well as A planarized surface of the second substrate provided by thinning the second substrate includes one of the second front surface and the second back surface.

18. The method according to claim 14, characterized in that, Further includes: A lug recess region is formed in one of the at least one first deep trench, wherein the lug recess region has a depth less than the sum of the thicknesses of all layers in the first alternating layer stack and is connected to an upper portion of the at least one first deep trench, and the first alternating layer stack is deposited in the lug recess region. as well as After the second metal bonding pads are bonded to the first metal bonding pads, a contact via structure is formed through the second substrate and on a portion of one of the at least two first metal electrode layers in the lug recess region.

19. The method according to claim 13, characterized in that, Further includes: An interconnect dielectric layer is formed above the second capacitor assembly; and Multiple contact via structures are formed through the interconnect dielectric layer, wherein each of the contact via structures is electrically connected to a set of a corresponding first metal electrode layer of the at least two first metal electrode layers and a corresponding second metal electrode layer of the at least two second metal electrode layers.

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