Tile-type phased array module based on AIP packaging

Abstract

The embodiment of the present disclosure provides a tile-type phased array module based on AIP packaging. The phased array module is composed of, from bottom to top: a waveguide structure cavity, a control board, and an AIP package chip; wherein a waveguide hole penetrating the waveguide structure cavity is provided at the center of the waveguide structure cavity; rectangular grooves are provided around the opening of the waveguide hole; rectangular fur buttons are provided in the rectangular grooves; a through opening is provided at the center of the control board; a waveguide interface is provided at the center of the lower surface of the AIP package chip; the rectangular fur button passes through the through opening at the center of the control board and is connected to the waveguide interface at the center of the lower surface of the AIP package chip. With this structure, the RF signal and the power control signal can be separated on the control board, thereby improving the quality of the RF signal and the power capacity of the phased array module.

Description

Technical Field

[0001] The present disclosure relates to the field of phased array antennas, and in particular to a tile-type phased array module based on AIP packaging. Background Art

[0002] In the existing tile-type phased array architecture, each module is relatively independent and has its own metal cavity, such as antenna array, T / R components and beamforming network, etc. These modules still need to be interconnected by various connectors for RF and low frequency, and a large number of connectors are needed, which makes the overall structure complex and costly. In addition, the phased array modules made by the existing technology are mostly concentrated in the Ku and Ka bands, and there are no or very few W-band tile-type phased array modules. Summary of the invention

[0003] The present disclosure provides a tile-type phased array module based on AIP packaging, and the phased array module is as follows from bottom to top:

[0004] Waveguide structure cavity, control board, AIP package chip;

[0005] A waveguide hole penetrating the waveguide structure cavity is arranged at the center of the waveguide structure cavity;

[0006] A rectangular groove is arranged around the waveguide hole opening; a rectangular wool button is arranged in the rectangular groove;

[0007] A through opening is provided in the center of the control panel;

[0008] A waveguide interface is provided at the center of the lower surface of the AIP packaged chip;

[0009] The rectangular fur button passes through the through opening in the center of the control board and is connected to the waveguide interface in the center of the lower surface of the AIP package chip.

[0010] Furthermore, a chip heat dissipation boss is provided on the upper surface of the waveguide structure cavity; a through square hole corresponding to the chip heat dissipation boss is also provided in the control board; a flip-chip T / R chip corresponding to the chip heat dissipation boss is also provided on the lower surface of the AIP packaged chip; the chip heat dissipation boss passes through the through square hole and contacts with the T / R chip for heat dissipation.

[0011] Furthermore, electric connector assembly grooves are arranged on both sides of the lower surface of the waveguide structure cavity; electric connector wiring grooves corresponding to the electric connector assembly grooves are arranged on both sides of the upper surface of the waveguide structure cavity; and electric connector welding ports corresponding to the electric connector assembly grooves and the electric connector wiring grooves are also arranged on both sides of the control board.

[0012] Furthermore, the waveguide structure cavity also includes:

[0013] A standard waveguide flange located at the center of the lower surface and directly connected to the standard waveguide and the standard waveguide-coaxial adapter;

[0014] The standard waveguide flange is provided with locating pins.

[0015] Furthermore, a BGA pad is provided on the upper surface of the control board; and a 400um metal solder ball corresponding to the BGA pad is provided on the lower surface of the AIP packaged chip.

[0016] Furthermore, the AIP packaged chip also includes:

[0017] Package substrate;

[0018] A feed radiating patch located in a waveguide interface on the lower surface of the package substrate;

[0019] The radiation array element is located on the upper surface of the packaging substrate.

[0020] Furthermore, the control board carries multiple AIP packaged chips.

[0021] Furthermore, when the control board carries N AIP packaged chips: the waveguide structure cavity is divided into a heat dissipation structure cavity and a flange structure cavity; at this time, N waveguide holes are arranged in the heat dissipation structure cavity; a magic T structure is arranged on the lower surface of the heat dissipation structure cavity; the magic T structure respectively connects the waveguide holes in the heat dissipation structure cavity and the flange structure cavity; N rectangular grooves and rectangular hair buttons corresponding to the waveguide holes are arranged on the upper surface of the heat dissipation structure cavity; and N through openings corresponding to the waveguide holes are arranged in the control board.

[0022] Furthermore, when the control board carries N AIP packaged chips: N groups of chip heat dissipation bosses are also provided on the upper surface of the heat dissipation structure cavity; N groups of through square holes corresponding to the chip heat dissipation bosses are also provided in the control board; and N groups of flip-chip T / R chips corresponding to the chip heat dissipation bosses are provided on the lower surface of the AIP packaged chip.

[0023] In the present disclosure, the waveguide structure cavity can not only transmit waveguide signals through the waveguide holes, but also dissipate heat for the AIP packaged chip through the chip heat dissipation bosses, while the control board only transmits power and control signals, thereby reducing the use of RF connectors and separating RF signals and power control signals on the control board, effectively reducing the design complexity of the control board and improving the power capacity of the phased array module.

[0024] It should be understood that the contents described in the summary of the invention are not intended to limit the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, among which:

[0026] Figure 1 A schematic diagram showing the simulation results of the radio frequency performance of BGA solder balls in a tile-type phased array module based on AIP packaging provided by an embodiment of the present disclosure is shown;

[0027] Figure 2 An axonometric diagram of the upper surface of a 64-channel AIP-packaged tile-type phased array module provided by an embodiment of the present disclosure is shown;

[0028] Figure 3 An axonometric diagram of the bottom surface of a 64-channel AIP-packaged tile-type phased array module provided by an embodiment of the present disclosure is shown;

[0029] Figure 4 An exploded diagram of a 64-channel AIP-packaged tile-type phased array module provided by an embodiment of the present disclosure is shown;

[0030] Figure 5 A cross-sectional view of a 64-channel AIP-packaged tiled phased array module provided by an embodiment of the present disclosure is shown.

[0031] Figure 6 A side view of a 64-channel AIP-packaged tile-type phased array module provided by an embodiment of the present disclosure is shown;

[0032] Figure 7 A schematic diagram of the upper surface of an AIP packaged chip in a 64-channel AIP-packaged tile-type phased array module provided by an embodiment of the present disclosure is shown;

[0033] Figure 8 A side view of an AIP packaged chip in a 64-channel AIP packaged tile-type phased array module provided by an embodiment of the present disclosure is shown;

[0034] Fig. 9 A schematic diagram of the bottom surface of an AIP package chip in a 64-channel AIP package-based tile-type phased array module provided by an embodiment of the present disclosure is shown;

[0035] Fig.10 A schematic diagram showing the distribution of transmission signals of AIP packaged chips in a 64-channel AIP-packaged tile-type phased array module provided by an embodiment of the present disclosure is shown;

[0036] Fig.11 A schematic diagram of the appearance of a control board in a 64-channel AIP-packaged tile-type phased array module provided in an embodiment of the present disclosure is shown;

[0037] Fig.12 A schematic diagram of the upper surface of the waveguide structure cavity in a 64-channel AIP-packaged tile-type phased array module provided by an embodiment of the present disclosure is shown;

[0038] Fig.13 A schematic diagram of the lower surface of the waveguide structure cavity in a 64-channel AIP-packaged tile-type phased array module provided by an embodiment of the present disclosure is shown;

[0039] Fig.14 A side view of a waveguide structure cavity in a 64-channel AIP-packaged tile-type phased array module provided by an embodiment of the present disclosure is shown;

[0040] Fig.15 A schematic diagram of a rectangular fur button shape in a tile-type phased array module based on AIP packaging provided by an embodiment of the present disclosure is shown;

[0041] Fig.16 A schematic diagram of a rectangular button structure in a tile-type phased array module based on AIP packaging provided by an embodiment of the present disclosure is shown;

[0042] Fig.17 The figure shows an axonometric diagram of the upper surface of a 256-channel AIP-packaged tile-type phased array module provided by an embodiment of the present disclosure;

[0043] Fig.18 The figure shows a schematic diagram of the lower surface axonometric measurement of a 256-channel AIP-packaged tile-type phased array module provided in an embodiment of the present disclosure;

[0044] Fig.19 An exploded diagram of a 256-channel AIP-packaged tile-type phased array module provided by an embodiment of the present disclosure is shown;

[0045] Fig. 20 A schematic diagram of the layout of a 256-channel AIP-packaged tile-type phased array module control board provided in an embodiment of the present disclosure is shown;

[0046] Fig.21 A schematic diagram of the upper surface of the heat dissipation structure in the 256-channel AIP-packaged tile-type phased array module provided by an embodiment of the present disclosure is shown;

[0047] Fig. 22 A schematic diagram of the lower surface of the heat dissipation structure in the 256-channel AIP-packaged tile-type phased array module provided by an embodiment of the present disclosure is shown;

[0048] Fig.23 A schematic diagram of the upper surface of the waveguide flange structure cavity in a 256-channel AIP-packaged tile-type phased array module provided by an embodiment of the present disclosure is shown;

[0049] Fig.24 A schematic diagram of the lower surface of the waveguide flange structure cavity in a 256-channel AIP-packaged tile-type phased array module provided by an embodiment of the present disclosure is shown;

[0050] Explanation of the numbers in the schematic diagram:

[0051] 1 waveguide structure cavity, 2 heat dissipation structure cavity, 3 flange structure cavity, 4 waveguide hole, 5 rectangular groove, 6 rectangular hair button, 7 control board, 8AIP package chip, 9 waveguide interface, 10 through opening, 11 standard waveguide flange, 12 positioning pin, 13 electrical connector assembly groove, 14 magic T structure, 15 chip heat dissipation boss, 16 electrical connector wiring groove, 17 fastening screw, 18 through square hole, 19 BGA pad, 20 electrical connector welding port, 21 package substrate, 22 feed radiation patch, 23 T / R chip, 24 400um metal solder ball, 25 radiation array element, 26 thermal grease sheet, 27 90um diameter metal solder ball. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0053] In addition, the term "and / or" in this article is only a description of the association relationship between the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0054] In the present disclosure, a waveguide structure cavity that can transmit waveguide signals and dissipate heat for AIP packaged chips is used in conjunction with a control board that only transmits power and control signals, thereby achieving separate transmission of RF signals, power and control signals, improving the quality of RF signals, reducing the use of RF connectors, reducing design complexity, and improving the power capacity of phased array antennas.

[0055] In the following, in conjunction with the accompanying drawings, a 64-channel tile-type phased array module based on AIP package provided by the present disclosure is described in detail by taking an example of a tile-type phased array module based on AIP package.

[0056] The architecture and assembly method of the tile-type phased array module based on AIP packaging provided by the embodiment of the present disclosure are as follows: Figure 2 to Figure 4 As shown, the various parts of the phased array module are interconnected through SMT welding or fasteners to achieve the transmission and reception of RF signals in the W band and above.

[0057] Figure 5 A cross-sectional view of a 64-channel AIP-packaged tiled phased array module provided by an embodiment of the present disclosure is shown. Figure 5 It can be seen that in the phased array module architecture, the RF signal, digital signal and control signal are transmitted separately.

[0058] Figure 6 The side view of the 64-channel AIP-packaged tile-type phased array module provided by the embodiment of the present disclosure is shown. The AIP packaged chip 8 is connected to the control board 7 through several 400um solder balls on the lower surface, and the control board 7 carrying the AIP packaged chip 8 is connected to the waveguide structure cavity 1 through the four corners of the fastening screws 17. At this time, the RF feed signal is transmitted to the AIP packaged chip 8 through the waveguide hole 4 in the center of the waveguide structure cavity 1, and after being processed inside the AIP packaged chip 8, the radiation array element 25 on its upper surface transmits the signal outward, and the power supply and control signal are transmitted through the electrical connectors on both sides of the cavity.

[0059] The specific functions of each part of the 64-channel AIP-packaged tiled phased array module provided by the embodiment of the present disclosure are described in detail below with reference to the accompanying drawings.

[0060] The tile-type phased array module based on AIP packaging provided by the embodiment of the present disclosure comprises, from bottom to top: a waveguide structure cavity 1, a control board 7, and an AIP packaging chip 8.

[0061] like Fig.13 As shown, the center of the lower surface of the waveguide structure cavity 1 is a standard waveguide flange 11, and the center of the standard waveguide flange 11 is a waveguide hole 4. The standard waveguide flange 11 is provided with a positioning pin 12, and the standard waveguide flange 11 can be directly connected to a standard waveguide tube or a waveguide-coaxial adapter to realize the transmission of RF feeding signals. Two J30 electrical connector assembly grooves 13 are provided on both sides of the lower surface of the waveguide structure cavity 1, and J30 electrical connector wiring grooves 16 corresponding to the J30 electrical connector assembly grooves 13 are provided on both sides of the upper surface of the waveguide structure cavity 1. The J30 electrical connector can be fixed to the structure cavity by two screws, and the 30 signal pins in the middle are connected to the corresponding interface of the control board 7, so as to realize the transmission of power and control signals.

[0062] In this embodiment, the standard waveguide flange 11 with the positioning pins 12 can be directly connected to the standard waveguide tube or the waveguide-coaxial adapter to realize the transmission of the RF feeding signal, reduce the use of RF connectors, and reduce the cost of the tile-type phased array module based on AIP packaging.

[0063] In this embodiment, the center of the upper surface of the waveguide structure cavity 1 is the opening of the waveguide hole 4, that is, a standard rectangular waveguide opening. According to different working frequency bands, its length and width dimensions a and b are shown in Table 1. For the convenience of description, the opening of the waveguide hole 4 is referred to as a standard rectangular waveguide opening below.

[0064] The dimensions of standard rectangular waveguide models are shown in Table 1:

[0065] Table 1

[0066]

[0067]

[0068] In this embodiment, taking the BJ900 standard waveguide as an example, its length and width dimensions a and b are respectively: a=0.127 mm, b=0.254 mm, and the wall thickness of the rectangular waveguide is 0.5 mm.

[0069] like Fig.12 , Fig.16 As shown, a rectangular groove 5 is left between the inner wall and the outer wall of the standard rectangular waveguide port, and a rectangular fur button 6 is arranged in the rectangular groove 5. The size of the rectangular groove 5 is Wg*Lg*Hg*Dg. The calculation formula of the rectangular groove 5 is as follows:

[0070] Wg=0.5+Dg+b(mm);

[0071] Lg = 0.5 + Dg + a (mm);

[0072] Hg = 0.1 mm to 0.3 mm;

[0073] Dg=0.1mm~0.2mm.

[0074] Wherein, Wg is the width of the outer wall of the rectangular groove 5, Lg is the length of the outer wall of the rectangular groove 5, Hg is the depth of the rectangular groove 5, and Dg is the width of the rectangular groove 5. a is the length of the long side of the standard waveguide, b is the length of the short side of the standard waveguide, Hg and Dg are flexibly selected according to the size of the waveguide interface 9 of the customized AIP package chip 8. In this embodiment, Hg is selected as 0.3mm and Dg is selected as 0.2mm. Then the corresponding size of the rectangular groove 5 is:

[0075] Wg=1.97mm, Lg=3.24mm, Hg=0.3mm, Dg=0.2mm.

[0076] In this embodiment, if the standard rectangular waveguide opening of the waveguide structure cavity 1 and the waveguide interface 9 at the center of the lower surface of the AIP package chip are fixed only by four fastening screws 17 around them, gaps are likely to occur, resulting in discontinuity of the "RF grounding" and affecting the performance of the RF signal.

[0077] To solve the above problems, the present disclosure provides Fig.15 The rectangular wool button 6 is shown.

[0078] In this embodiment, the rectangular wool button 6 is realized by changing the winding method of the twist pin of the existing cylindrical wool button and processing it into the required rectangle.

[0079] In this embodiment, the rectangular wool button 6 is a waveguide-microstrip transmission conversion structure.

[0080] In this embodiment, the material used for the rectangular wool button 6 is brass plated with gold. Fig.15 As shown, the finished dimensions are W*L*H*D.

[0081] The calculation formula for the size of the rectangular wool button 6 is as follows:

[0082] W = Wg (mm);

[0083] L = Lg (mm);

[0084] D = Dg (mm);

[0085] H=Hg+0.1(mm).

[0086] Wherein, W is the width of the rectangular fur button 6, L is the length of the rectangular fur button 6, H is the height of the rectangular fur button 6, and D is the thickness of the rectangular fur button 6. According to the different signal frequency bands used and the changes in the size of the standard rectangular waveguide port, the size of the rectangular fur button 6 will also be adjusted accordingly.

[0087] The size of the rectangular fur button 6 is mainly affected by the size of the rectangular groove 5. Taking the above BJ900 standard rectangular waveguide as an example, the corresponding size of the rectangular fur button 6 is W = 3.24mm, L = 1.97mm, H = 0.4mm, D = 0.2mm. It can be seen that the height of the rectangular fur button 6 is 0.1mm greater than the depth of the rectangular groove 5.

[0088] like Fig.16 As shown, when in use, the processed rectangular wool button 6 can be embedded into the rectangular groove 5. The elasticity of the rectangular wool button 6 can be used to improve the problem of discontinuous grounding of the RF signal, and the soft-hard connection transition between the standard rectangular waveguide port and the AIP package chip 8 can be achieved.

[0089] like Fig.11As shown, the center of the control board 7 is provided with a through opening 10 and a group of through square holes 18, corresponding to a waveguide interface 9 and a group of flip-chip T / R chips 23 on the AIP package chip 8, which are used to directly connect the waveguide structure cavity 1 with the AIP package chip 8 to realize the transmission of radio frequency signals. The upper surface of the control board 7 is also provided with a BGA pad 19 connected to the 400um metal solder ball 24 on the lower surface of the AIP package chip 8. Two J30 electrical connector welding ports 20 are also provided on both sides of the control board 7 for transmitting control signals and power signals.

[0090] In this embodiment, the electrical connector welding ports 20 on both sides of the control board 7 correspond to the electrical connector wiring grooves 16 provided on both sides of the upper surface of the waveguide structure cavity 1 and the electrical connector assembly grooves 13 provided on both sides of the lower surface of the waveguide structure cavity 1 .

[0091] In this embodiment, the rectangular wool button 6 passes through the through opening 10 in the control board 7 to connect to the waveguide interface 9 on the lower surface of the AIP package chip 8 .

[0092] In this embodiment, the control board 7 is made of multi-layer high-frequency board materials and is mainly used to send external control signals and power signals to the AIP packaged chip 8.

[0093] In the prior art, the control board 7 generally needs to process and transmit radio frequency signals, control signals and power signals at the same time, while the control board 7 in the present disclosure only needs to transmit control signals and power signals.

[0094] In this embodiment, a group of 4.6mm*3.56mm chip heat dissipation bosses 15 are arranged around the standard rectangular waveguide opening, and their outer dimensions are the same as the size of the flip-mounted T / R chip 23 on the AIP package chip 8. When in use, the waveguide structure cavity 1 is connected to the control board 7 through four fastening screws 17, and the rectangular waveguide directly contacts the waveguide interface 9 on the lower surface of the AIP package chip 8 to achieve waveguide transmission of the RF signal. At this time, the chip heat dissipation boss 15 passes through the through square hole 18 in the control board 7 and contacts the flip-mounted T / R chip 23 on the AIP package chip 8 to achieve heat dissipation and reduce the working temperature of the chip.

[0095] In this embodiment, each group of chip heat dissipation bosses 15 includes four chip heat dissipation bosses 15 , and the corresponding through square holes 18 and T / R chips 23 also include four.

[0096] In this embodiment, an elastic thermally conductive silicone grease sheet 26 is disposed between the flipped T / R chip 23 and the chip heat dissipation boss 15 to accelerate the heat dissipation of the T / R chip 23, thereby ensuring the stability of the electrical performance of the phased array module.

[0097] In this embodiment, the size of the entire waveguide structure cavity 1 is 50mm*50mm*8mm, wherein the standard waveguide flange 11 is 3mm thick. According to the actual use space, the size of the entire waveguide structure cavity 1 can also be reduced to 30mm*30mm*4mm, in which case only a smaller electrical connector needs to be selected for the transmission of power and control signals.

[0098] In this embodiment, the waveguide structure cavity 1 adopts the H59 copper nickel-gold plating process.

[0099] In the prior art, the structural cavity is usually only used for physical support and heat dissipation.

[0100] In this embodiment, the waveguide structure cavity 1 not only provides physical support and heat dissipation, but also realizes the transmission of radio frequency signals and power synthesis.

[0101] In this embodiment, the AIP package chip 8 is composed of a feeding radiation patch 22 , a T / R chip 23 , a 400 um metal solder ball 24 , an AIP package substrate 21 , and a radiation array element 25 .

[0102] In this embodiment, the upper surface of the packaging substrate 21 of the AIP packaged chip 8 is a radiation element 25 layer, the lower surface of the packaging substrate 21 of the AIP packaged chip 8 is an RF feeding layer, and the center of the lower surface is a feeding radiation patch 22, which is located in the waveguide interface 9. The RF feeding port of the patch is connected to the flip-chip T / R chip 23 through a board-level transmission line to realize the energy conversion of microstrip-waveguide. 400um metal solder balls 24 are also arranged on both sides of the lower surface of the packaging substrate 21, and the solder balls are used to realize the interaction between the power supply and control signal in the AIP packaged chip 8 and the external control board 7. The packaging substrate 21 of the AIP packaged chip 8 is made of high-frequency plate material pressed together, and the interior is divided into multiple layers, which is used to realize the power distribution and signal transmission between the feeding radiation patch 22 and the T / R chip 23, the RF signal transmission and distribution between the T / R chip 23 and the feeding radiation patch 22, and the power supply signal and control signal of the T / R chip 23 are transmitted to the 400um metal solder balls 24.

[0103] like Figure 7 As shown, the upper surface of the packaging substrate 21 is a radiation element 25 layer, which is composed of 64 radiation antenna patches arranged with a spacing of 2.125 mm, and is used to radiate signals to the outside or receive external signals to achieve signal transmission and reception.

[0104] like Fig. 9As shown, the lower surface of the package substrate is an RF feeding layer, which is flipped with a group of T / R chips 23 through 90um metal solder balls 27, and its size is 3.56mm*4.6mm*0.11mm. The center of the lower surface is a feeding radiation patch 22, which is surrounded by a waveguide interface 9. The RF feeding port of the feeding radiation patch 22 is connected to the flipped T / R chip 23 through a board-level transmission line to achieve microstrip-waveguide energy conversion.

[0105] In this embodiment, the T / R chip 23 is used to process the signals received by the 64 radiating patch antennas, or to process the signals at the feeding radiating patch 22 end and transmit them to the 64 radiating patch antennas for information transmission.

[0106] like Fig.10 As shown, there are multiple 400um metal solder balls 24 on both sides of the lower surface of the packaging substrate 21, which are used to connect the BGA pads 19 on the upper surface of the control board to realize the interaction between the power supply and control signals in the AIP package chip 8 and the external control board 7.

[0107] In this embodiment, the packaging substrate 21 is made of high-frequency plate materials pressed together and is divided into multiple layers inside, which is used to realize power distribution and signal transmission between the feeding radiation patch 22 and the T / R chip 23, RF signal transmission and distribution between the T / R chip 23 and 64 radiation patch antennas, and also used to transmit the power signal and control signal of the T / R chip 23 to the 400um metal solder ball 24.

[0108] In the prior art, the 400um metal solder balls 24 on the lower surface of the AIP packaged chip 8 not only need to transmit power and control signals, but also need to transmit radio frequency signals, which increases the transmission loss of the radio frequency signals.

[0109] In this embodiment, if Figure 8 As shown, the thickness of the flip-chip T / R chip 23 is 110um, and the small BGA solder ball is a metal solder ball with a diameter of 90um. In order to avoid interference between the flip-chip T / R chip 23 on the back and the control board 7 during AIP chip welding, the diameter of the large BGA solder ball needs to be greater than the height of the flip-chip T / R chip 23, that is, greater than 300um. Therefore, a metal solder ball with a diameter of 400um is selected in this embodiment.

[0110] like Figure 1 As shown in the figure, when using BGA large solder balls for W-band signal transmission, the simulation results show that the impedance of the BGA large solder balls does not match the AIP package chip 8 and the control board 7, resulting in large transmission loss and poor return loss. Generally speaking, the return loss dB (S (1,1)) curve should be less than -10dB in the working frequency band, but the simulation shows that the return loss is only -3dB, so it is not suitable to use BGA large solder balls to transmit W-band signals.

[0111] In this embodiment, if Fig.10 As shown, the 400 um metal solder ball 24 on the lower surface of the AIP packaged chip 8 only transmits power and control signals, and the RF signal is transmitted by the feeding radiation patch 22 .

[0112] In this embodiment, the AIP packaged chip 8 is a customized chip. Depending on the frequency band used, the T / R chip 23 of different frequency bands can be flipped and designed to meet the BJ900~BJ2600 standard rectangular waveguide port required by the national standard, which is used to realize the AIP packaged tile-type phased array module with an operating frequency band of 92GHz~0.3THz.

[0113] like Figure 2 to Figure 6 As shown, the 64-channel AIP-packaged tiled phased array module comprises, from bottom to top: a waveguide structure cavity 1, a control board 7, four pieces of thermal conductive silicone grease 26, a rectangular wool button 6, and an AIP package chip 8.

[0114] In this embodiment, the upper surface of the waveguide structure cavity 1 has a group of chip heat dissipation bosses 15, a standard rectangular waveguide opening, a rectangular groove 5, and a rectangular button 6. The two sides are wiring grooves 16 of the J30 electrical connector.

[0115] In this embodiment, the center of the lower surface of the waveguide structure cavity 1 is a standard waveguide flange 11, and the two sides are assembly grooves 13 of the J30 electrical connector.

[0116] In this embodiment, the control board 7 has an outer dimension of 50 mm*50 mm, and has a through opening 10, a group of through square holes 18, and a group of BGA pads 19 in the center of the control board 7. The control board 7 has J30 electrical connector welding ports 20 corresponding to the wiring grooves 16 and the assembly grooves 13 of the J30 electrical connector on both sides.

[0117] In this embodiment, the AIP package chip 8 is composed of 64 radiating patch antennas, an AIP package substrate 21 , 4 flip-chip T / R chips 23 , 400 um metal solder balls 24 and a feeding radiating patch 22 .

[0118] In this embodiment, the size of the AIP packaged chip 8 is 17 mm*17 mm*1.06 mm.

[0119] In this embodiment, the waveguide signal is transmitted from the waveguide hole 4 in the waveguide structure cavity 1 through the through opening 10 in the control board 7 to the AIP package chip 8, and the space radiation task is completed through the AIP package chip 8.

[0120] The above embodiment is described in detail by taking a 64-channel AIP-packaged tiled phased array module as an example.

[0121] The following introduces a tiled phased array module based on AIP package with a larger array surface by taking a 256-channel tiled phased array module based on AIP package as an example in conjunction with the accompanying drawings.

[0122] like Figure 17-Figure 19 As shown, the architecture of the 256-channel AIP-packaged tile phased array module is as follows from bottom to top: a waveguide structure cavity 1 composed of a flange structure cavity 3 and a heat dissipation structure cavity 2, a control board 7, 16 pieces of thermal conductive silicone grease 26, 4 rectangular wool buttons 6, and 4 AIP packaged chips 8. Among them, the 4 AIP packaged chips 8 arranged in a 2*2 arrangement are connected to the control board 7 through multiple 400um metal solder balls 24.

[0123] In this embodiment, in order to facilitate the processing of the magic T structure 14 inside the waveguide structure cavity 1, the originally integrated waveguide structure cavity 1 is divided into a heat dissipation structure cavity 2 and a flange structure cavity 3.

[0124] like Fig.21 As shown, the upper surface of the heat dissipation structure cavity 2 has four groups of chip heat dissipation bosses 15, four rectangular grooves 5, four rectangular hairy buttons 6, and four standard rectangular waveguide openings.

[0125] like Fig. 22 As shown, the heat dissipation structure cavity 2 realizes the synthesis of waveguide signals of four AIP packaged chips 8 through the magic T structure 14, reducing the original four waveguide signal feeding ports to one. The length and width of the magic T structure 14 are the same as the size of the waveguide hole 4, which is 1.27mm*2.54mm in this embodiment.

[0126] like Fig.23 , Fig.24 As shown, the center of the upper surface of the flange structure cavity 3 is a standard rectangular waveguide opening of 1.27 mm x 2.54 mm, which is used to realize the magic T structure 14, and the center of the lower surface of the flange structure cavity 3 is a standard waveguide flange 11. The flange structure cavity 3 is mechanically connected to the heat dissipation structure cavity 2 by fastening screws 17.

[0127] like Fig. 20 As shown, the outer dimensions of the control board 7 remain unchanged at 50 mm*50 mm, and there are 4 through openings 10, 4 groups of through square holes 18 and 4 groups of BGA pads 19 for soldering the AIP packaged chip 8 in the center of the control board 7.

[0128] In this embodiment, the waveguide signal enters the heat dissipation structure cavity 2 from the waveguide hole 4 in the flange structure cavity 1 through the magic T structure 14, and is then transmitted to the corresponding AIP packaged chip 8 through the waveguide hole 4 in the heat dissipation structure cavity 2, and the space radiation task is completed through the AIP packaged chip 8.

[0129] In this embodiment, the control board 7 is a control board 7 that carries a plurality of AIP packaged chips 8 .

[0130] In this embodiment, when the control board carries N AIP packaged chips 8: the waveguide structure cavity 1 is divided into a heat dissipation structure cavity 2 and a flange structure cavity 3; at this time, N waveguide holes 4 are arranged in the heat dissipation structure cavity 2; a magic T structure 14 is arranged on the lower surface of the heat dissipation structure cavity 2; the magic T structure 14 connects the waveguide holes 4 in the heat dissipation structure cavity 2 and the flange structure cavity 3 respectively; the upper surface of the heat dissipation structure cavity 2 is provided with N rectangular grooves 5 and rectangular fur buttons 6 corresponding to the waveguide holes 4; the control board 7 is provided with N through openings 10 corresponding to the waveguide holes 4. N groups of chip heat dissipation bosses 15 are also arranged on the upper surface of the heat dissipation structure cavity 2; N groups of through square holes 18 corresponding to the chip heat dissipation bosses 15 are also arranged in the control board 7; and N groups of flip-chip T / R chips 23 corresponding to the chip heat dissipation bosses 15 are arranged on the lower surface of the AIP packaged chip 8.

[0131] In this embodiment, when a plurality of AIP packaged chips 8 are arrayed, the waveguide structure cavity 1 and the control board 7 can be designed according to the number and arrangement of the AIP packaged chips 8 .

[0132] like Fig. 20 As shown, taking 4 2x2 arrayed AIP packaged chips 8 as an example, at this time, the waveguide structure cavity 1 is divided into a heat dissipation structure cavity 2 and a flange structure cavity 3. Among them, the structure of the flange structure cavity 3 remains unchanged, and there are 4 waveguide holes 4 in the heat dissipation structure cavity 2; a magic T structure 14 is provided on the lower surface of the heat dissipation structure cavity 2, and the magic T structure 14 connects the waveguide holes 4 in the heat dissipation structure cavity 2 and the flange structure cavity 3 respectively; the upper surface of the heat dissipation structure cavity 2 has 4 standard rectangular waveguide ports, 4 rectangular grooves 5 and 4 fur buttons 6, and 4 groups of chip heat dissipation bosses 15; the corresponding control board has 4 through openings 10 and 4 groups of through square holes 18, and 4 groups of BGA pads 19.

[0133] In this embodiment, it is only necessary to change the working frequency band of the AIP packaged chip 8 and modify the size of the waveguide structure cavity 1 and the size of the control board 7 accordingly. This solution can be applied to the Ku band, Ka waveguide, E band, W band and terahertz band.

[0134] According to the idea of ​​the 256-channel AIP-packaged tiled phased array module composed of four 2x2-arranged AIP packaged chips 8 in this embodiment, 3x3 (576 channels), 4x4 (1024 channels), and NxN tiled phased array modules can be easily realized. The present disclosure can form regular or irregular phased array modules of any scale according to the needs of use, and has greater array flexibility.

[0135] According to the embodiments of the present disclosure, the following technical effects are achieved:

[0136] In this embodiment, in view of the problems of large loss, complex structure, multiple connectors and high cost of the tile-type phased array module based on AIP packaging, a waveguide structure cavity is proposed that can not only transmit waveguide signals through waveguide holes, but also dissipate heat for AIP packaged chips through chip heat dissipation bosses. In combination with a control board that only transmits power and control signals, there is no need to consider the shielding isolation problem of RF signals and power control signals, and the separation transmission of RF signals and control signals is realized, which improves the quality of RF signals, reduces the design complexity, and increases the power capacity of signals, providing a physical basis for the realization of high-power phased array antennas. The structure is used as a basic unit to introduce in detail the array formation method of 64 channels, 256 channels and arrays of any scale, which can meet the use requirements of W band and above frequency bands, and can be widely used in aviation, aerospace, communications and other fields.

[0137] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should be aware that the present disclosure is not limited by the order of the actions described, because according to the present disclosure, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present disclosure.

[0138] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0139] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A tiled phased array module based on AIP packaging, characterized in that: The phased array modules are as follows from bottom to top: A waveguide structure cavity (1), a control board (7), and an AIP package chip (8); wherein: A waveguide hole (4) penetrating the waveguide structure cavity (1) is arranged at the center of the waveguide structure cavity (1); electrical connector assembly grooves (13) are arranged on both sides of the lower surface of the waveguide structure cavity (1); electrical connector wiring grooves (16) corresponding to the electrical connector assembly grooves (13) are arranged on both sides of the upper surface; and a chip heat dissipation boss (15) is also arranged on the upper surface; A rectangular groove (5) is arranged around the opening of the waveguide hole (4); a rectangular wool button (6) is arranged in the rectangular groove (5); The control board (7) is provided with a through opening (10) at the center, and electric connector welding ports (20) corresponding to the electric connector assembly groove (13) and the electric connector wiring groove (16) are provided on both sides of the control board (7), and the control board (7) is also provided with a through square hole (18) corresponding to the chip heat dissipation boss (15); A waveguide interface (9) is arranged at the center of the lower surface of the AIP package chip (8), and a flip-chip T / R chip (23) corresponding to the chip heat dissipation boss (15) is also arranged on the lower surface of the AIP package chip (8); The rectangular wool button (6) passes through the through opening (10) at the center of the control board (7) and is connected to the waveguide interface (9) at the center of the lower surface of the AIP package chip (8); The chip heat dissipation boss (15) passes through the through square hole (18) and contacts the T / R chip (23) to dissipate heat; The waveguide structure cavity (1) further comprises a standard waveguide flange (11) located at the center of the lower surface and directly connected to the standard waveguide tube and the standard waveguide-coaxial adapter; The standard waveguide flange (11) is provided with a positioning pin (12).

2. The phased array module according to claim 1, characterized in that: The upper surface of the control board (7) is also provided with a BGA pad (19); The lower surface of the AIP packaged chip (8) is also provided with a 400 um metal solder ball (24) corresponding to the BGA solder pad (19).

3. The phased array module according to claim 1, characterized in that: The AIP packaged chip (8) further comprises: A packaging substrate (21); A feeding radiation patch (22) located in the waveguide interface (9) on the lower surface of the packaging substrate (21); A radiation array element (25) is located on the upper surface of the packaging substrate (21).

4. The phased array module according to claim 1, characterized in that: The control board (7) carries a plurality of the AIP packaged chips (8).

5. The phased array module according to claim 4, characterized in that: When the control board (7) carries N AIP packaged chips (8): The waveguide structure cavity (1) is divided into a heat dissipation structure cavity (2) and a flange structure cavity (3); At this time, N waveguide holes (4) are provided in the heat dissipation structure cavity (2); A magic T structure (14) is provided on the lower surface of the heat dissipation structure cavity (2); The magic T structure (14) is respectively connected to the waveguide holes (4) in the heat dissipation structure cavity (2) and the flange structure cavity (3); The upper surface of the heat dissipation structure cavity (2) is provided with N rectangular grooves (5) and rectangular fur buttons (6) corresponding to the waveguide holes (4); The control board (7) is provided with N through openings (10) corresponding to the waveguide holes (4).

6. The phased array module according to claim 5, characterized in that: When the control board (7) carries N AIP packaged chips (8): The upper surface of the heat dissipation structure cavity (2) is also provided with N groups of chip heat dissipation bosses (15); The control board (7) is also provided with N groups of through square holes (18) corresponding to the chip heat dissipation bosses (15); The lower surface of the AIP packaged chip (8) is provided with N groups of flip-chip T / R chips (23) corresponding to the chip heat dissipation bosses (15).

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