Array substrate and display device

Abstract

An array substrate, the array substrate (10) comprising: a first substrate (101), and a plurality of pixel groups (A) and a plurality of columns of data lines (102) formed on the first substrate; the plurality of pixel groups are arranged in an array in the row direction (X) and the column direction (Y), each pixel group includes two sub-pixels arranged in the row direction; at least one sub-pixel of one of any two adjacent pixel groups in the row direction has the same color as one sub-pixel of the other; and the colors corresponding to any two adjacent sub-pixels in the row direction are different; each column of data lines and each column of pixel groups are alternately arranged in the row direction, each column of data lines is connected to each sub-pixel located in the same column and having the same corresponding color, and each column of data lines is connected to two sub-pixels having the same corresponding color in two pixel groups adjacent to its two sides in the row direction. The display effect of the array substrate can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to an array substrate and a display device. Background Art

[0002] With the continuous development of liquid crystal panels, high-resolution products have been continuously developed; however, current high-resolution products have a problem of insufficient charging, which easily causes phenomena such as horizontal stripes or vertical stripes in the products.

[0003] Disclosure Content

[0004] The purpose of the present disclosure is to provide an array substrate and a display device, thereby at least to some extent overcoming one or more problems caused by the limitations and defects of the related technologies.

[0005] The first aspect of the present disclosure provides an array substrate, which includes: a first substrate and a plurality of pixel groups and a plurality of columns of data lines formed on the first substrate;

[0006] The plurality of pixel groups are arranged in an array in the row direction and the column direction, and each pixel group includes two sub-pixels arranged in the row direction; at least one sub-pixel of one of any two adjacent pixel groups in the row direction has the same color as one sub-pixel of the other; and the colors corresponding to any two adjacent sub-pixels in the row direction are different;

[0007] Each column of the data lines and each column of the pixel groups are alternately arranged in the row direction, each column of the data lines is connected to the sub-pixels in the same column and having the same corresponding color, and each column of the data lines is connected to two sub-pixels in the two pixel groups adjacent to it on both sides in the row direction and having the same corresponding color.

[0008] In an exemplary embodiment of the present disclosure, the array substrate further includes a plurality of scan line groups;

[0009] Each scan line group includes two rows of scan lines, namely a first scan line and a second scan line, and the first scan line and the second scan line in each scan line group are respectively located on opposite sides of each row of pixel groups in the column direction;

[0010] Among them, the sub-pixels located in the even columns are connected to the adjacent first scan line, and the sub-pixels located in the odd columns are connected to the adjacent second scan line.

[0011] In an exemplary embodiment of the present disclosure,

[0012] Each of the sub-pixels in each row is divided into a plurality of pixel units arranged in sequence in the row direction, and each pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in sequence in the row direction;

[0013] Among them, the colors corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel are all different.

[0014] In an exemplary embodiment of the present disclosure, the sub-pixel includes a pixel electrode and a transistor; among them,

[0015] The gate of the transistor is a partial structure of the scan line;

[0016] The first pole of the transistor is arranged on the same layer as the data line and is connected;

[0017] The second pole of the transistor is arranged on the same layer as the data line, and a part of the second pole of the transistor is in contact with the pixel electrode.

[0018] In an exemplary embodiment of the present disclosure,

[0019] The scan line includes a plurality of scan segments arranged in sequence and connected in the row direction; each of the scan segments includes a first part, a transition connection part, and a second part arranged in sequence and connected in the row direction; the widths of the first part and the second part are greater than the width of the transition connection part, and the first part, the transition connection part, and the second part enclose a groove structure;

[0020] The orthographic projection of the active layer of the transistor on the first substrate is located within the orthographic projection of the first part on the first substrate, and a part of the first part constitutes the gate of the transistor;

[0021] The second pole of the transistor includes a first contact part in contact with the pixel electrode, a second contact part in contact with the active layer, and an electrode connection part connecting the first contact part and the second contact part;

[0022] Among them, the orthographic projection of the electrode connection part of the second pole on the first substrate overlaps with the orthographic projections of the first part, the second part, and the groove structure on the first substrate, and does not overlap with the orthographic projection of the transition connection part on the first substrate.

[0023] In an exemplary embodiment of the present disclosure, in each of the scan line groups:

[0024] The first part of the first scan line is opposite to the second part of the second scan line in the column direction, and the second part of the first scan line is opposite to the first part of the second scan line in the column direction;

[0025] Moreover, the notch orientation of the groove structure of the first scanning line is opposite to that of the second scanning line.

[0026] In an exemplary embodiment of the present disclosure,

[0027] The sub-pixel further includes a common electrode, which is located on a side of the pixel electrode away from the first substrate and is insulated from the pixel electrode;

[0028] Wherein, the orthographic projection of the common electrode on the first substrate overlaps with the orthographic projection of the pixel electrode on the first substrate.

[0029] In an exemplary embodiment of the present disclosure,

[0030] The common electrode includes a first edge conductive portion and a second edge conductive portion that are opposite and spaced apart in the column direction, and a plurality of first electrode strips that are located between the first edge conductive portion and the second edge conductive portion and are spaced apart in the column direction;

[0031] Moreover, the common electrode further includes a first conductive connection strip extending in the column direction, and the first conductive connection strip is located on the same side of the first edge conductive portion, the second edge conductive portion, and the plurality of first electrode strips in the row direction and is connected to the first edge conductive portion, the second edge conductive portion, and the plurality of first electrode strips;

[0032] Wherein, in the common electrode, the gap between the first electrode strip and the first edge conductive portion, the gap between two adjacent first electrode strips, and the gap between the first electrode strip and the second edge conductive portion are all first gaps, the extending direction of the first gap is the same as the extending direction of the first electrode strip, and the extending direction of the first electrode strip intersects both the row direction and the column direction.

[0033] In an exemplary embodiment of the present disclosure, in the common electrode, the end of the first gap away from the first conductive connection strip is in an open shape.

[0034] In an exemplary embodiment of the present disclosure,

[0035] The common electrode has a first group and a second group arranged in the column direction. The first group includes a plurality of first electrode strips arranged at intervals in the column direction and a first edge conductive portion located on a side of the plurality of first electrode strips away from the second group; the second group includes a plurality of second electrode strips arranged at intervals in the column direction and a second edge conductive portion located on a side of the plurality of second electrode strips away from the first group;

[0036] The common electrode further has a first conductive connection bar extending in the column direction, the first conductive connection bar being located on the same side of the first group and the second group in the row direction and connecting to the first edge conductive part, each of the first electrode bars, each of the second electrode bars, and the second edge conductive part;

[0037] Wherein, in the common electrode, the gap between the first electrode bar and the first edge conductive part and the gaps between two adjacent first electrode bars are all first gaps, the gap between the second electrode bar and the second edge conductive part and the gaps between two adjacent second electrode bars are all second gaps, the extending direction of the first gap is the same as the extending direction of the first electrode bar and intersects both the row direction and the column direction, the extending direction of the second gap is the same as the extending direction of the second electrode bar and intersects both the row direction and the column direction; and the extending direction of the first electrode bar intersects the extending direction of the second electrode bar.

[0038] In an exemplary embodiment of the present disclosure, the common electrode further has a second conductive connection bar and a conductive adjustment part connected to the second conductive connection bar, the second conductive connection bar extending in the column direction, the conductive adjustment part being located on the side of the second conductive connection bar close to the first conductive connection bar and between the first group and the second group; wherein,

[0039] One ends of the first electrode bars in the first group close to the second group and the second electrode bars in the second group close to the first group, which are far from the first conductive connection bar, are both connected to the second conductive connection bar;

[0040] The gap formed between the conductive adjustment part and the first electrode bar is a third gap, and the extending direction of the third gap is the same as the extending direction of the first gap;

[0041] The gap formed between the conductive adjustment part and the second electrode bar is a fourth gap, and the extending direction of the fourth gap is the same as the extending direction of the second gap.

[0042] In an exemplary embodiment of the present disclosure, the widths of the first electrode bar and the second electrode bar are equal, and the widths of the first gap, the second gap, the third gap, and the fourth gap are equal.

[0043] In an exemplary embodiment of the present disclosure, the ends of the first gap and the second gap far from the first conductive connection bar are open.

[0044] In an exemplary embodiment of the present disclosure, the common electrode is of an integral structure, and the common electrode is symmetrically arranged in a mirror image about the row direction.

[0045] In an exemplary embodiment of the present disclosure, in the pixel group, the common electrodes of the two sub-pixels are arranged in mirror symmetry with respect to the column direction, and share the first conductive connection bar to form an electrode mirror unit.

[0046] In an exemplary embodiment of the present disclosure, the array substrate further includes a plurality of common line groups, each common line group being located between the first scan line and the second scan line of a scan line group; and each common line group includes two common lines arranged in the same layer as the scan lines, namely a first common line and a second common line, and the first common line and the second common line in each common line group are respectively located on opposite sides of each row of pixel groups in the column direction; wherein,

[0047] The positive projection of the first edge conductive part of the electrode mirror unit on the first substrate overlaps with the positive projection of the first common line on the first substrate, and is connected to the first common line through a first via hole.

[0048] The positive projection of the second edge conductive part of the electrode mirror unit on the first substrate overlaps with the positive projection of the second common line on the first substrate, and is connected to the second common line through a second via hole.

[0049] In an exemplary embodiment of the present disclosure,

[0050] At least a part of the positive projection of the first via hole on the first substrate overlaps with the positive projection of the first common line on the first substrate;

[0051] At least a part of the positive projection of the second via hole on the first substrate overlaps with the positive projection of the second common line on the first substrate.

[0052] In an exemplary embodiment of the present disclosure, each common line group further includes a plurality of common connection lines arranged at intervals in the row direction and located between the first common line and the second common line, the common connection lines extending in the column direction and arranged in the same layer as the scan lines, and both ends of the common connection lines are respectively connected to the first common line and the second common line;

[0053] Wherein, the positive projection of the first conductive connection bar of each electrode mirror unit on the first substrate is located within the positive projection of a common connection line on the first substrate.

[0054] In an exemplary embodiment of the present disclosure,

[0055] A jumper wire is also provided between two adjacent electrode mirror units in the column direction; wherein,

[0056] The jumper wire is disposed on the same layer as the electrode mirror unit and is connected to two adjacent electrode mirror units in the column direction.

[0057] In an exemplary embodiment of the present disclosure, the jumper wire has a first connection portion, an intermediate connection portion, and a second connection portion that are arranged in sequence and connected in the column direction, and the widths of the first connection portion and the second connection portion are greater than the width of the intermediate connection portion;

[0058] Wherein, the middle region of the edge of one of two adjacent electrode mirror units in the column direction is in contact with the first connection portion, and the middle region of the edge of the other is in contact with the second connection portion.

[0059] In an exemplary embodiment of the present disclosure,

[0060] The orthographic projection of the first connection portion on the first substrate and the orthographic projection of the first transfer via hole on the first substrate have at least partial overlap;

[0061] The orthographic projection of the second connection portion on the first substrate and the orthographic projection of the second transfer via hole on the first substrate have at least partial overlap.

[0062] In an exemplary embodiment of the present disclosure, the data line has an alignment portion configured to be aligned with the spacer, and the orthographic projection of the alignment portion on the first substrate is located between adjacent two rows of the pixel groups;

[0063] Wherein, the width of other parts of the data line except the alignment portion is smaller than the width of the alignment portion; and the orthographic projection of the surface of the spacer close to the array substrate on the first substrate is located within the orthographic projection of the alignment portion on the first substrate.

[0064] In an exemplary embodiment of the present disclosure, the orthographic projection of the alignment portion on the first substrate is located between the orthographic projections of the first scan line of one of two adjacent scan line groups and the second scan line of the other on the first substrate.

[0065] A second aspect of the present disclosure provides a display device, which includes the array substrate described in any one of the above and a counter substrate disposed opposite to the array substrate.

[0066] Other features and advantages of the present disclosure will become apparent through the following detailed description, or will be partially learned through the practice of the present disclosure.

[0067] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit the present disclosure. Brief Description of the Drawings

[0068] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0069] Figure 1 Shows a schematic structural diagram of an array substrate in the related art;

[0070] Figure 2 Shows Figure 1 a timing diagram of the array substrate shown;

[0071] Figure 3 Shows a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;

[0072] Figure 4 Shows Figure 3 a timing diagram of the array substrate shown;

[0073] Figure 5 Shows a schematic structural diagram of each film layer stacked in an array substrate according to an embodiment of the present disclosure;

[0074] Figure 6 Shows a schematic cross-sectional structural diagram of an array substrate according to an embodiment of the present disclosure;

[0075] Figure 7 Shows Figure 5 a schematic structural diagram of a scanning segment of a scanning line in the array substrate shown in;

[0076] Figure 8 Shows Figure 5 a schematic structural diagram of a second pole of a transistor in the array substrate shown in;

[0077] Figure 9 Shows a schematic structural diagram of an electrode mirror unit in an array substrate according to an embodiment of the present disclosure;

[0078] Figure 10 Shows a schematic layout diagram of a plurality of electrode mirror units according to an embodiment of the present disclosure;

[0079] Figure 11 Shows a schematic layout diagram of a plurality of electrode mirror units according to another embodiment of the present disclosure;

[0080] Figure 12Shows a schematic structural diagram of an electrode mirror unit in an array substrate according to another embodiment of the present disclosure;

[0081] Figure 13 Shows Figure 5 A schematic structural diagram of a common line group in the array substrate shown in;

[0082] Figure 14 Shows a schematic diagram of the positional relationship between a plurality of electrode mirror units and a common line group according to an embodiment of the present disclosure;

[0083] Figure 15 Shows Figure 5 A schematic diagram of the positional relationship between the array substrate and the spacer shown in. Description of the Drawings

[0085] 10. Array substrate; 101. First substrate; A. Pixel group; A1. First sub-pixel; A2. Second sub-pixel; A3. Third sub-pixel; 102. Data line; 1021. Alignment part; X. Row direction; Y. Column direction; 103a. First scanning line; 103b. Second scanning line; 1031. First part; 1032. Transition connection part; 1033. Second part; 1034. Groove structure; 104. Pixel electrode; 1051. First pole; 1052. Second pole; 10521. First contact part; 10522. Second contact part; 10523. Electrode connection part; 1053. Active layer; 106. Common electrode; 1061. First edge conductive part; 1062. Second edge conductive part; 1063. First electrode strip; 1064. First conductive connection strip; 1065. Second electrode strip; 1066. Second conductive connection strip; 1067. Conductive adjustment part; S1. First gap; S2. Second gap; S3. Third gap; S4. Fourth gap; 107a. First common line; 107b. Second common line; 107c. Common connection line; H1. First transfer via; H2. Second transfer via; 108. Jumper wire; 1081. First connection part; 1082. Intermediate connection part; 1083. Second connection part; 109. Gate insulating layer; 110. Passivation layer; 20. Spacer. Detailed Embodiments

[0086] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed description will be omitted.

[0087] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the drawings. It can be understood that if the device of the icon is flipped so that it is upside down, the component described as "upper" will become the component described as "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0088] The terms "a", "an", "the", "said" and "at least one" are used to denote the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to denote an open-ended inclusion meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0089] The resolution of a conventional 8K display panel is 7680×4320, that is: it has 7680 columns of pixel units and 4320 rows of pixel units, wherein each pixel unit includes three sub-pixels.

[0090] In an 8K display panel, for a single-gate (that is: each row of pixel units is driven by a row of scan lines) pixel architecture, each column of sub-pixels is paired with a data line. That is to say, a total of 7680×3 (23040) data lines are required in the entire 8K display panel. Taking each data driver IC (integrated circuit) driving 960 data lines as an example, 24 data driver ICs are required to drive an 8K resolution display panel.

[0091] It should be noted that the data driver IC mentioned in this disclosure can be fixed on a flexible printed circuit board, that is: this data driver IC can also be called a COF (Chip On Film), but it is not limited to this. The data driver IC can also be directly integrated on an array substrate, etc.

[0092] In an 8K display panel, for a double-gate (that is: each row of pixel units is driven by two rows of scan lines) pixel architecture, every two adjacent columns of sub-pixels are paired with a data line. In this way, compared with the aforementioned single-gate pixel architecture, the number of COFs for driving the data lines can be reduced by half, that is: it becomes 12 COFs, which can greatly reduce the manufacturing cost of the panel.

[0093] Based on the foregoing, it can be known that in an 8K display panel, in a single-gate pixel architecture, the number of scan lines is 4,320 rows. Taking a frame frequency of 60Hz as an example, the charging time for each row of pixel units is 3.7us. For a dual-gate pixel architecture, the halving of the number of data lines is based on doubling the number of scan lines. The number of scan lines is 4,320×2 (a total of 8,640) rows. At a frame frequency of 60Hz, the charging time for each row of pixels is reduced to 1.85us. That is to say, the charging rate of pixels in the dual-gate pixel architecture is greatly reduced compared to that in the single-gate pixel architecture, and it is easy to have more image quality problems.

[0094] Figure 1 FIG. shows an array substrate with a dual-gate pixel architecture mentioned in the related art; as Figure 1 shown, this array substrate may include a plurality of pixel units arranged in an array in the row direction X and the column direction Y. Each pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel arranged in the row direction X. Among them, for the convenience of subsequent description, each row of pixel units can be divided into a plurality of pixel groups A arranged in sequence in the row direction X. Each pixel group A includes two adjacent sub-pixels in the row direction X. For example, two adjacent pixel units in the row direction X can be divided into three pixel groups. It should be noted that the red sub-pixel refers to the sub-pixel corresponding to the red filter block, the green sub-pixel refers to the sub-pixel corresponding to the green filter block, and the blue sub-pixel refers to the sub-pixel corresponding to the blue filter block.

[0095] As Figure 1 shown, this array substrate may further include a plurality of columns of data lines 102 and a plurality of scan line groups. Among them, each column of data lines 102 and each column of pixel groups A are alternately arranged in the row direction X; and the two sub-pixels of each pixel group A are connected to the same column of data lines 102, and two adjacent pixel groups A in the column direction Y are respectively connected to different columns of data lines 102. Each scan line group corresponds to a row of pixel groups A. Specifically, each scan line group may include two scan lines, namely the first scan line 103a and the second scan line 103b. The first scan line 103a and the second scan line 103b of each scan line group are respectively located on the opposite sides of a row of pixel groups in the column direction Y, and the first scan line 103a in each scan line group is connected to the sub-pixels located in odd columns in a row of pixel groups A, and the second scan line 103b is connected to the sub-pixels located in even columns in this row of pixel groups.

[0096] Based on Figure 1 the array substrate shown, during the image quality test process, for example: during the image quality test of monochromatic red, monochromatic green, monochromatic blue, red-green mixing, blue-green-red, and red-blue mixing, there will be a problem that some sub-pixels have pre-charging resulting in a long charging time, and some sub-pixels do not have pre-charging resulting in a short charging time, thus easily causing problems of horizontal stripes or vertical stripes.

[0097] Taking the display of a monochromatic red screen as an example: The high level of each scanning line lasts for 4H. It should be noted that in this disclosure, 4H is taken as an example, and actually 2H / 3H / 4H / 5H / 6H / 7H / 8H are all applicable to the technology of this disclosure. Combining Figure 1 and Figure 2 as shown, the gate signals corresponding to the red sub-pixels R1 / R2 / R3 / R4 are G1 / G2 / G3 / G4 respectively. The actual data charging time of the red sub-pixels R1 / R2 / R3 / R4 is only the last 1H time within the 4H high level time of the gate signals G1 / G2 / G3 / G4, and the previous 3H are all pre-charging times. D1 is the data signal of the sub-pixel R1, D2 is the data signal of the sub-pixels R1 / R2, and D3 is the data signal of R4; it should be noted that Figure 1 and Figure 2 the data signals D1 / D3 in are positive data signals, that is: D1(+) / D3(+); the data signal D2 is a negative data signal, that is: D2(-).

[0098] For the three red sub-pixels R1 / R2 / R4, within the previous 1H time of their charging, the data line level is inconsistent with the charging level of this red sub-pixel, so pre-charging cannot be achieved. That is, the actual charging time of each red sub-pixel is 1H (in a display product with an 8K 60Hz dual-gate pixel architecture, 1H = 1.85us). Considering the signal line delay, the actual charging time is shorter than 1.85us; for the red sub-pixel R3, within the previous 1H time of its charging, the data signal is the data of the red sub-pixel R2, and the red sub-pixel R3 and the red sub-pixel R2 need to be charged with the same data, which is equivalent to the charging time of the red sub-pixel R3 being 2H. This will cause the charging rate of the red sub-pixel R3 to be higher than that of the red sub-pixels R1 / R2 / R4, resulting in uneven screen brightness.

[0099] To solve the foregoing technical problems, the embodiments of this disclosure provide an array substrate, which can be used in liquid crystal display products, but is not limited thereto, depending on the specific situation.

[0100] As Figure 3 shown, the array substrate 10 of the embodiments of this disclosure may include a first substrate ( Figure 3not marked in the figure) and a plurality of pixel groups A and a plurality of data lines 102 formed on the first substrate. Among them, the plurality of pixel groups A are arranged in an array in the row direction X and the column direction Y. Each pixel group A includes two sub-pixels arranged in the row direction X. Among any two adjacent pixel groups A in the row direction X, at least one sub-pixel of one pixel group A has the same color as a sub-pixel of the other pixel group A. And among any two adjacent sub-pixels in the row direction X, the corresponding colors are different. Each column of data lines 102 and each column of pixel groups A are alternately arranged in the row direction X. Each column of data lines 102 is connected to each sub-pixel located in the same column and having the same corresponding color, and each column of data lines 102 is connected to two sub-pixels having the same corresponding color in two pixel groups A located on its adjacent sides in the row direction X.

[0101] In addition, the array substrate 10 may further include a plurality of scan line groups. Each scan line group includes two rows of scan lines, namely the first scan line 103a and the second scan line 103b. The first scan line 103a and the second scan line 103b in each scan line group are respectively located on the opposite sides of each row of pixel groups A in the column direction Y. Among them, the sub-pixels located in the even columns are connected to the adjacent first scan line 103a, and the sub-pixels located in the odd columns are connected to the adjacent second scan line 103b.

[0102] It should be noted that the first scan line 103a and the second scan line 103b are arranged on the same layer, and may be located on the side of the data line 102 close to the first substrate. It should be understood that an insulating layer is provided between the first scan line 103a, the second scan line 103b and the data line 102.

[0103] In the present disclosure, "arranged on the same layer" means that a film layer for forming a specific pattern is formed by using the same film formation process, and then a layer structure is formed by using the same mask through a single patterning process. That is, a single patterning process corresponds to one mask (also called a photomask). According to the different specific patterns, a single patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. Thereby simplifying the manufacturing process, saving the manufacturing cost, and improving the production efficiency.

[0104] In an embodiment of the present disclosure, each row of sub-pixels is divided into a plurality of pixel units arranged in sequence in the row direction X. Each pixel unit includes a first sub-pixel A1, a second sub-pixel A2, and a third sub-pixel A3 arranged in sequence in the row direction X. Among them, the colors corresponding to the first sub-pixel A1, the second sub-pixel A2, and the third sub-pixel A3 are all different. For example, the first sub-pixel A1 can be a red sub-pixel, the second sub-pixel A2 can be a green sub-pixel, and the third sub-pixel A3 can be a blue sub-pixel. However, this is not limited thereto. The first sub-pixel A1, the second sub-pixel A2, and the third sub-pixel A3 can also be other colors, depending on the specific situation.

[0105] Based on the array substrate of the embodiment of the present disclosure mentioned above, all the sub-pixels connected to each column of data lines 102 are of the same color. Among them, as Figure 3 shown, the data lines 102 corresponding to the data signal D1 drive all green sub-pixels, the data lines 102 corresponding to the data signal D2 drive all red sub-pixels, and the data lines 103 corresponding to the data signal D3 drive all blue sub-pixels. It should be noted that Figure 3 and Figure 4 the data signals D1 / D3 in are positive data signals, that is: D1(+) / D3(+); the data signal D2 is a negative data signal, that is: D2(-). As Figure 3 shown, each column of data lines 102 does not drive the sub-pixels adjacent to it, but drives the sub-pixels separated from it by one sub-pixel.

[0106] In an embodiment of the present disclosure, taking the display of a monochromatic red screen as an example: the high level of each row of scan lines lasts for 4H. In the present disclosure, taking 4H as an example, in fact, 2H / 3H / 4H / 5H / 6H / 7H / 8H are all applicable to the technology of the present disclosure. Combining Figure 3 and Figure 4 shown, the gate signals corresponding to the red sub-pixels R1 / R2 / R3 / R4 are G1 / G2 / G3 / G4 respectively. Among them, the last 1H of the 4H high-level time of the gate signals G1 / G2 / G3 / G4 is the actual data charging time of the red sub-pixels R1 / R2 / R3 / R4, and the previous 3H are all pre-charging times. For the pixel structure provided by the present disclosure, when displaying a monochromatic screen, the data on the data lines 102 within one frame are all the same. Therefore, the actual charging time of each sub-pixel is 4H, and the actual charging time of all red sub-pixels is 4H. This not only makes the picture quality more uniform, but also improves the overall brightness of the picture because the actual charging time of the sub-pixels is longer. Especially in 8K dual-gate pixel architecture products, the pixel charging rate is relatively low, and this pixel architecture has a more obvious effect on improving the picture quality. Because all the sub-pixels connected to each column of data lines 102 in this pixel architecture are of the same color, it is possible to support the simultaneous opening of the gates of every two rows of sub-pixels, doubling the pixel charging time, thereby improving the pixel charging rate of each row.

[0107] The structure of the array substrate according to the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0108] As Figure 6 shown, the first substrate 101 may be a single-layer structure, but is not limited thereto. The first substrate 101 may also include a multi-layer structure. For example, the material of the first substrate 101 may be glass, but is not limited thereto. The material of the first substrate 101 may also be other materials, such as polyimide (PI) and other materials, depending on the specific situation.

[0109] Combined with Figure 5 and Figure 7 shown, the scan lines 103a, 103b include a plurality of scan segments arranged and connected in sequence in the row direction X. Each scan segment includes a first part 1031, a transition connection part 1032, and a second part 1033 arranged and connected in sequence in the row direction X; the widths of the first part 1031 and the second part 1033 are greater than the width of the transition connection part 1032, and the first part 1031, the transition connection part 1032, and the second part 1033 enclose a groove structure 1034.

[0110] It should be noted that the width of the structure mentioned in the present disclosure is the dimension in the direction perpendicular to the extension direction of this structure.

[0111] As Figure 5 and Figure 7 shown, in each scan line group: the first part 1031 of the first scan line 103a is opposite to the second part 1033 of the second scan line 103b in the column direction Y, and the second part 1033 of the first scan line 103a is opposite to the first part 1031 of the second scan line 103b in the column direction Y; and the notch orientation of the groove structure 1034 of the first scan line 103a is opposite to the notch orientation of the second scan line 103b; it should be understood that the notch of the groove structure 1034 is the opening where the groove structure 1034 is opposite to the transition connection part 1032 in the column direction Y.

[0112] In the embodiments of the present disclosure, combined with Figure 5 and Figure 6 shown, the sub-pixel may include a pixel electrode 104, a transistor, and a common electrode 106, where:

[0113] The transistor may include an active layer 1053, a gate, and a first electrode 1051 and a second electrode 1052 disposed on the same layer. For example, the first electrode 1051 and the second electrode 1052 may be disposed on the same layer as the data line 102. Among them, a gate insulating layer 109 may be further disposed between the gate of the transistor and the active layer 1053 to insulate the gate from the active layer 1053. The gate insulating layer 109 may be made of an inorganic material, such as inorganic materials like silicon oxide and silicon nitride. It should be noted that the gate may be disposed on the same layer as the aforementioned first scan line 103a and second scan line 103b, and the gate may be a part of the aforementioned first scan line 103a or second scan line 103b. That is to say, a partial structure of the first scan line 103a or second scan line 103b may be used as the gate of the transistor. The first electrode 1051 and the second electrode 1052 may be respectively connected to two doped regions (i.e., source doped region and drain doped region) of the active layer 1053. The first electrode 1051 and the second electrode 1052 may include a metal material or an alloy material, such as a single-layer or multi-layer metal structure formed by molybdenum, aluminum, titanium, etc. For example, the multi-layer structure is a multi-metal layer stack, such as a three-layer metal stack of titanium, aluminum, and titanium (Ti / Al / Ti), etc.

[0114] For example, the transistor according to an embodiment of the present disclosure may be a bottom-gate type, that is: the gate may be first formed on the first substrate 101, and the gate may include a metal material or an alloy material, such as including molybdenum, aluminum, titanium, etc., to ensure its good electrical conductivity; then, a gate insulating layer 109 is formed on the first substrate 101. As Figure 6 shown, the gate insulating layer 109 covers the gate; then an active layer 1053 is formed on the side of the gate insulating layer 109 away from the first substrate 101, that is: the active layer 1053 is located on the side of the gate away from the first substrate 101, and the active layer 1053 overlaps with the orthographic projection of the gate on the first substrate 101. For example, the orthographic projection of the active layer 1053 on the first substrate 101 may be located within the orthographic projection of the gate on the first substrate; the first electrode 1051 and the second electrode 1052 may be formed after the active layer 1053 is formed. Among them, one end of the first electrode 1051 may be located on the side of the active layer 1053 away from the first substrate 101 and in contact with the source doped region of the active layer 1053, and the other end of the first electrode 1051 is connected to the data line 40; one end of the second electrode 1052 may be located on the side of the active layer 1053 away from the first substrate 101 and in contact with the active layer 1053, and the other end of the second electrode 1052 may be connected to the pixel electrode 104.

[0115] It should be noted that the contact mentioned in the embodiments of the present disclosure refers to the direct bonding of two components without other film layers therebetween, that is, the two components do not need to be connected through other structures (for example, via vias). In addition, it should also be noted that the transistors in the embodiments of the present disclosure are not limited to the bottom-gate type mentioned above, but may also be top-gate type.

[0116] Based on the structure of the scanning line mentioned above, in combination with Figures 5 to 7 As shown, the orthographic projection of the active layer 1053 of the transistor in the embodiments of the present disclosure on the first substrate 101 may be located within the orthographic projection of the first part 1031 of the scanning line on the first substrate 101, and a part of the first part 1031 of the scanning line may form the gate of the transistor.

[0117] In addition, in combination with Figure 5 、 Figure 7 and Figure 8 As shown, the second pole 1052 of the transistor mentioned above may include a first contact part 10521 connected to the pixel electrode 104, a second contact part 10522 in contact with the active layer 1053, and an electrode connection part 10523 connecting the first contact part 10521 and the second contact part 10522; wherein, the orthographic projection of the electrode connection part 10523 of the second pole 1052 on the first substrate 101 overlaps with the orthographic projections of the first part 1031, the second part 1033 and the groove structure 1034 on the first substrate 101, and does not overlap with the orthographic projection of the transition connection part 1032 on the first substrate 101.

[0118] In the embodiments of the present disclosure, by designing the second pole 1052 of the transistor with the scanning line as above, it is convenient for the second pole 1052 of the transistor to be accurately aligned with the gate, that is, it can prevent the misalignment between the second pole 1052 of the transistor and the gate, which may cause the parasitic capacitance between two adjacent transistors in the row direction X (that is, the parasitic capacitance between the second pole 1052 of the transistor and the gate) to be different, and further avoid problems such as abnormal image quality.

[0119] In the embodiments of the present disclosure, as Figure 6 shown, the pixel electrode 104 may be formed on the gate insulating layer 109 after the formation of the first pole 1051 and the second pole 1052, as Figure 5 and Figure 6As shown, the orthographic projection of the pixel electrode 104 on the first substrate 101 does not overlap with the orthographic projection of the active layer 12 on the first substrate 101, and the orthographic projection of the pixel electrode 104 on the first substrate 101 overlaps with the orthographic projection of a part of the second electrode 1052 on the first substrate 101 and is in contact with the pixel electrode 104. Specifically, the pixel electrode 104 can be in contact with the first contact portion 10521 of the second electrode 1052. That is to say, there is no other film layer between the pixel electrode 104 and the second electrode 1052, and they are directly bonded together without being connected through a via hole. In this way, compared with the related art in which the pixel electrode 104 and the second electrode 1052 are connected through a via hole, while improving the aperture ratio of the product, it can also improve the shortage of other structural design spaces (i.e., Margin), and avoid the risk of undercut when the via hole is formed, thereby improving the display uniformity.

[0120] It should be noted that the pixel electrode 104 in the embodiment of the present disclosure is not limited to being formed on the gate insulating layer 109 after the first electrode 1051 and the second electrode 1052 are formed. This pixel electrode 104 can also be formed on the gate insulating layer 109 after the active layer 1053 is formed and before the first electrode 1051 and the second electrode 1052 are formed, as long as it is ensured that a part of the pixel electrode 104 is in contact with the second electrode 1052.

[0121] For example, the material of the pixel electrode 104 in the embodiment of the present disclosure is different from the material of the aforementioned second electrode 1052. This pixel electrode 104 can be a transparent electrode, and its material can be ITO (indium tin oxide) material, but it is not limited thereto, and it can also be made of transparent materials such as indium zinc oxide (IZO) and zinc oxide (ZnO).

[0122] In the embodiment of the present disclosure, as shown in Figure 5 and Figure 6 the common electrode 106 can be located on the side of the pixel electrode 104 away from the first substrate 101 and is insulated from the pixel electrode 104. That is to say, a passivation layer 110 can be provided between the common electrode 106 and the pixel electrode 104, and the orthographic projection of the common electrode 106 on the first substrate 101 overlaps with the orthographic projection of the pixel electrode 104 on the first substrate 101, which can increase the storage capacitance. It should be understood that the passivation layer 110 mentioned here and the aforementioned gate insulating layer 109 are both film layers provided as a whole layer and can cover each film layer structure located under them. This passivation layer 110 can be an inorganic film layer such as silicon nitride, but it is not limited thereto, and it can also be an organic film layer, etc., depending on the specific situation.

[0123] For example, the material of the common electrode 106 may be the same as that of the pixel electrode 104. The common electrode 106 may be a transparent electrode, and its material may be ITO (indium tin oxide) material, but it is not limited thereto. Transparent materials such as indium zinc oxide (IZO) and zinc oxide (ZnO) may also be used.

[0124] In the embodiment of the present disclosure, the pixel electrode 104 may be a plate-shaped electrode, that is, there are no slits on the pixel electrode 104; while the common electrode 106 may be a slit electrode, that is, the common electrode 106 may have slits; specifically, the common electrode 106 in the embodiment of the present disclosure may have the following several design schemes:

[0125] Scheme 1

[0126] The common electrode of this scheme is a single-domain structure. Specifically, as Figure 9 shown, the common electrode 106 may include a first edge conductive part 1061 and a second edge conductive part 1062 that are opposite and spaced apart in the column direction Y, and a plurality of first electrode bars 1063 that are located between the first edge conductive part 1061 and the second edge conductive part 1062 and are spaced apart in the column direction Y; and the common electrode 106 further includes a first conductive connection bar 1064 that extends in the column direction Y. The first conductive connection bar 1064 is located on the same side of the first edge conductive part 1061, the second edge conductive part 1062, and the plurality of first electrode bars 1063 in the row direction X, and is connected to the first edge conductive part 1061, the second edge conductive part 1062, and the plurality of first electrode bars 1063.

[0127] Among them, in the common electrode 106, the slits between the first electrode bar 1063 and the first edge conductive part 1061, the slits between two adjacent first electrode bars 1063, and the slits between the first electrode bar 1063 and the second edge conductive part 1062 may all be the first slits S1. The extending direction of the first slits S1 is the same as the extending direction (i.e., the length direction) of the first electrode bar 1063, and the extending direction of the first electrode bar 1063 intersects both the row direction X and the column direction Y.

[0128] Optionally, in the common electrode 106, the end of the first slit S1 far from the first conductive connection bar 1064 is in an open state, that is, the position of the common electrode 106 of each sub-pixel close to the data line 102 adopts an open design. Such a design can reduce the dark field area of the pixel and improve the aperture ratio of the pixel compared with the scheme in the related art where the periphery of the slit is in a closed state.

[0129] In the embodiment of the present disclosure, as Figure 10 shown, the extending directions of the first electrode bars 1063 of two adjacent common electrodes in the column direction Y are parallel to each other.

[0130] Scheme 2

[0131] The main difference between Solution 2 and Solution 1 is that, as Figure 11 shown, two adjacent common electrodes 106 in the column direction Y are arranged in mirror symmetry with respect to the row direction X, so as to be able to expand the viewing angle, that is: the product with this feature can be applied to products with a wide viewing angle. It should be noted that in this solution, the common electrode 106 is also a single-domain structure. For other designs of this common electrode 106, reference can be made to the description of Solution 1, and it will not be repeated here.

[0132] Solution 3

[0133] The common electrode of this solution is a double-domain structure. Specifically, as Figure 12 shown, the common electrode 106 has a first group and a second group arranged in the column direction Y. The first group includes a plurality of first electrode strips 1063 arranged at intervals in the column direction Y and a first edge conductive part 1061 located on the side of the plurality of first electrode strips 1063 away from the second group; the second group includes a plurality of second electrode strips 1065 arranged at intervals in the column direction Y and a second edge conductive part 1062 located on the side of the plurality of second electrode strips 1065 away from the first group; the common electrode 106 further has a first conductive connection strip 1064 extending in the column direction Y. The first conductive connection strip 1064 is located on the same side of the first group and the second group in the row direction X and is connected to the first edge conductive part 1061, each first electrode strip 1063, each second electrode strip 1065, and the second edge conductive part 1062.

[0134] Among them, in the common electrode 106, the gap between the first electrode strip 1063 and the first edge conductive part 1061 and the gaps between adjacent first electrode strips 1063 are all first gaps S1, and the gap between the second electrode strip 1065 and the second edge conductive part 1062 and the gaps between adjacent second electrode strips 1065 are all second gaps S2. The extending direction of the first gap S1 is the same as the extending direction of the first electrode strip 1063 and intersects both the row direction X and the column direction Y. The extending direction of the second gap S2 is the same as the extending direction of the second electrode strip 1065 and intersects both the row direction X and the column direction Y; and the extending direction of the first electrode strip 1063 intersects the extending direction of the second electrode strip 1065.

[0135] Optionally, the common electrode 106 further has a second conductive connection strip 1066 and a conductive adjustment part 1067 connected to the second conductive connection strip 1066. The second conductive connection strip 1066 extends in the column direction Y, and the conductive adjustment part 1067 is located on the side of the second conductive connection strip 1066 close to the first conductive connection strip 1064 and between the first group and the second group.

[0136] Among them, one end of the first electrode strip 1063 in the first group close to the second group and one end of the second electrode strip 1065 in the second group close to the first group, which are far from the first conductive connection strip 1064, are both connected to the second conductive connection strip 1066; a gap formed between the conductive adjustment portion 1067 and the first electrode strip 1063 is the third gap S3, and the extending direction of the third gap S3 is the same as that of the first gap S1; a gap formed between the conductive adjustment portion 1067 and the second electrode strip 1065 is the fourth gap S4, and the extending direction of the fourth gap S4 is the same as that of the second gap S2.

[0137] In this solution, by providing the second conductive connection strip 1066 and the conductive adjustment portion 1067 connected to the second conductive connection strip 1066, it can be ensured that the electric field at the junction of the first group and the second group in the common electrode 106 is closer to the electric field at other parts of the common electrode 106, thereby ensuring display uniformity.

[0138] Optionally, in this solution, the widths of the first electrode strip 1063 and the second electrode strip 1065 can be equal, and the widths of the first gap S1, the second gap S2, the third gap S3, and the fourth gap S4 can be equal to ensure electric field uniformity, thereby ensuring display uniformity.

[0139] In this solution, the ends of the first gap S1 and the second gap S2 far from the first conductive connection strip 1064 are open, that is: the position of the common electrode 106 of each sub-pixel close to the data line 102 can adopt an open design. Compared with the solution in the related art where the gaps are all closed around, this design can reduce the dark area of the pixel and improve the aperture ratio of the pixel.

[0140] It should be understood that the common electrode 106 of the present disclosure can be an integral structure, and the common electrode 106 is symmetrically arranged about the row direction X to ensure display uniformity at each part of the common electrode 106.

[0141] The above three solutions are the preferred solutions for the common electrode 106 of the embodiments of the present disclosure, that is: the common electrode 106 of the embodiments of the present disclosure can adopt any one of the above three solutions; however, it should be understood that the common electrode 106 of the embodiments of the present disclosure is not limited to the three solutions mentioned above, and can also adopt a single-domain structure with all gaps closed around (the difference from the solution one mentioned above is that the gaps are closed around, and the other designs can be the same) or a double-domain structure with all gaps closed around (the difference from the solution three mentioned above is that all the gaps are closed around, and the other designs can be the same), depending on the specific situation.

[0142] Based on the common electrode 106 mentioned in any of the foregoing solutions, optionally, as Figure 10 and Figure 12As shown, in pixel group A, the common electrodes 106 of two sub-pixels are symmetrically arranged in a mirror image about the column direction Y, and share the first conductive connection bar 1064 to form an electrode mirror unit. Such a design can save design space and also reduce the dark field area to increase the light transmittance.

[0143] In an embodiment of the present disclosure, in combination with Figure 5 , Figure 13 and Figure 14 As shown, the array substrate 10 may further include a plurality of common line groups. Each common line group is located between the first scanning line 103a and the second scanning line 103b of a scanning line group; and each common line group includes two rows of common lines arranged on the same layer as the scanning lines, namely the first common line 107a and the second common line 107b. The first common line 107a and the second common line 107b in each common line group are respectively located on the opposite sides of each row of pixel groups A in the column direction Y.

[0144] Wherein, the positive projection of the first edge conductive part 1061 of the electrode mirror unit on the first substrate 101 overlaps with the positive projection of the first common line 107a on the first substrate 101, and is connected to the first common line 107a through the first transfer via hole H1; the positive projection of the second edge conductive part 1062 of the electrode mirror unit on the first substrate 101 overlaps with the positive projection of the second common line 107b on the first substrate 101, and is connected to the second common line 107b through the second transfer via hole H2.

[0145] Optionally, in combination with Figure 5 , Figure 13 and Figure 14 As shown, at least a part of the positive projection of the first transfer via hole H1 on the first substrate 101 overlaps with the positive projection of the first common line 107a on the first substrate 101; at least a part of the positive projection of the second transfer via hole H2 on the first substrate 101 overlaps with the positive projection of the second common line 107b on the first substrate 101.

[0146] Specifically, a part of the first transfer via hole H1 overlaps with the orthographic projection of the first common line 107a on the first substrate 101, and another part of the first transfer via hole H1 is located outside the orthographic projection of the first common line 107a on the first substrate 101 (i.e., does not overlap with the orthographic projection of the first common line 107a on the first substrate 101), so as to improve the subsequent alignment film diffusion uniformity; similarly, a part of the second transfer via hole H2 overlaps with the orthographic projection of the second common line 107b on the first substrate 101, and another part of the second transfer via hole H2 is located outside the orthographic projection of the second common line 107b on the first substrate 101 (i.e., does not overlap with the orthographic projection of the second common line 107b on the first substrate 101).

[0147] In an embodiment of the present disclosure, as Figure 13 shown, each common line group may further include a plurality of common connection lines 107c that are arranged at intervals in the row direction X and are located between the first common line 107a and the second common line 107b. The common connection lines 107c extend in the column direction Y and are arranged on the same layer as the aforementioned scanning lines, and both ends of the common connection lines 107c are respectively connected to the first common line 107a and the second common line 107b. Such a design can ensure the common signal uniformity and improve the display uniformity.

[0148] Among them, the orthographic projection of the first conductive connection bar 1064 of each electrode mirror unit on the first substrate 101 may be located within the orthographic projection of a common connection line 107c on the first substrate 101. Such a design can reduce the dark field area and improve the transmittance.

[0149] It should be understood that the orthographic projection of any structure in the common line group of the embodiment of the present disclosure on the first substrate 101 does not overlap with the orthographic projection of any structure in the scanning line group on the first substrate 101.

[0150] In an embodiment of the present disclosure, in combination with Figure 5 、 Figure 10 and Figure 11 shown, a jumper wire 108 may also be provided between two adjacent electrode mirror units in the column direction Y; among them, the jumper wire 108 is arranged on the same layer as the aforementioned electrode mirror unit and is connected to two adjacent electrode mirror units in the column direction Y to further ensure the common signal uniformity and improve the display uniformity.

[0151] Optionally, as Figure 10 and Figure 11As shown, the jumper wire 108 has a first connection portion 1081, an intermediate connection portion 1082, and a second connection portion 1083 that are arranged in sequence and connected in the column direction Y. The widths of the first connection portion 1081 and the second connection portion 1083 are greater than the width of the intermediate connection portion 1082. Among them, in the column direction Y, the middle region of the edge of one of the two adjacent electrode mirror units is in contact with the first connection portion 1081, and the middle region of the edge of the other is in contact with the second connection portion 1083.

[0152] Furthermore, the orthographic projection of the first connection portion 1081 on the first substrate 101 and the orthographic projection of the first transfer via hole H1 on the first substrate 101 have at least partial overlap; that is to say, the first connection portion 1081 can be connected to the first common line 107a through the first transfer via hole H1. The orthographic projection of the second connection portion 1083 on the first substrate 101 and the orthographic projection of the second transfer via hole H2 on the first substrate 101 have at least partial overlap, and the second connection portion 1083 can be connected to the second common line 107b through the second transfer via hole H2.

[0153] In the embodiments of the present disclosure, by designing the widths of the first connection portion 1081 and the second connection portion 1083 of the jumper wire 108 to be greater than the width of the intermediate connection portion 1082, while reducing the generation of parasitic capacitance, the connection areas at the aforementioned transfer via holes H1 and H2 can be ensured, thereby ensuring the connection stability at the transfer via holes H1 and H2.

[0154] In the embodiments of the present disclosure, as Figure 5 and Figure 15 shown, the data line 102 has an alignment portion 1021 configured to be aligned with the spacer 20. The orthographic projection of this alignment portion 1021 on the first substrate 101 is located between adjacent rows of pixel groups A, so that the orthographic projection of the spacer 20 on the first substrate 101 is located between adjacent rows of pixel groups A. In this way, it is possible to avoid the situation where the spacer 20 slips into the opening area during a drop test or a pressure test, resulting in light leakage, and ensure the product reliability.

[0155] Among them, in order to ensure the support stability of the spacer 20, the alignment portion 1021 of the data line 102 can be designed to be wider, and in order to ensure the light transmittance, the widths of other parts of the data line 102 except the alignment portion 1021 are designed to be narrower; that is to say, the widths of other parts of the data line 102 except the alignment portion 1021 are smaller than the width of the alignment portion 1021; and the orthographic projection of the surface of the spacer 20 close to the array substrate 10 on the first substrate 101 is located within the orthographic projection of the alignment portion 1021 on the first substrate 101.

[0156] Optionally, the orthographic projection of the alignment portion 1021 of the data line 102 on the first substrate 101 is located between the orthographic projection of the first scan line 103a of one of the adjacent two scan line groups and the orthographic projection of the second scan line 103b of the other on the first substrate 101. Such a design can utilize the overlapping portions of the first scan line 103a and the data line 102 and the overlapping portions of the second scan line 103b and the data line 102 as barriers to further prevent the spacer 20 from slipping into the opening area during a drop test or a pressure test, resulting in light leakage, and ensuring the product reliability.

[0157] It should be understood that the orthographic projection of the alignment portion 1021 of the data line 102 on the first substrate 101 does not overlap with the orthographic projection of any structure in the aforementioned common line group and scan line group on the first substrate 101.

[0158] The embodiment of the present disclosure also provides a display device, which can be a liquid crystal display device, but is not limited thereto. And the display device of the embodiment of the present disclosure may include the array substrate 10 described in any of the foregoing embodiments, which will not be repeated here. And this display device may further include a counter substrate (not shown in the figure) disposed opposite to the array substrate 10 and a liquid crystal layer (not shown in the figure) located between the array substrate 10 and the counter substrate. The liquid crystal molecules of this liquid crystal layer can be negative liquid crystals to improve the transmittance, but are not limited thereto, and can also be positive liquid crystals.

[0159] In the embodiment of the present disclosure, the display device may further include the aforementioned spacer 20. This spacer 20 can be integrated on the counter substrate, but is not limited thereto, and can also be integrated on the array substrate 10, depending on the specific situation.

[0160] Among them, the counter substrate of the present disclosure may include a second substrate (not shown in the figure) and a black matrix layer (not shown in the figure) located on the side of the second substrate close to the array substrate 10. This black matrix layer may have a shielding area and a light-transmitting area. The orthographic projection of this shielding area on the first substrate 101 completely covers the transistors of the sub-pixels, the scan line group, the data line 102, the common line group, and the spacer 20, and the shielding area 601 may also cover the edges of the common electrode 106 and the pixel electrode 104; while the orthographic projection of the light-transmitting area on the first substrate 101 may be located within the orthographic projection of the common electrode 106 and the pixel electrode 104 on the first substrate 101.

[0161] In addition, the counter substrate of the present disclosure may further include a color filter layer, and this color filter layer may include a red filter block, a green filter block, a blue filter block, and so on.

[0162] It should be noted that this color filter layer is not limited to being integrated in the counter substrate, and can also be integrated in the array substrate 10, depending on the specific situation.

[0163] According to an embodiment of the present disclosure, the specific type of the display device is not particularly limited, and any type of display device commonly used in the art may be used. For example, a television, an in-vehicle display, etc. Those skilled in the art can make corresponding selections according to the specific use of the display device, which will not be elaborated here.

[0164] It should be noted that in addition to the aforementioned array substrate, counter substrate, and liquid crystal layer, the display device further includes other necessary components and compositions. Taking a display as an example, it may further include a backlight module, a housing, a main circuit board, a power cord, etc. Those skilled in the art can make corresponding supplements according to the specific usage requirements of the display device, which will not be elaborated here.

[0165] After considering the specification and practicing the content disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only illustrative, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. An array substrate (10), wherein, it includes: a first substrate (101), and a plurality of pixel groups (A) and a plurality of columns of data lines (102) formed on the first substrate (101); the plurality of pixel groups (A) are arranged in an array in the row direction (X) and the column direction (Y), each pixel group (A) includes two sub-pixels arranged in the row direction (X); at least one sub-pixel of one of any two adjacent pixel groups (A) in the row direction (X) has the same color as one sub-pixel of the other; and the colors of any two adjacent sub-pixels in the row direction (X) are different; the array substrate (10) further includes a plurality of scan line groups; each scan line group includes two rows of scan lines, namely a first scan line (103a) and a second scan line (103b); each column of the data lines (102) and each column of the pixel groups (A) are alternately arranged in the row direction (X), each column of the data lines (102) is connected to each sub-pixel in the same column and with the same corresponding color, and each column of the data lines (102) is connected to two sub-pixels with the same corresponding color in the two pixel groups (A) adjacent to its two sides in the row direction (X); the sub-pixel includes a pixel electrode (104) and a transistor; the gate of the transistor is a partial structure of the scan line; the first pole (1051) of the transistor is arranged on the same layer as the data line (102) and is connected; the second pole (1052) of the transistor is arranged on the same layer as the data line (102), and a part of the second pole (1052) of the transistor is in contact with the pixel electrode (104); the scan line includes a plurality of scan segments arranged in sequence and connected in the row direction (X); each scan segment includes a first part (1031), a transition connection part (1032), and a second part (1033) arranged in sequence and connected in the row direction (X); the widths of the first part (1031) and the second part (1033) are greater than the width of the transition connection part (1032), and the first part (1031), the transition connection part (1032), and the second part (1033) enclose a groove structure (1034); the positive projection of the active layer (1053) of the transistor on the first substrate (101) is located within the positive projection of the first part (1031) on the first substrate (101), and a part of the first part (1031) constitutes the gate of the transistor; the second pole (1052) of the transistor includes a first contact part (10521) in contact with the pixel electrode (104), a second contact part (10522) in contact with the active layer (1053), and an electrode connection part (10523) connecting the first contact part (10521) and the second contact part (10522); The positive projection of the electrode connection portion (10523) of the second pole (1052) on the first substrate (101) overlaps with the positive projections of the first portion (1031), the second portion (1033), and the groove structure (1034) on the first substrate (101), and does not overlap with the positive projection of the transition connection portion (1032) on the first substrate (101).

2. The array substrate (10) according to claim 1, wherein, The first scan line (103a) and the second scan line (103b) in each scan line group are respectively located on opposite sides of each row of pixel groups (A) in the column direction (Y); wherein, the sub-pixels located in even columns are connected to the adjacent first scan line (103a), and the sub-pixels located in odd columns are connected to the adjacent second scan line (103b).

3. The array substrate (10) according to claim 2, wherein, Each row of sub-pixels is divided into a plurality of pixel units arranged in sequence in the row direction (X), and each pixel unit includes a first sub-pixel (A1), a second sub-pixel (A2), and a third sub-pixel (A3) arranged in sequence in the row direction (X); wherein, the colors corresponding to the first sub-pixel (A1), the second sub-pixel (A2), and the third sub-pixel (A3) are all different.

4. The array substrate (10) according to claim 3, wherein, In each scan line group: The first portion (1031) of the first scan line (103a) is opposite to the second portion (1033) of the second scan line (103b) in the column direction (Y), and the second portion (1033) of the first scan line (103a) is opposite to the first portion (1031) of the second scan line (103b) in the column direction (Y); and the notch orientations of the groove structures (1034) of the first scan line (103a) are opposite to the notch orientations of the second scan line (103b).

5. The array substrate (10) according to claim 1, wherein, The sub-pixel further includes a common electrode (106), and the common electrode (106) is located on the side of the pixel electrode (104) away from the first substrate (101) and is insulated from the pixel electrode (104); wherein, the positive projection of the common electrode (106) on the first substrate (101) overlaps with the positive projection of the pixel electrode (104) on the first substrate (101).

6. The array substrate (10) according to claim 5, wherein, The common electrode (106) includes a first edge conductive portion (1061) and a second edge conductive portion (1062) that are opposite and spaced apart in the column direction (Y), and a plurality of first electrode strips (1063) that are located between the first edge conductive portion (1061) and the second edge conductive portion (1062) and are spaced apart in the column direction (Y); And the common electrode (106) further includes a first conductive connection bar (1064) extending in the column direction (Y), and the first conductive connection bar (1064) is located on the same side of the first edge conductive part (1061), the second edge conductive part (1062) and the plurality of first electrode bars (1063) in the row direction (X), and is connected to the first edge conductive part (1061), the second edge conductive part (1062) and the plurality of first electrode bars (1063); Wherein, in the common electrode (106), the gaps between the first electrode bar (1063) and the first edge conductive part (1061), between two adjacent first electrode bars (1063), and between the first electrode bar (1063) and the second edge conductive part (1062) are all first gaps (S1), the extending direction of the first gaps (S1) is the same as the extending direction of the first electrode bar (1063), and the extending direction of the first electrode bar (1063) intersects both the row direction (X) and the column direction (Y).

7. The array substrate (10) according to claim 6, Wherein, In the common electrode (106), the end of the first gap (S1) away from the first conductive connection bar (1064) is in an open shape.

8. The array substrate (10) according to claim 5, Wherein, The common electrode (106) has a first group and a second group arranged in the column direction (Y). The first group includes a plurality of first electrode bars (1063) arranged at intervals in the column direction (Y) and a first edge conductive part (1061) located on the side of the plurality of first electrode bars (1063) away from the second group; the second group includes a plurality of second electrode bars (1065) arranged at intervals in the column direction (Y) and a second edge conductive part (1062) located on the side of the plurality of second electrode bars (1065) away from the first group; The common electrode (106) further has a first conductive connection bar (1064) extending in the column direction (Y), and the first conductive connection bar (1064) is located on the same side of the first group and the second group in the row direction (X), and is connected to the first edge conductive part (1061), each of the first electrode bars (1063), each of the second electrode bars (1065) and the second edge conductive part (1062); Among them, in the common electrode (106), the gaps between the first electrode strip (1063) and the first edge conductive part (1061) and between two adjacent first electrode strips (1063) are both the first gap (S1), and the gaps between the second electrode strip (1065) and the second edge conductive part (1062) and between two adjacent second electrode strips (1065) are both the second gap (S2). The extending direction of the first gap (S1) is the same as the extending direction of the first electrode strip (1063) and intersects both the row direction (X) and the column direction (Y). The extending direction of the second gap (S2) is the same as the extending direction of the second electrode strip (1065) and intersects both the row direction (X) and the column direction (Y); and the extending direction of the first electrode strip (1063) intersects the extending direction of the second electrode strip (1065).

9. The array substrate (10) according to claim 8, wherein, the common electrode (106) further has a second conductive connection strip (1066) and a conductive adjustment part (1067) connected to the second conductive connection strip (1066). The second conductive connection strip (1066) extends in the column direction (Y), and the conductive adjustment part (1067) is located on the side of the second conductive connection strip (1066) close to the first conductive connection strip (1064) and between the first group and the second group; wherein, one ends of the first electrode strip (1063) in the first group close to the second group and the second electrode strip (1065) in the second group close to the first group, which are far from the first conductive connection strip (1064), are both connected to the second conductive connection strip (1066); the gap formed between the conductive adjustment part (1067) and the first electrode strip (1063) is the third gap (S3), and the extending direction of the third gap (S3) is the same as the extending direction of the first gap (S1); the gap formed between the conductive adjustment part (1067) and the second electrode strip (1065) is the fourth gap (S4), and the extending direction of the fourth gap (S4) is the same as the extending direction of the second gap (S2).

10. The array substrate (10) according to claim 9, wherein, the widths of the first electrode strip (1063) and the second electrode strip (1065) are equal, and the widths of the first gap (S1), the second gap (S2), the third gap (S3) and the fourth gap (S4) are equal.

11. The array substrate (10) according to claim 10, wherein, the ends of the first gap (S1) and the second gap (S2) far from the first conductive connection strip (1064) are in an open shape.

12. The array substrate (10) according to claim 10, wherein, the common electrode (106) is of an integral structure, and the common electrode (106) is arranged in mirror symmetry about the row direction (X).

13. The array substrate (10) according to claim 6 or 8, wherein, in the pixel group (A), the common electrodes (106) of two sub-pixels are arranged in mirror symmetry with respect to the column direction (Y), and share the first conductive connection bar (1064) to form an electrode mirror unit.

14. The array substrate (10) according to claim 13, wherein, the array substrate (10) further includes a plurality of common line groups, each common line group is located between the first scan line (103a) and the second scan line (103b) of a scan line group; and each common line group includes two common lines arranged on the same layer as the scan lines, namely a first common line (107a) and a second common line (107b), and the first common line (107a) and the second common line (107b) in each common line group are respectively located on opposite sides of each row of pixel groups (A) in the column direction (Y); wherein, the positive projection of the first edge conductive part (1061) of the electrode mirror unit on the first substrate (101) overlaps with the positive projection of the first common line (107a) on the first substrate (101), and is connected to the first common line (107a) through a first via hole (H1); the positive projection of the second edge conductive part (1062) of the electrode mirror unit on the first substrate (101) overlaps with the positive projection of the second common line (107b) on the first substrate (101), and is connected to the second common line (107b) through a second via hole (H2).

15. The array substrate (10) according to claim 14, wherein, at least part of the positive projection of the first via hole (H1) on the first substrate (101) overlaps with the positive projection of the first common line (107a) on the first substrate (101); at least part of the positive projection of the second via hole (H2) on the first substrate (101) overlaps with the positive projection of the second common line (107b) on the first substrate (101).

16. The array substrate (10) according to claim 14, wherein, each common line group further includes a plurality of common connection lines (107c) arranged at intervals in the row direction (X) and located between the first common line (107a) and the second common line (107b), the common connection lines (107c) extend in the column direction (Y) and are arranged on the same layer as the scan lines, and both ends of the common connection lines (107c) are respectively connected to the first common line (107a) and the second common line (107b); wherein, the positive projection of the first conductive connection bar (1064) of each electrode mirror unit on the first substrate (101) is located within the positive projection of a common connection line (107c) on the first substrate (101).

17. The array substrate (10) according to claim 16, wherein, A jumper wire (108) is further disposed between two adjacent electrode mirror units in the column direction (Y); wherein, the jumper wire (108) is disposed on the same layer as the electrode mirror unit and is connected to two adjacent electrode mirror units in the column direction (Y).

18. The array substrate (10) according to claim 17, wherein, the jumper wire (108) has a first connection portion (1081), an intermediate connection portion (1082), and a second connection portion (1083) that are sequentially arranged and connected in the column direction (Y), and the widths of the first connection portion (1081) and the second connection portion (1083) are greater than the width of the intermediate connection portion (1082); wherein, in the column direction (Y), the middle region of the edge of one of two adjacent electrode mirror units is in contact with the first connection portion (1081), and the middle region of the edge of the other is in contact with the second connection portion (1083).

19. The array substrate (10) according to claim 18, wherein, the orthographic projection of the first connection portion (1081) on the first substrate (101) and the orthographic projection of the first transfer via hole (H1) on the first substrate (101) have at least partial overlap; the orthographic projection of the second connection portion (1083) on the first substrate (101) and the orthographic projection of the second transfer via hole (H2) on the first substrate (101) have at least partial overlap.

20. The array substrate (10) according to claim 2, wherein, the data line (102) has an alignment portion (1021) configured to be aligned with the spacer (20), and the orthographic projection of the alignment portion (1021) on the first substrate (101) is located between two adjacent rows of the pixel groups (A); wherein, the widths of other portions of the data line (102) except the alignment portion (1021) are smaller than the width of the alignment portion (1021); and the orthographic projection of the surface of the spacer (20) close to the array substrate (10) on the first substrate (101) is located within the orthographic projection of the alignment portion (1021) on the first substrate (101).

21. The array substrate (10) according to claim 20, wherein, the orthographic projection of the alignment portion (1021) on the first substrate (101) is located between the orthographic projections of the first scan line (103a) of one of two adjacent scan line groups and the second scan line (103b) of the other on the first substrate (101).

22. A display device, wherein, it includes the array substrate (10) according to any one of claims 1 to 21 and a counter substrate disposed opposite to the array substrate (10).

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