Resistive memory devices and methods of operating resistive memory devices

Abstract

Resistive memory devices and methods of operating resistive memory devices can be provided herein. A resistive memory device can include strings coupled between one or more source lines and one or more bit lines, each string including a set of one or more resistive memory cells; one or more word lines respectively coupled to the set of one or more resistive memory cells; and a voltage generator configured to control a level of a turn-on voltage to be applied to one or more unselected word lines among the one or more word lines as a function of a programming target state of a subset of resistive memory cells, the subset of resistive memory cells including one or more selected resistive memory cells among the set of one or more resistive memory cells.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to resistive memory devices and methods of operating the resistive memory devices, and more specifically, to resistive memory devices and programming methods for the resistive memory devices. Background Technology

[0002] Memory devices can be classified into volatile memory devices in which the data stored is lost when power is interrupted and non-volatile memory devices in which the data stored is retained even when power is interrupted.

[0003] Examples of non-volatile memory devices may include NAND flash memory, NOR flash memory, resistive memory (or resistive random access memory: ReRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), etc.

[0004] In these examples, resistive RAM (ReRAM) may include a data storage layer for storing data and electrodes in contact with both ends of the data storage layer. The data storage layer can be programmed or erased by a resistance that varies with the voltage applied to the electrodes. For example, unipolar or bipolar resistive RAM materials can be used as the data storage layer. Summary of the Invention

[0005] Embodiments of this disclosure may provide a resistive memory device. The resistive memory device may include: one or more strings respectively connected between one or more source lines and one or more bit lines, each string comprising a set of one or more resistive memory cells; one or more word lines respectively connected to the set of one or more resistive memory cells; and a voltage generator configured to control the level of a turn-on voltage to be applied to one or more unselected word lines among the one or more word lines based on a programming target state of a subset of the resistive memory cells, the subset of resistive memory cells including one or more selected resistive memory cells within the set of one or more resistive memory cells.

[0006] Embodiments of this disclosure provide a method for operating a resistive memory device during a programming operation performed on a resistive memory cell connected between one or more source lines and one or more bit lines. The method may include: applying a ground voltage to one or more source lines and applying a set voltage higher than the ground voltage to one or more bit lines selected from the one or more bit lines; applying a turn-off voltage to a selected word line of a selected resistive memory cell connected to the resistive memory cell; and applying a turn-on voltage to an unselected word line of an unselected resistive memory cell connected to the resistive memory cell, the level of which is controlled according to a programming target state of the selected resistive memory cell.

[0007] Embodiments of this disclosure may provide a method for operating a resistive memory device. The method may include: applying a ground voltage to a selected bit line and a reset voltage to a selected source line; applying a turn-off voltage to a selected word line; and applying a turn-on voltage to an unselected word line, wherein the reset voltage may be controlled according to a programming target state of the selected memory cell connected to the selected word line. Attached Figure Description

[0008] Figure 1 This illustrates the principle underlying data storage in resistive memory devices.

[0009] Figure 2 This is a perspective view illustrating a resistive memory device according to the present disclosure.

[0010] Figure 3 This is a circuit diagram illustrating a resistive memory device according to the present disclosure.

[0011] Figure 4 This is a diagram illustrating a method for erasing a selected memory cell.

[0012] Figure 5 This is a diagram illustrating a method for programming a selected memory cell to a first target state.

[0013] Figure 6 This is a diagram illustrating a method for programming a selected memory cell to a second target state.

[0014] Figure 7 This is a diagram illustrating the state of a memory cell based on its current.

[0015] Figure 8 This is a diagram illustrating the threshold voltage distribution based on the programming scheme.

[0016] Figure 9 This is a flowchart illustrating programming operations according to this disclosure.

[0017] Figure 10This is an example based on reference. Figure 9 A graph showing the threshold voltage distribution of the memory cells for the described programming operations.

[0018] Figure 11 This is a diagram illustrating programming operations according to a first embodiment of the present disclosure.

[0019] Figure 12A , Figure 12B , Figure 12C and Figure 12D This is a diagram illustrating the steps of programming operations according to the first embodiment.

[0020] Figure 13 This is a diagram illustrating programming operations according to a second embodiment of the present disclosure.

[0021] Figure 14A and Figure 14B This is a diagram illustrating the steps of programming operations according to the second embodiment.

[0022] Figure 15 This is a diagram illustrating programming operations according to a third embodiment of the present disclosure.

[0023] Figure 16A , Figure 16B , Figure 16C and Figure 16D This is a diagram illustrating the steps of programming operations according to the third embodiment.

[0024] Figure 17 This is a diagram illustrating a memory device according to the present disclosure.

[0025] Figure 18 This is a diagram illustrating a memory card system using a memory device according to the present disclosure.

[0026] Figure 19 This is a diagram illustrating a solid-state drive (SSD) system that utilizes a memory device according to the present disclosure. Detailed Implementation

[0027] The specific structural or functional descriptions of the embodiments of this disclosure set forth in this specification or application are illustrative of embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0028] Some embodiments of this disclosure relate to a resistive memory device that can store multiple bits in a single memory cell and a method of operating the resistive memory device.

[0029] Figure 1 This illustrates the principle underlying data storage in resistive memory devices.

[0030] Reference Figure 1 The memory cell MC included in the resistive memory device may include a bottom electrode BE, a top electrode TE, and a data storage layer DS. The bottom electrode BE and the top electrode TE may each be made of a conductive material, and the data storage layer DS may be made of a variable resistance material.

[0031] Each of the bottom electrode BE and the top electrode TE may be made of any one or more materials selected from aluminum (Al), copper (Cu), titanium nitride (TiN), titanium aluminum nitride (TixAlyNz), iridium (Ir), platinum (Pt), silver (Ag), gold (Au), polycrystalline silicon, tungsten (W), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), nickel (Ni), cobalt (Co), chromium (Cr), antimony (Sb), iron (Fe), molybdenum (Mo), palladium (Pd), tin (Sn), zirconium (Zr), zinc (Zn), iridium oxide (IrO2), and strontium zirconate (StZrO3).

[0032] The data storage layer DS can be made of either bipolar resistive memory (BRP) or unipolar resistive memory (TRP) materials. Bipolar resistive memory materials can be set or reset depending on the different voltages applied to the bottom electrode BE and the top electrode TE. Perovskite-based materials can be used as bipolar resistive memory materials. Unipolar resistive memory materials can be programmed to set or reset states even with voltage pulses of the same polarity. As a unipolar resistive memory material, materials such as nickel oxide (NiO) can be used. x ) or titanium dioxide (TiO) x Transition metal oxides such as )

[0033] In the data storage layer DS, there exist spaces where atoms are missing, called vacancies (VCs). Because vacancy VCs are polar, they can migrate depending on the voltage applied to the top electrode TE and the bottom electrode BE. For example, when a reset voltage Vreset is applied to the top electrode TE and a ground voltage GND is applied to the bottom electrode BE, the vacancy VC can migrate towards the bottom electrode BE. In this case, the current path PT through which electrons can move between the top electrode TE and the bottom electrode BE is blocked, thus increasing the resistance. This state is called a "high resistance state: HRS". The current path PT can also be referred to as a "filament".

[0034] When a set voltage Vset is applied to the top electrode TE and a ground voltage GND is applied to the bottom electrode BE, the vacancies accumulated on the bottom electrode BE can migrate toward the top electrode TE, thus creating a current path PT through which electrons can move between the bottom electrode BE and the top electrode TE. This state is called the "low resistance state: LRS".

[0035] In other words, under the high-resistance state (HRS), the current in the data storage layer (DS) can decrease due to the increase in the resistance of the data storage layer (DS), while under the low-resistance state (LRS), the current in the data storage layer (DS) can increase due to the decrease in the resistance of the data storage layer (DS). The memory cell (MC) can be programmed to a set state, a reset state, or erased according to the resistance state.

[0036] Because the voltage that can be applied to the top electrode TE and the bottom electrode BE is unaffected Figure 1 Due to limitations in the implementation methods, voltages with various levels can be used.

[0037] Figure 2 This is a perspective view illustrating a resistive memory device according to the present disclosure.

[0038] Reference Figure 2 A resistive memory device may include a memory block, each memory block comprising a plurality of memory cells, and... Figure 2 The image shows a portion of a storage block.

[0039] The memory block may include first memory cells MC1 to nth memory cells MCn vertically stacked on a substrate SUB. When the substrate SUB is formed along the XY plane, the memory block can be formed in the Z direction perpendicular to the XY plane. For example, source lines SL and bit lines BL may be stacked on top of the substrate SUB, and interlayer insulating layers IS and conductive layers CL may be alternately stacked between the source lines SL and bit lines BL. For example, the interlayer insulating layer IS may be made of oxide, and the conductive layers CL may be made of tungsten. Some conductive layers CL may be used as word lines, and some conductive layers may be used as select lines (or select lines).

[0040] Each memory cell may include a first barrier layer 1BX, a data storage layer DS, and a second barrier layer 2BX passing through an interlayer insulating layer IS and a conductive layer CL in the vertical direction (i.e., the Z direction). For example, the first barrier layer 1BX may be formed in a cylindrical shape passing through the interlayer insulating layer IS and the conductive layer CL in the vertical direction (i.e., the Z direction), the data storage layer DS may be formed in a cylindrical shape along the inner wall of the first barrier layer 1BX, and the second barrier layer 2BX may be formed in a cylindrical shape along the inner wall of the data storage layer DS. A plug PL with a cylindrical shape may be formed in the hollow space within the second barrier layer 2BX. Each of the first barrier layer 1BX, the second barrier layer 2BX, and the plug PL may be made of oxide, and the data storage layer DS may be made of a bipolar resistive memory material or a unipolar resistive memory material.

[0041] In the first barrier layer 1BX, the data storage layer DS, and the second barrier layer 2BX formed along a vertical direction (e.g., the Z direction), the layer formed on the layer where the conductive layer CL is formed can be used as a memory cell or a selection transistor. For example, the first memory cell MC1 to the nth memory cell MCn can be sequentially formed on top of the source line SL, and the drain selection transistor DST can be formed on top of the nth memory cell MCn.

[0042] Figure 3 This is a circuit diagram illustrating a resistive memory device according to the present disclosure.

[0043] Reference Figure 3 The first to nth memory cells and the drain select transistor DST can form a single string, and multiple strings can be connected between the bit line BL and the source line SL. Therefore, since multiple bit lines BL are connected to a memory block, multiple strings can be included in a single memory block. The selected string Sel_ST during a programming or read operation can be determined based on the voltage applied to the selected drain select line Sel_DSL in the drain select line DSL. For example, when a ground voltage is applied to the unselected drain select line Unsel_DSL and a conduction voltage is applied to the selected drain select line Sel_DSL, the string ST connected to the selected drain select line Sel_DSL can be selected. In an embodiment, the string ST connected to the unselected drain select line Unsel_DSL can be the unselected string Unsel_ST. In other words, during a programming or read operation, the string ST connected to the selected drain select line Sel_DSL among the multiple strings connected to the multiple bit lines BL can be the target of the programming or read operation.

[0044] When the first memory cell MC1 to the nth memory cell MCn and the drain selection transistor DST included in the selected string Sel_ST are implemented as resistive memory elements, the top node of each memory cell or selection transistor can be the top electrode TE, and its bottom node can be the bottom electrode BE. When the first memory cell MC1 is described by way of example, the node between the first memory cell MC1 and the second memory cell MC2 can be the top electrode TE, and the source line SL can be the bottom electrode BE. Therefore, the first memory cell MC1 can be set or reset according to the voltage applied to the channel between the first memory cell MC1 and the second memory cell MC2 and the voltage applied to the source line SL.

[0045] Figure 4 This is a diagram illustrating a method for erasing a selected memory cell.

[0046] Reference Figure 4 The example illustrates a structure in which eight memory cells and a drain select transistor are connected in a string. First word lines WL1 through eight word lines WL8 can be connected to memory cells, and drain select line DSL can be connected to the drain select transistor. Assuming the fifth word line WL5 is the selected word line Sel_WL, then the fifth memory cell MC5 connected to the fifth word line WL5 is the memory cell selected for the erase operation.

[0047] A reset voltage Vreset can be applied to the source line SL, and a ground voltage GND can be applied to the bit line BL. A turn-off voltage Voff can be applied to the selected word line Sel_WL, and an erase turn-on voltage eVon can be applied to the unselected word line Unsel_WL (excluding the selected word line Sel_WL) and the drain select line DSL.

[0048] The reset voltage Vreset can be set to a negative voltage lower than the ground voltage GND. The shutdown voltage Voff can be set to the ground voltage GND, and the erase on-state voltage eVon can be set to a positive voltage higher than the shutdown voltage Voff. The erase on-state voltage eVon can be set to transmit the reset voltage Vreset applied to the source line SL to the fifth memory cell MC5, and to transmit the ground voltage GND applied to the bit line BL to the fifth memory cell MC5. The principle on which the fifth memory cell MC5 connected to the selected word line Sel_WL enters the erase state ERS is described below.

[0049] When the erase on-state voltage eVon is applied to the gates of the fourth memory cell MC4 and the sixth memory cell MC6, which are unselected memory cells, the vacant spaces in the fourth memory cell MC4 and the sixth memory cell MC6 can migrate toward the word line to form a current path. In other words, the fourth memory cell MC4 can be the bottom electrode, and the sixth memory cell MC6 can be the top electrode, relative to the fifth memory cell MC5.

[0050] Because a reset voltage Vreset is applied to the fourth memory cell MC4 and a ground voltage GND is applied to the sixth memory cell MC6, the reset voltage Vreset is applied to the bottom electrode of the fifth memory cell MC5 and the ground voltage GND is applied to the top electrode of the fifth memory cell MC5. Therefore, vacant cells in the fifth memory cell MC5 can migrate away from the fourth memory cell MC4 and towards the sixth memory cell MC6, thus allowing the fifth memory cell MC5 to enter a high-resistance state HRS. In this embodiment, the high-resistance state HRS can be defined as the erase state ERS.

[0051] Figure 5 This is a diagram illustrating a method for programming a selected memory cell to a first target state.

[0052] Reference Figure 5 Assuming that the fifth word line WL5 is the selected word line Sel_WL, the fifth memory cell MC5 connected to the fifth word line WL5 is the selected memory cell to be programmed into the first programming state PV1.

[0053] A ground voltage GND can be applied to the source line SL, and a set voltage Vset can be applied to the bit line BL. A turn-off voltage Voff can be applied to the selected word line Sel_WL, a first turn-on voltage 1Von can be applied to the unselected word line Unsel_WL (excluding the selected word line Sel_WL), and a first turn-on voltage 1Von or a voltage higher than the first turn-on voltage 1Von can be applied to the drain selection line DSL.

[0054] The set voltage Vset can be set to a positive voltage higher than the ground voltage GND, while the turn-off voltage Voff can be set to the ground voltage GND. The first turn-on voltage 1Von can be set to a positive voltage higher than the turn-off voltage Voff. The first turn-on voltage 1Von can be configured to transmit the ground voltage GND applied to the source line SL to the fifth memory cell MC5, and to transmit the set voltage Vset applied to the bit line BL to the fifth memory cell MC5. The principle on which the fifth memory cell MC5, connected to the selected word line Sel_WL, is programmed to the first programming state PV1 is described below.

[0055] When a first on-state voltage 1Von is applied to the gates of the fourth memory cell MC4 and the sixth memory cell MC6, which are unselected memory cells, a current path can be formed as the vacant spaces in the fourth memory cell MC4 and the sixth memory cell MC6 migrate toward the word line. That is, the fourth memory cell MC4 can be the bottom electrode, while the sixth memory cell MC6 can be the top electrode, relative to the fifth memory cell MC5.

[0056] Because ground voltage GND is applied to the fourth memory cell MC4 and set voltage Vset is applied to the sixth memory cell MC6, ground voltage GND is applied to the bottom electrode of the fifth memory cell MC5, and set voltage Vset is applied to the top electrode of the fifth memory cell MC5. Therefore, a vacancy in the fifth memory cell MC5 can be connected between the fourth memory cell MC4 and the sixth memory cell MC6, and thus the fifth memory cell MC5 can enter a first low resistance state 1LRS. That is, because a current path is formed through the first on-state voltage 1Von, and the current amount can be determined based on the current path, the set voltage Vset transmitted to the sixth memory cell MC6 can have a lower level than the set voltage Vset applied to the bit line BL. Therefore, based on the level of the set voltage Vset transmitted through the sixth memory cell MC6, the resistance of the fifth memory cell MC5 can be programmed into the first low resistance state 1LRS. In this embodiment, the first low resistance state 1LRS is defined as a first programming state PV1.

[0057] Figure 6 This is a diagram illustrating a method for programming a selected memory cell to a second target state.

[0058] Reference Figure 6 Assuming that the fifth word line WL5 is the selected word line Sel_WL, the fifth memory cell MC5 connected to the fifth word line WL5 is the selected memory cell to be programmed into the second programming state PV2.

[0059] A ground voltage GND can be applied to the source line SL, and a set voltage Vset can be applied to the bit line BL. A turn-off voltage Voff can be applied to the selected word line Sel_WL, a second turn-on voltage 2Von can be applied to the unselected word line Unsel_WL (excluding the selected word line Sel_WL), and a second turn-on voltage 2Von or a voltage higher than the second turn-on voltage 2Von can be applied to the drain select line DSL.

[0060] The set voltage Vset can be set to a positive voltage higher than the ground voltage GND, and the turn-off voltage Voff can be set to the ground voltage GND. The second turn-on voltage 2Von can be set to a higher voltage than the first turn-on voltage (i.e., Figure 5 The positive voltage 2Von is applied to the source line SL. The second turn-on voltage 2Von can be set to transmit the ground voltage GND applied to the source line SL to the fifth memory cell MC5, and to transmit the set voltage Vset applied to the bit line BL to the fifth memory cell MC5. The following describes the principle on which the state of the fifth memory cell MC5 connected to the selected word line Sel_WL is programmed to a second programming state PV2, which is higher than the first programming state PV1.

[0061] When the second on-state voltage 2Von is applied to the gates of the fourth memory cell MC4 and the sixth memory cell MC6, which are unselected memory cells, a current path can be formed as the vacant spaces in the fourth memory cell MC4 and the sixth memory cell MC6 migrate toward the word line. That is, relative to the fifth memory cell MC5, the fourth memory cell MC4 can be the bottom electrode, while the sixth memory cell MC6 can be the top electrode.

[0062] Because ground voltage GND is applied to the fourth memory cell MC4 and set voltage Vset is applied to the sixth memory cell MC6, ground voltage GND is applied to the bottom electrode of the fifth memory cell MC5, and set voltage Vset is applied to the top electrode of the fifth memory cell MC5. Therefore, the empty space in the fifth memory cell MC5 can be connected between the fourth memory cell MC4 and the sixth memory cell MC6, thus allowing the fifth memory cell MC5 to enter a second low-resistance state 2LRS. Since a current path is formed through a second on-state voltage higher than the first on-state voltage 1Von, the level of the set voltage Vset transmitted to the sixth memory cell MC6 can be higher than the level of the set voltage Vset transmitted through the first on-state voltage Vset. Therefore, based on the level of the set voltage Vset transmitted through the sixth memory cell MC6, the resistance of the fifth memory cell MC5 can be programmed to a second low-resistance state 2LRS lower than the first low-resistance state 1LRS. In this embodiment, the second low-resistance state 2LRS is defined as a second programming state PV2.

[0063] As described above, the resistance of the selected memory cell can be controlled by adjusting the level of the on-state voltage applied to the Unsel_WL word line. Since the current flowing through the selected memory cell is determined by its resistance, the memory cell can be programmed into various states.

[0064] Figure 7 This is a diagram illustrating the state of a memory cell based on current.

[0065] Reference Figure 7The selected memory cell can be programmed or erased to have various resistance values. For example, when a set voltage Vset is applied to the top electrode of the memory cell, the memory cell can be programmed to any one of the first programming states PV1 to the third programming state PV3 while the current of the memory cell increases. Then, when a reset voltage Vreset is applied to the top electrode, the memory cell can be erased to enter the erase state ERS while the current of the memory cell decreases, and when a reset voltage Vreset lower than the previous voltage is applied to the top electrode, the memory cell can be programmed to any one of the first programming states PV1 to the third programming state PV3 while the current of the memory cell increases again.

[0066] In the above description, although it is stated that the state of the memory cell changes according to the voltage of the top electrode, the state of the memory cell can also change according to the voltage of the bottom electrode.

[0067] Figure 8 This is a diagram illustrating the threshold voltage distribution based on the programming scheme.

[0068] Reference Figure 8 As described in the above embodiments, the scheme for programming the selected memory cell to the erase state ERS and the first programming states PV1 to the third programming states PV3 can be considered a multi-level cell (MLC) scheme. In a multi-level cell (MLC) scheme, a memory cell can store two bits of data. Each selected memory cell can be erased to a single high-resistance state or can be programmed to any of three low-resistance states. As the threshold voltage distribution becomes higher, the resistance becomes lower, and then the amount of current flowing through the selected memory cell can increase.

[0069] In addition to the multi-level cell (MLC) scheme, this embodiment can also be applied to the three-level cell (TLC) scheme in which three bits of data are stored in one memory cell, and can also be applied to schemes that are higher than the three-level cell (TLC) scheme.

[0070] Figure 9 This is a flowchart illustrating programming operations according to this disclosure.

[0071] Reference Figure 9 It can perform programming operations on selected memory cells, such that after an erase operation has been performed on the selected memory cells, the selected memory cells are programmed in ascending order of threshold voltage distribution. In other words, programming operations can be performed in order of resistance of the selected memory cells from higher to lower levels or in order of current of the selected memory cells from lower to higher levels.

[0072] For example, before performing a programming operation on the selected memory cell, an erase operation can be performed on the selected memory cell in step S91. When the erase operation ends, in step S92, a first programming operation can be performed on the memory cell to be programmed into the lowest level first programming state PV1 or a higher programming state. The first programming operation can be performed by applying a turn-off voltage to the selected word line and a first on-state voltage 1Von to the unselected word line. During the verification operation performed in the first programming operation, it can be determined whether the current generated by the selected memory cell is the first current. When the current generated by the selected memory cell is the first current, in step S93, a second programming operation can be performed on the memory cell to be programmed into the second programming state PV2 or a higher programming state. During the second programming operation, a second on-state voltage 2Von higher than the first on-state voltage 1Von can be applied to the unselected word line. When the programming operation performed on the selected memory cell that has reached the kth programming state PVk with the highest threshold voltage ends in step S94 according to the above scheme, the programming operation on the selected memory cell can be terminated.

[0073] Figure 10 This is an example based on reference. Figure 9 A graph showing the threshold voltage distribution of the memory cells for the described programming operations.

[0074] The following will refer to Figure 9 and Figure 10 This describes a method for programming selected memory cells using a multilevel cell (MLC) scheme.

[0075] After the erase operation S91 has been performed on the selected memory cell, a first programming operation S92 can be performed to program the selected memory cell to a first programming state PV1. The memory cells selected in the first programming operation S92 may include memory cells whose target state is the first programming state PV1, and memory cells to be programmed to a second programming state PV2 and a third programming state PV3 that are higher than the first programming state PV1. In other words, memory cells whose target states are the first programming state PV1 to the third programming state PV3 can be programmed simultaneously during the first programming operation S92. As used herein with respect to programming, the terms "simultaneously" and "at the same time" mean that programming occurs over overlapping time intervals. For example, if the first programming occurs over a first time interval, and the second programming occurs simultaneously over a second time interval, then the first and second time intervals overlap at least partially, such that there exists a time when both the first and second programming occur.

[0076] When the first programming operation S92 ends, a second programming operation S93 can be performed on the memory cell that is to be programmed to the second programming state PV2 or the third programming state PV3 among the memory cells that are programmed to the first programming state PV1 to the third programming state PV3. That is, during the second programming operation S93, the memory cell whose target state is the second programming state PV2 or the third programming state PV3 can be programmed simultaneously and then have the second programming state PV2.

[0077] When the second programming operation S93 ends, the third programming operation S94 can be performed on the memory cell that is to be programmed to the third programming state PV3 among the memory cells that are programmed to the second programming state PV2 or the third programming state PV3. That is, when in Figure 9 When k is 3 in the k-th programming operation, the third programming operation S94 is the last programming operation to be executed.

[0078] As described above, the method of programming memory cells in ascending order of current is described in detail below.

[0079] Figure 11 This is a diagram illustrating programming operations according to a first embodiment of the present disclosure.

[0080] Reference Figure 11 In the programming operation according to the first embodiment, the on-state voltage applied to the unselected word line can be controlled to program the memory cell into various programming states.

[0081] Before programming the selected memory cell, an erase operation can be performed on the selected memory cell. During the erase operation, a ground voltage GND can be applied to the selected bit line Sel_BL, and a reset voltage Vreset can be applied to the source line SL. Because the erase operation is performed on all memory cells included in the selected page, all bit lines can be set to the selected bit line Sel_BL during the erase operation. During the erase operation, a turn-off voltage Voff can be applied to the selected word line Sel_WL, and an erase-on voltage eVon can be applied to the unselected word line Unsel_WL. To turn on the drain select transistor included in the same string as the selected memory cell, an erase-on voltage eVon can be applied to the selected drain select line Sel_DSL. A turn-off voltage Voff can be applied to the unselected drain select line Unsel_DSL.

[0082] During the first programming operation, which programs a memory cell in the erase state ERS with a target state of first programming state PV1, a set voltage Vset can be applied to the selected bit line Sel_BL, and a ground voltage GND can be applied to the unselected bit line Unsel_BL. Here, the ground voltage GND can be applied to the source line SL. During the first programming operation, a turn-off voltage Voff can be applied to the selected word line Sel_WL, and a first turn-on voltage 1Von can be applied to the unselected word line Unsel_WL. To turn on the drain select transistor included in the same string as the selected memory cell, a first turn-on voltage 1Von or a voltage higher than the first turn-on voltage 1Von can be applied to the selected drain select line Sel_DSL. A turn-off voltage Voff can be applied to the unselected drain select line Unsel_DSL.

[0083] A second programming operation, which programs a memory cell in a memory cell programmed to a first programming state PV1 and whose target state is a second programming state PV2, can be performed in a similar manner to the first programming operation. For example, during the second programming operation, a second on-state voltage of 2Von, higher than the first on-state voltage of 1Von, can be applied to the unselected word line Unsel_WL, and a second on-state voltage of 2Von or higher can be applied to the selected drain select line Sel_DSL. The voltages applied to the other lines can be the same as those in the first programming operation.

[0084] The third programming operation, which programs a memory cell in the memory cell programmed to the second programming state PV2 and whose target state is the third programming state PV3, can be performed in a similar manner to the second programming operation. For example, during the third programming operation, a third on-state voltage of 3Von, higher than the second on-state voltage of 2Von, can be applied to the unselected word line Unsel_WL, and a third on-state voltage of 3Von or higher can be applied to the selected drain select line Sel_DSL. The voltages applied to the other lines can be the same as those in the first programming operation.

[0085] The k-th programming operation, which programs a memory cell in the (k-1)th programming state PVk-1 to a memory cell whose target state is the k-th programming state PVk (which is the highest state), can be performed in a similar manner to the (k-1)-th programming operation. For example, during the k-th programming operation, the k-th turn-on voltage kVon, which is the highest voltage among the turn-on voltages, can be applied to the unselected word line Unsel_WL, and the k-th turn-on voltage kVon can also be applied to the selected drain selection line Sel_DSL. The voltages applied to the other lines can be the same as those applied to the other lines in the first programming operation.

[0086] Figures 12A to 12D This is a diagram illustrating the steps in a programming operation according to the first embodiment, wherein the following describes a method for programming four memory cells connected to the selected word line Sel_WL into different states.

[0087] Reference Figure 12A Assume that the target state of the memory cell connected to the first bit line BL1 and the selected word line Sel_WL is the erase state ERS, the target state of the memory cell connected to the second bit line BL2 and the selected word line Sel_WL is the first programming state PV1, the target state of the memory cell connected to the third bit line BL3 and the selected word line Sel_WL is the second programming state PV2, and the target state of the memory cell connected to the fourth bit line BL4 and the selected word line Sel_WL is the fourth programming state PV4.

[0088] Before programming the memory cell connected to the selected word line Sel_WL, an erase operation can be performed to erase the memory cell connected to the selected word line Sel_WL.

[0089] During the erase operation, a ground voltage GND can be applied to the first bit line BL1 through the fourth bit line BL4, and a reset voltage Vreset can be applied to the first source line SL1 through the fourth source line SL4. A turn-off voltage Voff can be applied to the selected word line Sel_WL, and an erase turn-on voltage eVon can be applied to the unselected word line Unsel_WL. An erase turn-on voltage eVon or a voltage higher than the erase turn-on voltage eVon can be applied to the drain select line DSL.

[0090] When the erase on-state voltage eVon is applied to the unselected word line Unsel_WL, which is located between the selected word line Sel_WL and the source lines SL1 to SL4, a current path can be formed between the selected word line Sel_WL and the source lines SL1 to SL4. Therefore, the reset voltage Vreset can be transmitted up to the memory cell connected to the selected word line Sel_WL. When the erase on-state voltage eVon is applied to the unselected word line Unsel_WL and the drain select line DSL, which are located between the selected word line Sel_WL and the bit lines BL1 to BL4, a current path can be formed between the selected word line Sel_WL and the bit lines BL1 to BL4. Therefore, the ground voltage GND can be transmitted up to the memory cell connected to the selected word line Sel_WL.

[0091] When the reset voltage Vreset is applied to the bottom of the memory cell connected to the selected word line Sel_WL and the ground voltage GND is applied to the top of the memory cell, the resistance of the memory cell connected to the selected word line Sel_WL increases, so the memory cell connected to the selected word line Sel_WL can enter the erase state ERS.

[0092] Reference Figure 12B A first programming operation can be performed on memory cells in the erase state ERS that are to be programmed to a first programming state PV1 or a higher programming state. For example, since the target state of the memory cell connected to the first bit line BL1 and the selected word line Sel_WL is the erase state ERS, during the first programming operation, the first bit line BL1 is an unselected bit line, and the remaining bit lines (i.e., the second bit line BL2 to the fourth bit line BL4) are selected bit lines. When the ground voltage GND is applied together to the first source lines SL1 to the fourth source lines SL4, the ground voltage GND can be applied to the first bit line BL1, which is an unselected bit line, and a set voltage Vset can be applied to the second bit lines BL2 to the fourth bit lines BL4.

[0093] To transmit the set voltage Vset applied to the second bit line BL2 through the fourth bit line BL4 to the selected memory cell, a first on-state voltage 1Von can be applied to the unselected word line Unsel_WL between the selected word line Sel_WL and the drain select line DSL. A first on-state voltage 1Von or a voltage higher than the first on-state voltage 1Von can also be applied to the drain select line DSL. When a voltage higher than the first on-state voltage 1Von is applied to the drain select line DSL, the set voltage Vset applied to the bit line can be transmitted to the string without loss. The first on-state voltage 1Von can be set to a positive voltage higher than the erase on-state voltage eVon.

[0094] In order to transmit the ground voltage GND applied to the second source line SL2 to the fourth source line SL4 to the selected memory cell, a first on-state voltage 1Von can also be applied to the unselected word line Unsel_WL between the selected word line Sel_WL and the second source line SL2 to the fourth source line SL4.

[0095] The first on-state voltage 1Von can be set to a voltage higher than the erase on-state voltage eVon and lower than the set voltage Vset. Since the current between the selected word line Sel_WL and the second bit line BL2 to the fourth bit line BL4 is determined based on the first on-state voltage 1Von, the voltage applied to the top electrode of the selected memory cell can be lower than the set voltage Vset applied to the second bit line BL2 to the fourth bit line BL4. Therefore, the selected memory cell can be programmed to have a first resistance. Here, the first resistance can be lower than the resistance of the memory cell in the erase state ERS, and can be the highest of the resistance values ​​that the memory cell to be programmed can have.

[0096] Reference Figure 12CA second programming operation can be performed on memory cells that are programmed to the first programming state PV1 and are to be programmed to the second programming state PV2 or a higher programming state. For example, since the memory cell connected to the first bit line BL1, the second bit line BL2, and the selected word line Sel_WL has already been programmed to the target state, during the second programming operation, the first bit line BL1 and the second bit line BL2 are unselected bit lines, and the remaining bit lines (i.e., the third bit line BL3 and the fourth bit line BL4) are selected bit lines. When the ground voltage GND is applied together to the first source lines SL1 to the fourth source lines SL4, the ground voltage GND can be applied to the first bit line BL1 and the second bit line BL2, which are unselected bit lines, and the set voltage Vset can be applied to the third bit line BL3 and the fourth bit line BL4.

[0097] In order to transmit the set voltage Vset applied to the third bit line BL3 and the fourth bit line BL4 to the selected memory cell, a second on-state voltage 2Von higher than the first on-state voltage 1Von can be applied to the unselected word line Unsel_WL between the selected word line Sel_WL and the drain select line DSL, and a voltage of the second on-state voltage 2Von or higher can be applied to the drain select line DSL.

[0098] In order to transmit the ground voltage GND applied to the third source line SL3 and the fourth source line SL4 to the selected memory cell, a second on-state voltage 2Von can also be applied to the unselected word line Unsel_WL between the selected word line Sel_WL and the third source line SL3 and the fourth source line SL4.

[0099] Since the second on-state voltage 2Von can be set to a voltage higher than the first on-state voltage 1Von and lower than the set voltage Vset, the current between the selected word line Sel_WL and the third bit line BL3 and the fourth bit line BL4 can be determined based on the second on-state voltage 2Von. Therefore, the voltage to be applied to the top electrode of the selected memory cell can be lower than the set voltage Vset applied to the third bit line BL3 and the fourth bit line BL4. Thus, the selected memory cell can be programmed to have a second resistance lower than the first resistance.

[0100] Reference Figure 12DA third programming operation can be performed on memory cells that are programmed to the second programming state PV2 and are to be programmed to the third programming state PV3. For example, since the memory cell connected to the first bit line BL1 to the third bit line BL3 and the selected word line Sel_WL has been programmed to the target state, during the third programming operation, the first bit line BL1 to the third bit line BL3 are unselected bit lines and the fourth bit line BL4 is the selected bit line. When the ground voltage GND is applied together to the first source line SL1 to the fourth source line SL4, the ground voltage GND can be applied to the first bit line BL1 to the third bit line BL3 as unselected bit lines, and the set voltage Vset can be applied to the fourth bit line BL4 as the selected bit line.

[0101] In order to transmit the set voltage Vset applied to the fourth bit line BL4 to the selected memory cell, a third on-state voltage 3Von, which is higher than the second on-state voltage 2Von, can be applied to the unselected word line Unsel_WL between the selected word line Sel_WL and the drain select line DSL, and a third on-state voltage 3Von can be applied to the drain select line DSL.

[0102] In order to transmit the ground voltage GND applied to the fourth source line SL4 to the selected memory cell, a third on-state voltage 3Von can also be applied to the unselected word line Unsel_WL between the selected word line Sel_WL and the fourth source line SL4.

[0103] The third on-state voltage 3Von can be set to a voltage higher than the second on-state voltage 2Von and lower than or equal to the set voltage Vset. Since the current between the selected word line Sel_WL and the fourth bit line BL4 can be determined based on the third on-state voltage 3Von, the voltage to be applied to the top electrode of the selected memory cell can be lower than or equal to the set voltage Vset applied to the fourth bit line BL4. Therefore, the selected memory cell can be programmed to have a third resistance lower than the second resistance.

[0104] Figure 13 This is a diagram illustrating programming operations according to a second embodiment of the present disclosure.

[0105] Reference Figure 13 In order to program memory cells to various programming states during programming operations according to the second embodiment, the on-state voltage applied to the unselected word line can be kept uniform, and the reset voltage applied to the source line can be controlled.

[0106] Before performing a programming operation on the selected memory cell, an erase operation can be performed on the selected memory cell. During the erase operation on the selected memory cell, a set voltage Vset can be applied to the selected bit line Sel_BL, and a ground voltage GND can be applied to the source line SL. Because the set voltage Vset is a positive voltage, the high-resistance state of the memory cell is defined as the erase state ERS during the programming operation according to the second embodiment. During the erase operation, a turn-off voltage Voff can be applied to the selected word line Sel_WL, and a turn-on voltage Von can be applied to the unselected word line Unsel_WL. The turn-on voltage Von can be set to the highest voltage among the first turn-on voltage 1Von to the kth turn-on voltage kVon used in the programming operation according to the first embodiment. For example, the turn-on voltage Von used in the programming operation according to the second embodiment can be the kth turn-on voltage kVon used in the programming operation according to the first embodiment. To turn on the drain selection transistor that is included in the same string as the selected memory cell, an on-state voltage Von can be applied to the selected drain selection line Sel_DSL, and an off-state voltage Voff can be applied to the unselected drain selection line Unsel_DSL.

[0107] To simultaneously program selected memory cells in the erase state ERS to the first programming state PV1 through the k-th programming state PVk, the first reset voltage 1Vreset through the k-th reset voltage kVreset can be selectively applied to the source line SL connected to the string. For example, during programming operations, a ground voltage GND can be applied to the bit line BL, a turn-off voltage Voff can be applied to the selected word line Sel_WL and the unselected drain select line Unsel_DSL, and a turn-on voltage Von can be applied to the unselected word line Unsel_WL and the selected drain select line Sel_DSL.

[0108] The following describes in detail the application of the first reset voltage 1Vreset to the kth reset voltage kVreset to the source line SL.

[0109] A first reset voltage of 1Vreset, lower than ground voltage GND, can be applied to the source line SL of the string connected to the memory cell to be programmed into the first programming state PV1. The first programming state PV1 can be defined as a first low-resistance state lower than the erase state ERS. Therefore, the current of the memory cell programmed into the first programming state PV1 is greater than the current of the memory cell in the erase state ERS.

[0110] A second reset voltage of 2Vreset, lower than the first reset voltage of 1Vreset, can be applied to the source line SL of the string connected to the memory cell to be programmed into the second programming state PV2. The second programming state PV2 can be defined as a second low-resistance state with a lower resistance than that of the first programming state PV1. Therefore, the current of the memory cell programmed into the second programming state PV2 is greater than the current of the memory cell programmed into the first programming state PV1.

[0111] Using the above scheme, in order to program the selected memory cell to the third programming state PV3 to the kth programming state PVk, the remaining reset voltages can be applied to the source line SL connected to the corresponding string, namely, the third reset voltage 3Vreset to the kth reset voltage kVreset. The first reset voltage 1Vreset to the kth reset voltage kVreset can all be set to a voltage lower than the ground voltage GND, and the kth reset voltage kVreset among the first reset voltage 1Vreset to the kth reset voltage kVreset can be set to the lowest voltage.

[0112] Figure 14A and Figure 14B This is a diagram illustrating the steps of programming operations according to the second embodiment.

[0113] Reference Figure 14A Assume that the target state of the memory cell connected to the first bit line BL1 and the selected word line Sel_WL is the erase state ERS, the target state of the memory cell connected to the second bit line BL2 and the selected word line Sel_WL is the first programming state PV1, the target state of the memory cell connected to the third bit line BL3 and the selected word line Sel_WL is the second programming state PV2, and the target state of the memory cell connected to the fourth bit line BL4 and the selected word line Sel_WL is the fourth programming state PV4.

[0114] Before programming the memory cell connected to the selected word line Sel_WL, an erase operation can be performed to erase the memory cell connected to the selected word line Sel_WL.

[0115] During the erase operation, a set voltage Vset can be applied to the first bit line BL1 through the fourth bit line BL4, and a ground voltage GND can be applied to the first source line SL1 through the fourth source line SL4. A turn-off voltage Voff can be applied to the selected word line Sel_WL, and a turn-on voltage Von can be applied to the unselected word line Unsel_WL and the selected drain selection line Sel_DSL.

[0116] The turn-on voltage Von can be set to the highest voltage among the first turn-on voltage 1Von to the kth turn-on voltage kVon used in the programming operation according to the first embodiment. For example, the kth turn-on voltage kVon used in the programming operation according to the first embodiment can be set to the turn-on voltage Von in the programming operation according to the second embodiment.

[0117] When the on-state voltage Von is applied to the unselected word line Unsel_WL, which is located between the selected word line Sel_WL and the source lines SL1 to SL4, a current path can be formed between the selected word line Sel_WL and the source lines SL1 to SL4. Therefore, the ground voltage GND can be transmitted up to the memory cell connected to the selected word line Sel_WL. When the on-state voltage Von is applied to the unselected word line Unsel_WL and the drain select line DSL, which are located between the selected word line Sel_WL and the bit lines BL1 to BL4, a current path can be formed between the selected word line Sel_WL and the bit lines BL1 to BL4. Therefore, the set voltage Vset can be transmitted up to the memory cell connected to the selected word line Sel_WL.

[0118] When the ground voltage GND is applied to the bottom of the memory cell connected to the selected word line Sel_WL and the set voltage Vset is applied to the top of the memory cell, the resistance of the memory cell connected to the selected word line Sel_WL increases, so the memory cell connected to the selected word line Sel_WL can enter the erase state ERS.

[0119] Reference Figure 14B To program the selected memory cell to the first programming state PV1 through the third programming state PV3, a turn-off voltage Voff can be applied to the selected word line Sel_WL, and a turn-on voltage Von can be applied to the unselected word line Unsel_WL and the selected drain selection line Sel_DSL. A ground voltage GND can be applied to the first bit line BL1 through the fourth bit line BL4, and different voltages can be applied to the first source line SL1 through the fourth source line SL4 depending on the target state of the selected memory cell. For example, when the target state of the memory cell connected to the first source line SL1 and the selected word line Sel_WL is the erase state ERS, the memory cell has already been erased by an erase operation, so a ground voltage GND can be applied to the first source line SL1.

[0120] When the target state of the selected memory cell connected to the second source line SL2 is the first programming state PV1, a first reset voltage of 1Vreset, lower than the ground voltage GND, can be applied to the second source line SL2. When the target state of the selected memory cell connected to the third source line SL3 is the second programming state PV2, a second reset voltage of 2Vreset, lower than the first reset voltage of 1Vreset, can be applied to the third source line SL3. When the target state of the selected memory cell connected to the fourth source line SL4 is the third programming state PV3, a third reset voltage of 3Vreset, lower than the second reset voltage of 2Vreset, can be applied to the fourth source line SL4.

[0121] Figure 15 This is a diagram illustrating programming operations according to a third embodiment of the present disclosure.

[0122] Reference Figure 15 To perform the programming operation according to the third embodiment, a source select line is provided between the word line and the source line. For example, a source select transistor can be added between the memory cell and the source line, and the source select line can be connected to the gate of the source select transistor. As in the case of the drain select line DSL, the source select lines SSL can be connected to different bit lines, and the source select lines connected to the same bit line can be separate. During the programming operation according to the third embodiment, the selected memory cell can be programmed by controlling the voltage applied to the selected source select line Sel_SSL.

[0123] Before programming the selected memory cell, an erase operation can be performed on the selected memory cell. During the erase operation, a ground voltage GND can be applied to the first bit line BL1 through the fourth bit line BL4, and a reset voltage Vreset can be applied to the source line SL. Because the erase operation is performed on all memory cells included in the selected page, all bit lines can be set to the selected bit line Sel_BL during the erase operation. During the erase operation, a turn-off voltage Voff can be applied to the selected word line Sel_WL, and an erase-on voltage eVon can be applied to the unselected word line Unsel_WL. To turn on the drain select transistor included in the same string as the selected memory cell, an erase-on voltage eVon can also be applied to the selected drain select line Sel_DSL. A turn-off voltage Voff can be applied to the unselected drain select line Unsel_DSL.

[0124] During the first programming operation, when programming a memory cell in the erase state ERS with a target state of first programming state PV1, a set voltage Vset can be applied to the selected bit line Sel_BL, and a ground voltage GND can be applied to the unselected bit line Unsel_BL. A ground voltage GND can be applied to the source line SL. During the first programming operation, a turn-off voltage Voff can be applied to the selected word line Sel_WL, and a k-th turn-on voltage kVon can be applied to the unselected word line Unsel_WL. The k-th turn-on voltage kVon can be the same as the highest voltage among the first turn-on voltage 1Von to the k-th turn-on voltage kVon used in the programming operation according to the first embodiment. To turn on the drain selection transistor included in the same string as the selected memory cell, a k-th turn-on voltage kVon can also be applied to the selected drain selection line Sel_DSL, and a turn-off voltage Voff can be applied to the unselected drain selection line Unsel_DSL. To program a memory cell whose target state is the first programming state PV1 to the first programming state PV1, a first on-state voltage 1Von can be applied to the selected source select line Sel_SSL. That is, when the first on-state voltage 1Von, which is the lowest voltage among the first on-state voltage 1Von to the kth on-state voltage kVon, is applied to the selected source select line Sel_SSL, the on-state level of the source select transistor decreases, thus reducing the hierarchy of the current path between the source line SL, which is grounded (GND), and the selected memory cell. Therefore, since the selected memory cell enters a first low-resistance state lower than the erase state ERS, the selected memory cell can be programmed to the first programming state PV1.

[0125] A second programming operation, which programs a memory cell in a memory cell programmed to a first programming state PV1 and whose target state is a second programming state PV2, can be performed in a similar manner to the first programming operation. For example, during the second programming operation, a second turn-on voltage of 2Von, higher than the first turn-on voltage of 1Von, can be applied to the selected source selection line Sel_SSL. The voltages applied to the other lines can be the same as those in the first programming operation.

[0126] The third programming operation, which programs a memory cell in the memory cell programmed to the second programming state PV2 and whose target state is the third programming state PV3, can be performed in a similar manner to the first programming operation. For example, during the third programming operation, a third turn-on voltage of 3Von, higher than the second turn-on voltage 2Von, can be applied to the selected source selection line Sel_SSL. The voltages applied to the other lines can be the same as those in the first programming operation.

[0127] The k-th programming operation, which programs a memory cell in a memory cell programmed to the (k-1)th programming state PVk-1 with a target state of PVk, can be performed in a similar manner to the first programming operation. For example, during the k-th programming operation, a k-th turn-on voltage, which is the highest of the first turn-on voltage 1Von to the k-th turn-on voltage kVon, can be applied to the selected source selection line Sel_SSL. The voltages applied to the other lines can be the same as those in the first programming operation.

[0128] Figures 16A to 16D This is a diagram illustrating the steps of programming operations according to the third embodiment.

[0129] Reference Figure 16A Assume that the target state of the memory cell connected to the first bit line BL1 and the selected word line Sel_WL is the erase state ERS, the target state of the memory cell connected to the second bit line BL2 and the selected word line Sel_WL is the first programming state PV1, the target state of the memory cell connected to the third bit line BL3 and the selected word line Sel_WL is the second programming state PV2, and the target state of the memory cell connected to the fourth bit line BL4 and the selected word line Sel_WL is the fourth programming state PV4.

[0130] Before programming the memory cell connected to the selected word line Sel_WL, an erase operation can be performed on the memory cell connected to the selected word line Sel_WL.

[0131] During the erase operation, a ground voltage GND can be applied to the first bit line BL1 through the fourth bit line BL4, and a reset voltage Vreset can be applied to the first source line SL1 through the fourth source line SL4. A turn-off voltage Voff can be applied to the selected word line Sel_WL, and an erase turn-on voltage eVon can be applied to the unselected word line Unsel_WL. An erase turn-on voltage eVon or a voltage higher than the erase turn-on voltage eVon can be applied to the selected drain selection line Sel_DSL.

[0132] When the erase on-state voltage eVon is applied to the unselected word line Unsel_WL, which is located between the selected word line Sel_WL and the source lines SL1 to SL4, a current path can be formed between the selected word line Sel_WL and the source lines SL1 to SL4. Therefore, the reset voltage Vreset can be transmitted up to the memory cell connected to the selected word line Sel_WL. When the erase on-state voltage eVon is applied to the unselected word line Unsel_WL and the selected drain select line Sel_DSL, which are located between the selected word line Sel_WL and the bit lines BL1 to BL4, a current path can be formed between the selected word line Sel_WL and the bit lines BL1 to BL4. Therefore, the ground voltage GND can be transmitted up to the memory cell connected to the selected word line Sel_WL.

[0133] When the reset voltage Vreset is applied to the bottom of the memory cell connected to the selected word line Sel_WL and the ground voltage GND is applied to the top of the memory cell, the resistance of the memory cell connected to the selected word line Sel_WL increases, so the memory cell connected to the selected word line Sel_WL can enter the erase state ERS.

[0134] Reference Figure 16B A first programming operation can be performed on a memory cell in the erase state ERS that is to be programmed to a first programming state PV1 or a higher programming state. For example, since the target state of the memory cell connected to the first source line SL1 and the selected word line Sel_WL is the erase state ERS, during the first programming operation, the first bit line BL1 is an unselected bit line, and the remaining bit lines (i.e., the second bit line BL2 to the fourth bit line BL4) are selected bit lines.

[0135] When a ground voltage GND is applied to the first source line SL1 to the fourth source line SL4, the ground voltage GND can be applied to the first bit line BL1, which is an unselected bit line, and the set voltage Vset can be applied to the second bit line BL2 to the fourth bit line BL4, which are selected bit lines.

[0136] To transmit the set voltage Vset applied to the second bit line BL2 through the fourth bit line BL4 to the selected memory cell, the highest of the on-state voltages can be applied to the unselected word line Unsel_WL between the selected word line Sel_WL and the selected drain select line Sel_DSL. For example, when the highest state among the target states of the memory cell is the third programming state PV3, a third on-state voltage 3Von corresponding to the third programming state PV3 can be applied to the unselected word line Unsel_WL. Alternatively, a third on-state voltage 3Von can be applied to the selected drain select line Sel_DSL. The third on-state voltage 3Von can be set to a positive voltage lower than the set voltage Vset.

[0137] In order to transmit the ground voltage GND applied to the first source line SL1 to the fourth source line SL4 to the selected memory cell, a third on-state voltage 3Von can also be applied to the selected word line Sel_WL and the unselected word line Unsel_WL between the first source line SL1 to the fourth source line SL4.

[0138] A first on-state voltage of 1Von, lower than the third on-state voltage of 3Von, can be applied to the selected source select line Sel_SSL. In other words, in order to program the selected memory cell to the first programming state PV1, a first on-state voltage of 1Von corresponding to the first programming state PV1 can be applied to the selected source select line Sel_SSL.

[0139] Since the current between the selected word line Sel_WL and the second source lines SL2 to SL4 can be determined based on the first on-state voltage 1Von applied to the selected source select line Sel_SSL, the voltage applied to the bottom electrode of the selected memory cell can be higher than the ground voltage GND applied to the second source lines SL2 to SL4. Therefore, the selected memory cell can be programmed to have a first resistance.

[0140] Reference Figure 16C A second programming operation can be performed on memory cells that are programmed to the first programming state PV1 and are to be programmed to the second programming state PV2 or a higher programming state. For example, since the target state of the memory cell connected to the first source line SL1 and the second source line SL2 and the selected word line Sel_WL is the erase state ERS or the first programming state PV1, during the second programming operation, the first bit line BL1 and the second bit line BL2 are unselected bit lines, while the third bit line BL3 and the fourth bit line BL4 are selected bit lines.

[0141] When ground voltage GND is applied to the first source line SL1 to the fourth source line SL4, the ground voltage GND can be applied to the first bit line BL1 and the second bit line BL2, which are unselected bit lines, and the set voltage Vset can be applied to the third bit line BL3 and the fourth bit line BL4, which are selected bit lines.

[0142] To transmit the set voltage Vset applied to the third bit line BL3 and the fourth bit line BL4 to the selected memory cell, a third on-state voltage 3Von can be applied to the unselected word line Unsel_WL between the selected word line Sel_WL and the selected drain select line Sel_DSL. Alternatively, a third on-state voltage 3Von can be applied to the selected drain select line Sel_DSL.

[0143] In order to transmit the ground voltage GND applied to the first source line SL1 to the fourth source line SL4 to the selected memory cell, a third on-state voltage 3Von can also be applied to the selected word line Sel_WL and the unselected word line Unsel_WL between the first source line SL1 to the fourth source line SL4.

[0144] A second on-state voltage of 2Von, lower than the third on-state voltage 3Von and higher than the first on-state voltage 1Von, can be applied to the selected source select line Sel_SSL. In other words, in order to program the selected memory cell to the second programming state PV2, a second on-state voltage of 2Von corresponding to the second programming state PV2 can be applied to the selected source select line Sel_SSL.

[0145] Since the current between the selected word line Sel_WL and the third and fourth source lines SL3 and SL4 can be determined based on the second on-state voltage 2Von applied to the selected source selection line Sel_SSL, the voltage applied to the bottom electrode of the selected memory cell can be higher than the ground voltage GND applied to the third and fourth source lines SL3 and SL4. Therefore, the selected memory cell can be programmed to have a second resistance lower than the first resistance.

[0146] Reference Figure 16D A third programming operation can be performed on a memory cell that is programmed to the second programming state PV2 and is to be programmed to the third programming state PV3. For example, since the target state of the memory cell connected to the first source line SL1 to the third source line SL3 and the selected word line Sel_WL is either the erase state ERS or any one of the first programming state PV1 to the second programming state PV2, during the third programming operation, the first bit line BL1 to the third bit line BL3 are unselected bit lines and the fourth bit line BL4 is selected bit line.

[0147] When the ground voltage GND is applied together to the first source line SL1 to the fourth source line SL4, the ground voltage GND can be applied to the first bit line BL1 to the third bit line BL3, which are unselected bit lines, and the set voltage Vset can be applied to the fourth bit line BL4, which is selected bit line.

[0148] To transmit the set voltage Vset applied to the fourth bit line BL4 to the selected memory cell, a third on-state voltage 3Von can be applied to the unselected word line Unsel_WL between the selected word line Sel_WL and the selected drain select line Sel_DSL. Alternatively, a third on-state voltage 3Von can be applied to the selected drain select line Sel_DSL.

[0149] In order to transmit the ground voltage GND applied to the first source line SL1 to the fourth source line SL4 to the selected memory cell, a third on-state voltage 3Von can also be applied to the unselected word line Unsel_WL between the selected word line Sel_WL and the first source line SL1 to the fourth source line SL4.

[0150] Alternatively, a third on-state voltage 3Von can be applied to the selected source select line Sel_SSL. In other words, in order to program the selected memory cell to the third programming state PV3, a third on-state voltage 3Von corresponding to the third programming state PV3 can be applied to the selected source select line Sel_SSL.

[0151] Because the current between the selected word line Sel_WL and the fourth source line SL4 can be determined based on the third on-state voltage 3Von applied to the selected source select line Sel_SSL, the ground voltage GND applied to the fourth source line SL4 can be transmitted to the bottom electrode of the selected memory cell. Therefore, the selected memory cell can be programmed to have a third resistance lower than the second resistance.

[0152] The programming operations described in the first to third embodiments can be combined with each other for execution. For example, when controlling the on-state voltage applied to the unselected word line Unsel_WL based on the target state of the selected memory cell, the reset voltage applied to the selected source line or the on-state voltage applied to the selected source select line can be controlled simultaneously.

[0153] Figure 17 This is a diagram illustrating a memory device according to the present disclosure.

[0154] Reference Figure 17 The memory device 1100 may include a memory cell array 110 in which data is stored, and peripheral circuitry 120 to 170 capable of performing programming, reading, or erasing operations.

[0155] The memory cell array 110 may include multiple memory blocks for storing data. Each memory block may include multiple memory cells, and the memory cells may be implemented as resistive memory cells according to the foregoing embodiments.

[0156] The peripheral circuits 120 to 170 may include a row decoder 120, a voltage generator 130, a page buffer group 140, a column decoder 150, an input / output circuit 160, and a control logic circuit 170.

[0157] The row decoder 120 can select a single memory block from the memory blocks included in the memory cell array 110 in response to the row address RADD, and can send an operating voltage Vop to the word line, drain select line and source select line connected to the selected memory block.

[0158] Voltage generator 130 can generate and output operating voltages Vop required for various operations in response to opcode OPCD. For example, voltage generator 130 can generate operating voltages Vop, including ground voltage, set voltage, reset voltage, turn-on voltage, erase turn-on voltage, turn-off voltage, read voltage, erase voltage, and verification voltage, in response to opcode OPCD, and can selectively output the generated operating voltages. Voltage generator 130 can control the level of the turn-on voltage to be applied to the unselected word line based on the target state of the selected memory cell in response to opcode OPCD. Voltage generator 130 can control the level of the reset voltage to be applied to the selected source line based on the target state of the selected memory cell in response to opcode OPCD. Voltage generator 130 can control the level of the turn-on voltage to be applied to the selected source select line based on the target state of the selected memory cell in response to opcode OPCD.

[0159] Page buffer group 140 can be coupled to memory cell array 110 via bit lines. For example, page buffer group 140 may include page buffers coupled to corresponding bit lines. Page buffers can operate simultaneously in response to page buffer control signal PBSIG and can temporarily store data during programming or reading operations. Page buffers can sense bit line voltages that vary with the threshold voltage of the memory cell during reading or verification operations. That is, based on the result of the sensing operation performed by the page buffers, it can be determined whether the threshold voltage of the memory cell is lower or higher than the read voltage or verification voltage.

[0160] The column decoder 150 can transfer data DATA between the input / output circuitry 160 and the page buffer group 140 in response to the column address CADD.

[0161] Input / output circuit 160 can be connected to the controller via input / output lines IO. Input / output circuit 160 can receive / output commands (CMD), addresses (ADD), and data (DATA) via input / output lines IO. For example, input / output circuit 160 can send commands (CMD) and addresses (ADD) received via input / output lines IO to control logic circuit 170, and can send data (DATA) received via input / output lines IO to column decoder 150. Input / output circuit 160 can output data (DATA) received from column decoder 150 to the controller via input / output lines IO.

[0162] The control logic circuit 170 can output the opcode OPCD, row address RADD, page buffer control signal PBSIG, and column address CADD in response to the command CMD and address ADD. For example, the control logic circuit 170 may include software that executes an algorithm in response to the command CMD and hardware that outputs various signals based on the address ADD and the algorithm. The control logic circuit 170 can perform programming operations based on the settings in the first to third embodiments described above.

[0163] Figure 18 This is a diagram illustrating a memory card system using a memory device according to the present disclosure.

[0164] Reference Figure 18 The memory card system 3000 may include a controller 3100, a memory device 3200, and a connector 3300.

[0165] The controller 3100 can be connected to the memory device 3200. The memory device 3200 can be connected to... Figure 17 The illustrated memory device 1100 is configured in the same manner. The controller 3100 can access the memory device 3200. For example, the controller 3100 can control programming, reading, or erasing operations of the memory device 3200, or it can control background operations of the memory device 3200. The controller 3100 can provide an interface between the memory device 3200 and the host. The controller 3100 can run firmware for controlling the memory device 3200. In this example, the controller 3100 may include components such as random access memory (RAM), a processor, a host interface, a memory interface, and an error correction block.

[0166] Controller 3100 can communicate with external devices via connector 3300. Controller 3100 can communicate with external devices (e.g., a host) based on a specific communication protocol. In embodiments, controller 3100 can communicate with external devices via at least one of various interface protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Fast (PCI-E), Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and High-Speed ​​Non-Volatile Memory (NVMe) protocol. In embodiments, connector 3300 can be defined by at least one of the aforementioned communication protocols.

[0167] The controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 can be integrated into a single semiconductor device, which can then form a memory card such as a Personal Computer Memory Card International Association (PCMCIA), a Compact Flash Memory Card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, Micro MMC, or eMMC), an SD card (SD, Mini SD, Micro SD, or SDHC), or a Universal Flash Memory (UFS) card.

[0168] Figure 19 This is a diagram illustrating a solid-state drive (SSD) system using a memory device according to the present disclosure.

[0169] Reference Figure 19 The SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 can exchange signals with the host 4100 through a signal connector 4001 and can receive power PWR through a power connector 4002. The SSD 4200 may include a controller 4210, memory devices 4221 to 422n, an auxiliary power supply 4230, and a cache memory 4240.

[0170] According to embodiments of this disclosure, each of the memory devices 4221 to 422n can be associated with a reference. Figure 17 The memory device 1100 described is configured in the same manner.

[0171] The controller 4210 can control the memory devices 4221 to 422n in response to signals received from the host 4100. In implementations, the signals can be signals based on the interface between the host 4100 and the SSD 4200. For example, such signals can be signals defined by at least one of various interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and High-Speed ​​Non-Volatile Memory (NVMe) interfaces.

[0172] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can be supplied with power voltage from host 4100 and can be used for charging. When power supply from host 4100 is not smooth, auxiliary power supply 4230 can provide power voltage to SSD 4200. In implementations, auxiliary power supply 4230 can be located inside or outside SSD 4200. For example, auxiliary power supply 4230 can be located within the motherboard and can also provide auxiliary power to SSD 4200.

[0173] Buffer memory 4240 can be used as a buffer memory for SSD 4200. For example, buffer memory 4240 can temporarily store data received from host 4100 or data received from memory devices 4221 to 422n, or it can temporarily store metadata (e.g., mapping tables) of memory devices 4221 to 422n. Buffer memory 4240 may include volatile memory such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR) SDRAM, and low power DDR (LPDDR) SDRAM, or non-volatile memory such as ferroelectric RAM (FRAM), resistive RAM (ReRAM), spin-transfer torque magnetic RAM (STT-MRAM), and phase-change RAM (PRAM).

[0174] In an embodiment, this disclosure allows two or more bits of data to be stored in each memory cell constituting a resistive memory device, thereby increasing the storage capacity of the resistive memory device.

[0175] Cross-reference to related applications

[0176] This application claims priority to Korean Patent Application No. 10-2021-0081963, filed with the Korean Intellectual Property Office on June 24, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A resistive memory device, the resistive memory device comprising: One or more strings, each string being connected between one or more source lines and one or more bit lines, each string comprising a collection of one or more resistive memory cells; One or more word lines, each of which is connected to a set of one or more resistive memory cells; as well as A voltage generator controls the level of the on-state voltage to be applied to one or more unselected word lines of one or more word lines based on the programming target state of a subset of resistive memory cells, the subset of resistive memory cells including one or more selected resistive memory cells in the set of one or more resistive memory cells.

2. The resistive memory device according to claim 1, wherein, The voltage generator increases the level of the turn-on voltage when the programmed target state rises.

3. The resistive memory device according to claim 2, wherein, The on-state voltage is set to a positive voltage higher than the ground voltage.

4. The resistive memory device according to claim 1, wherein, The voltage generator generates a ground voltage to be applied to one or more source lines and generates a set voltage to be applied to one or more bit lines.

5. The resistive memory device according to claim 4, wherein, The set voltage is set to a positive voltage higher than the ground voltage.

6. The resistive memory device according to claim 1, wherein, The voltage generator generates a shutdown voltage to be applied to the selected word line, which is connected to one or more selected resistive memory cells included in a subset of the resistive memory cells.

7. The resistive memory device according to claim 6, wherein, The shutdown voltage is set to the ground voltage.

8. The resistive memory device according to claim 1, wherein, When one or more source lines are respectively connected to each of the one or more strings, the voltage generator generates a ground voltage to be applied to the one or more bit lines and controls a reset voltage to be applied to one or more source lines respectively connected to the one or more strings according to the programmed target state.

9. The resistive memory device according to claim 8, wherein, The reset voltage is set to a negative voltage that is lower than the ground voltage.

10. The resistive memory device according to claim 8, wherein, The voltage generator reduces the level of the reset voltage when the programmed target state rises.

11. A method of operating a resistive memory device during a programming operation performed on a resistive memory cell, the resistive memory cell being coupled between one or more source lines and one or more bit lines, the method comprising the steps of: Apply a ground voltage to one or more source lines and apply a set voltage higher than the ground voltage to one or more bit lines selected from the one or more bit lines; A shutdown voltage is applied to the selected word line of the selected resistive memory cell connected to the resistive memory cell. as well as An on-state voltage is applied to the unselected word line of the unselected resistive memory cell connected to the resistive memory cell. The level of the on-state voltage is controlled according to the programming target state of the selected resistive memory cell.

12. The method according to claim 11, wherein, The shutdown voltage is set to the ground voltage.

13. The method according to claim 11, wherein, The on-voltage is set to a positive voltage that is higher than the off-voltage.

14. The method according to claim 11, wherein, The level of the conduction voltage is controlled to become higher as the programming target state increases.

15. The method according to claim 11, wherein, When the programming operation is performed on the selected resistive memory cell, the shutdown voltage is applied to the bit line connected to the resistive memory cell whose programming target state is erased or has been programmed to the programming target state.

16. The method of claim 11, further comprising the step of: When a resistive memory cell whose programming target state is a first programming state is programmed into the first programming state, the resistive memory cell whose programming target state is a second programming state is programmed into the first programming state.

17. The method according to claim 16, wherein, The steps for programming a resistive memory cell whose programming target state is the second programming state include the following steps: The ground voltage is applied to the unselected bit line among the one or more bit lines and to the one or more source lines, and the set voltage is applied to the remaining bit lines other than the unselected bit line. Apply a shutdown voltage to the selected word line; and A voltage higher than the on-state voltage is applied to the unselected word line.

18. A method of operating a resistive memory device, the method comprising the steps of: Apply a ground voltage to the selected position line and a reset voltage to the selected source line; Apply a shutdown voltage to the selected word line; as well as Apply a conduction voltage to the unselected word line. The reset voltage is controlled based on the programming target state of the selected memory cell connected to the selected word line.

19. The method according to claim 18, wherein, The level of the reset voltage is set to increase as the programming target state increases.

20. The method according to claim 18, wherein, The reset voltage is set to a negative voltage that is lower than the ground voltage.

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