16-channel front-end readout circuit with signal pile-up prevention function

Abstract

The application relates to a 16-channel front-end reading circuit with a signal pile-up prevention function, belonging to the field of microelectronics technology, comprising 16 analog channels, a bias generation circuit (H) and a signal pile-up prevention logic circuit (I), wherein each analog channel is composed of a charge-sensitive amplifier (A), a leakage current compensation circuit (B), a zero-pole elimination circuit (C), a shaper (D), a baseline holding circuit (E), a peak detection holding circuit (F) and a time discriminator (G). The input signals of the 16 analog channels come from the output signals of a detector, the 16 analog channels share an energy output end EOUT and a time output end TOUT, the bias circuit provides bias voltage and accurate reference voltage for the 16 channels, and the signal pile-up prevention logic circuit enables or shields any channel in the 16 channels, so that the circuit can effectively prevent the signal pile-up problem in the same channel or among the channels under high input frequency.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of microelectronics technology, and particularly relates to a readout circuit, and particularly relates to a 16-channel front-end readout circuit with a signal accumulation prevention function. BACKGROUND

[0002] Radiation detection systems are widely used in medical imaging, space exploration, security inspection, and radiation source identification. The front-end readout circuit is responsible for amplifying, filtering, and selecting the weak electrical signals output by the detector into stable voltage or current signals, so the performance of the readout circuit directly affects the final detection results. In imaging applications such as medical imaging, there is usually a certain requirement for the resolution of the final image, so the readout circuit must integrate multiple channels. Therefore, the present application integrates 16 channels.

[0003] A conventional multi-channel readout circuit, as shown in FIG. 1, includes a charge-sensitive amplifier (A), a leakage current compensation circuit (B), a zero-pole cancellation circuit (C), a shaper (D), a baseline holding circuit (E), a peak detection holding circuit (F), a time discriminator (G), and a bias generation circuit (H). After amplifying, filtering, shaping, peak holding, and time discrimination of the input signals from the detector, the energy signal EOUT and the time signal TOUT are output separately, which means that an n-channel readout circuit has as many as 2n output ports, which seriously occupies the chip area and also has the disadvantage of excessive wiring in subsequent use. Figure 1 SUMMARY The present application aims to solve the problems of the prior art. A 16-channel front-end readout circuit with a signal accumulation prevention function is proposed. The technical solution of the present application is as follows:

[0004] A 16-channel front-end readout circuit with a signal accumulation prevention function includes:

[0005] 16 analog channels, a bias generation circuit, and a signal accumulation prevention logic circuit. The analog channels are used to convert the weak electrical signals collected by the detector into stable and reliable voltage signals, and output the over-threshold signal and peak-reached flag signal of the output signal. The bias generation circuit provides the necessary bias voltage and reference voltage for the 16 analog channels and the signal accumulation prevention logic circuit. The signal accumulation prevention logic circuit is used to coordinate the 16 analog channels and prevent signal accumulation at the output end.

[0006]

[0007] ​Each analog channel comprises a charge sensitive amplifier, a leakage current compensation circuit, a zero-pole cancellation circuit, a shaper, a baseline holding circuit, a peak detection holding circuit and a time discriminator, the input of the charge sensitive amplifier is from the charge signal collected by the radiation detector, the output of the charge sensitive amplifier is connected to the input of the zero-pole cancellation circuit, the output of the zero-pole cancellation circuit is connected to the input of the baseline holding circuit and the input of the shaper, the output of the shaper, the output of the baseline holding circuit, the input of the peak detection holding circuit and the input of the time discriminator are connected together, the output of the peak detection holding circuit of each channel shares an energy output port EOUT, the output of the time discriminator and the peak detection holding circuit peak flag signal output are connected together and then input into the anti-coincidence logic circuit, the output of the anti-coincidence logic circuit is returned to the 16 analog channels and outputs a time signal TOUT, the bias generation circuit is connected to the 16 channels and the anti-coincidence logic circuit, the charge sensitive amplifier is a voltage amplifier with an integral capacitor, the charge sensitive amplifier amplifies the detector output signal into an exponential decay signal and then outputs the signal into the shaper, the shaper filters and shapes the exponential decay signal, filters out noise and shapes the signal into a quasi-Gaussian waveform, the peak detection holding circuit holds the signal peak and outputs a peak flag signal, and the time discriminator outputs an over-threshold signal by comparing the shaper output signal with a threshold signal.

[0008] Further, the leakage current compensation circuit can compensate the leakage current of the detector under bias to ensure that the charge sensitive amplifier is not saturated; the shaper is a first-order CR-RC bandpass filter, which can filter out high-frequency and low-frequency noise in the frequency domain, and shape the exponential decay signal output by the charge sensitive amplifier into a quasi-Gaussian waveform in the time domain, so that the subsequent peak detection holding circuit can better perform peak holding and output a peak flag signal.

[0009] Further, the bias generation circuit comprises a bandgap reference circuit BGREF, a differential linear voltage regulator circuit LDO, a bias circuit Bias_CSA&LCC of the charge sensitive amplifier and the leakage current compensation circuit, a bias circuit Bias_SHAPER&BLH of the shaper and the baseline holding circuit, and a bias circuit Bias_PDH&DIS of the peak detection holding circuit and the time discriminator.

[0010] The bandgap reference circuit generates a reference voltage V BG of 1.2V and a current I PTAT of 10uA which is positively correlated with temperature, V BG and I PTATAll of them are input to LDO, which adopts two-stage error amplifier and nested Miller compensation capacitor to generate reference voltage V REF , threshold voltage V TH , and other three bias voltages VBL, VBP and VCP, where VBP and VCP are input to Bias_CSA&LCC, Bias_SHAPER&BLH and Bias_PDH&DIS, VCSAP, VCSAN and VP output by Bias_CSA&LCC are connected to charge sensitive amplifier and leakage current compensation circuit of each channel, VCN, VBN, VBLP, VBNL output by Bias_SHAPER&BLH and VBL output by LDO are connected to shaper and baseline holding circuit in each analog channel, and VBNP, VCNP output by Bias_PDH&DIS are also input to peak detection holding circuit and time discriminator of each channel as bias voltages.

[0011] Further, the bandgap reference circuit BGREF adopts common circuit structure of common-source and common-gate current mirror clamping and two PNP transistors, and the ratio of radiation junction area of the transistors is 1:35, the voltage difference linear voltage regulator circuit LDO adopts conventional two-stage error amplifier structure, the frequency compensation mode adopts compensation mode of nested Miller capacitor, and the three bias circuits of bias circuit Bias_CSA&LCC of charge sensitive amplifier and leakage current compensation circuit, bias circuit Bias_SHAPER&BLH of shaper and baseline holding circuit, and bias circuit Bias_PDH&DIS of peak detection holding circuit and time discriminator all adopt conventional current mirror clamping mode to generate current required by the modules.

[0012] Further, the anti-signal accumulation logic circuit comprises two D flip-flops, D1 and D2, a two-input NAND gate with a reset end, a NOT gate and a two-input NOR gate; two inputs of the NAND gate are respectively a threshold crossing signal DISO output by an in-channel time discriminator and a peak reaching flag signal PDO output by a peak detection holding circuit, an output end of the NAND gate is connected to a clock CP end of D1 and an input end of the NOT gate, an output end of the NOT gate is connected to an input end of D2, an output end of D2 is connected to an input port of the first flip-flop, a global holding signal AHOLD is connected to the CP end of D2, an output end of D1 is a request signal REQ output to an external ADC, two inputs of the NOR gate are respectively a channel reset signal RESET and an ADC conversion completion signal ADCEND, and an output end of the NOR gate is connected to the reset end of the NAND gate.

[0013] The advantages and beneficial effects of the present application are as follows:

[0014] 1. The 16-channel front-end readout circuit with anti-signal accumulation function in the present application is used for detecting the charge signal output by a radiation detector, and outputs a voltage signal proportional to energy and a time signal of signal generation. Traditional readout circuits usually adopt an N-input-2N-output readout mode, that is, there are 2N output ports for N channels, which are output in parallel to the back end for processing, and there are disadvantages of large chip area and numerous pins. The multi-channel coordination of the traditional circuit is usually processed by the digital system of the back end, and the multi-channel coordination function is not integrated on a chip. The entire circuit of the present application integrates 16 channels and coordinates the enablement and output end of the 16 channels through a logic control circuit, so that the 16 channels share one output port, which saves the output port of the circuit, and further saves the chip area and chip output pins.

[0015] 2, The application is to solve the signal accumulation problem in the same channel and the signal accumulation problem between different channels when reading out multiple channels, and a logic circuit with a signal accumulation prevention function is proposed. The signal accumulation prevention logic circuit mainly generates a channel holding signal in time through the threshold crossing signal in the channel and the peak reaching flag signal, which is used to shield the current channel and the other 15 channels. During the shielding period, the charge sensitive amplifier and the shaper do not work. At the same time of the channel holding signal output, the whole circuit will output a request signal to the off-chip ADC, indicating that there is data in the channel to be processed at this time. After the ADC processing is completed, the ADC conversion completion signal will be input to the readout circuit, which is used to reset each channel and wait for the input of the subsequent signal. Through this method, when the time interval between two times is very short (less than 200ns), the 16-channel front-end readout circuit of the application can prevent the signal accumulation problem in the same channel and between different channels. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a traditional multi-channel block diagram.

[0017] Figure 2 is a 16-channel block diagram of the application.

[0018] Figure 3 is a bias generation circuit of the application.

[0019] Figure 4 is a signal accumulation prevention logic circuit of the application.

[0020] Figure 5 is a single-channel transient simulation result.

[0021] Figure 6 is a multi-channel transient simulation result. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the application will be described in detail below with reference to the drawings in the embodiments of the application. The described embodiments are only a part of the embodiments of the application.

[0023] The technical solution of the application to solve the above technical problems is:

[0024] In the embodiments of the application, the 16-channel readout circuit is innovative, which amplifies, filters and shapes the output signal of the radiation detector, and has the advantage of multiple channels sharing one output port. In addition, the readout circuit of the design has a signal accumulation prevention function. In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the drawings and specific embodiments.

[0025] EMBODIMENT

[0026] AsFigure 2 The 16-channel front-end readout circuit with signal pile-up prevention function comprises 16 analog channels, a bias generating circuit (H) and a signal pile-up prevention logic circuit (I). The analog channels can convert the weak electric signals collected by the detector into stable and reliable voltage signals proportional to energy, and output the over-threshold signals and peak-reached flag signals of the channels. The energy signals output by the 16 channels share an output terminal EOUT, and the over-threshold signals and peak-reached flag signals are connected to the signal pile-up prevention logic circuit, which returns control signals to each analog channel and outputs a time signal TOUT. The bias generating circuit provides necessary bias voltage and reference voltage for the 16 analog channels and the signal pile-up prevention logic circuit. The single channel mainly comprises a charge-sensitive amplifier (A), a leakage current compensation circuit (B), a zero-pole cancellation circuit (C), a shaper, a baseline holding circuit (D), a peak detection holding circuit (F) and a time discriminator (G), which are the same as those of the prior art, and will not be described here. The input of the charge-sensitive amplifier is from the charge signal collected by the radiation detector, the output of the charge-sensitive amplifier is connected to the input of the zero-pole cancellation circuit, the output of the zero-pole cancellation circuit is connected to the input of the baseline holding circuit and the input of the shaper, respectively, the output of the shaper, the output of the baseline holding circuit, the input of the peak detection holding circuit and the input of the time discriminator are connected together, the output of the peak detection holding circuit of each channel shares an energy output port EOUT, and the output of the time discriminator and the peak-reached flag signal output of the peak detection holding circuit are connected together and then input into the signal pile-up prevention logic circuit. The charge-sensitive amplifier integrates the charge signal output by the detector into an exponentially decaying voltage signal through the integral capacitor of negative feedback, the zero-pole cancellation circuit is used to offset the pole generated by the charge-sensitive amplifier, the leakage current compensation circuit can compensate the leakage current of the detector under bias to ensure that the charge-sensitive amplifier is not saturated. The shaper is a first-order CR-RC band-pass filter, which can filter out high-frequency and low-frequency noise in the frequency domain, and shape the exponentially decaying signal output by the charge-sensitive amplifier into a quasi-Gaussian waveform in the time domain, so that the subsequent peak detection holding circuit can better perform peak holding and output a peak-reached flag signal. The time discriminator can output an over-threshold signal when the waveform output by the shaper exceeds the threshold, marking that the channel is occupied. Figure 1 The 16-channel front-end readout circuit with signal pile-up prevention function comprises 16 analog channels, a bias generating circuit (H) and a signal pile-up prevention logic circuit (I). The analog channels can convert the weak electric signals collected by the detector into stable and reliable voltage signals proportional to energy, and output the over-threshold signals and peak-reached flag signals of the channels. The energy signals output by the 16 channels share an output terminal EOUT, and the over-threshold signals and peak-reached flag signals are connected to the signal pile-up prevention logic circuit, which returns control signals to each analog channel and outputs a time signal TOUT. The bias generating circuit provides necessary bias voltage and reference voltage for the 16 analog channels and the signal pile-up prevention logic circuit. The single channel mainly comprises a charge-sensitive amplifier (A), a leakage current compensation circuit (B), a zero-pole cancellation circuit (C), a shaper, a baseline holding circuit (D), a peak detection holding circuit (F) and a time discriminator (G), which are the same as those of the prior art, and will not be described here. The input of the charge-sensitive amplifier is from the charge signal collected by the radiation detector, the output of the charge-sensitive amplifier is connected to the input of the zero-pole cancellation circuit, the output of the zero-pole cancellation circuit is connected to the input of the baseline holding circuit and the input of the shaper, respectively, the output of the shaper, the output of the baseline holding circuit, the input of the peak detection holding circuit and the input of the time discriminator are connected together, the output of the peak detection holding circuit of each channel shares an energy output port EOUT, and the output of the time discriminator and the peak-reached flag signal output of the peak detection holding circuit are connected together and then input into the signal pile-up prevention logic circuit. The charge-sensitive amplifier integrates the charge signal output by the detector into an exponentially decaying voltage signal through the integral capacitor of negative feedback, the zero-pole cancellation circuit is used to offset the pole generated by the charge-sensitive amplifier, the leakage current compensation circuit can compensate the leakage current of the detector under bias to ensure that the charge-sensitive amplifier is not saturated. The shaper is a first-order CR-RC band-pass filter, which can filter out high-frequency and low-frequency noise in the frequency domain, and shape the exponentially decaying signal output by the charge-sensitive amplifier into a quasi-Gaussian waveform in the time domain, so that the subsequent peak detection holding circuit can better perform peak holding and output a peak-reached flag signal. The time discriminator can output an over-threshold signal when the waveform output by the shaper exceeds the threshold, marking that the channel is occupied.

[0027] As Figure 3As shown, the bias generation circuit includes a bandgap reference circuit (BGREF), a differential linear regulator circuit (LDO), a bias circuit for a charge-sensitive amplifier and leakage current compensation circuit (Bias_CSA&LCC), a bias circuit for a shaper and baseline hold circuit (Bias_SHAPER&BLH), and a bias circuit for a peak detection and hold circuit and a time discriminator (Bias_PDH&DIS). The bandgap reference circuit generates a 1.2V reference voltage using a current mirror clamping method. BG ) and a temperature-dependent current of 10uA (I PTAT V BG with I PTAT All inputs are fed into the LDO, which uses a two-stage error amplifier and nested Miller compensation capacitors to generate a reference voltage V. REF Threshold voltage V TH In addition, there are three other bias voltages, VBL, VBP, and VCP. VBP and VCP are input to Bias_CSA&LCC, Bias_SHAPER&BLH, and Bias_PDH&DIS. The VCSAP, VCSAN, and VP signals output by Bias_CSA&LCC are connected to the charge-sensitive amplifier and leakage current compensation circuit of each channel. The VCN, VBN, VBLP, and VBNL outputs of Bias_SHAPER&BLH, as well as the VBL output of LDO, are connected to the shaper and baseline hold circuit in each analog channel. The VBNP and VCNP outputs of Bias_PDH&DIS are also input as bias voltages to the peak detection and hold circuit and time discriminator of each channel.

[0028] The bandgap reference circuit BGREF employs a common common-source cascode current mirror clamping circuit structure with two PNP transistors, and the ratio of the transistor's radial junction area is 1:35. The differential linear regulator (LDO) circuit uses a traditional two-stage error amplifier structure, and the frequency compensation method employs nested Miller capacitors. The three bias circuits—Bias_CSA&LCC for the charge-sensitive amplifier and leakage current compensation circuit, Bias_SHAPER&BLH for the shaper and baseline hold circuit, and Bias_PDH&DIS for the peak detection and hold circuit and time discriminator—all use a conventional current mirror copying method to generate the current required by the module. Since the above structures all utilize existing technology, their specific circuit details are not described here.

[0029] like Figure 4As shown, the anti-signal accumulation logic circuit includes two D flip-flops, D1 and D2, a two-input NAND gate with a reset end, a NOT gate and a two-input NOR gate. The two inputs of the NAND gate are the over-threshold signal DISO output by the in-channel time discriminator and the peak-reached flag signal PDO output by the peak detection holding circuit, the output of the NAND gate is connected to the clock CP end of D1 and the input of the NOT gate, the output of the NOT gate is connected to the input of D2, the output of D2 is connected to the input port of the first flip-flop, the global holding signal AHOLD is connected to the CP end of D2, the output of D1 is the request signal REQ output to the external ADC, or the two inputs of the NOR gate are the channel reset signal RESET and the ADC conversion completion signal ADCEND, or the output of the NOR gate is connected to the reset end of the NAND gate. The anti-signal accumulation logic circuit mainly outputs the request signal to the external ADC by detecting the over-threshold signal and the peak-reached flag signal, and returns the HOLD signal to the current channel to keep the current channel from being disturbed, and releases the current channel and the other 15 channels when the external ADC conversion is completed.

[0030] Simulation results

[0031] As shown in Figure 5 , the CZTO is the output signal of the CZT detector, and the charge signals with equivalent charge amounts of 8 fC, 10 fC and 5 fC are injected at 0 ns, 500 ns and 1500 ns, respectively. When the output signal SPO of the SHAPER exceeds the set threshold VTH, the time discriminator outputs the over-threshold signal DISO. PHO first rises with SPO, and when SPO reaches the peak value, PHO keeps the peak value signal unchanged, and then PDH outputs the peak flag signal PDO. At the same time, the REQ signal is output to pull up the HOLD signal, and the REQ signal indicates that the current channel is occupied and sent to the external ADC, and the HOLD signal will close the PDH and DIS of the current channel and the remaining 15 channels, to ensure that the incident signal injected into the current channel is shielded during the external ADC conversion. As shown in Figure 4 , during the period when the HOLD signal is high, the second signal injection does not trigger DIS and PDH, and PDO always maintains the peak value of the first signal; after the ADC conversion is completed, an ADCEND signal is returned to the current channel to reset the channel and prepare for the next incident. As shown in the third signal at 1500 ns, through simulation, it can be seen that the single-channel readout timing can effectively avoid the signal accumulation in the single-channel.

[0032] As shown in Figure 6As shown, under the same conditions, 8fC of charge is injected into the first channel at 0ns, and then 10fC and 5fC of charge signals are sequentially injected into the second channel at 500ns and 1500ns respectively. The transient simulation is performed on the 16 channels to obtain the multi-channel timing simulation result. The 16 channels share one output terminal (OUT). SPO1 and SPO2 are the output waveforms of the two channels SHAPER respectively, REQ1 and REQ2 are the request signals of the two channels respectively, and REQ is the overall request signal of the 16 channels or thereafter. When the first channel is incident, the PDH circuit of the channel will connect the channel peak value holding signal to the shared output terminal OUT through the transmission gate. After the peak value is detected, the REQ1 signal of the first channel will be pulled high, and the remaining 15 channels will be disabled through the REQ signal. At 500ns, that is, the data of the first channel is not processed, 10fC of charge signal is output to the second channel. As can be seen from the figure, there is no peak value signal of the second incident at the OUT port, and the OUT port still maintains the peak value of the first incident. At 1500ns, that is, the data of the first channel has been processed, 5fC of charge is injected into the second channel, and it can be seen that the REQ2 output is normal and the third incident signal is well maintained during the high level of REQ2. When REQ is pulled low, the other channels are released to wait for the next incident. It can be seen that the multi-channel readout circuit designed in this paper can not only avoid the signal accumulation in the single channel, but also avoid the signal accumulation between channels while sharing one output port.

[0033] As can be seen from the above results, the 16-channel front-end readout circuit with the signal accumulation prevention function meets the needs of the radiation detector front-end readout circuit, 16 channels share one output port, and can prevent signal accumulation in the channel and between channels.

[0034] It should also be noted that the terms "comprising", "containing" or any other variant thereof are intended to cover non-exclusive inclusions, such that a process, method, article or apparatus that comprises a list of elements does not only include those elements, but can also include other elements not expressly listed or inherent to such process, method, article or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus that includes the element.

[0035] The above examples are understood to be used only for illustrating the present application and not for limiting the protection scope of the present application. After reading the content of the present application, the skilled person can make various changes or modifications to the present application, and these equivalent changes and modifications also fall within the scope defined by the claims of the present application.

Claims

1. A 16-channel front-end readout circuit with anti-signal stacking function, characterized in that, include: The system includes 16 analog channels, a bias generation circuit, and an anti-signal accumulation logic circuit. The analog channels convert the weak electrical signals collected by the detector into stable and reliable voltage signals, and output over-threshold signals and peak-reaching marker signals. The bias generation circuit provides bias voltage and reference voltage for the 16 analog channels and the anti-signal accumulation logic circuit, which coordinates the 16 analog channels and prevents signal accumulation at the output. Each analog channel includes a charge-sensitive amplifier, a leakage current compensation circuit, a pole-zero elimination circuit, a shaper, a baseline hold circuit, a peak detection and hold circuit, and a time discriminator. The input of the charge-sensitive amplifier comes from the charge signal collected by the radiation detector. The output of the charge-sensitive amplifier is connected to the input of the pole-zero elimination circuit. The output of the pole-zero elimination circuit is connected to the input of the baseline hold circuit and the input of the shaper. The outputs of the shaper, the baseline hold circuit, the peak detection and hold circuit, and the time discriminator are connected together. The outputs of the peak detection and hold circuit of each channel share a common energy output port EOUT. The output of the time discriminator and the peak mark of the peak detection and hold circuit are also connected together. After the signal outputs are connected together, they are input into the anti-signal stacking logic circuit. The output of the anti-signal stacking logic circuit is then returned to the 16 analog channels and outputs the time signal TOUT. The bias generation circuit is connected to the 16 channels and the anti-signal stacking logic circuit respectively. The charge-sensitive amplifier is a voltage amplifier with an integrating capacitor. The charge-sensitive amplifier amplifies the detector output signal into an exponentially decaying signal and then outputs it to the shaper. The shaper can filter and shape this exponentially decaying signal, filtering out noise and shaping the signal waveform into a quasi-Gaussian waveform. The peak detection and holding circuit can hold the peak of the signal and output the peak mark signal. The time discriminator outputs the over-threshold signal by comparing the shaper output signal with the threshold signal. The anti-signal accumulation logic circuit includes two D flip-flops, D1 and D2, and also includes a two-input NAND gate with a reset terminal, an NOT gate, and a two-input NOR gate. The two inputs of the NAND gate are the over-threshold signal DISO output by the channel time discriminator and the peak mark signal PDO output by the peak detection and hold circuit, respectively. The output of the NAND gate is connected to the clock CP terminal of D1 and the input of the NOT gate. The output of the NOT gate is connected to the input of D2. The output of D2 is connected to the input port of the first flip-flop. The global hold signal AHOLD is connected to the CP terminal of D2. The output of D1 is the request signal REQ output to the external ADC. The two inputs of the NOR gate are the channel reset signal RESET and the ADC conversion completion signal ADCEND, respectively. The output of the NOR gate is connected to the reset terminal of the NAND gate. The anti-signal accumulation logic circuit mainly maintains the channel from interference by detecting the over-threshold signal and the peak mark signal, outputting a request signal to the external ADC, and returning a HOLD signal to the channel. When the external ADC conversion is completed, it releases the channel and the other 15 channels.

2. The 16-channel front-end readout circuit with anti-signal stacking function according to claim 1, characterized in that, The leakage current compensation circuit can compensate for the leakage current of the detector under bias voltage, ensuring that the charge-sensitive amplifier is not saturated; the shaper is a first-order CR-RC bandpass filter, which can filter out high-frequency and low-frequency noise in the frequency domain and shape the exponentially decaying signal output by the charge-sensitive amplifier into a quasi-Gaussian waveform in the time domain, so that the subsequent peak detection and hold circuit can better hold the peak, and the peak mark signal is output by the peak detection and hold circuit.

3. A 16-channel front-end readout circuit with anti-signal stacking function according to claim 1, characterized in that, The bias generation circuit includes a bandgap reference circuit BGREF, a differential voltage linear regulator circuit LDO, a bias circuit Bias_CSA&LCC for a charge-sensitive amplifier and a leakage current compensation circuit, a bias circuit Bias_SHAPER&BLH for a shaper and a baseline hold circuit, and a bias circuit Bias_PDH&DIS for a peak detection hold circuit and a time discriminator. The bandgap reference circuit generates a reference voltage V of 1.2V. BG And a current I that is positively correlated with temperature, which is 10uA. PTAT V BG with I PTAT All inputs are fed into the LDO, which generates a reference voltage V. REF Threshold voltage V TH In addition, there are three other bias voltages, VBL, VBP, and VCP. VBP and VCP are input to Bias_CSA&LCC, Bias_SHAPER&BLH, and Bias_PDH&DIS. The VCSAP, VCSAN, and VP signals output by Bias_CSA&LCC are connected to the charge-sensitive amplifier and leakage current compensation circuit of each channel. The VCN, VBN, VBLP, and VBNL outputs of Bias_SHAPER&BLH, as well as the VBL output of LDO, are connected to the shaper and baseline hold circuit in each analog channel. The VBNP and VCNP outputs of Bias_PDH&DIS are also input as bias voltages to the peak detection and hold circuit and time discriminator of each channel.

4. A 16-channel front-end readout circuit with anti-signal stacking function according to claim 3, characterized in that, The bandgap reference circuit BGREF uses a common circuit structure with common source and common gate current mirror clamping and consists of two PNP transistors with a transistor radial junction area ratio of 1:

35. The differential voltage linear regulator circuit LDO uses a traditional two-stage error amplifier structure, and the frequency compensation method uses nested Miller capacitors. The three bias circuits—Bias_CSA&LCC for the charge-sensitive amplifier and leakage current compensation circuit, Bias_SHAPER&BLH for the shaper and baseline hold circuit, and Bias_PDH&DIS for the peak detection and hold circuit and time discriminator—all use a conventional current mirror copying method to generate the current required by the module.

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