A fully integrated low jitter phase-locked loop

Abstract

The present invention provides a fully integrated low-jitter phase-locked loop, comprising a frequency detector, a first charge pump, a second charge pump, a third charge pump, an on-chip loop filter, a linear voltage-controlled leakage compensation circuit, a voltage-controlled oscillator, and a programmable frequency divider. The capacitor in the on-chip loop filter uses a thin-gate MOS capacitor to save area, the first charge pump and the second charge pump can reduce the size of the capacitor in the loop filter, further reduce the area, and facilitate on-chip integration; the thin-gate MOS capacitor has a large leakage at high temperature, the third charge pump and the linear voltage-controlled leakage compensation circuit realize leakage compensation for the on-chip filter capacitor, and reduce the jitter of the phase-locked loop output signal.

Description

Technical Field

[0001] The invention relates to the field of frequency synthesizers, and in particular to a fully integrated low-jitter phase-locked loop circuit. Background Art

[0002] Phase-locked loops can be used in communication transceivers to provide local oscillator signals for frequency conversion systems; they can also be used in single-chip processor chips to provide clock signals for digital units therein. A fully integrated phase-locked loop can reduce the number of peripheral components and reduce the complexity of the system. The capacitors in the loop filter within the phase-locked loop are the difficulty in achieving full integration of the phase-locked loop, especially in phase-locked loops with large frequency division ratios. To ensure the stability of the loop, the capacitors in the loop filter can reach the nanofarad level, and the capacitance density of thin-gate MOS capacitors is much greater than that of thick-gate MOS capacitors, MIM capacitors, and metal finger capacitors. Most of the capacitors in the loop filter use thin-gate MOS capacitors to save chip area. However, the gate leakage of thin-gate MOS capacitors is large, causing sawtooth ripples in the control voltage of the voltage-controlled oscillator in the phase-locked loop, which in turn causes jitter in the output clock signal of the phase-locked loop. Summary of the invention

[0003] Purpose of the invention: In order to overcome at least one problem of the prior art, the present invention provides a fully integrated phase-locked loop with small area and low jitter.

[0004] In order to achieve the above object, the present invention adopts the following technical solutions:

[0005] A fully integrated low-jitter phase-locked loop comprises a frequency detector, a first charge pump, a second charge pump, a third charge pump, an on-chip loop filter, a linear voltage-controlled leakage compensation circuit, a voltage-controlled oscillator and a programmable frequency divider.

[0006] The frequency and phase detector detects the frequency and phase of the input reference signal and the frequency-divided signal, and outputs a pull-up control signal UP and a pull-down control signal DN of the charge pump according to the detection results.

[0007] The first charge pump is a main charge pump of the phase-locked loop, the pull-up control signal UP output by the phase frequency detector controls the pull-up current, and the pull-down control signal DN controls the pull-down current;

[0008] The second charge pump has an output current direction opposite to that of the first charge pump, that is, the pull-up control signal UP output by the frequency detector and the phase detector controls the pull-down current, and the pull-down control signal DN controls the pull-up current, and cooperates with the first charge pump to reduce the size of the capacitor in the on-chip loop filter;

[0009] The third charge pump has the same output current direction as the second charge pump, that is, the pull-up control signal UP output by the frequency detector and phase detector controls the pull-down current, and the pull-down control signal DN controls the pull-up current, which is used to charge and discharge the capacitor in the linear voltage-controlled leakage compensation circuit.

[0010] The linear voltage-controlled leakage compensation circuit is used to detect the output voltage of the third charge pump and compensate for the leakage of the capacitors in the on-chip loop filter;

[0011] The on-chip loop filter is used to filter the output signal of the first charge pump to obtain a filtered signal;

[0012] The voltage-controlled oscillator is used to output a clock signal according to the filtered signal;

[0013] The programmable frequency divider is used to divide the frequency of the clock signal and output the divided signal to the frequency discriminator and phase detector.

[0014] Further, the on-chip loop filter is of a second-order structure, including a first resistor R1, a first capacitor C1, and a second capacitor C2. The output terminal VC1 of the first charge pump is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the output terminal VC2 of the second charge pump and also to one end of the first capacitor C1. The other end of the first capacitor C1 is connected to the ground. One end of the second capacitor C2 is connected to the output terminal VC1 of the first charge pump, and the other end is grounded. VC1 is the control voltage of the voltage-controlled oscillator. The first capacitor C1 and the second capacitor C2 in the on-chip loop filter both adopt thin-gate MOS capacitors to reduce the area.

[0015] Further, the direction of the output current of the second charge pump is opposite to that of the first charge pump, and the current magnitude of the second charge pump is a times that of the first charge pump, where 0 < a < 1. The current magnitude of the first charge pump is I CP , the current magnitude of the second charge pump is a*I CP , the current magnitude of the third charge pump is I CP3 . Then, for the on-chip loop filter, the current flowing through the first resistor R1 and the second capacitor C2 is still the current I of the first charge pump CP , and the second charge pump only acts on the first capacitor C1, that is, the current flowing through the first capacitor C1 is the sum of the currents of the first charge pump and the second charge pump, that is, (1 - a)*I CP . When the first capacitor C1 is 1 - a times that when there is only the first charge pump, their transfer functions are equivalent, that is, the second charge pump is equivalent to amplifying the first capacitor C1 by 1 / (1 - a) times. The first charge pump and the second charge pump can reduce the size of the capacitors in the loop filter, further reduce the area, and are easy to integrate on the chip.

[0016] Furthermore, the current of the third charge pump is a small current, and its direction is opposite to that of the first charge pump. The greater the leakage of the capacitor in the on-chip loop filter, the greater the pull-down current of the third charge pump, that is, the smaller the voltage at the output end of the third charge pump; the linear voltage-controlled leakage compensation circuit detects the output voltage of the third charge pump. When the voltage at the output end of the third charge pump decreases, the linear voltage-controlled leakage compensation circuit performs leakage compensation on the capacitor in the on-chip loop filter, and the size of the compensation current is linearly related to the size of the voltage at the output end of the third charge pump, thereby reducing the jitter of the phase-locked loop output signal.

[0017] Furthermore, the linear voltage-controlled compensation circuit includes a first PMOS tube M1, a third capacitor C3 and a second resistor R2, the output end of the third charge pump is connected to the gate of the first PMOS tube M1, the source of the first PMOS tube M1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the power supply voltage VDD; one end of the third capacitor C3 is connected to the gate of the first PMOS tube M1, and the other end is connected to the power supply voltage VDD; the drain of the first PMOS tube M1 is connected to the output end of the second charge pump; the second resistor R2 is connected between the source of the first PMOS tube M1 and the power supply, so that the drain current of the first PMOS tube M1 is linearly related to the gate voltage.

[0018] Furthermore, the leakage of the third capacitor C3 is much smaller than the leakage of the capacitor in the on-chip loop filter, and can be implemented by using a thick-gate MOS capacitor, a MIM capacitor or a metal finger capacitor.

[0019] Furthermore, the capacitor in the on-chip loop filter is implemented by a thin-gate MOS capacitor to reduce the capacitor area.

[0020] Furthermore, the frequency and phase detector includes a first D flip-flop, a second D flip-flop and an AND gate, wherein the D input terminal of the first D flip-flop is connected to the power supply voltage VDD, the clock input terminal CK is connected to the reference signal Fref, and the output terminal Q is connected to the pull-up control signal UP; the D input terminal of the second D flip-flop is connected to the power supply voltage VDD, the clock input terminal CK is connected to the frequency division signal Fdiv, and the output terminal Q is connected to the pull-down control signal DN; UP and DN are respectively connected to the two input terminals of the AND gate, and the output terminal of the AND gate is connected to the reset input terminal R of the first D flip-flop and the reset input terminal R of the second D flip-flop.

[0021] Furthermore, the bias voltage generating circuit provides bias voltages for the first charge pump, the second charge pump and the third charge pump, including providing a first bias voltage VN1 and a second bias voltage VN2 for the NMOS tubes in the first charge pump, the second charge pump and the third charge pump, and providing a third bias voltage VP1 and a fourth bias voltage VP2 for the PMOS tube.

[0022] Further, the first charge pump includes a fourteenth NMOS tube M14, a fifteenth NMOS tube M15, a sixteenth PMOS tube M16, a seventeenth PMOS tube M17, a first switch SW1, and a second switch SW2. The fourteenth NMOS tube M14 and the fifteenth NMOS tube M15 form an NMOS cascode current source to provide a pull-down current; the sixteenth PMOS tube M16 and the seventeenth PMOS tube M17 form a PMOS cascode current source to provide a pull-up current. The gate of the fourteenth NMOS tube M14 is connected to the first bias voltage VN1, the source is grounded, and the drain is connected to the source of the fifteenth NMOS tube M15. The gate of the fifteenth NMOS tube M15 is connected to the second bias voltage VN2, and the drain is connected to one end of the second switch SW2. The other end of the second switch SW2 is connected to the output end VC1 of the first charge pump. The gate of the seventeenth PMOS tube M17 is connected to the third bias voltage VP1, the source is connected to the power supply voltage VDD, the drain is connected to the source of the sixteenth PMOS tube M16, the gate of the sixteenth PMOS tube M16 is connected to the fourth bias voltage VP2, the drain is connected to one end of the first switch SW1, and the other end of the first switch SW1 is connected to the output end VC1 of the first charge pump. The control end of the first switch SW1 is connected to the pull-up control signal UP, and the control end of the second switch SW2 is connected to the pull-down control signal DN;

[0023] The circuit structures of the second charge pump and the third charge pump are the same as that of the first charge pump, but the output current directions are opposite to that of the first charge pump, that is, the pull-up control signal UP output by the frequency detector and phase detector controls the pull-down current, and the pull-down control signal DN controls the pull-up current.

[0024] In order to achieve the above-mentioned purpose, the present invention provides a beneficial effect: the fully integrated phase-locked loop of the present invention can reduce the size of the capacitor in the on-chip loop filter, and at the same time the linear voltage-controlled leakage compensation circuit can compensate for the leakage of the capacitor, thereby realizing a fully integrated, small-area, low-jitter on-chip phase-locked loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more clear.

[0026] Figure 1 It is a structural block diagram of the fully integrated low-jitter phase-locked loop of the present invention.

[0027] Figure 2 It is a structural diagram of the frequency and phase detector of the present invention.

[0028] Figure 3 It is a structural diagram of the charge pump and the linear voltage-controlled leakage compensation circuit of the present invention.

[0029] Figure 4 It is a waveform diagram of the linear voltage-controlled leakage compensation circuit of the present invention when it is closed and opened. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] The fully integrated low-jitter phase-locked loop provided in this embodiment can be applied to communication transceiver to provide a local oscillator signal for a frequency conversion system; it can also be used in a single-chip processor chip to provide a clock signal for a digital unit therein.

[0032] like Figure 1 As shown, this embodiment provides a fully integrated low-jitter phase-locked loop, including a phase frequency detector, a first charge pump, a second charge pump, a third charge pump, an on-chip loop filter, a linear voltage-controlled leakage compensation circuit, a voltage-controlled oscillator, and a programmable frequency divider. The reference signal output by the crystal oscillator is connected to the reference signal input terminal of the phase frequency detector, and the phase frequency detector outputs a pull-up control signal UP and a pull-down control signal DN. UP is connected to the control terminal of the pull-up switch of the first charge pump, the control terminal of the pull-down switch of the second charge pump, and the control terminal of the pull-down switch of the third charge pump; DN is connected to the control terminal of the pull-down switch of the first charge pump, the control terminal of the pull-up switch of the second charge pump, and the control terminal of the pull-up switch of the third charge pump. The output terminal VC1 of the first charge pump is connected to the voltage-controlled oscillator after being filtered by the on-chip loop filter, the output terminal VC2 of the second charge pump is connected to one end of the first capacitor C1 in the on-chip loop filter, the output terminal of the third charge pump is connected to the input terminal of the linear voltage-controlled leakage compensation circuit, and the output terminal of the linear voltage-controlled leakage compensation circuit is connected to the output terminal VC2 of the second charge pump. The output end of the voltage controlled oscillator is connected to the input end of the programmable frequency divider, and the output end of the programmable frequency divider is connected to the frequency division signal input end of the frequency and phase detector.

[0033] In the present invention, the capacitor in the on-chip loop filter adopts a thin-gate MOS capacitor to save area, the first charge pump and the second charge pump can reduce the size of the capacitor in the loop filter, further reduce the area, and facilitate on-chip integration; the thin-gate MOS capacitor has a large leakage at high temperature, the third charge pump and the linear voltage-controlled leakage compensation circuit realize leakage compensation for the on-chip filter capacitor, and reduce the jitter of the phase-locked loop output signal.

[0034] In this embodiment, the frequency detector detects the frequency and phase of the input reference signal and the frequency-divided signal, and outputs the pull-up control signal UP and the pull-down control signal DN of the charge pump according to the detection results. Figure 2 As shown, as a preferred solution, the frequency discriminator and phase detector includes a first D flip-flop, a second D flip-flop and an AND gate. The D input terminal of the first D flip-flop is connected to the power supply voltage VDD, the clock input terminal CK is connected to the reference signal Fref, and the output terminal Q is connected to the pull-up control signal UP. The D input terminal of the second D flip-flop is connected to the power supply voltage VDD, the clock input terminal CK is connected to the divided frequency signal Fdiv, and the output terminal Q is connected to the pull-down control signal DN. UP and DN are respectively connected to the two input terminals of the AND gate, and the output terminal of the AND gate is connected to the reset input terminal R of the first D flip-flop and the reset input terminal R of the second D flip-flop.

[0035] In the present invention, the first charge pump is the main charge pump of the phase-locked loop. The pull-up control signal UP output by the frequency discriminator and phase detector controls the pull-up current, and the pull-down control signal DN controls the pull-down current; the second charge pump has an output current direction opposite to that of the first charge pump, that is, the pull-up control signal UP output by the frequency discriminator and phase detector controls the pull-down current, and the pull-down control signal DN controls the pull-up current, which can cooperate with the first charge pump to reduce the size of the capacitor in the on-chip loop filter; the third charge pump has an output current direction the same as that of the second charge pump, and charges and discharges the capacitor in the linear voltage-controlled leakage compensation circuit.

[0036] In this embodiment, the on-chip loop filter is of a second-order structure, including a first resistor R1, a first capacitor C1 and a second capacitor C2. The output terminal VC1 of the first charge pump is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the output terminal VC2 of the second charge pump and is also connected to one end of the first capacitor C1. The other end of the first capacitor C1 is connected to the ground. One end of the second capacitor C2 is connected to the output terminal VC1 of the first charge pump, and the other end is grounded. VC1 is the control voltage of the voltage-controlled oscillator. The first capacitor C1 and the second capacitor C2 in the loop filter both adopt thin-gate MOS capacitors to reduce the area.

[0037] In the present invention, the output current direction of the second charge pump is opposite to that of the first charge pump, and the current magnitude of the second charge pump is a times that of the first charge pump, where 0 < a < 1. Denote the current magnitude of the first charge pump as I CP , and the current magnitude of the second charge pump as a*I CP , and the current magnitude of the third charge pump as I CP3 . Then for the on-chip loop filter, the current flowing through the first resistor R1 and the second capacitor C2 is still the current I of the first charge pump CP , and the second charge pump only acts on the first capacitor C1, that is, the current flowing through the first capacitor C1 is the sum of the currents of the first charge pump and the second charge pump, that is, (1 - a)*I CP. When the first capacitor C1 is 1-a times of that when there is only the first charge pump, the transfer functions of the two are equivalent, that is, the second charge pump is equivalent to amplifying the first capacitor C1 by 1 / (1-a) times. The current of the third charge pump is a small current, and its direction is opposite to that of the first charge pump. The greater the capacitance leakage in the on-chip loop filter, the greater the pull-down current of the third charge pump, that is, the smaller the voltage at the output end of the third charge pump; the linear voltage-controlled leakage compensation circuit detects the output voltage of the third charge pump, and performs leakage compensation on the capacitance in the on-chip loop filter, and the magnitude of the compensation current I COMP The voltage at the output terminal of the third charge pump is linearly related.

[0038] As a preferred solution, Figure 3As shown, the first charge pump, the second charge pump, and the third charge pump use the same bias voltage, which is provided by the same bias voltage generating circuit, and the current size of the charge pump is determined by the width of the MOS tube. The bias voltage generating circuit provides two bias voltages VN1 and VN2 for the NMOS tube, and two bias voltages VP1 and VP2 for the PMOS tube. The bias voltage generating circuit includes a first current source IB1, a second current source IB2, the second NMOS tube to the eighth NMOS tube M2, M3, M4, M5, M6, M7, M8, and the tenth PMOS tube to the thirteenth PMOS tube M10, M11, M12 and M13. The first current source IB1 is connected to the drain of the second NMOS tube M2 and the gate of the third NMOS tube M3, the gate of the second NMOS tube M2 is connected to the gate of the fourth NMOS tube M4, the source of the second NMOS tube M2 is connected to the drain of the third NMOS tube M3, the source of the third NMOS tube M3 is grounded, and the gate of the third NMOS tube M3 is the first bias voltage VN1. The second current source IB2 is connected to the gate of the fourth NMOS tube M4, the gate of the fourth NMOS tube M4 and the gate of the fifth NMOS tube M5, the source of the fourth NMOS tube M4 is connected to the drain of the fifth NMOS tube M5, the source of the fifth NMOS tube M5 is grounded, and the gate of the fifth NMOS tube M5 is the second bias voltage VN2. The first bias voltage VN1 is connected to the gates of the seventh NMOS tube M7 and the ninth NMOS tube M9, and the second bias voltage VN2 is connected to the gates of the sixth NMOS tube M6 and the eighth NMOS tube M8. The source of the seventh NMOS tube M7 is grounded, and the drain is connected to the source of the sixth NMOS tube M6, and the drain of the sixth NMOS tube M6 is connected to the drain of the tenth PMOS tube M10; the source of the ninth NMOS tube M9 is grounded, and the drain is connected to the source of the eighth NMOS tube M8, and the drain of the eighth NMOS tube M8 is connected to the drain of the twelfth PMOS tube M12. The gate of the tenth PMOS tube M10 is connected to the gate of the twelfth PMOS tube M12 and the gate of the thirteenth PMOS tube M13, the source of the tenth PMOS tube M10 is connected to the drain of the eleventh PMOS tube M11, the source of the eleventh PMOS tube M11 is connected to the power supply voltage VDD, the gate of the eleventh PMOS tube M11 is connected to the drain of the tenth PMOS tube M10, which is the third bias voltage VP1. The source of the twelfth PMOS tube M12 is connected to the drain of the thirteenth PMOS tube M13, the source of the thirteenth PMOS tube M13 is connected to the power supply voltage VDD, and the gate of the thirteenth PMOS tube M13 is the fourth bias voltage VP2.

[0039] In this embodiment, the first charge pump includes a fourteenth NMOS tube M14, a fifteenth NMOS tube M15, a sixteenth PMOS tube M16, a seventeenth PMOS tube M17, a first switch SW1, and a second switch SW2. The fourteenth NMOS tube M14 and the fifteenth NMOS tube M15 form an NMOS cascode current source to provide a pull-down current; the sixteenth PMOS tube M16 and the seventeenth PMOS tube M17 form a PMOS cascode current source to provide a pull-up current. The gate of the fourteenth NMOS tube M14 is connected to the first bias voltage VN1, the source is grounded, and the drain is connected to the source of the fifteenth NMOS tube M15. The gate of the fifteenth NMOS tube M15 is connected to the second bias voltage VN2, and the drain is connected to one end of the second switch SW2. The other end of the second switch SW2 is connected to the output end VC1 of the first charge pump. The gate of the seventeenth PMOS tube M17 is connected to the third bias voltage VP1, the source is connected to the power supply voltage VDD, the drain is connected to the source of the sixteenth PMOS tube M16, the gate of the sixteenth PMOS tube M16 is connected to the fourth bias voltage VP2, the drain is connected to one end of the first switch SW1, and the other end of the first switch SW1 is connected to the output end VC1 of the first charge pump. The control end of the first switch SW1 is connected to the pull-up control signal UP, and the control end of the second switch SW2 is connected to the pull-down control signal DN.

[0040] In this embodiment, the second charge pump includes an eighteenth NMOS tube M18, a nineteenth NMOS tube M19, a twentieth PMOS tube M20, a twenty-first PMOS tube M21, a third switch SW3, and a fourth switch SW4. The eighteenth NMOS tube M18 and the nineteenth NMOS tube M19 form an NMOS cascode current source to provide a pull-down current; the twentieth PMOS tube M20 and the twenty-first PMOS tube M21 form a PMOS cascode current source to provide a pull-up current. The gate of the eighteenth NMOS tube M18 is connected to the voltage VN1, the source is grounded, and the drain is connected to the source of the nineteenth NMOS tube M19. The gate of the nineteenth NMOS tube M19 is connected to the voltage VN2, and the drain is connected to one end of the fourth switch SW4. The other end of the fourth switch SW4 is connected to the output end VC2 of the second charge pump. The gate of the 21st PMOS transistor M21 is connected to the voltage VP1, the source is connected to the power supply voltage VDD, the drain is connected to the source of the 20th PMOS transistor M20, the gate of the 20th PMOS transistor M20 is connected to the voltage VP2, the drain is connected to one end of the third switch SW3, and the other end of the third switch SW3 is connected to the output end VC2 of the second charge pump. The control end of the third switch SW3 is connected to the pull-down control signal DN, and the control end of the fourth switch SW4 is connected to the pull-up control signal UP.

[0041] In this embodiment, the third charge pump includes a twenty-second NMOS tube M22, a twenty-third NMOS tube M23, a twenty-fourth PMOS tube M24, a twenty-fifth PMOS tube M25, a fifth switch SW5, and a sixth switch SW6. The twenty-second NMOS tube M22 and the twenty-third NMOS tube M23 form an NMOS cascode current source to provide a pull-down current; the twenty-fourth PMOS tube M24 and the twenty-fifth PMOS tube M25 form a PMOS cascode current source to provide a pull-up current. The gate of the twenty-second NMOS tube M22 is connected to the voltage VN1, the source is grounded, and the drain is connected to the source of the twenty-third NMOS tube M23. The gate of the twenty-third NMOS tube M23 is connected to the voltage VN2, and the drain is connected to one end of the sixth switch SW6. The other end of the sixth switch SW6 is connected to the output end of the third charge pump. The gate of the twenty-fifth PMOS tube M25 is connected to the voltage VP1, the source is connected to the power supply voltage VDD, the drain is connected to the source of the twenty-fourth PMOS tube M24, the gate of the twenty-fourth PMOS tube M24 is connected to the voltage VP2, the drain is connected to one end of the fifth switch SW5, and the other end of the fifth switch SW5 is connected to the output end of the third charge pump. The control end of the fifth switch SW5 is connected to the pull-down control signal DN, and the control end of the sixth switch SW6 is connected to the pull-up control signal UP.

[0042] As a preferred solution, Figure 3 As shown, the linear voltage-controlled compensation circuit includes a first PMOS tube M1, a third capacitor C3 and a second resistor R2. The output end of the third charge pump is connected to the gate of the first PMOS tube M1, the source of the first PMOS tube M1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the power supply voltage VDD. One end of the third capacitor C3 is connected to the gate of the first PMOS tube M1, and the other end is connected to the power supply voltage VDD. The drain of the first PMOS tube M1 is connected to VC2. The second resistor R2 is located between the source of the first PMOS tube M1 and the power supply. Due to the negative feedback of the source, the drain current of the first PMOS tube M1 is linearly related to the gate voltage. The third capacitor C3 serves as an integral capacitor of the third charge pump. When the capacitor in the on-chip loop filter has leakage, the width of the UP signal pulse is wider than the width of the DN signal pulse, so that the third charge pump pulls down the current for more time than pulls up the current, thereby reducing the voltage of the gate of the first PMOS tube M1, and then the drain current of the first PMOS tube M1 increases, compensating for the leakage of the capacitor in the on-chip loop filter. The leakage of the third capacitor C3 is much smaller than the leakage of the capacitor in the on-chip loop filter, and can be implemented by using a thick-gate MOS capacitor, a MIM capacitor or a metal finger capacitor.

[0043] The voltage-controlled oscillator and the programmable frequency divider belong to the prior art and are not limited in the embodiments of the present invention.

[0044] Figure 4 The waveform diagram of the linear voltage-controlled leakage compensation circuit of the present invention when it is turned off and on. When the linear voltage-controlled leakage compensation circuit is turned off, the voltage VC1 at the output terminal of the first charge pump gradually decreases due to the leakage of the on-chip loop filter capacitor, and the frequency detector outputs the pull-up control signal UP and the pull-down control signal DN according to the frequency period of the reference signal Fref, and the pulse width of the pull-up control signal UP is wider than the pulse width of the pull-down control signal DN to compensate for the voltage VC1 at the output terminal of the first charge pump, thereby causing the voltage VC1 at the output terminal of the first charge pump to be a periodic sawtooth wave, thereby causing the jitter of the phase-locked loop output clock signal. When the linear voltage-controlled leakage compensation circuit is turned on, the drain current I of the first PMOS tube M1 COMP Compensate for the leakage I of the on-chip loop filter capacitor LEAK The pulse width of the pull-up control signal UP output by the phase frequency detector is the same as the pulse width of the pull-down control signal DN, and the voltage VC1 at the output terminal of the first charge pump is a stable DC signal.

[0045] The phase-locked loop of the present invention can reduce the jitter in the output clock signal and facilitate full integration. When the second pulse count is used to correct the RTC (real-time clock) circuit in the MCU (Microcontroller Unit), the stability of the clock signal is very high. The low-jitter fully integrated phase-locked loop of the present invention can improve the second pulse count accuracy and reduce the error of the RTC circuit.

[0046] The present invention provides a fully integrated low jitter phase-locked loop. There are many methods and ways to implement the technical solution. The above is only a specific implementation of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention. All components not specified in this embodiment can be implemented by existing technologies.

Claims

1. A fully integrated low jitter phase-locked loop, characterized in that: It includes a phase frequency detector, a first charge pump, a second charge pump, a third charge pump, a linear voltage-controlled leakage compensation circuit, an on-chip loop filter, a voltage-controlled oscillator, and a programmable frequency divider: The phase frequency detector is used to detect the frequency and phase of the input reference signal and the divided signal, and output the pull-up control signal UP and the pull-down control signal DN of the charge pump according to the detection results; The first charge pump is the main charge pump of the fully integrated low-jitter phase-locked loop. The pull-up control signal UP output by the phase frequency detector controls the pull-up current, and the pull-down control signal DN controls the pull-down current; The second charge pump outputs a current in the opposite direction to the first charge pump, that is, the pull-up control signal UP output by the phase frequency detector controls the pull-down current, and the pull-down control signal DN controls the pull-up current, which is used to cooperate with the first charge pump to reduce the size of the capacitor in the on-chip loop filter; The third charge pump outputs a current in the same direction as the second charge pump, that is, the pull-up control signal UP output by the phase frequency detector controls the pull-down current, and the pull-down control signal DN controls the pull-up current, which is used to charge and discharge the capacitor in the linear voltage-controlled leakage compensation circuit; The linear voltage-controlled leakage compensation circuit is used to detect the output voltage of the third charge pump and compensate for the leakage of the capacitor in the on-chip loop filter; The on-chip loop filter is used to filter the output signal of the first charge pump to obtain a filtered signal; The voltage-controlled oscillator is used to output a clock signal according to the filtered signal; The programmable frequency divider is used to divide the clock signal and output the divided signal to the phase frequency detector.

2. A fully integrated low jitter phase-locked loop according to claim 1, characterized in that: The current magnitude of the second charge pump is a times that of the first charge pump, where 0 < a < 1, and the capacitance C1 in the on-chip loop filter is 1 - a times that when there is only the first charge pump.

3. A fully integrated low jitter phase-locked loop according to claim 1, characterized in that: The current of the third charge pump is less than that of the second charge pump. When the leakage of the capacitor in the on-chip loop filter becomes larger, the pull-down current of the third charge pump becomes larger, that is, the voltage at the output end of the third charge pump becomes smaller; when the voltage at the output end of the third charge pump becomes smaller, the linear voltage-controlled leakage compensation circuit compensates for the leakage of the capacitor in the on-chip loop filter, and the magnitude of the compensation current is linearly related to the voltage magnitude at the output end of the third charge pump.

4. A fully integrated low jitter phase-locked loop according to claim 3, characterized in that: The linear voltage-controlled leakage compensation circuit includes a first PMOS transistor M1, a third capacitor C3, and a second resistor R2. The output end of the third charge pump is connected to the gate of the first PMOS transistor M1. The source of the first PMOS transistor M1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the power supply voltage VDD; one end of the third capacitor C3 is connected to the gate of the first PMOS transistor M1, and the other end is connected to the power supply voltage VDD; the drain of the first PMOS transistor M1 is connected to the output end of the second charge pump; the second resistor R2 is connected between the source of the first PMOS transistor M1 and the power supply, so that the drain current of the first PMOS transistor M1 is linearly related to the gate voltage.

5. A fully integrated low jitter phase-locked loop according to claim 4, characterized in that: The leakage of the third capacitor C3 is less than that of the capacitor in the on-chip loop filter, and thick-gate MOS capacitors, MIM capacitors, or metal finger capacitors are used.

6. A fully integrated low jitter phase-locked loop according to claim 5, characterized in that: The capacitor in the on-chip loop filter is implemented by a thin-gate MOS capacitor.

7. A fully integrated low jitter phase-locked loop according to claim 6, characterized in that: The frequency and phase detector includes a first D flip-flop, a second D flip-flop and an AND gate, wherein the D input terminal of the first D flip-flop is connected to a power supply voltage VDD, the clock input terminal CK is connected to a reference signal Fref, and the output terminal Q is connected to a pull-up control signal UP; the D input terminal of the second D flip-flop is connected to the power supply voltage VDD, the clock input terminal CK is connected to a frequency division signal Fdiv, and the output terminal Q is connected to a pull-down control signal DN; UP and DN are respectively connected to two input terminals of the AND gate, and the output terminal of the AND gate is connected to a reset input terminal R of the first D flip-flop and a reset input terminal R of the second D flip-flop.

8. A fully integrated low jitter phase-locked loop according to claim 7, characterized in that: The on-chip loop filter is a second-order structure, including a first resistor R1, a first capacitor C1 and a second capacitor C2. The first charge pump output terminal VC1 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to the output terminal VC2 of the second charge pump, and is also connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the ground; one end of the second capacitor C2 is connected to the first charge pump output terminal VC1, and the other end is grounded.

9. A fully integrated low jitter phase-locked loop according to claim 8, characterized in that: It also includes a bias voltage generating circuit, which provides bias voltages for the first charge pump, the second charge pump and the third charge pump, including providing a first bias voltage VN1 and a second bias voltage VN2 for the NMOS tubes in the first charge pump, the second charge pump and the third charge pump, and providing a third bias voltage VP1 and a fourth bias voltage VP2 for the PMOS tubes in the first charge pump, the second charge pump and the third charge pump.

10. A fully integrated low jitter phase-locked loop according to claim 9, characterized in that: The first charge pump includes a fourteenth NMOS tube M14, a fifteenth NMOS tube M15, a sixteenth PMOS tube M16, a seventeenth PMOS tube M17, a first switch SW1 and a second switch SW2; the fourteenth NMOS tube M14 and the fifteenth NMOS tube M15 form an NMOS common source and common gate current source to provide a pull-down current; the sixteenth PMOS tube M16 and the seventeenth PMOS tube M17 form a PMOS common source and common gate current source to provide a pull-up current; the gate of the fourteenth NMOS tube M14 is connected to the first bias voltage VN1, the source is grounded, the drain is connected to the source of the fifteenth NMOS tube M15, and the gate of the fifteenth NMOS tube M15 is connected to to the second bias voltage VN2, the drain is connected to one end of the second switch SW2, and the other end of the second switch SW2 is connected to the output end VC1 of the first charge pump; the gate of the seventeenth PMOS tube M17 is connected to the third bias voltage VP1, the source is connected to the power supply voltage VDD, the drain is connected to the source of the sixteenth PMOS tube M16, the gate of the sixteenth PMOS tube M16 is connected to the fourth bias voltage VP2, the drain is connected to one end of the first switch SW1, and the other end of the first switch SW1 is connected to the output end VC1 of the first charge pump; the control end of the first switch SW1 is connected to the pull-up control signal UP, and the control end of the second switch SW2 is connected to the pull-down control signal DN; The circuit structures of the second charge pump and the third charge pump are the same as that of the first charge pump, but the output current directions are opposite to that of the first charge pump, that is, the pull-up control signal UP output by the frequency detector and phase detector controls the pull-down current, and the pull-down control signal DN controls the pull-up current.

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